01st week of 2017 patent applcation highlights part 51 |
Patent application number | Title | Published |
20170005006 | GATE STACK FORMED WITH INTERRUPTED DEPOSITION PROCESSES AND LASER ANNEALING | 2017-01-05 |
20170005007 | SEMICONDUCTOR PROCESS | 2017-01-05 |
20170005008 | SEMICONDUCTOR DEVICE HAVING GATE STRUCTURE AND METHOD FOR FABRICATING THE SAME | 2017-01-05 |
20170005009 | MOSFET DEVICES WITH ASYMMETRIC STRUCTURAL CONFIGURATIONS INTRODUCING DIFFERENT ELECTRICAL CHARACTERISTICS | 2017-01-05 |
20170005010 | Germanium-Based CMOS Comprising Silicon Cap Formed Over PMOS Region Having A Thickness Less Than That Over NMOS Region | 2017-01-05 |
20170005011 | FINFET Devices and Methods of Forming | 2017-01-05 |
20170005012 | STACKED SHORT AND LONG CHANNEL FINFETS | 2017-01-05 |
20170005013 | Workpiece Processing Technique | 2017-01-05 |
20170005014 | TEST STRUCTURE MACRO FOR MONITORING DIMENSIONS OF DEEP TRENCH ISOLATION REGIONS AND LOCAL TRENCH ISOLATION REGIONS | 2017-01-05 |
20170005015 | MONITOR PROCESS FOR LITHOGRAPHY AND ETCHING PROCESSES | 2017-01-05 |
20170005016 | PROTECTIVE FILM-FORMING FILM, SHEET FOR FORMING PROTECTIVE FILM, COMPLEX SHEET FOR FORMING PROTECTIVE FILM, AND INSPECTION METHOD | 2017-01-05 |
20170005017 | DETECTION APPARATUS, LITHOGRAPHY APPARATUS, METHOD OF MANUFACTURING ARTICLE, AND DETECTION METHOD | 2017-01-05 |
20170005018 | METHOD AND DEVICE FOR INSPECTION OF A SEMICONDUCTOR DEVICE | 2017-01-05 |
20170005019 | SEMICONDUCTOR WAFER PROCESSING METHODS AND APPARATUS | 2017-01-05 |
20170005020 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE | 2017-01-05 |
20170005021 | EPOXY RESIN COMPOSITION, SEMICONDUCTOR SEALING AGENT, AND SEMICONDUCTOR DEVICE | 2017-01-05 |
20170005022 | PACKAGING STRUCTURE, PACKAGING METHOD AND TEMPLATE USED IN PACKAGING METHOD | 2017-01-05 |
20170005023 | ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOF | 2017-01-05 |
20170005024 | SEMICONDUCTOR DEVICE | 2017-01-05 |
20170005025 | Electronic device and method of manufacturing the same | 2017-01-05 |
20170005026 | NANOPARTICLE THERMAL INTERFACE AGENTS FOR REDUCING THERMAL CONDUCTANCE RESISTANCE | 2017-01-05 |
20170005027 | 3D Chip-On-Wafer-On-Substrate Structure With Via Last Process | 2017-01-05 |
20170005028 | LEADFRAME PACKAGE WITH STABLE EXTENDED LEADS | 2017-01-05 |
20170005029 | METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE HAVING A MULTI-LAYER ENCAPSULATED CONDUCTIVE SUBSTRATE AND STRUCTURE | 2017-01-05 |
20170005030 | Flat No-Leads Package With Improved Contact Pins | 2017-01-05 |
20170005031 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MOUNTING STRUCTURE | 2017-01-05 |
20170005032 | LEAD FRAME AND STACK PACKAGE MODULE INCLUDING THE SAME | 2017-01-05 |
20170005033 | SUBSTRATE, LIGHT-EMITTING DEVICE WITH SUBSTRATE, METHOD OF MANUFACTURING SUBSTRATE ASSEMBLY AND METHOD OF MANUFACTURING LIGHT-EMITTING DEVICE WITH SUBSTRATE | 2017-01-05 |
20170005034 | PACKAGE STRUCTURE | 2017-01-05 |
20170005035 | Stacked Semiconductor Devices and Methods of Forming Same | 2017-01-05 |
20170005036 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME | 2017-01-05 |
20170005037 | METHOD TO REDUCE RESISTANCE FOR A COPPER (CU) INTERCONNECT LANDING ON MULTILAYERED METAL CONTACTS, AND SEMICONDUCTOR STRUCTURES FORMED THEREFROM | 2017-01-05 |
20170005038 | CVD METAL SEED LAYER | 2017-01-05 |
20170005039 | SELF-FORMING BARRIER FOR SUBTRACTIVE COPPER | 2017-01-05 |
20170005040 | ULTRATHIN SUPERLATTICE OF MnO/Mn/MnN AND OTHER METAL OXIDE/METAL/METAL NITRIDE LINERS AND CAPS FOR COPPER LOW DIELECTRIC CONSTANT INTERCONNECTS | 2017-01-05 |
20170005041 | METHOD TO REDUCE TRAP-INDUCED CAPACITANCE IN INTERCONNECT DIELECTRIC BARRIER STACK | 2017-01-05 |
20170005042 | SEMICONDUCTOR DEVICE PACKAGES | 2017-01-05 |
20170005043 | INTEGRATED CIRCUIT (IC) INCLUDING SEMICONDUCTOR RESISTOR AND RESISTANCE COMPENSATION CIRCUIT AND RELATED METHODS | 2017-01-05 |
20170005044 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME | 2017-01-05 |
20170005045 | SEMICONDUCTOR DEVICE AND METHOD | 2017-01-05 |
20170005046 | ISOLATOR AND METHOD OF MANUFACTURING ISOLATOR | 2017-01-05 |
20170005047 | ELECTRONIC APPARATUS OPERABLE IN HIGH FREQUENCIES | 2017-01-05 |
20170005048 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE | 2017-01-05 |
20170005049 | Semiconductor Package System and Method | 2017-01-05 |
20170005050 | CHIP WITH I/O PADS ON PERIPHERIES AND METHOD MAKING THE SAME | 2017-01-05 |
20170005051 | Semiconductor Device And Bump Formation Process | 2017-01-05 |
20170005052 | UNDER BUMP METALLURGY (UBM) AND METHODS OF FORMING SAME | 2017-01-05 |
20170005053 | CHIP MOUNTING STRUCTURE | 2017-01-05 |
20170005054 | POST-PASSIVATION INTERCONNECT STRUCTURE AND METHODS THEREOF | 2017-01-05 |
20170005055 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME | 2017-01-05 |
20170005056 | SYSTEMS AND METHODS FOR HIGH-SPEED, LOW-PROFILE MEMORY PACKAGES AND PINOUT DESIGNS | 2017-01-05 |
20170005057 | CHIP PACKAGE | 2017-01-05 |
20170005058 | CHIP PACKAGE | 2017-01-05 |
20170005059 | Bump-on-Trace Structures with High Assembly Yield | 2017-01-05 |
20170005060 | PACKAGING DEVICE AND METHOD OF MAKING THE SAME | 2017-01-05 |
20170005061 | SEMI-CONDUCTOR PACKAGE STRUCTURE | 2017-01-05 |
20170005062 | DIE-BONDING LAYER FORMATION FILM, PROCESSED PRODUCT HAVING DIE-BONDING LAYER FORMATION FILM ATTACHED THERETO, AND SEMICONDUCTOR DEVICE | 2017-01-05 |
20170005063 | REFLOW APPARATUS | 2017-01-05 |
20170005064 | BONDING DEVICE | 2017-01-05 |
20170005065 | BONDING DEVICE | 2017-01-05 |
20170005066 | METHOD OF MANUFACTURING A FUNCTIONAL INLAY | 2017-01-05 |
20170005067 | Packages for Semiconductor Devices, Packaged Semiconductor Devices, and Methods of Packaging Semiconductor Devices | 2017-01-05 |
20170005068 | THREE-DIMENSIONAL MOUNTING METHOD AND THREE-DIMENSIONAL MOUNTING DEVICE | 2017-01-05 |
20170005069 | Wafer Backside Interconnect Structure Connected to TSVs | 2017-01-05 |
20170005070 | Method of manufacturing a semiconductor package | 2017-01-05 |
20170005071 | STRUCTURE AND FORMATION METHOD FOR CHIP PACKAGE | 2017-01-05 |
20170005072 | STRUCTURE AND FORMATION METHOD FOR CHIP PACKAGE | 2017-01-05 |
20170005073 | 3DIC Stacking Device and Method of Manufacture | 2017-01-05 |
20170005074 | 3D PACKAGE STRUCTURE AND METHODS OF FORMING SAME | 2017-01-05 |
20170005075 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME | 2017-01-05 |
20170005076 | Stacked Integrated Circuits with Redistribution Lines | 2017-01-05 |
20170005077 | Electronic Devices With Soft Input-Output Components | 2017-01-05 |
20170005078 | LIGHT EMITTING DEVICE | 2017-01-05 |
20170005079 | METHOD FOR PRODUCING OPTOELECTRONIC SEMICONDUCTOR DEVICES AND OPTOELECTRONIC SEMICONDUCTOR DEVICE | 2017-01-05 |
20170005080 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE | 2017-01-05 |
20170005081 | ESD PROTECTION STRUCTURE | 2017-01-05 |
20170005082 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | 2017-01-05 |
20170005083 | DISPLAY DEVICE | 2017-01-05 |
20170005084 | PROTECTIVE CIRCUIT FOR CATHODE LAYER, PROTECTIVE METHOD AND OLED DISPLAY DEVICE | 2017-01-05 |
20170005085 | LATERAL BICMOS REPLACEMENT METAL GATE | 2017-01-05 |
20170005086 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR CIRCUIT INCLUDING THE SAME | 2017-01-05 |
20170005087 | DISTRIBUTED DECOUPLING CAPACITOR | 2017-01-05 |
20170005088 | DISTRIBUTED DECOUPLING CAPACITOR | 2017-01-05 |
20170005089 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SAME | 2017-01-05 |
20170005090 | FINFET with U-Shaped Channel | 2017-01-05 |
20170005091 | Semiconductor Devices and Method for Forming Semiconductor Devices | 2017-01-05 |
20170005092 | LOW END PARASITIC CAPACITANCE FINFET | 2017-01-05 |
20170005093 | Semiconductor Device with Split Work Functions | 2017-01-05 |
20170005094 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF | 2017-01-05 |
20170005095 | SANDWICH EPI CHANNEL FOR DEVICE ENHANCEMENT | 2017-01-05 |
20170005096 | SUB WORD LINE DRIVER OF A SEMICONDUCTOR MEMORY DEVICE | 2017-01-05 |
20170005097 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME | 2017-01-05 |
20170005098 | STRUCTURE AND METHOD TO PREVENT EPI SHORT BETWEEN TRENCHES IN FINFET EDRAM | 2017-01-05 |
20170005099 | METHODS OF FABRICATING SEMICONDUCTOR DEVICE | 2017-01-05 |
20170005100 | SEMICONDUCTOR DEVICE INCLUDING DUMMY METAL | 2017-01-05 |
20170005101 | INTEGRATED CIRCUIT STRUCTURE WITH METHODS OF ELECTRICALLY CONNECTING SAME | 2017-01-05 |
20170005102 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME | 2017-01-05 |
20170005103 | One Time Programmable Memory with a Twin Gate Structure | 2017-01-05 |
20170005104 | SHALLOW TRENCH AIR GAPS AND THEIR FORMATION | 2017-01-05 |
20170005105 | Height Reduction in Memory Periphery | 2017-01-05 |