01st week of 2022 patent applcation highlights part 60 |
Patent application number | Title | Published |
20220005912 | ARRAY SUBSTRATE AND DISPLAY PANEL - An array substrate and a display panel are disclosed. The array substrate includes: a base substrate including a display region and a peripheral region; a plurality of sub-pixels in the display region; a plurality of data lines in the display region; a plurality of first power lines in the display region; a plurality of data lead lines in the peripheral region; a plurality of selection switches in the peripheral region; a plurality of data signal input lines in the peripheral region; a first power bus in the peripheral region; and a plurality of connection portions electrically connecting the first power bus to the plurality of first power lines, respectively. The plurality of connection portions include a plurality of first connection portions and a plurality of second connection portions on both sides of the plurality of first connection portions. | 2022-01-06 |
20220005913 | ELECTRONIC SUBSTRATE, METHOD OF MANUFACTURING ELECTRONIC SUBSTRATE, AND DISPLAY PANEL - An electronic substrate, a method of manufacturing an electronic substrate, and a display panel are provided. The electronic substrate includes a base substrate, and the base substrate includes a display area and a peripheral area. The electronic substrate further includes sub-pixels and data lines in the display area, and a plurality of signal input pads, a plurality of first detection lines, and a plurality of second detection lines in the peripheral area. The first detection lines and the second detection lines are on a side of the signal input pads away from the display area, and are electrically connected to the signal input pads. The first detection lines are made of a non-metallic conductive material, the second detection lines are made of a metal conductive material, and at least one of the plurality of first detection lines is provided between every two adjacent second detection lines. | 2022-01-06 |
20220005914 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a display device includes forming a first hole that extends into a substrate, through a first wet etching process using a first etchant and forming a second hole that extends from the first hole further into the substrate, through a second wet etching process using a second etchant. The second etchant has a pH different from a pH of the first etchant. | 2022-01-06 |
20220005915 | DISPLAY DEVICE - A display device includes a display panel including a plurality of display pads, a portion of the plurality of display pads being extended along a first direction and arranged along a second direction intersecting the first direction, and a flexible circuit board including a plurality of substrate pads electrically connected to the plurality of display pads, and a plurality of dummy pads spaced apart from the plurality of substrate pads and arranged in parallel to the plurality of substrate pads along the second direction, a portion of the plurality of dummy pads have an extension length in the first direction and a width in the second direction substantially same as an extension length in the first direction and a width in the second direction, respectively, of the plurality of substrate pads. | 2022-01-06 |
20220005916 | DISPLAY DEVICE - A display device that can prevent deformation of a reflective electrode in a structure has an auxiliary connection pattern formed of the same materials of an anode including the reflective electrode for high reflection characteristics, so as to ensure a reliable voltage drop structure of a cathode and to improve transmission efficiency of transmission parts and luminance of emission parts in a structure having both the transmission parts and the emission parts. | 2022-01-06 |
20220005917 | DISPLAY DEVICE - A display device includes: a base layer comprising a top surface, a bottom surface opposite the top surface, and a plurality of side surfaces connecting the top surface and the bottom surface, wherein a display area and a non-display area adjacent to the display area are defined; an outer line overlapping the non-display area, on the top surface, and adjacent to any one of the plurality of side surfaces; a light emitting element layer overlapping the display area, on the top surface, and comprising a light emitting element; and a connection line connecting the outer line and the light emitting element, wherein the outer line comprises a center line extending from the connection line in a first direction and a branch line extending from the center line in a second direction crossing the first direction. | 2022-01-06 |
20220005918 | DISPLAY DEVICE HAVING MULTIPLE PROTECTIVE FILMS AND WIRING LAYER - According to one embodiment, a display device includes a pixel area including pixels each including at least one thin film transistor includes a semiconductor layer and a gate electrode, a first terminal area including a first wiring line disposed thereon connected to the at least one thin film transistor, a first protective film provided on the semiconductor layer, the gate electrode and the first wiring line, a first insulating film provided on the first protective film, a second protective film provided on the first insulating film, a second insulating film provided on the second protective film, a first opening formed in the first terminal area, and partially exposing the first wiring line, and a second opening formed to correspond to the first opening. | 2022-01-06 |
20220005919 | DISPLAY PANEL AND DISPLAY DEVICE - Provided are a display panel and a display device. The display panel includes a substrate, a light-emitting element located on a side of the substrate, and a deformation module located between the substrate and the light-emitting element and including at least one deformation element. In a direction perpendicular to a plane where the substrate is located, the at least one deformation element in the deformation module overlaps the light-emitting element. Provided are a display panel and a display device to change a light-emitting angle of a light-emitting element, so that users can obtain a better view angle and the display effect can be improved. | 2022-01-06 |
20220005920 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel, including a main display area and a light-transmitting display area; wherein the main display area surrounds the light-transmitting display area; the display panel includes: a substrate; an organic electroluminescent element array, including a plurality of organic electroluminescent elements disposed on the substrate; the driving circuit array is disposed on the substrate and is adapted to be matched with a high voltage source and a low voltage source for driving each of the organic light-emitting electroluminescent elements; wherein in the transparent display area, the driving circuit array includes a passive driving circuit array; the passive driving circuit array is configured to drive the organic electroluminescent element of the light-transmitting display area to display. | 2022-01-06 |
20220005921 | TOUCH DISPLAY PANEL AND DISPLAY DEVICE - Provided are a touch display panel and a display device. The touch display panel includes a first substrate and a second substrate disposed opposite to the first substrate. In a non-display area, multiple first conductive structures and multiple metal wires are configured on one side of the first substrate facing to the second substrate, and multiple second conductive structures are configured on one side of the second substrate facing to the first substrate. Each first conductive structure is electrically connected to a respective second conductive structure. Each first conductive structure includes a first transmit electrode and a first gasket structure that is disposed between the first transmit electrode and the first substrate. The first transmit electrode is electrically connected to a metal wire and the respective one second conductive structure. The first gasket structure includes multiple first recessed portions. | 2022-01-06 |
20220005922 | METHOD OF FORMING A SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR - In an embodiment, a semiconductor device includes a resistor that overlies a doped region of the semiconductor device. The resistor is formed into a pattern of a polygon spiral. An embodiment of the pattern of the resistor includes sides and corners. The material of the sides has a low resistivity and the material of the corners has a higher resistivity. | 2022-01-06 |
20220005923 | THIN FILM STRUCTURE INCLUDING DIELECTRIC MATERIAL LAYER AND ELECTRONIC DEVICE EMPLOYING THE SAME - Disclosed are a thin film structure and an electronic device including the same. The disclosed thin film structure includes a dielectric material layer between a first material layer and a second material layer. The dielectric material layer includes a dopant in a matrix material having a fluorite structure. The dielectric material layer is uniformly doped with a low concentration of the dopant, and has ferroelectricity. | 2022-01-06 |
20220005924 | SEMICONDUCTOR DEVICE HAVING A SUPER JUNCTION STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a super junction and a method of manufacturing the semiconductor device capable of obtaining a high breakdown voltage are provided, whereby charge balance of the super junction is further accurately controlled in the semiconductor device that is implemented by an N-type pillar and a P-type pillar. The semiconductor device includes a semiconductor substrate; and a blocking layer including a first conductive type pillar and a second conductive type pillar that extend in a vertical direction on the semiconductor substrate and that are alternately arrayed in a horizontal direction, wherein, in the blocking layer, a density profile of a first conductive type dopant may be uniform in the horizontal direction, and the density profile of the first conductive type dopant may vary in the vertical direction. | 2022-01-06 |
20220005925 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, INVERTER CIRCUIT, DRIVER DEVICE, VEHICLE, AND ELEVATOR - This semiconductor device according to an embodiment includes: a silicon carbide layer; a gate electrode; a silicon oxide layer between the silicon carbide layer and the gate electrode; and a region between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration not less than 1×10 | 2022-01-06 |
20220005926 | SEMICONDUCTOR DEVICE INCLUDING SUPERLATTICE WITH OXYGEN AND CARBON MONOLAYERS - A semiconductor device may include a semiconductor layer and a superlattice adjacent the semiconductor layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one non-semiconductor monolayer in a first group of layers of the superlattice may comprise oxygen and be devoid of carbon, and the at least one non-semiconductor monolayer in a second group of layers of the superlattice may comprise carbon. | 2022-01-06 |
20220005927 | METHOD FOR MAKING SEMICONDUCTOR DEVICE INCLUDING SUPERLATTICE WITH OXYGEN AND CARBON MONOLAYERS - A method for making a semiconductor device may include forming a superlattice adjacent a semiconductor layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one non-semiconductor monolayer in a first group of layers of the superlattice may comprise oxygen and be devoid of carbon, and the at least one non-semiconductor monolayer in a second group of layers of the superlattice may comprise carbon. | 2022-01-06 |
20220005928 | SILICON CARBIDE SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD OF THE SAME - In a guard ring section of a silicon carbide semiconductor device, an electric field relaxation layer for relaxing an electric field is formed in a surface layer portion of a drift layer, so that electric field is restricted from penetrating between guard rings. Thus, an electric field concentration is relaxed. Accordingly, a SiC semiconductor device having a required withstand voltage is obtained. | 2022-01-06 |
20220005929 | MEMORY TRANSISTOR WITH MULTIPLE CHARGE STORING LAYERS AND A HIGH WORK FUNCTION GATE ELECTRODE - Semiconductor devices including non-volatile memory transistors and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the memory transistor comprises an oxide-nitride-oxide (ONO) stack on a surface of a semiconductor substrate, and a high work function gate electrode formed over a surface of the ONO stack. Preferably, the gate electrode comprises a doped polysilicon layer, and the ONO stack comprises multi-layer charge storing layer including at least a substantially trap free bottom oxynitride layer and a charge trapping top oxynitride layer. More preferably, the device also includes a metal oxide semiconductor (MOS) logic transistor formed on the same substrate, the logic transistor including a gate oxide and a high work function gate electrode. In certain embodiments, the dopant is a P+ dopant and the memory transistor comprises N-type (NMOS) silicon-oxide-nitride-oxide-silicon (SONOS) transistor while the logic transistor a P-type (PMOS) transistor. Other embodiments are also disclosed. | 2022-01-06 |
20220005930 | APPARATUS WITH MULTIDIELECTRIC SPACERS ON CONDUCTIVE REGIONS OF STACK STRUCTURES, AND RELATED METHODS - Apparatus (e.g., semiconductor devices) include stack structures with at least one conductive region and at least one nonconductive material. A multidielectric spacer is adjacent the at least one conductive region and comprises first and second dielectric materials. The first dielectric material, adjacent the at least one conductive region, includes silicon and nitrogen. The second dielectric material, adjacent the first dielectric material, comprises silicon-carbon bonds and defines a substantially straight, vertical, outer sidewall. In methods to form such apparatus, the first dielectric material may be formed with selectivity on the at least one conductive region, and the second dielectric material may be formulated and formed to exhibit etch resistance. | 2022-01-06 |
20220005931 | SEMICONDUCTOR DEVICE AND FORMING METHOD THEREOF - A semiconductor device and a forming method thereof are provided. The semiconductor device includes a substrate, a fin located on the substrate, and a gate structure located on the substrate and across the fin. The fin includes a first region, and the fin of the first region includes a gate groove and a channel layer located between adjacent gate grooves. The gate structure covers a sidewall and a top of the fin of the first region, fills the gate groove and surrounds the channel layer. A width of the gate structure located in the gate groove is smaller than a width of the gate structure located on the top of the fin of the first region. | 2022-01-06 |
20220005932 | NON-VOLATILE MEMORY SYSTEMS BASED ON SINGLE NANOPARTICLES FOR COMPACT AND HIGH DATA STORAGE ELECTRONIC DEVICES - There is provided a structure of a nano memory system. The disclosed unit nano memory cell comprises a single isolated nanoparticle placed on the surface of a semiconductor substrate ( | 2022-01-06 |
20220005933 | VARIED SILICON RICHNESS SILICON NITRIDE FORMATION - A method to fabricate a non-planar memory device including forming a multi-layer silicon nitride structure substantially perpendicular to a top surface of the substrate. There may be multiple non-stoichiometric silicon nitride layers, each including a different or same silicon richness value from one another. | 2022-01-06 |
20220005934 | Self-Aligned Source and Drain Contacts - Self-aligned semiconductor FET device source and drain contacts and techniques for formation thereof are provided. In one aspect, a semiconductor FET device includes: at least one gate disposed on a substrate; source and drains on opposite sides of the at least one gate; gate spacers offsetting the at least one gate from the source and drains; lower source and drain contacts disposed on the source and drains; upper source and drain contacts disposed on the lower source and drain contacts; and a silicide present between the lower source and drain contacts and the upper source and drain contacts. | 2022-01-06 |
20220005935 | SELF-ALIGNED BOTTOM SPACER EPI LAST FLOW FOR VTFET - A method is presented for forming a vertical transport field effect transistor (VTFET). The method includes forming a plurality of fins over a substrate, depositing a sacrificial material adjacent the plurality of fins, forming self-aligned spacers adjacent the plurality of fins, removing the sacrificial material to define openings under the self-aligned spacers, filling the openings with bottom spacers, depositing an interlayer dielectric (ILD) after patterning, laterally etching the substrate such that bottom surfaces of the plurality of fins are exposed, the lateral etching defining cavities within the substrate, and filling the cavities with an epitaxial material such that epitaxial regions are defined each having a symmetric tapered shape under a twin-fin structure. The single fin device can be formed through additional patterning and bottom epi under the single fin device that has an asymmetric tapered shape. | 2022-01-06 |
20220005936 | STACKED VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY (EEPROM) DEVICES - A vertically stacked set of an n-type vertical transport field effect transistor (n-type VT FET) and a p-type vertical transport field effect transistor (p-type VT FET) is provided. The vertically stacked set of the n-type VT FET and the p-type VT FET includes a first bottom source/drain layer on a substrate, that has a first conductivity type, a lower channel pillar on the first bottom source/drain layer, and a first top source/drain on the lower channel pillar, that has the first conductivity type. The vertically stacked set of the n-type VT FET and the p-type VT FET further includes a second bottom source/drain on the first top source/drain, that has a second conductivity type different from the first conductivity type, an upper channel pillar on the second bottom source/drain, and a second top source/drain on the upper channel pillar, that has the second conductivity type. | 2022-01-06 |
20220005937 | SELECTIVE SILICON ETCH FOR GATE ALL AROUND TRANSISTORS - Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a trimmed semiconductor material between source regions and drain regions of the device. The method includes selectively isotropically etching semiconductor material layers between source regions and drain regions of an electronic device. | 2022-01-06 |
20220005938 | POLARIZATION CONTROLLED TRANSISTOR - A transistor includes a first layer comprising a group III-nitride semiconductor. A second layer comprising a group III-nitride semiconductor is disposed over the first layer. A third layer comprising a group III-nitride semiconductor is disposed over the second layer. An interface between the second layer and the third layer form a polarization heterojunction. A fourth layer comprising a group III-nitride semiconductor is disposed over the third layer. An interface between the third layer and the fourth layer forms a pn junction. A first electrical contact pad is disposed on the fourth layer. A second electrical contact pad is disposed on the third layer. A third electrical contact pad is electronically coupled to bias the polarization heterojunction. | 2022-01-06 |
20220005939 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - The present disclosure relates to a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer above the substrate, a semiconductor stack disposed on and in contact with the first nitride semiconductor layer, and a first electrode in contact with the semiconductor stack. Wherein the semiconductor stack comprises a first layer and a second layer, and a lattice constant of the first layer along an a-axis is less than the second layer. | 2022-01-06 |
20220005940 | SEMICONDUCTOR DEVICE AND FORMING METHOD THEREOF - A semiconductor device and a forming method thereof are provided. The forming method includes forming an initial dummy gate structure on a substrate. The initial dummy gate structure extends along a first direction. The forming method also includes forming a source/drain doped layer in the substrate on two sides of the initial dummy gate structure, forming an initial conductive layer on the source/drain doped layer and covering a sidewall and a top surface of the source/drain doped layer, and after forming the initial conductive layer, removing the initial dummy gate structure. | 2022-01-06 |
20220005941 | GATE INDUCED DRAIN LEAKAGE REDUCTION IN FINFETS - A method of forming a semiconductor device that includes forming an inner dielectric spacer and outer dielectric spacer combination structure on a sacrificial gate structure that is present on a fin structure, wherein the inner dielectric spacer and outer dielectric spacer combination structure separates source and drain regions from the sacrificial gate structure. The method further includes removing the inner sidewall dielectric spacer; and forming a channel epitaxial wrap around layer on the portion of the fin structure that is exposed by removing the inner sidewall dielectric spacer. The method further includes removing the sacrificial gate structure to provide a gate opening to a channel portion of the fin structure, wherein the gate opening exposes the channel epitaxial wrap around layer; and forming a functional gate structure within the gate opening. | 2022-01-06 |
20220005942 | VERTICAL HIGH-BLOCKING III-V BIPOLAR TRANSISTOR - A vertical high-blocking III-V bipolar transistor, which includes an emitter, a base and a collector. The emitter has a highly doped emitter semiconductor contact region of a first conductivity type and a first lattice constant. The base has a low-doped base semiconductor region of a second conductivity type and the first lattice constant. The collector has a layered low-doped collector semiconductor region of the first conductivity type with a layer thickness greater than 10 μm and the first lattice constant. The collector has a layered highly doped collector semiconductor contact region of the first conductivity type. A first metallic connecting contact layer is formed in regions being integrally connected to the emitter. A second metallic connecting contact layer is formed in regions being integrally connected to the base. A third metallic connecting contact region is formed at least in regions being arranged beneath the collector. | 2022-01-06 |
20220005943 | QUANTUM DOT DEVICES WITH TOP GATES - Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a plurality of gates disposed on the quantum well stack; and a top gate at least partially disposed on the plurality of gates such that the plurality of gates are at least partially disposed between the top gate and the quantum well stack. | 2022-01-06 |
20220005944 | SEMICONDUCTOR DEVICE STRUCTURES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device structure includes a substrate, a channel layer, a barrier layer and a doped group III-V layer. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The doped group III-V layer is disposed on the barrier layer. The doped group III-V layer includes a first portion and a second portion. The first portion has a first concentration of a first element. The second portion is adjacent to the first portion and has a second concentration of the first element. The gate structure is disposed on the first portion of the doped group III-V layer. The first concentration of the first element is different from the second concentration of the first element. | 2022-01-06 |
20220005945 | COMPOUND SEMICONDUCTOR DEVICE, COMPOUND SEMICONDUCTOR SUBSTRATE, AND METHOD FOR MANUFACTURING COMPOUND SEMICONDUCTOR DEVICE - A compound semiconductor device, a compound semiconductor substrate, and a method for manufacturing of a compound semiconductor device. Compound semiconductor device | 2022-01-06 |
20220005946 | SEMICONDUCTOR DEVICES AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a substrate including a fin-type active region, the fin-type active region extending in a first direction; a plurality of channel layers on the fin-type active region, the plurality of channel layers including an uppermost channel layer, a lowermost channel layer, and an intermediate channel layer isolated from direct contact with each other in a direction perpendicular to an upper surface of the substrate; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; a gate insulating film between the plurality of channel layers and the gate electrode; and source/drain regions electrically connected to the plurality of channel layers. In a cross section taken in the second direction, the uppermost channel layer has a width greater than a width of the intermediate channel layer. | 2022-01-06 |
20220005947 | SEMICONDUCTOR DEVICE - An object is to provide a technique capable of reducing a parasitic capacitance in a semiconductor device with high accuracy. A semiconductor device includes: a base region; a source region; a second trench passing through the base region to reach the drift layer; a second protective layer disposed in a bottom portion of the second trench; a source electrode, at least part of which is disposed in the second trench, to be electrically connected to a first protective layer, the base region, and the source region; and a source side connection layer of a second conductivity type constituting at least part of a lateral portion of the second trench and connected to the base region and the second protective layer. | 2022-01-06 |
20220005948 | FIN FIELD EFFECT TRANSISTOR WITH FIELD PLATING - An integrated circuit (IC) having a fin field effect transistor (FinFET) includes a substrate with a fin extending from a surface of the substrate. The fin includes a source region, a drain region, a drift region, and field plating oxide layer. The drift region is adjacent the drain region. The field plating oxide layer is on a first side, a second side, and a third side of the drift region. | 2022-01-06 |
20220005949 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor structure including: forming a drift well in a substrate, in which the drift well includes first dopants having a first conductivity type; forming an isolation structure over the drift well; forming a well region in the drift well and spaced apart from the isolation structure, such that a top portion of the drift well is between the well region and the isolation structure; doping the top portion with second dopants having a second conductivity type different from the first conductivity type, such that a doping concentration of the second dopants in the top potion is lower than a doping concentration of the first dopants in the top portion after doping the top portion; and forming a gate structure extending from the isolation structure to the well region and covering the top portion of the drift well. | 2022-01-06 |
20220005950 | Integrated Assemblies having Transistors Configured for High-Voltage Applications, and Methods of Forming Integrated Assemblies - Some embodiments include an integrated assembly having a first gate operatively adjacent a channel region, a first source/drain region on a first side of the channel region, and a second source/drain region on an opposing second side of the channel region. The first source/drain region is spaced from the channel region by an intervening region. The first and second source/drain regions are gatedly coupled to one another through the channel region. A second gate is adjacent a segment of the intervening region and is spaced from the first gate by an insulative region. A lightly-doped region extends across the intervening region and is under at least a portion of the first source/drain region. Some embodiments include methods of forming integrated assemblies. | 2022-01-06 |
20220005951 | Strained Semiconductor FET Devices with Epitaxial Quality Improvement - Strained semiconductor FET devices with epitaxial quality improvement are provided. In one aspect, a semiconductor FET device includes: a substrate; at least one device stack including active layers oriented horizontally one on top of another on the substrate; gates surrounding at least a portion of each of the active layers; gate spacers alongside the gates; and source/drains, interconnected by the active layers, on opposite sides of the gates, wherein the source/drains are offset from the gates by inner spacers, wherein the source/drains include an epitaxial material having a low defect density which induces strain in the active layers, and wherein the gate spacers are formed from a same material as the inner spacers. A method of forming the semiconductor FET device using a spacer last process is also provided. | 2022-01-06 |
20220005952 | STRUCTURE WITH TWO ADJACENT METAL LAYERS IN GATE STRUCTURE - A structure includes a semiconductor fin; a first source/drain region and a second source/drain region in the semiconductor fin; a first doping region about the first source/drain region, defining a channel region in the semiconductor fin; and a second doping region about the second source/drain region, defining a drain extension in the semiconductor fin. A gate structure is over the channel region and the drain extension. The gate structure includes a gate dielectric layer, a first metal layer adjacent a second metal layer over the gate dielectric layer, and a contiguous gate conductor over the first metal layer and the second metal layer. One of the metal layers is over the channel region and the other is over the drain extension. The metal layers may have different thicknesses and/or work functions, to improve transconductance and RF performance of an LDMOS FinFET including the structure. | 2022-01-06 |
20220005953 | SEMICONDUCTOR DEVICE HAVING A NECKED SEMICONDUCTOR BODY AND METHOD OF FORMING SEMICONDUCTOR BODIES OF VARYING WIDTH - Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body. | 2022-01-06 |
20220005954 | IC STRUCTURE WITH FIN HAVING SUBFIN EXTENTS WITH DIFFERENT LATERAL DIMENSIONS - An integrated circuit (IC) structure includes a semiconductor fin having a first longitudinal extent and a second longitudinal extent. The semiconductor fin has an upper fin portion having a uniform lateral dimension in the first longitudinal extent and the second longitudinal extent, a first subfin portion under the upper fin portion in the first longitudinal extent having a first lateral dimension, and a second subfin portion under the upper fin portion in the second longitudinal extent having a second lateral dimension different than the first lateral dimension. The second subfin may be used in a drain extension region of a laterally-diffused metal-oxide semiconductor (LDMOS) device. The second subfin reduces subfin current and improves HCI reliability, regardless of the type of LDMOS device. | 2022-01-06 |
20220005955 | DISPLAY PANEL AND ELECTRONIC DEVICE - The present disclosure provides a display panel and an electronic device. The display panel comprises: a substrate, wherein a metal layer and an anti-reflection film are disposed on the substrate, the anti-reflection film is disposed on a light-emitting side of the metal layer, and the anti-reflection film comprises a protective layer and a darkening layer; wherein the protective layer is disposed between the darkening layer and the metal layer, and a material of the darkening layer comprises at least one of Mo | 2022-01-06 |
20220005956 | DISPLAY PANEL AND ELECTRONIC DEVICE - A display panel and an electronic device are disclosed. The display panel includes a metal oxide semiconductor layer disposed on a substrate. Part of a gate insulating layer is disposed on the metal oxide semiconductor layer. Part of a first metal layer is disposed on the gate insulating layer. The first metal layer includes a gate electrode. A protection layer is disposed on the gate electrode, the gate insulating layer, and the metal oxide semiconductor layer, and the protection layer is made of a metal oxide. | 2022-01-06 |
20220005957 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device includes the following steps. An opening is formed penetrating a dielectric layer on a semiconductor substrate. A stacked structure is formed on the dielectric layer. The stacked structure includes a first semiconductor layer partly formed in the opening and partly formed on the dielectric layer, a sacrificial layer formed on the first semiconductor layer, and a second semiconductor layer formed on the sacrificial layer. A patterning process is performed for forming a fin-shaped structure including the first semiconductor layer, the sacrificial layer, and the second semiconductor layer. An etching process is performed to remove the sacrificial layer in the fin-shaped structure. The first semiconductor layer in the fin-shaped structure is etched to become a first semiconductor wire by the etching process. The second semiconductor layer in the fin-shaped structure is etched to become a second semiconductor wire by the etching process. | 2022-01-06 |
20220005958 | SEMICONDUCTOR DEVICES - A semiconductor device includes an active region on a substrate extending in a first direction, the active region having an upper surface and sidewalls, a plurality of channel layers above the active region to be vertically spaced apart from each other, a gate electrode extending in a second direction to intersect the active region and partially surrounding the plurality of channel layers, and a source/drain region on the active region on at least one side of the gate electrode and in contact with the plurality of channel layers, and extending from the sidewalls of the active region having a major width in the second direction in a first region adjacent to a lowermost channel layer adjacent to the active region among the plurality of channel layer. | 2022-01-06 |
20220005959 | SILICON CARBIDE POWER DIODE DEVICE AND FABRICATION METHOD THEREOF - A silicon carbide power diode device has a silicon carbide substrate on which a silicon carbide epitaxial layer with an active region is provided. A Schottky metal layer is on the active region, and a first electrode layer is on the Schottky metal layer. A first ohmic contact is on the silicon carbide substrate, and a second electrode layer is on the first ohmic contact. The active region of the silicon carbide epitaxial layer has a plurality of first P-type regions, a plurality of second P-type regions, and N-type regions. The first P-type regions and the second P-type regions lacking an ohmic contact are spaced apart with dimensions of the second P-type regions being minimized and the N-type regions being maximized for given dimensions of the first P-type region. Second ohmic contacts are located between the first P-type region and the Schottky metal layer. | 2022-01-06 |
20220005960 | INTEGRATED CIRCUIT INCLUDING A CAPACITIVE ELEMENT AND CORRESPONDING MANUFACTURING METHOD - A semiconductor substrate includes excavations which form trenches sunk. A capacitive element includes: a first dielectric envelope conforming to sides and bottoms of the trenches; a first semiconductor layer conforming to a surface of the first dielectric envelope in the trenches; a second dielectric envelope conforming to a surface of the first semiconductor layer in the trenches; and a second semiconductor layer conforming to a surface of the second dielectric envelope in the trenches. | 2022-01-06 |
20220005961 | Photoelectric Detector And Method of Making The Same - Various embodiments of a photodetector having a reflector are described. The photodetector includes a waveguide layer disposed on top of a substrate, an avalanche multiplication detection region disposed on top of the waveguide layer, and a reflector disposed adjacent to a rear surface of the waveguide layer. The waveguide layer includes a narrower input section and a wider detection section concatenated with the input section. The waveguide layer may also include a tapering section having a changing width that follows the detection section. The reflector may be a one-dimensional photonic crystal, a two-dimensional photonic crystal, or a bulk material. A careful design of the reflector and the waveguide layer of the photodetector is helpful in achieving a high responsivity and a high operation speed at the same time. | 2022-01-06 |
20220005962 | Transparent Multi-Layer Assembly and Production Method - A transparent multi-layer assembly includes a transparent carrier structure comprising a polymer material and an electrically conductive transparent layer comprising an electrically conductive oxide. A silicon carbide layer is arranged as an adhesion promoter between the transparent carrier structure and the electrically conductive transparent layer. | 2022-01-06 |
20220005963 | FILTERING PANEL AND PHOTOVOLTAIC MODULE INCLUDING SAME - A filtering panel includes a molding layer part; a pattern layer part having an incident surface through which light emitted from a light source and viewing light transmitted to an observer enter, and an accommodation surface which is the reverse surface of the incident surface, wherein the molding layer part is stacked on the incident surface so as to be adjacent thereto, and the pattern layer part adjusts the optical paths of the emitted light and the viewing light; and a filtering layer part formed on a lower incident surface of the pattern layer part having the incident surface of the viewing light that enters from a lower region below a horizontal reference line, wherein the reflectivity of the visible light in the viewing light incident on the lower region is made greater than that of an upper region above the reference line by means of mirror reflection. | 2022-01-06 |
20220005964 | SEMINCONDUCTOR COMPONENT AND METHOD FOR SINGULATING A SEMICONDUCTOR COMPONENT HAVING A PN JUNCTION - A a semiconductor component ( | 2022-01-06 |
20220005965 | SOLAR CELL MODULE - A solar cell module comprises cell groups each containing solar cells, and each solar cell includes photoelectric converters, N number of which being connected in series, and first, second and third terminals. When the first terminal on one end of a first cell group has a reference potential, the second terminal on the other end of the mth cell group is connected to the first terminal on one end of another cell group, and N number of the third terminals of the mth cell group are respectively connected to N number of the first terminals of an m+1th cell group. The difference in potential between the second terminal on the other end of the mth cell group and the first terminal on one end of the other cell group is 10% or less of the difference in potential between the second and first terminals of the mth cell group. | 2022-01-06 |
20220005966 | CARRIER-SELECTIVE CONTACT JUNCTION SILICON SOLAR CELL AND MANUFACTURING METHOD THEREFOR - In a carrier-selective contact junction silicon solar cell according to the present invention, a copper iodine thin film as a hole-selective contact layer is formed through low-temperature annealing so that excellent p-type semiconductor properties are maintained, and electrical conductivity and passivation properties become excellent, thereby improving photoelectric conversion efficiency. | 2022-01-06 |
20220005967 | VISIBLE LIGHT DETECTOR WITH HIGH-PHOTORESPONSE BASED ON TiO2/MoS2 HETEROJUNCTION AND PREPARATION THEREOF - In the field of photoelectric devices, a visible light detector is provided with high-photoresponse based on a TiO | 2022-01-06 |
20220005968 | PHOTODETECTOR - A photodetector comprising an optical waveguide structure comprising at least three stripes spaced from one another such that a slot is present between each two adjacent stripes of the at least three stripes. A graphene absorption layer is provided over or underneath the at least three stripes. There is an electrode for each stripe, over or underneath the graphene absorption layer. The photodetector is configured such that two adjacent electrodes are biased using opposite polarities to create a p-n junction effect in a portion of the graphene absorption layer. In particular the portion of the graphene absorption layer is located over or underneath each respective slot between said each two adjacent stripes. | 2022-01-06 |
20220005969 | SOLAR CELL MODULE MANUFACTURING METHOD AND SOLAR CELL MODULE - First, first cell wiring members from the first solar cell and second cell wiring members from the second solar cell are sandwiched between a wiring member film and a second bridge wiring member. Subsequently, the first cell wiring members and the second cell wiring members are connected to the second bridge wiring member by applying heat to at least the first cell wiring members, the second cell wiring members, and the second bridge wiring member by induction heating. | 2022-01-06 |
20220005970 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND MANUFACTURING METHOD - The present invention provides a semiconductor light emitting device including a substrate, a first semiconductor layer, a first cladding layer, an active layer, a second cladding layer and a second semiconductor layer, and a manufacturing method. The first semiconductor layer may be an n-type semiconductor including a III-V semiconductor or a II-VI semiconductor. The second semiconductor layer may be a p-type semiconductor including a I-VII semiconductor. The semiconductor light emitting device may further include a third cladding layer between the active layer and the second cladding layer, the third cladding layer including a III-V semiconductor or a II-VI semiconductor. Therefore, by providing the hybrid type semiconductor light emitting device and the manufacturing method thereof, the luminous efficiency limit of the p-type semiconductor can be overcome. | 2022-01-06 |
20220005971 | PASSIVATION COVERED LIGHT EMITTING UNIT STACK - A light emitting diode (LED) pixel for a display including a light emitting structure including at least one active layer and configured to generate light, a first passivation layer covering the light emitting structure, a protection structure disposed on the first passivation layer, a plurality of lower via contacts passing through the first passivation layer and electrically connected to the light emitting structure; and a plurality of upper via contacts passing through the protection structure and electrically connected to the lower via contacts, respectively, in which the lower via contacts and the upper via contacts are disposed outside of the at least one active layer. | 2022-01-06 |
20220005972 | IMAGE DISPLAY DEVICE - An image display device includes a drive circuit substrate, micro LED elements, and a wavelength conversion layer that converts excitation light emitted from the micro LED elements and that emits converted long-wavelength light to a side opposite to the drive circuit substrate, the micro LED elements and the wavelength conversion layer being sequentially stacked on the drive circuit substrate. The micro LED elements include a first multilayer film that reflects the long-wavelength light converted by the wavelength conversion layer. | 2022-01-06 |
20220005973 | RESONANT OPTICAL CAVITY LIGHT EMITTING DEVICE - Resonant optical cavity light emitting devices are disclosed, where the device includes a substrate, a first spacer region, a light emitting region, a second spacer region, and a reflector. The light emitting region is configured to emit a target emission deep ultraviolet wavelength and is positioned at a separation distance from the reflector. The reflector may be a distributed Bragg reflector. The device has an optical cavity comprising the first spacer region, the second spacer region and the light emitting region, where the optical cavity has a total thickness less than or equal to K·λ/n. K is a constant ranging from 0.25 to 10, λ is the target wavelength, and n is an effective refractive index of the optical cavity at the target wavelength. | 2022-01-06 |
20220005974 | Radiation-Emitting Semiconductor Chip - In an embodiment a radiation-emitting semiconductor chip includes a semiconductor body having an active region configured to generate radiation, a first contact layer having a first contact area for external electrical contacting the radiation-emitting semiconductor chip and a first contact finger structure connected to the first contact area, a second contact layer having a second contact area for external electrical contacting the radiation-emitting semiconductor chip and a second contact finger structure connected to the second contact area, wherein the first contact finger structure and the second contact finger structure overlap in places in plan view of the radiation-emitting semiconductor chip, a current distribution layer electrically conductively connected to the first contact layer, a connection layer electrically conductively connected to the first contact layer via the current distribution layer and an insulation layer containing a dielectric material, wherein the insulation layer is arranged in places between the connection layer and the current distribution layer. | 2022-01-06 |
20220005975 | DISPLAY DEVICE - A display device includes a substrate and a pixel on the substrate. The pixel has an alignment area, and the alignment area has a first alignment area, a second alignment area spaced apart from the first alignment area in a first direction, and a non-alignment area extending around a periphery of the alignment area. The pixel includes: a first electrode and a second electrode extending in the first direction across the alignment area and being spaced apart from each other; a first bank in the non-alignment area and extending along a boundary of the pixel; an alignment control layer including a first alignment control pattern, the first alignment control pattern being spaced apart from the first bank in the non-alignment area between the first alignment area and the second alignment area; and a first light emitting element between the first electrode and the second electrode in the first alignment area. | 2022-01-06 |
20220005976 | MICRO LED DEVICE AND METHOD FOR MANUFACTURING SAME - A micro-LED device of the present disclosure includes a crystal growth substrate ( | 2022-01-06 |
20220005977 | METHOD FOR MANUFACTURING DISPLAY PANEL, DISPLAY PANEL, AND DISPLAY APPARATUS - A method for manufacturing a display panel ( | 2022-01-06 |
20220005978 | LIGHT-EMITTING DEVICE AND DISPLAY DEVICE HAVING SAME - A light emitting device may include: an emission area; an insulating pattern in the emission area, the insulating pattern including at least one recess and a protrusion around the recess; a first electrode on the insulating pattern and overlapping a first area of the recess and the protrusion in a periphery of the first area; a second electrode on the insulating pattern and spaced from the first electrode in a first direction, the second electrode overlapping a second area of the recess and the protrusion in a periphery of the second area; and a light emitting diode in the recess and electrically connected between the first electrode and the second electrode. | 2022-01-06 |
20220005979 | DISPLAY DEVICE - A display device includes a plurality of pixels, each of the plurality of pixels including an emission area, a first electrode and a second electrode that are disposed in the emission area to be spaced apart from each other, and a plurality of light emitting elements that are electrically connected between the first and second electrodes, and a bank disposed between the emission area of each of the plurality of pixels to enclose the emission area. The first electrode includes a first electrode part disposed in the emission area to be adjacent to a first side of the second electrode, a second electrode part disposed in the emission area to be adjacent to a second side of the second electrode, and a third electrode part electrically connecting the first and second electrode parts and disposed in the emission area to be adjacent to a third side of the second electrode. | 2022-01-06 |
20220005980 | MICRO-LEDS WITH ULTRA-LOW LEAKAGE CURRENT - Micro-scale light emitting diodes (micro-LEDs) with ultra-low leakage current results from a sidewall passivation method for the micro-LEDs using a chemical treatment followed by conformal dielectric deposition, which reduces or eliminates sidewall damage and surface recombination, and the passivated micro-LEDs can achieve higher efficiency than micro-LEDs without sidewall treatments. Moreover, the sidewall profile of micro-LEDs can be altered by varying the conditions of chemical treatment. | 2022-01-06 |
20220005981 | OPTOELECTRONIC DEVICE WITH A MARKER AND METHOD OF MANUFACTURING OPTOELECTRONIC DEVICES - A method of manufacturing optoelectronic components includes providing a plurality of optoelectronic semiconductor chips embedded in a carrier layer, wherein a conversion layer is applied to the optoelectronic semiconductor chips and the carrier layer, creating markings in and/or on the conversion layer, and severing the carrier layer to obtain optoelectronic devices, the optoelectronic devices each having at least one of the markings, wherein the at least one marking is at least one recess in the conversion layer. | 2022-01-06 |
20220005982 | WHITE LIGHT SOURCE AND ILLUMINATION APPARATUS FOR LIGHTING IN LITHOGRAPHY PROCESS - The present invention relates to a white light source and illumination apparatus for limiting wavelength of 450 nm or less and, more particularly, to a white light source and illumination apparatus for lighting in a lithography or other process, capable of realizing white light even with the limited wavelength of 450 nm or less light. Disclosed is a white light illumination apparatus for limiting wavelength of 450 nm or less, the apparatus comprising a white light source comprising: a blue light-emitting diode element having an emission peak wavelength of 450-490 nm; and an encapsulation layer which encapsulates the blue light-emitting diode element, wherein in the encapsulation layer, one or more phosphors which realize white light emission along with the blue light-emitting diode element, and a blocking agent which blocks light of wavelength of 450 nm or less are scattered, thus forming a first peak region at a wavelength of 450-490 nm and a second peak region which realizes white light emission in combination with the first peak region and limiting the wavelength of 450 nm or less. | 2022-01-06 |
20220005983 | LIGHT EMITTING DIODE PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE - A light emitting diode package structure and a manufacturing method thereof and a display device are provided. The light emitting diode package structure includes a blue light emitting diode and a phosphor layer. The phosphor layer is disposed on the blue light emitting diode package structure, and the phosphor layer includes an encapsulation layer and a plurality of phosphor powders. The phosphor powders are disposed in the encapsulation layer and consist of green phosphor powders, red phosphor powders, and yellow phosphor powders, in which a weight percentage of the yellow phosphor powders ranges from 1% to 10%. | 2022-01-06 |
20220005984 | LED PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME, AND LED DISPLAY - An LED package structure and a method of manufacturing the same, and an LED display are provided. The method of manufacturing the LED package structure includes: providing a plurality of LED chips, each of the LED chips having two exposed conductive pads; forming a plurality of quantum dot material layers for respectively enclosing the LED chips; and respectively forming a plurality of blue light scattering material layers on the quantum dot material layers. The LED package structure includes the LED chip that has the two exposed conductive pads, the quantum dot material layer for enclosing the LED chip, and the blue light scattering material layer that is disposed on the quantum dot material layer. | 2022-01-06 |
20220005985 | DISPLAY DEVICE - A display device includes a first light emitting element which overlaps a first light emitting region, and emits first color light, a first wavelength conversion pattern which overlaps the first light emitting element, and wavelength-converts the first color light into a second color light, and a first color filter which overlaps the first wavelength conversion pattern, and includes a first light absorbing colorant and a colorant of the second color, where the colorant of the second color blocks transmission of the first color light and transmits the second color light, where the colorant of the second color transmits light in a first overlapping wavelength range in which a first emission spectrum of the first wavelength conversion pattern overlaps a first light absorption spectrum of the first wavelength conversion pattern, and where the first light absorbing colorant absorbs the light in the first overlapping wavelength range. | 2022-01-06 |
20220005986 | METALLIC STRUCTURE FOR OPTICAL SEMICONDUCTOR DEVICE, METHOD FOR PRODUCING THE SAME, AND OPTICAL SEMICONDUCTOR DEVICE USING THE SAME - A metallic structure for an optical semiconductor device including a conductive base body having disposed thereon metallic layers in the following order: a nickel or nickel alloy plated layer, a gold or gold alloy plated layer, and an indium or indium alloy plated layer, wherein the indium or indium alloy plated layer has a thickness in a range of 0.002 μm or more and 0.3 μm or less. | 2022-01-06 |
20220005987 | LENS ARRANGEMENTS FOR LIGHT-EMITTING DIODE PACKAGES - Solid-state lighting devices including light-emitting diodes (LEDs) and lens arrangements for packaged LED devices are disclosed. An LED package may include one or more LED chips on a submount with a lens positioned on the submount to form a cavity. The one or more LED chips may reside in the cavity without direct encapsulation materials that would otherwise contact the one or more LED chips and any corresponding wirebonds. In this manner, the one or more LED chips may be driven with higher drive currents while reducing degradation and mechanical strain effects related to differences in coefficients of thermal expansion with typical encapsulant materials. LED packages may also be configured with one or more apertures that allow air flow between an interior volume of a cavity and an ambient environment outside the LED package to promote heat dissipation at higher drive currents. | 2022-01-06 |
20220005988 | LED DISPLAY SCREEN - An LED display screen, comprising: an LED array, consisting of multiple LED light-emitting units and used for emitting a light; an optical diffusion film, provided at a light exit side of the LED array; a matrix shading frame, comprising multiple hollow shading gratings, the hollow shading gratings corresponding one-to-one to the LED light-emitting units; and a substrate, used for supporting the LED array and the matrix shading frame, where the light emitted by the LED light-emitting units, after running through the hollow shading gratings, is diffused to a viewer side via the optical diffusion film, and the LED light-emitting units emit the light towards the hollow shading gratings. The LED display screen prevents external ambient lights from being shone to optical surfaces of the LED light-emitting units and being reflected thereby, thus increasing the contrast of the LED display screen. | 2022-01-06 |
20220005989 | LIGHT EMITTING DRIVE SUBSTRATE AND MANUFACTURING METHOD THEREOF, LIGHT EMITTING SUBSTRATE AND DISPLAY DEVICE - A light emitting drive substrate, a manufacturing method of the light emitting drive substrate, a light emitting substrate and a display device. The light emitting drive substrate includes a first light-emitting subregion, a second light-emitting subregion, a periphery area, a first power supply wire and a second power supply wire. A resistance between the first end and the second end of the first power supply wire is equal to a resistance between the first end and the second end of the second power supply wire, and a wire length between the first end and the second end of the first power supply wire is not equal to a wire length between the first end and the second end of the second power supply wire. | 2022-01-06 |
20220005990 | BACKPLANE AND GLASS-BASED CIRCUIT BOARD - A backplane and a glass-based circuit board. The backplane includes: a base substrate and a plurality of light-emitting units, arranged in an array on the base substrate. Each of the light-emitting units ( | 2022-01-06 |
20220005991 | LIGHT EMITTING DEVICE STRUCTURE AND METHOD FOR MANUFACTURING SAME - A light emitting element structure may include at least one light emitting element which is disposed on a substrate and spaced apart from each other, and extends in a direction perpendicular to the substrate; an auxiliary layer which is disposed on the substrate, exposes at least a portion of the upper surface of the substrate, and surrounds the outer surface of the light emitting element; a current spreading layer which is disposed on the auxiliary layer and electrically contacts an end of the light emitting element; a first pad which is electrically connected to the end of the light emitting element, disposed on the current spreading layer, and does not to overlap the light emitting element; and a second pad which is electrically connected to another end of the light emitting element disposed on the upper surface of the exposed substrate and spaced apart from the auxiliary layer. | 2022-01-06 |
20220005992 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD FOR LIGHT EMITTING DEVICE - A light emitting device includes: a base including: a first lead including: a first A surface, a first B surface opposite to the first A surface, and a first C surface located between the first A surface and the first B surface and defining at least one first protrusion, a second lead separated from the first lead, and a resin body covering the first C surface and holding the first lead and the second lead; a light emitting element disposed on the first A surface; and a protecting member disposed continuously on at least a portion of the first A surface and in at least a portion of a gap between the first protrusion and the resin body. In a cross-sectional view, the first protrusion extends from a first end portion of the first A surface at a second lead side toward the second lead. | 2022-01-06 |
20220005993 | LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A light-emitting device includes a lead frame having a first surface on which a patterned conductive layer is provided, and a light-emitting element. The light-emitting element includes an insulating substrate formed on the first surface, a plurality of light-emitting units formed on the insulating substrate, at least one first electrode, at least one second electrode and at least a pair of bonding wires. The first and second electrodes are respectively placed in electrical connection with a first one and a second one of the light-emitting units, and are disposed outward of the light-emitting units. Each of the pair of bonding wires is disposed to electrically connect a respective one of the first and second electrodes to the patterned conductive layer. | 2022-01-06 |
20220005994 | DISPLAY DEVICE - According to one embodiment, a display device includes a substrate, a pixel electrode disposed on the substrate, a light emitting element mounted on the pixel electrode, a drive transistor configured to control a current supplied to the light emitting element through the pixel electrode, and a conductive layer formed between the pixel electrode and the drive transistor so as to at least partially overlap with the pixel electrode in a planar view. The conductive layer does not overlap with a region of the pixel electrode on which the light emitting element is mounted in a planar view. | 2022-01-06 |
20220005995 | LIGHT-EMITTING DEVICE WITH ELECTRIC POWER GENERATION FUNCTION, LIGHTING DEVICE, AND DISPLAY DEVICE - A light-emitting device with an electric power generation function includes a thermal conductive LED board that includes a thermal conductive base having a mounting surface and an open surface, and a board wiring provided on the mounting surface. An LED element is connected with the board wiring. A thermoelectric element is electrically insulated from the thermal conductive base, and thermally coupled with the thermal conductive base. The thermoelectric element includes a casing unit having a housing unit, and includes, in the housing unit, a first electrode unit, a second electrode unit having a work function different from a work function of the first electrode unit, and a middle unit including nanoparticles having a work function between the work function of the first electrode unit and the work function of the second electrode unit. The casing unit is provided on the open surface of the thermal conductive base. | 2022-01-06 |
20220005996 | THERMOELECTRIC POWER GENERATION MODULE - A thermoelectric power generation module includes two substrates, a thermoelectric conversion element, a sealing portion sealing peripheral edges of upper and lower surfaces, a first solder between the upper surface and the sealing portion, and a second solder between the lower surface and the sealing portion. At least one of outer and inner edges of the first solder or the sealing portion is deviated from the first solder or the sealing portion. At least one of outer and inner edges of the second solder or the sealing portion is deviated from the second solder or the sealing portion. At least one of the outer and inner edges of the first solder has a fillet shape between the upper surface and the sealing portion. At least one of the outer and inner edges of the second solder has a fillet shape between the lower surface and the sealing portion. | 2022-01-06 |
20220005997 | THERMOELECTRIC GENERATION MODULE - A thermoelectric generation module includes a first substrate and a second substrate, a plurality of first electrodes and second electrodes that are arranged on the first substrate and the second substrate, a thermoelectric conversion element arranged between the first electrode and the second electrode, and a terminal pin connected to the second electrode. The second substrate includes an insulator layer made of an electrical insulating material, a through-hole that penetrates the insulator layer for insertion of the terminal pin, and an annular metal layer arranged at a peripheral portion of the through-hole. A space between the terminal pin and the through-hole is sealed by solder. | 2022-01-06 |
20220005998 | SUPERCONDUCTING BILAYERS OF TWO-DIMENSIONAL MATERIALS WITH INTEGRATED JOSEPHSON JUNCTIONS - Josephson junctions (JJ) based on bilayers of azimuthally misaligned two-dimensional materials having superconducting states are provided. Also provided are electronic devices and circuits incorporating the JJs as active components and methods of using the electronic devices and circuits. The JJs are formed from bilayers composed of azimuthally misaligned two-dimensional materials having a first superconducting segment and a second superconducting segment separated by a weak-link region that is integrated into the bilayer. | 2022-01-06 |
20220005999 | AMORPHOUS SUPERCONDUCTING ALLOYS FOR SUPERCONDUCTING CIRCUITS - Techniques facilitating formation of amorphous superconducting alloys for superconducting circuits are provided. A device can comprise one or more superconducting components that comprise an amorphous superconducting alloy comprising two or more elements. At least one element of the two or more elements is a superconducting element. | 2022-01-06 |
20220006000 | ELECTRICAL COMPONENT - The present invention relates to an electrical component for a microelectromechanical systems (MEMS) device, in particular, but not limited to, an electromechanical actuator. In one aspect, the present invention provides an insulated electrical component for a microelectromechanical systems device comprising: i) a substrate layer comprising first and second sides spaced apart in a thickness direction; ii) one or more electrical elements arranged over the first side of the substrate layer, wherein each of the one or more electrical elements comprises: a) a ceramic member; and b) first and second electrodes disposed adjacent the ceramic member such that a potential difference may be established between the first and second electrodes and through the ceramic member during operation; iii) a continuous insulating layer, or laminate of insulating layers, arranged to overlie each of the one or more electrical elements arranged on the first side of the substrate layer; and iv) a passivation layer, or laminate of multiple passivation layers, disposed adjacent to, and at least partially overlying, each of the one or more electrical elements so as to provide electrical passivation between the first and second electrodes of each of the one or more electrical elements; wherein: a) the passivation layer, or at least an innermost layer of the laminate of multiple passivation layers which is disposed adjacent each of the one or more underlying electrical elements, is discontinuous; and/or b) the laminate of multiple passivation layers is recessed at a side which faces away from each of the underlying electrical elements, wherein a recess is provided in a region overlying each of the one or more electrical elements, such that the laminate of passivation layers is thinner in a thickness direction across the recess compared to other non-recessed regions of the laminate of passivation layers. | 2022-01-06 |
20220006001 | ELECTRICAL COMPONENT - The present invention relates to an electrical component for a microelectromechanical systems (MEMS) device, in particular, but not limited to, an electromechanical actuator. In one aspect, the present invention provides an electrical component for a microelectromechanical systems device comprising: i) a substrate layer; ii) a plurality of adjacent electrical elements arranged over the substrate layer, where each electrical element is separated from a neighbouring electrical element by an intermediate region, each of the plurality of electrical elements comprising: a) a ceramic member; and b) first and second electrodes disposed adjacent the ceramic member such that a potential difference may be established between the first and second electrodes and through the ceramic member during operation; iii) a passivation layer, or a laminate of multiple passivation layers, at least partially overlying each of the plurality of electrical elements so as to provide electrical passivation between the first and second electrodes of each of the plurality of electrical elements; wherein the passivation layer, or at least an innermost layer of the laminate of passivation layers which is disposed adjacent each underlying electrical element, is discontinuous over at least one intermediate region between neighbouring electrical elements of the electrical component. | 2022-01-06 |
20220006002 | METHODS FOR MANUFACTURING ULTRASOUND TRANSDUCERS AND OTHER COMPONENTS - The disclosed technology features methods for the manufacture of electrical components such as ultrasound transducers. In particular, the disclosed technology provides methods of patterning electrodes, e.g. in the connection of an ultrasound transducer to an electrical circuit; methods of depositing metal on surfaces; and methods of making integrated matching layers for an ultrasound transducer. The disclosed technology also features ultrasound transducers produced by the methods described herein. | 2022-01-06 |
20220006003 | Flexible Piezoceramic Composites and Method for Fabricating Thereof - The present invention provides a flexible piezoelectric composite including a three-dimensional interconnected piezoelectric ceramic framework based on a porous organic template with sufficient stiffness and infiltrated with a flexible polymer matrix. A method for fabricating the flexible piezoelectric composition is also described herein. | 2022-01-06 |
20220006004 | MAGNETIC RECORDING ARRAY, NEUROMORPHIC DEVICE, AND METHOD OF CONTROLLING MAGNETIC RECORDING ARRAY - A magnetic recording array according to the present embodiment includes a plurality of spin elements, a first reference cell, and a second reference cell, wherein the plurality of spin elements, the first reference cell, and the second reference cell each have a wiring and a stacked body including a first ferromagnetic layer stacked on the wiring, wherein the electrical resistance of the wiring of the first reference cell is higher than the electrical resistance of the wiring of each spin element, and wherein the electrical resistance of the wiring of the second reference cell is lower than the electrical resistance of the wiring of each spin element. | 2022-01-06 |
20220006005 | Sputter Deposited Crystalline Ordered Topological Insulator/Ferromagnet (TI/FM) Thin Film Heterostructures for Spintronics Applications - A sputter growth method for a crystalline ordered topological insulator (TI) material on an amorphous substrate, which is possible to use at a CMOS-compatible temperature. The process can be integrated into CMOS fabrication processes for Spin Orbit Torque (SOT) devices. The resulting material can include a thin film crystalline ordered TI layer, sputter deposited on an amorphous substrate, and an adjacent ferromagnetic (FM) layer in which spin-orbit torque is provided by the TI layer, for example to cause switching in magnetic states in a magnetic memory device. | 2022-01-06 |
20220006006 | SPIN CURRENT MAGNETIZATION REVERSAL-TYPE MAGNETORESISTIVE EFFECT ELEMENT AND METHOD FOR PRODUCING SPIN CURRENT MAGNETIZATION REVERSAL-TYPE MAGNETORESISTIVE EFFECT ELEMENT - A spin current magnetization rotational magnetoresistance effect element includes a magnetoresistance effect element including a first ferromagnetic metal layer in which a direction of magnetization is fixed, a second ferromagnetic metal layer configured for a direction of magnetization to be changed, and a nonmagnetic layer provided between the first ferromagnetic metal layer and the second ferromagnetic metal layer and a spin-orbit torque wiring extending in a first direction intersecting a lamination direction of the magnetoresistance effect element and joined to the second ferromagnetic metal layer. Furthermore, in the spin current magnetization rotational magnetoresistance effect element, the spin-orbit torque wiring containing a pure spin current generation part made of a material that generates a pure spin current and a low resistance part made of a material having electric resistance lower than electrical resistance of the pure spin current generation part. | 2022-01-06 |
20220006007 | MAGNETORESISTANCE EFFECT ELEMENT - A magnetoresistance effect element includes: a first ferromagnetic layer; a second ferromagnetic layer; and a non-magnetic layer provided between the first ferromagnetic layer and the second ferromagnetic layer, wherein at least one of the first ferromagnetic layer and the second ferromagnetic layer includes a first layer and a second layer in order from the side closer to the non-magnetic layer, the first layer contains a crystallized Co-based Heusler alloy, at least a part of the second layer is crystallized, the second layer contains a ferromagnetic element, boron element and an additive element, and the additive element is any element selected from a group consisting of Ti, V, Cr, Cu, Zn, Zr, Mo, Ru, Pd, Ta, W, Ir, Pt, and Au. | 2022-01-06 |
20220006008 | LOW CURRENT RRAM-BASED CROSSBAR ARRAY CIRCUITS IMPLEMENTED WITH INTERFACE ENGINEERING TECHNOLOGIES - Interface engineering technologies relating to low current RRAM-based crossbar array circuits are disclosed. An apparatus, in some implementations, includes: a substrate; a bottom electrode formed on the substrate; a first geometric confining layer formed on the bottom electrode. The first geometric confining layer comprises a first plurality of pin-holes. The apparatus further comprises a base oxide layer formed on the first geometric confining layer and connected to a first top surface of the bottom electrode via the first pin-holes; and a top electrode formed on the base oxide layer. The base oxide layer comprises one of: TaO | 2022-01-06 |
20220006009 | RESISTIVE MEMORY WITH EMBEDDED METAL OXIDE FIN FOR GRADUAL SWITCHING - A method is presented for enabling heat dissipation in resistive random access memory (RRAM) devices. The method includes forming a first thermal conducting layer over a bottom electrode, depositing a metal oxide liner over the first thermal conducting layer, forming a second thermal conducting layer over the metal oxide liner, recessing the second thermal conducting layer to expose the first thermal conducting layer, and forming a top electrode in direct contact with the first and second thermal conducting layers. | 2022-01-06 |
20220006010 | METHOD AND APPARATUS FOR MANUFACTURING FLEXIBLE LIGHT EMITTING DEVICE - According to a flexible light-emitting device production method of the present disclosure, after an intermediate region ( | 2022-01-06 |
20220006011 | METHOD OF MANUFACTURING DISPLAY PANEL AND METHOD OF MANUFACTURING FUNCTIONAL LAYER THEREOF - The disclosure provides a method of manufacturing a display panel and a method of manufacturing a functional layer thereof. The method of manufacturing the functional layer includes following steps: forming an ink layer on a display area of a substrate by inkjet printing, wherein the ink layer includes a solute and a solvent configured to dissolve the solute, different positions of the ink layer have same amount of the solute, and an amount of the solvent in a periphery of the ink layer is greater than an amount of the solvent in a middle portion of the ink layer; and evaporating the solvent in the ink layer to form the functional layer with uniform thickness. | 2022-01-06 |