01st week of 2016 patent applcation highlights part 57 |
Patent application number | Title | Published |
20160005611 | Method for manufacturing semiconductor device - The invention relates to a method for forming a uniform silicide film using a crystalline semiconductor film in which orientation of crystal planes is controlled, and a method for manufacturing a thin film transistor with less variation in electric characteristics, which is formed over an insulating substrate using the silicide film. A semiconductor film over which a cap film is formed is irradiated with a laser to be crystallized under the predetermined condition, so that a crystalline semiconductor film including large grain crystals in which orientation of crystal planes is controlled in one direction is formed. The crystalline semiconductor film is used for silicide, whereby a uniform silicide film can be formed. | 2016-01-07 |
20160005612 | Silicon Dry Etching Method - A dry etching method according to the present invention is for etching a silicon layer as a processing target in a processing room, characterized by supplying an iodine heptafluoride-containing etching gas from a gas supply source at a supply pressure of 66 kPa to 0.5 MPa, evacuating the processing room to an internal pressure lower than the supply pressure of the etching gas and, while maintaining the etching gas at the supply pressure, introducing the etching gas into the evacuated processing room so as to etch the silicon layer by the etching gas. It is possible by this dry etching method to etch the silicon upon adiabatic expansion of the etching gas under mild pressure conditions, with no fear of equipment load and equipment cost increase, and achieve good uniformity of in-plane etching amount distribution. | 2016-01-07 |
20160005613 | PROCESS FOR TREATING A STRUCTURE - The disclosure relates to a process for treating a structure, the structure comprising, from its back side to its front side, a carrier substrate, an insulating layer and a useful layer, the useful layer having a free surface, the structure being placed in an atmosphere containing chemical species, the chemical species being capable of reacting chemically with the useful layer. This treatment process is noteworthy in that the useful layer is heated by a pulsed laser beam, the beam sweeping the free surface, the wavelength of the beam differing by, at most, plus or minus 15 nm from a central wavelength, the central wavelength being chosen so that the sensitivity of the reflectivity of the structure relative to the insulating layer is zero. | 2016-01-07 |
20160005614 | Spacer Etching Process for Integrated Circuit Design - A method includes forming a first material layer on a substrate and performing a first patterning process using a first layout to form a first plurality of trenches in the first material layer. The method further includes performing a second patterning process using a second layout to form a second plurality of trenches in the first material layer, wherein the second layout a cut pattern for the first layout. The method further includes forming spacer features on sidewalls of both the first and second pluralities of trenches, wherein the spacer features have a thickness and the cut pattern corresponds to a first trench of the second plurality whose width is less than twice the thickness of the spacer features. The method further includes removing the first material layer; forming a second material layer on the substrate and within openings defined by the spacer features; and removing the spacer features. | 2016-01-07 |
20160005615 | METHOD OF FORMING PATTERNS OF SEMICONDUCTOR DEVICE - A method of forming patterns of a semiconductor device includes forming a material film on a substrate, forming a hard mask on the material film, forming a first mold mask pattern and a second mold mask pattern on the hard mask, forming a pair of first spacers to cover opposite sidewalls of the first mold mask pattern, and a pair of second spacers to cover opposite sidewalls of the second mold mask pattern, forming a first gap and a second gap to expose the hard mask by removing the first mold mask pattern and the second mold mask pattern, the first gap being formed between the pair of first spacers and the second gap being formed between the pair of second spacers, forming a mask pattern on the hard mask to cover the first gap and expose the second gap, forming an auxiliary pattern to cover the second gap, removing the mask pattern; and forming a hard mask pattern by patterning the hard mask using the first spacers, the second spacers and the auxiliary pattern as a mask. | 2016-01-07 |
20160005616 | THIN FILM TRANSISTOR SUBSTRATE, LIQUID CRYSTAL DISPLAY PANEL HAVING THE SAME AND METHOD OF MANUFACTURING THE SAME - A thin film transistor substrate includes a gate electrode arranged on a substrate, a gate insulation layer arranged on the gate electrode, an active pattern arranged on the gate insulation layer, a source electrode overlapping a first end portion of the active pattern, and a drain electrode overlapping a second and opposite end portion of the active pattern. A fluorocarbon-like material is arranged on one or more of surfaces of at least one of the active pattern, the source electrode and the drain electrode, and on a photoresist pattern used in the formation process of the thin film substrate. The fluorocarbon-like material on the photoresist pattern serves to maintain a shape and size of the photoresist pattern during subsequent patterning processes. | 2016-01-07 |
20160005617 | METHOD FOR INTEGRATED CIRCUIT PATTERNING - A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The plurality of lines is removed, thereby providing a patterned first spacer layer over the substrate. The method further includes forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto sidewalls of the patterned first spacer layer, and forming a patterned material layer over the second spacer layer with a second mask. Whereby, the patterned material layer and the second spacer layer collectively define a plurality of trenches. | 2016-01-07 |
20160005618 | COMPLIANT POLISHING PAD AND POLISHING MODULE - A polishing device includes a housing, a flexible base coupled to the housing, and a contact region disposed on a first side of the flexible base, wherein the flexible base expands and contracts based on pressure contained within the housing and a second side of the flexible base to form a contact area on the first side that is less than a surface area of the flexible base. | 2016-01-07 |
20160005619 | SYSTEMS AND METHODS FOR CHEMICAL MECHANICAL PLANARIZATION WITH PHOTO-CURRENT DETECTION - A method includes performing a chemical-mechanical planarization (CMP) on an article, providing a polishing fluid capable of transferring charges to the article, and detecting a current generated in response to the charges transferred to the article. An apparatus that is capable of performing the method and a system that includes the apparatus are also disclosed. | 2016-01-07 |
20160005620 | CONTROL OF O-INGRESS INTO GATE STACK DIELECTRIC LAYER USING OXYGEN PERMEABLE LAYER - A method of manufacturing a semiconductor structure, by depositing a dielectric layer is a dummy gate, or an existing gate structure, prior to the formation of gate spacers. Following the formation of spacers, and in some embodiments replacing a dummy gate with a final gate structure, oxygen is introduced to a gate dielectric through a diffusion process, using the deposited dielectric layer as a diffusion pathway. | 2016-01-07 |
20160005621 | ETCHING METHOD, ETCHING APPARATUS AND STORAGE MEDIUM - A method for etching a silicon oxide film on a target substrate where an etching area is partitioned by pattern layers and stopping the etching before a base layer of the silicon oxide layer is etched is disclosed. The method includes heating the target substrate in a vacuum atmosphere and intermittently supplying, as an etching gas, at least one of a processing gas containing a hydrogen fluoride gas and an ammonia gas in a pre-mixed state and a processing gas containing a compound of nitrogen, hydrogen and fluorine to the target substrate from a gas supply unit multiple times. | 2016-01-07 |
20160005622 | METHOD FOR REDUCING NONUNIFORMITY OF FORWARD VOLTAGE OF SEMICONDUCTOR WAFER - There is provided a method for reducing the nonuniformity of forward voltage Vf of an N-type semiconductor wafer in which density of impurities included in an N-layer is nonuniformly distributed in a plane view of the semiconductor wafer. The method reduces the nonuniformity of forward voltage, by irradiating charged particles to the N-type semiconductor wafer, and generating defects in the N-layer to reduce the nonuniformity of forward voltage. In one aspect of the method, charged particles are irradiated so that a reaching positon in a depth direction or an irradiation density may differ according to the density of impurities in the N-layer in the plane view of the semiconductor wafer. | 2016-01-07 |
20160005623 | METHOD FOR PURIFYING METALLURGICAL SILICON - The present disclosure provides a method for upgrading materials, for example crystalline metallurgical silicon, to remove impurities using microwave processing to induce migration of impurities in the material to one or both of internal surfaces where they are trapped and neutralized or one or more external surfaces followed by trapping of the impurity by binding to gettering agents on the surface with subsequent removal of the impurity and gettering agent. | 2016-01-07 |
20160005624 | METHOD OF FORMING A PATTERN IN A SEMICONDUCTOR DEVICE AND METHOD OF FORMING A GATE USING THE SAME - A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized. | 2016-01-07 |
20160005625 | Hardmask composition and method of forming pattern using the hardmask composition - A hardmask composition includes a first material including one of an aromatic ring-containing monomer and a polymer containing a repeating unit including an aromatic ring-containing monomer, a second material including at least one of a hexagonal boron nitride and a precursor thereof, a chalcogenide-based material and a precursor thereof, and a two-dimensional carbon nanostructure and a precursor thereof, the two-dimensional carbon nanostructure containing about 0.01 atom % to about 40 atom % of oxygen, and a solvent. | 2016-01-07 |
20160005626 | EXPOSED DIE CLIP BOND POWER PACKAGE - In an example embodiment, an integrated circuit (IC) comprises a device die having a top-side surface and an under-side surface, the top-side surface having bond pads connected to active circuit elements, the under-side surface having a conductive surface. A first set of lead frame clips having upper portions and lower portions, are solder-anchored, on the upper portions, to a first set of bond pads; the lower portions are flush with the conductive surface. Wires are bonded to an additional set of bond pads opposite the first set of bond pads and to lower lead frame portions of a second set of lead frame clips opposite the first set of lead frame clips; the lower lead frame portions of the second set of lead frame clips are flush with the conductive surface. The device is encapsulated in a molding compound leaving exposed the conductive surface and underside surfaces of the first and second sets of the lead frame portions. | 2016-01-07 |
20160005627 | ULTRA-THIN POWER TRANSISTOR AND SYNCHRONOUS BUCK CONVERTER HAVING CUSTOMIZED FOOTPRINT - A power field-effect transistor package is fabricated. A leadframe including a flat plate and a coplanar flat strip spaced from the plate is provided. The plate has a first thickness and the strip has a second thickness smaller than the first thickness. A field-effect power transistor chip having a third thickness is provided. A first and second contact pad on one chip side and a third contact pad on the opposite chip side are created. The first pad is attached to the plate and the second pad to the strip. Terminals are concurrently attached to the plate and the strip so that the terminals are coplanar with the third contact pad. The thickness difference between plate and strip and spaces between chip and terminals is filled with an encapsulation compound having a surface coplanar with the plate and the opposite surface coplanar with the third pad and terminals. The chip, leadframe and terminals are integrated into a package having a thickness equal to the sum of the first and third thicknesses. | 2016-01-07 |
20160005628 | WAFER LEVEL PACKAGING METHOD AND INTEGRATED ELECTRONIC PACKAGE - A wafer level packaging method entails providing electronic devices and providing a platform structure having cavities extending through the platform structure. The platform structure is mounted to a temporary support. One or more electronic devices are placed in the cavities with an active side of each electronic device facing the temporary support. The platform structure and the electronic devices are encapsulated in an encapsulation material to produce a panel assembly. Redistribution layers may be formed over the panel assembly, after which the panel assembly may be separated into a plurality of integrated electronic packages. The platform structure may be formed from a semiconductor material, and platform segments within each package provide a fan-out region for conductive interconnects, as well as provide a platform for a metallization layer and/or for forming through silicon vias. | 2016-01-07 |
20160005629 | PACKAGING STRUCTURAL MEMBER - A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate. | 2016-01-07 |
20160005630 | SUBSTRATE TREATING APPARATUS AND METHOD OF TREATING SUBSTRATE - A substrate treating apparatus includes a rotating and holding unit that rotates a substrate, a first supply source that supplies first pure water having a first temperature, a second supply source that supplies second pure water having a second temperature higher than the first temperature, a treatment solution supply unit that supplies a treatment solution to a central section of an upper surface of the substrate, a first supply unit that supplies a first liquid containing the first pure water to a central section of a lower surface of the substrate, a second supply unit that supplies a second liquid containing the second pure water to a peripheral section and an intermediate section of the lower surface, and a heat amount control unit that independently controls an amount of heat to be supplied by the first supply unit and an amount of heat to be supplied by the second supply unit. | 2016-01-07 |
20160005631 | APPARATUS FOR COUPLING A HOT WIRE SOURCE TO A PROCESS CHAMBER - Apparatus for coupling a hot wire source to a process chamber is provided herein. In some embodiments, an apparatus for coupling a hot wire source to a process chamber may include: a housing having an open end and a through hole formed through a top and a bottom of the housing; and a filament assembly configured to be disposed within the housing, the filament assembly having a frame and a plurality of filaments disposed across the frame, wherein the plurality of filaments of the filament assembly are substantially parallel with the top and the bottom of the housing and at least a portion of the plurality of filaments are disposed within the through hole of the housing when the filament assembly is disposed within the housing. | 2016-01-07 |
20160005632 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - According to one embodiment, there is provided a substrate processing apparatus including a processing chamber, a substrate processing unit, and a monitoring unit. A stage is placed in the processing chamber. A substrate is able to be put on the stage. The substrate processing unit is configured to process the substrate inside the processing chamber. The monitoring unit is configured to monitor a mass of the substrate via the stage with performing a correction according to a pressure, in a period when the substrate is being processed by the substrate processing unit. | 2016-01-07 |
20160005633 | HIGH EFFICIENCY BUFFER STOCKER - A high-efficiency buffer stocker is disclosed. The buffer stocker includes an overhead transport track for supporting overhead transport vehicles carrying wafer containers and at least one conveyor system or conveyor belt provided beneath the overhead transport track for receiving the wafer containers from the overhead transport vehicles on the overhead transport track. The buffer stocker is capable of absorbing the excessive flow of wafer containers between a processing tool and a stocker, for example, to facilitate the orderly and efficient flow of wafers between sequential process tools in a semiconductor fabrication facility, for example. | 2016-01-07 |
20160005634 | METHOD OF FABRICATING SEMICONDUCTOR PACKAGE, SEMICONDUCTOR CHIP SUPPORTING CARRIER AND CHIP MOUNTING DEVICE - In fabricating semiconductor packages, a first supporting unit is supported by a supporting substrate with one surface of an adhesive sheet directed upward, the first supporting unit being constituted by attaching the adhesive sheet having an adhesive layer as the one surface thereof and a non-adhesive layer as the other surface thereof to a frame member; semiconductor chips are mounted on the one surface of the adhesive sheet; on the adhesive sheet, a resin portion containing the semiconductor chips is formed by resin-sealing the semiconductor chips; the first supporting unit is removed from the second supporting unit; the resin portion is stripped from the adhesive sheet; external connection members are formed at the semiconductor chips contained in the resin portion; and portions between the respective semiconductor chips contained in the resin portion are cut to obtain individual semiconductor packages. | 2016-01-07 |
20160005635 | ATTACHMENT METHOD - An attachment method including an overlapping step of overlapping a support plate over a substrate under a reduced pressure environment; a temporary fixing step of temporarily fixing the support plate to the substrate; and an attaching step of attaching the support plate to the substrate under a reduced pressure environment. The method further includes, prior to the overlapping step, at least one of a first heating step in which heating is performed under an atmospheric pressure environment and a second heating step in which heating is performed under a reduced pressure environment. | 2016-01-07 |
20160005636 | SUCTION DEVICE, CARRY-IN METHOD, CARRIER SYSTEM AND EXPOSURE APPARATUS, AND DEVICE MANUFACTURING METHOD - In a carrier system, a chuck unit is used to hold a placed wafer from above, and vertical-motion pins use suction to hold the wafer from below. Then, the chuck unit and the vertical-motion pins are subsequently lowered until a bottom surface of the wafer comes into contact with a wafer table. During the lowering, the holding force exerted by the chuck unit and the arrangement of chuck members are optimally adjusted such that, as a result of the restraint of the wafer by the chuck unit and the vertical-motion pins, localized surplus-restraint is imparted to the wafer, and warping does not occur. | 2016-01-07 |
20160005637 | DEVICES FOR METHODOLOGIES RELATED TO WAFER CARRIERS - Disclosed are systems, devices and methodologies for handling wafers in wafer processing operations through use of wafer carriers. In an example situation, a wafer carrier can be configured as a plate to allow bonding of a wafer thereto to provide support for the wafer during some processing operations. Upon completion of such operations, the processed wafer can be separated from the support plate so as to allow further processing. Various devices and methodologies related to such wafer carriers for efficient handling of wafers are disclosed. | 2016-01-07 |
20160005638 | SUBSTRATE TRANSFER ROBOT END EFFECTOR - Embodiments of apparatus for supporting a substrate are disclosed herein. In some embodiments, an apparatus for supporting a substrate includes a support member; and a plurality of substrate contact elements protruding from the support member, wherein each of the plurality of substrate contact elements includes: a first contact surface to support a substrate when placed thereon; and a second contact surface extending from the first contact surface, wherein the second contact surface is adjacent a periphery of the substrate to prevent radial movement of the substrate, wherein the first contact surface is at a first angle with respect to the support member and the second contact surface is at a second angle with respect to the support member, and wherein the first angle is between about 3 degrees and 5 degrees. | 2016-01-07 |
20160005639 | SAMPLE HOLDER - A sample holder includes a substrate composed of ceramics, having a sample holding surface provided in an upper face thereof; a supporting member composed of metal, an upper face of the supporting member covering a lower face of the substrate; and a joining layer composed of indium or an indium alloy, the substrate and the supporting member being joined to each other via the joining layer. The joining layer has a layer region in at least one of a joining surface to the substrate and a joining surface to the supporting member, a content percentage of indium oxides of the layer region being higher than that of an intermediate region in a thickness direction of the joining layer. | 2016-01-07 |
20160005640 | METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film. | 2016-01-07 |
20160005641 | GAP-FILL METHODS - Provided are gap-fill methods. The methods comprise: (a) providing a semiconductor substrate having a relief image on a surface of the substrate, the relief image comprising a plurality of gaps to be filled, wherein the gaps have a width of 50 nm or less; (b) applying a gap-fill composition over the relief image, wherein the gap-fill composition comprises a first polymer comprising a crosslinkable group, a second polymer comprising a chromophore, wherein the first polymer and the second polymer are different, a crosslinker, an acid catalyst and a solvent, wherein the gap-fill composition is disposed in the gaps; (c) heating the gap-fill composition at a temperature to cause the first polymer to self-crosslink and/or to crosslink with the second polymer to form a crosslinked polymer; (d) forming a photoresist layer over the substrate comprising the crosslinked polymer-filled gaps; (e) patternwise exposing the photoresist layer to activating radiation; and (f) developing the photoresist layer to form a photoresist pattern. The methods find particular applicability in the manufacture of semiconductor devices for the filling of high aspect ratio gaps with an antireflective coating material. | 2016-01-07 |
20160005642 | ISOLATION TRENCH THROUGH BACKSIDE OF SUBSTRATE - Among other things, one or more semiconductor arrangements comprising isolation trenches, and techniques for forming such isolation trenches are provided. A substrate comprises a front side surface and a backside surface. One or more devices are formed over the front side surface. A wet etch is performed to form a tapered portion of an isolation trench. A dry etch is performed to form a non-tapered portion of the isolation trench. Because both the wet etch and the dry etch are performed, etching time is reduced compared to merely using the dry etch due to the wet etch having a relatively faster etch rate than the dry etch. In an embodiment, the isolation trench provides isolation for a current leakage path associated with a device or other material formed over the front side surface. In an embodiment, metal is formed within the isolation trench for backside metallization. | 2016-01-07 |
20160005643 | Handle Substrate, Composite Substrate for Semiconductor, and Semiconductor Circuit Board and Method for Manufacturing the Same - It is provided a handle substrate of a composite substrate for a semiconductor. The handle substrate is composed of a translucent polycrystalline alumina. A purity of alumina of the translucent polycrystalline alumina is 99.9% or higher, an average of a total forward light transmittance of the translucent polycrystalline alumina is 60% or higher in a wavelength range of 200 to 400 nm, and an average of a linear light transmittance of the translucent polycrystalline alumina is 15% or lower in a wavelength range of 200 to 400 nm. | 2016-01-07 |
20160005644 | SURFACE TREATMENT METHOD, SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE - Provided are methods of surface treatment, semiconductor devices and methods of forming the semiconductor device. The methods of forming the semiconductor device include forming a first oxide layer and a second oxide layer on a substrate. The first and second oxide layers are patterned to form a contact hole exposing the substrate. A sidewall of the first oxide layer exposed by the contact hole reacts with HF to form a first reaction layer and a sidewall of the second oxide layer exposed by the contact hole reacts with NH | 2016-01-07 |
20160005645 | METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING A CONDUCTIVE VIA STRUCTURE - A method for fabricating a semiconductor device includes forming a first photo-sensitive layer over a contact pad, wherein the contact pad is on a substrate. The method further includes patterning the first photo-sensitive layer to form a first opening over a portion of the contact pad. The method further includes plating a conductive via in the first opening; and removing the first photo-sensitive layer. The method further includes forming a passivation layer over the substrate, contact pad, and conductive via, and exposing the conductive via by grinding the passivation layer. The method further includes forming a second photo-sensitive layer over the conductive via and passivation layer. The method further includes patterning the second photo-sensitive layer to form a second opening larger than and completely exposing the conductive via. The method further includes plating a conductive pillar in the second opening; and removing the second photo-sensitive layer. | 2016-01-07 |
20160005646 | MAGNETIC TRAP FOR CYLINDRICAL DIAMAGNETIC MATERIALS - A method for self-aligning diamagnetic materials includes contacting first and second magnets together other along a contact line so as to generate a diametric magnetization that is perpendicular to the contact line. A diamagnetic rod is positioned with respect to the first and second magnets to levitate above the contact line of the first and second magnets. | 2016-01-07 |
20160005647 | Contacts for Semiconductor Devices and Methods of Forming Thereof - A method for a method of forming a semiconductor device includes providing a semiconductor substrate having a bottom surface opposite a top surface with circuitry disposed at the top surface. The method further includes forming a first metal layer having a first metal over the bottom surface of the semiconductor substrate. The first metal layer is formed by depositing an adhesion promoter followed by depositing the first metal. | 2016-01-07 |
20160005648 | Method and Apparatus for Back End of Line Semiconductor Device Processing - A method of forming a device may include: forming an opening through a dielectric layer and an underlying etching stop layer to expose a metal line. The method may further include the step of catalytically growing a graphene layer on an exposed surface of the metal line, and depositing an amorphous carbon layer on sidewalls of the opening. The steps of catalytically growing the graphene layer and depositing the amorphous carbon layer may be performed simultaneously. | 2016-01-07 |
20160005649 | SELECTIVE FORMATION OF METALLIC FILMS ON METALLIC SURFACES - Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on copper instead of insulating or dielectric materials. In some embodiments, a first precursor forms a layer on the first surface and is subsequently reacted or converted to form a metallic layer. The deposition temperature may be selected such that a selectivity of above about 50% or even about 90% is achieved. | 2016-01-07 |
20160005650 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The method includes forming a gate structure over a substrate and forming source and drain regions adjacent to the gate structure. The method also includes forming a first ILD layer surrounding the gate structure over the source and drain regions and forming a contact modulation structure over the gate structure. The method also includes etching the first ILD layer and the contact modulation structure to form a first contact trench over the source and drain regions and a second contact trench over the gate structure. The method further includes forming a first contact in the first contact trench and a second contact in the second contact trench. In addition, the first ILD layer has a first etching rate and the contact modulation structure has a second etching rate that is less than the first etching rate. | 2016-01-07 |
20160005651 | WORKPIECE PROCESSING METHOD - Disclosed is a method of processing a workpiece so as to form an opening that extends from an oxide region to a base layer through a portion between the raised regions. The method includes: (1) a step of forming an opening in the oxide region to expose a second section between the raised regions; and (2) a step of etching a residue made of silicon oxide and existing within the opening and a second section. In the second step, a denatured region is formed by exposing the workpiece to plasma of a mixed gas including a hydrogen-containing gas and NF | 2016-01-07 |
20160005652 | INSERTABLE APERTURE MOLDING - Top and bottom ferrous carrier plates have a plurality of pairs of mating window cavities. Pairs of mating nonferrous pre-molded inserts with mating mold cavities snap into mating window cavities with a rubberized retainer ring therebetween to create floating mating pre-molded insert molds in multiple material carrier plate assemblies. Liquefied material is dispensed through pot bushings and plungers in each top pre-molded insert. The liquefied material flows though gate openings located in each insert top surface filling the mold cavities. The liquefied material then solidifies to its permanent shape in the mold cavities. | 2016-01-07 |
20160005653 | FLEXIBLE WAFER-LEVEL CHIP-SCALE PACKAGES WITH IMPROVED BOARD-LEVEL RELIABILITY - Consistent with an example embodiment, there is a method for manufacturing integrated circuit (IC) devices from a wafer substrate, the wafer substrate having a front-side surface with active devices and a back-side surface. A temporary covering to the front-side of the wafer substrate is applied. The back-side of the wafer substrate having a pre-grind thickness is ground to a post-grind thickness. To a predetermined thickness, the back-side of the wafer substrate is coated with a resilient coating. The wafer is mounted onto a second carrier tape on its back-side surface. After removing the temporary carrier tape from the front-side of the wafer substrate, the wafer is sawed along active device boundaries and active devices are singulated. | 2016-01-07 |
20160005654 | SYSTEM FOR MANUFACTURING A SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - Provided are a system and method for manufacturing a semiconductor package. The system includes: a laser marker configured to irradiate a first laser beam on a strip to make a mark on the strip; and a laser saw configured to irradiate a second laser beam on the strip to cut the strip into individual semiconductor packages. | 2016-01-07 |
20160005655 | METHOD OF FORMING A SEMICONDUCTOR DIE - In one embodiment, semiconductor die having non-rectangular shapes and die having various different shapes are formed and singulated from a semiconductor wafer. | 2016-01-07 |
20160005656 | Fin Spacer Protected Source and Drain Regions in FinFETs - A method includes forming Shallow Trench Isolation (STI) regions in a semiconductor substrate and a semiconductor strip between the STI regions. The method also include replacing a top portion of the semiconductor strip with a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer has a first germanium percentage higher than a second germanium percentage of the second semiconductor layer. The method also includes recessing the STI regions to form semiconductor fins, forming a gate stack over a middle portion of the semiconductor fin, and forming gate spacers on sidewalls of the gate stack. The method further includes forming fin spacers on sidewalls of an end portion of the semiconductor fin, recessing the end portion of the semiconductor fin, and growing an epitaxial region over the end portion of the semiconductor fin. | 2016-01-07 |
20160005657 | SEMICONDUCTOR STRUCTURE WITH INCREASED SPACE AND VOLUME BETWEEN SHAPED EPITAXIAL STRUCTURES - A semiconductor structure includes a bulk silicon substrate and one or more silicon fins coupled to the bulk silicon substrate. Stress-inducing material(s), such as silicon, are epitaxially grown on the fins into naturally diamond-shaped structures using a controlled selective epitaxial growth. The diamond shaped structures are subjected to annealing at about 750° C. to about 850° C. to increase an area of (100) surface orientation by reshaping the shaped structures from the annealing. Additional epitaxial material is grown on the increased (100) area. Multiple cycles of increasing the area of (100) surface orientation (e.g., by the annealing) and growing additional epitaxial material on the increased area are performed to decrease the width of the shaped structures, increasing the space between them to prevent them from merging, while also increasing their volume. | 2016-01-07 |
20160005658 | METAL GATE STRUCTURE AND METHOD OF MAKING THE SAME - A metal gate structure includes a substrate including a dense region and an iso region. A first metal gate structure is disposed within the dense region, and a second metal gate structure is disposed within the iso region. The first metal gate structure includes a first trench disposed within the dense region, and a first metal layer disposed within the first trench. The second metal gate structure includes a second trench disposed within the iso region, and a second metal layer disposed within the second trench. The height of the second metal layer is greater than the height of the first metal layer. | 2016-01-07 |
20160005659 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Embodiments provide methods of manufacturing a semiconductor device. The method includes forming an interlayer insulating layer on a substrate; forming a plurality of contact holes penetrating the interlayer insulating layer, the plurality of contact holes arranged along a first direction and a second direction perpendicular to the first direction; and forming contacts in the contact holes, each contact hole being formed using a photo mask that is distinct from a photo mask used for forming a contact hole immediately adjacent to each contact hole in the first direction and distinct from a photo mask used for forming a contact hole immediately adjacent to each contact hole in the second direction, and top surfaces of the contacts being at a same level from the substrate. | 2016-01-07 |
20160005660 | High Efficiency FinFET Diode - Disclosed are methods to form a FinFET diode of high efficiency, designed to resolve the degradation problem with a conventional FinFET diode arising from reduced active area, and a method of fabrication. The FinFET diode has a doped substrate, two spaced-apart groups of substantially parallel, equally-spaced, elongated semiconductor fin structures, dielectric layers formed between the two groups and among the fin structures for insulation, a plurality of substantially equal-spaced and parallel elongated gate structures perpendicularly traversing both groups of the fin structures, and two groups of semiconductor strips respectively formed lengthwise upon the two groups of the fin structures. The two groups of semiconductor strips are doped to have opposite conductivity types, p-type and n-type. The FinFET diode further has metal contacts formed upon the semiconductor strips. In an embodiment, the semiconductor strips may be integrally formed with the fin structures by epitaxial growth and in-situ doped. | 2016-01-07 |
20160005661 | LIGHT EXPOSURE CONDITION ANALYSIS METHOD, NONTRANSITORY COMPUTER READABLE MEDIUM STORING A LIGHT EXPOSURE CONDITION ANALYSIS PROGRAM, AND MANUFACTURING METHOD FOR A SEMICONDUCTOR DEVICE - According to one embodiment, a pattern formed through light exposure is observed under two or more different optical conditions, and a focus shift and exposure amount in the light exposure are estimated based on a brightness value of the pattern under each of the optical conditions. | 2016-01-07 |
20160005662 | LOCALIZED STRESS MODULATION FOR OVERLAY AND EPE - Embodiments of the disclosure provide apparatus and methods for localized stress modulation for overlay and edge placement error (EPE) using electron or ion implantation. In one embodiment, a process for correcting overlay error on a substrate generally includes performing a measurement process in a metrology tool on a substrate to obtain a substrate distortion or an overlay error map, determining doping parameters to correct overlay error or substrate distortion based on the overlay error map, and providing a doping recipe to a doping apparatus based on the doping parameters determined to correct substrate distortion or overlay error. Embodiments may also provide performing a doping treatment process on the substrate using the determined doping repair recipe, for example, by comparing the overlay error map or substrate distortion with a database library stored in a computing system. | 2016-01-07 |
20160005663 | EXTENDED CONTACT AREA FOR LEADFRAME STRIP TESTING - A leadframe strip includes a plurality of unit leadframes connected to a periphery of the leadframe strip, each unit leadframe having a die paddle, a plurality of leads and a semiconductor die attached to the die paddle. The leadframe strip is tested by electrically isolating at least the leads from the periphery of the leadframe strip such that at least some of the leads extend uninterrupted beyond a final lead outline of the unit leadframes after electrical isolation from the periphery of the leadframe strip. The semiconductor dies are tested, which includes probing the die paddles and the leads that extend uninterrupted beyond the final lead outline of the unit leadframes after electrical isolation from the periphery of the leadframe strip. The unit leadframes are severed from the leadframe strip along the final lead outline of the unit leadframes after testing the semiconductor dies. | 2016-01-07 |
20160005664 | METHOD FOR MEASURING RECOMBINATION LIFETIME OF SILICON SUBSTRATE - Provided is a method of measuring a recombination lifetime of a silicon substrate, which is capable of evaluating metal contamination and crystal defects in a silicon substrate manufacturing process and a device manufacturing process with high accuracy. The method includes: measuring a recombination lifetime of a silicon substrate after subjecting a surface of the silicon substrate to chemical passivation processing; and performing ultraviolet protection processing of protecting at least the silicon substrate from ultraviolet rays during a period from the chemical passivation processing to a time when the measurement of the recombination lifetime is completed. | 2016-01-07 |
20160005665 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Reading reliability of a code formed in a semiconductor device is improved. | 2016-01-07 |
20160005666 | ENDPOINT BOOSTER SYSTEMS AND METHODS FOR OPTICAL ENDPOINT DETECTION - An endpoint booster transports an optical signal from inside of a plasma etch chamber through a viewport to an optical cable outside of the plasma etch chamber. The optical signal is analyzed to determine an endpoint of a plasma process. The endpoint booster inhibits process byproducts from accumulating on the viewport during the plasma process, which increases the time between chamber cleanings. The reduction in chamber downtime for cleaning increases production throughput. | 2016-01-07 |
20160005667 | SYSTEMS AND METHODS FOR CHEMICAL MECHANICAL PLANARIZATION WITH PHOTOLUMINESCENCE QUENCHING - A method includes performing a chemical-mechanical planarization (CMP) on an article, providing a polishing fluid including luminescent particles capable of generating a fluorescent light in response to a light incident on the article, and detecting an intensity of the fluorescent light. An apparatus that is capable of performing the method and a system that includes the apparatus are also disclosed. | 2016-01-07 |
20160005668 | FLOW METERING FOR DISPENSE MONITORING AND CONTROL - Methods and systems of accurately dispensing a viscous fluid onto a substrate. In an embodiment, a method includes using an electronic flow meter device to produce electrical flow meter output signals and performing a responsive control function in a closed loop manner by adjusting at least one dispensing parameter to correct for a difference between an output data set and a reference data set. In another embodiment, a system includes a control operatively coupled to a gas flow meter device and to a weigh scale allowing for a density of an amount of viscous material to be determined. In another embodiment, a method includes using a control coupled to both a gas flow meter device and a weigh scale and performing a responsive control function in a closed loop manner by adjusting at least one dispensing parameter using gas flow meter output signals and weigh scale output signals. | 2016-01-07 |
20160005669 | METHOD OF FORMING SHALLOW TRENCH ISOLATION STRUCTURE - A method of forming a shallow trench isolation (STI) structure in a substrate includes forming a pad oxide layer over the substrate. The method includes forming a nitride-containing layer over the pad oxide layer, wherein the nitride-containing layer has a first thickness. The method further includes forming the STI structure extending through the nitride-containing layer, into the substrate. The STI structure has a height above a top surface of the pad oxide layer. The method includes establishing a correlation between the first thickness, the height of the STI structure above the top surface of the pad oxide layer, and an offset between the first thickness and the height of the STI structure above the top surface of the pad oxide layer. The method includes calculating the height of the STI structure above the pad oxide layer based on the correlation, and selectively removing a determined thickness of the STI structure. | 2016-01-07 |
20160005670 | SEMICONDUCTOR DEVICE - A semiconductor device includes a supporting plate including a first surface, a second surface opposite to the first surface, and a through hole extending from the first surface to the second surface; and a semiconductor unit fixed to the first surface. The semiconductor unit includes an insulating plate, a circuit plate fixed to a front surface of the insulating plate, a semiconductor chip fixed to the circuit plate, and a protruding metal block fixed to a rear surface of the insulating plate and penetrating through the through hole to extend to the second surface. | 2016-01-07 |
20160005671 | RESIN-SEALED ELECTRONIC CONTROL DEVICE - The present invention is intended to increase the moisture resistance of a resin-sealed electronic control device. The resin-sealed electronic control device includes: a semiconductor chip; a chip capacitor; a chip resistor; a bonding member; a substrate; a case; a heat radiating plate; a glass coating; and a first sealing material. The glass coating directly covers the electronic circuit formed by the element group including: the semiconductor chip; the chip capacitor; and the chip resistor, the bonding member and the substrate, and is sealed by the first sealing material. By being water impermeable, the glass coating prevents water absorption in the vicinity of the element group, and can prevent an increase in the leak current of the semiconductor chip due to water absorption, and an insulation performance drop such as lowered insulation resistance caused by migration within the element group. | 2016-01-07 |
20160005672 | ELECTRONIC PACKAGE AND METHOD OF CONNECTING A FIRST DIE TO A SECOND DIE TO FORM AN ELECTRONIC PACKAGE - Some embodiments relate to an electronic package. The electronic package includes a substrate and a die attached to the substrate. The electronic package further includes an underfill positioned between the die and the substrate due to capillary action. A support surrounds the die. The support provides the same beneficial fillet geometry on all die edges. Therefore, the support provides similar stress reduction on all die edges. Other embodiments relate to method of fabricating an electronic package. The method includes attaching a die to a substrate and inserting an underfill between the die and the substrate using capillary action. The method further includes placing a support around the die such that the support surrounds the die. | 2016-01-07 |
20160005673 | Electronic component and method for dissipating heat from a semiconductor die - In an embodiment, an electronic component includes a dielectric core layer having a thickness, at least one semiconductor die embedded in the dielectric core layer and electrically coupled to at least one contact pad arranged on a first side of the dielectric core layer, and a heat dissipation layer arranged on a second side of the dielectric core layer and thermally coupled to the semiconductor die. The semiconductor die has a thickness that is substantially equal to, or greater than, or equal to the thickness of the dielectric core layer. The heat dissipation layer includes a material with a substantially isotropic thermal conductivity. | 2016-01-07 |
20160005674 | INTEGRATED CIRCUIT ASSEMBLY AND INTEGRATED CIRCUIT PACKAGING STRUCTURE - An integrated circuit packaging structure includes a chip, an electrical bump, a heat dissipation bump, a lead frame, and a sealant. The chip includes an active surface and an electronic component that is formed by using a semiconductor process. The electrical bump is electrically connected to the electronic component through the active surface. The heat dissipation bump is connected to the active surface. The lead frame is electrically connected to the electrical bump. The sealant covers the chip, the lead frame, and the electrical bump, wherein the heat dissipation bump and a part of the lead frame are exposed without being covered. The height of the heat dissipation bump relative to the active surface is unequal to that of the electrical bump relative to the active surface. | 2016-01-07 |
20160005675 | Double sided cooling chip package and method of manufacturing the same - A double sided cooling chip package is provided, wherein the package comprises a first heat sink; a second heat sink; a stacked chip arrangement comprising a first electronic chip, a second electronic chip and an interfacing substrate arranged between the first electronic chip and the second electronic chip and comprising electric circuitry on at least one main surface, wherein one of the first electronic chip and the second electronic chip is electrically connected to the electric circuitry of the interfacing substrate; and wherein the first electronic chip is attached to the first heat sink and the second electronic chip is attached to the second heat sink. | 2016-01-07 |
20160005676 | SEMICONDUCTOR DEVICE - A semiconductor device | 2016-01-07 |
20160005677 | THERMALLY CONDUCTIVE SHEET, CURED PRODUCT THEREOF, AND SEMICONDUCTOR DEVICE - A thermally conductive sheet includes a thermosetting resin and an inorganic filler material. When a pore diameter distribution is measured through mercury intrusion technique for the inorganic filler material, a pore diameter distribution curve of the inorganic filler material has a first maximum value in the range where the pore diameter R is greater than or equal to 0.1 μm and less than or equal to 5.0 μm, and a second maximum value in the range where the pore diameter R is greater than or equal to 10 μm and less than or equal to 30 μm, and the difference between a second pore diameter at the second maximum value and a first pore diameter at the first maximum value is greater than or equal to 9.9 μm and less than or equal to 25 μm. | 2016-01-07 |
20160005678 | ELECTRONIC DEVICE COMPRISING AN IMPROVED LEAD FRAME - An electronic device includes a chip and a support element which supports the chip. Leads are provided to be electrically coupled to at least one terminal of the chip. A coupling element is mounted to a free region of the support element that is not occupied by the chip. The coupling element includes a conductive portion electrically connected to at least one lead and to the at least one terminal of the chip to obtain an electrical coupling. | 2016-01-07 |
20160005679 | EXPOSED DIE QUAD FLAT NO-LEADS (QFN) PACKAGE - Consistent with an example embodiment, there is a method for packaging an integrated circuit (IC) device. The method comprises attaching a lead frame to the carrier tape; the lead frame has an array of device positions on the carrier tape and pad landings surround the device positions for making electrical connections to the plurality of active device die. A plurality of active device die are mounted on the carrier tape within the array of device positions; each said active device die has bond pads, each of said active device die has been subjected to back-grinding to a prescribed thickness and has a solderable conductive surface on its underside. On the bond pads, the plurality of active devices are wire bonded to the pad landings on the lead frame. The lead frame and wire bonded active devices are encapsulated, leaving the solderable die backside and lead frame backside exposed. | 2016-01-07 |
20160005680 | Exposed-Heatsink Quad Flat No-Leads (QFN) Package - Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device having enhanced heat dissipation. The method comprises providing a heat sink array having a top-side surface and an under-side surface; the heat sink array has die placement areas on the top-side surface. A plurality of active device die are die bonded onto the die placement areas on the heat sink array. The plurality of active device die are singulated into an individual heat sink device die having a heat sink portion attached to its underside. | 2016-01-07 |
20160005681 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes a frame formed of a metal and including multiple grooves formed in a surface, and, a semiconductor chip connected with the surface of the frame. A semiconductor device includes the semiconductor chip, and a base frame formed of copper and bonded to the bottom face of the semiconductor chip. In addition, the semiconductor chip and the base frame are bonded together by surface activation. | 2016-01-07 |
20160005682 | Matrix Lid Heatspreader for Flip Chip Package - A method and apparatus are provided for manufacturing a lead frame based thermally enhanced flip chip package with an exposed heat spreader lid array ( | 2016-01-07 |
20160005683 | PRINTED CIRCUIT BOARD FOR SEMICONDUCTOR PACKAGE - A printed circuit board for a semiconductor package including a printed circuit board body, a plurality of ball lands on one surface of the printed circuit board body, a first plating layer on a portion of each of the ball lands, and a second plating layer on another portion of each of the ball lands may be provided. An upper surface of the first plating layer may be coplanar with an upper surface of the second plating layer. | 2016-01-07 |
20160005684 | Electronic component and method for electrically coupling a semiconductor die to a contact pad - In an embodiment, an electronic component includes a dielectric core layer, one or semiconductor dies comprising a first major surface, a first electrode arranged on the first major surface and a second major surface that opposes the first major surface. One or more slots are arranged within the dielectric core layer adjacent the semiconductor die and a redistribution structure electrically couples the first electrode to a component contact pad arranged adjacent the second major surface of the semiconductor die. The semiconductor die is embedded in the dielectric core layer and a portion of the redistribution structure is arranged on side walls of the slot. | 2016-01-07 |
20160005685 | WIRING SUBSTRATE - A wiring substrate includes a wiring layer. Metal posts are arranged on the wiring layer. The metal posts are used to mount an electronic component. A protective layer covers a surface of the wiring layer on which the metal posts are arranged. The wiring layer includes a seed layer and a metal plating layer. The metal plating layer has a size that is the same as that of the seed layer in a plan view. The metal posts each include an upper end, which projects from the protective layer, and a lower end, which has a width that is the same as that of the upper end or greater. The protective layer includes a fillet for each metal post. The fillet extends toward an upper end surface of the corresponding metal post and contacts a side surface of the corresponding metal posts. | 2016-01-07 |
20160005686 | FOUR D DEVICE PROCESS AND STRUCTURE - A 4D device comprises a 2D multi-core logic and a 3D memory stack connected through the memory stack sidewall using a fine pitch T&J connection. The 3D memory in the stack is thinned from the original wafer thickness to no remaining Si. A tounge and groove device at the memory wafer top and bottom surfaces allows an accurate stack alignment. The memory stack also has micro-channels on the backside to allow fluid cooling. The memory stack is further diced at the fixed clock-cycle distance and is flipped on its side and re-assembled on to a template into a pseudo-wafer format. The top side wall of the assembly is polished and built with BEOL to fan-out and use the T&J fine pitch connection to join to the 2D logic wafer. The other side of the memory stack is polished, fanned-out, and bumped with C4 solder. The invention also comprises a process for manufacturing the device. In another aspect, the invention comprises a 4D process and device for over 50× greater than 2D memory density per die and an ultra high density memory. | 2016-01-07 |
20160005687 | RADIO FREQUENCY POWER DEVICE - An electronic RF power device includes a transistor chip, a device input terminal and a device output terminal. Further, the electronic RF power device includes an output impedance transformation circuit, an output contact clip bonded to the transistor chip and to the output device terminal and at least one bond wire bonded to the output impedance transformation circuit and to the transistor chip. | 2016-01-07 |
20160005688 | SEMICONDUCTOR DEVICE - A semiconductor device of the disclosure comprises: a first wiring disposed on a semiconductor substrate; a first insulating film disposed on the first wiring; a first via disposed in the first insulating film so as to be connected to the first wiring; a second wiring disposed on the first insulating film so as to be connected to the first wiring through the first via; a first organic insulating film disposed on the second wiring; a second via disposed in the first organic insulating film so as to be connected to the second wiring; a third wiring disposed on the first organic insulating film so as to be connected to the second wiring through the second via; and a second organic insulating film disposed on the first organic insulating film. A pad opening portion through which the third wiring is exposed is provided in the second organic insulating film, and the first via, the second via, the second wiring, and the third wiring are made of metal whose main component is copper. | 2016-01-07 |
20160005689 | Interconnect Structure and Method of Forming the Same - An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a low-k (LK) dielectric layer over a substrate; a first conductive feature in the LK dielectric layer, wherein the first conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a first bottom surface contacting the LK dielectric layer; a first dielectric feature along an upper portion of the first sidewall, wherein a length of the first dielectric feature is at least 10 percent less than a length of the first sidewall; and a second dielectric feature along an upper portion of the second sidewall. The interconnect structure may also include a second conductive feature adjacent to the first conductive feature in the LK dielectric layer. | 2016-01-07 |
20160005690 | ELECTRICAL FUSE WITH METAL LINE MIGRATION - An electrical fuse device is disclosed. A circuit apparatus can include the fuse device, a first circuit element and a second circuit element. The fuse includes a first contact that has a first electromigration resistance, a second contact that has a second electromigration resistance and a metal line, which is coupled to the first contact and to the second contact, that has a third electromigration resistance that is lower than the second electromigration resistance. The first circuit element is coupled to the first contact and the second circuit element coupled to the second contact. The fuse is configured to conduct a programming current from the first contact to the second contact through the metal line. Further, the programming current causes the metal line to electromigrate away from the second contact to electrically isolate the second circuit element from the first circuit element. | 2016-01-07 |
20160005691 | Hybrid Copper Structure for Advance Interconnect Usage - The present disclosure relates to a method of forming a BEOL metallization layer that uses different conductive materials (e.g., metals) to fill different size openings in an inter-level dielectric layer, and an associated apparatus. In some embodiments, the present disclosure relates to an integrated chip having a first plurality of metal interconnect structures disposed within a first BEOL metallization layer, which include a first conductive material. The integrated chip also has a second plurality of metal interconnect structures disposed within the first BEOL metallization layer at positions laterally separated from the first plurality of metal interconnect structures. The second plurality of metal interconnect structures have a second conductive material that is different than the first conductive material. By forming different metal interconnect structures on a same BEOL metallization layer using different conductive materials, gap-fill problems in narrow BEOL metal interconnect structures can be mitigated, thereby improving reliability of integrated chips. | 2016-01-07 |
20160005692 | INTERCONNECTS WITH FULLY CLAD LINES - A metallization layer including a fully clad interconnect and a method of forming a fully clad interconnect. An opening is formed in a dielectric layer, wherein the dielectric layer has a surface and the opening includes walls and a bottom. A diffusion barrier layer and an adhesion layer are deposited on the dielectric layer. An interconnect material is deposited on the dielectric layer and reflowed into the opening forming an interconnect. An adhesion capping layer and diffusion barrier capping layer are deposited over the interconnect. The interconnect is surrounded by the adhesion layer and the adhesion capping layer and the adhesion layer and the adhesion capping layer are surrounded by the diffusion barrier layer and the diffusion capping layer. | 2016-01-07 |
20160005693 | Semiconductor Constructions - Some embodiments include a construction having conductive structures spaced from one another by intervening regions. Insulative structures are within the intervening regions. The insulative structures include dielectric spacers and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps. The dielectric capping material is between the dielectric spacers and not over upper surfaces of the dielectric spacers. Some embodiments include a construction having a first conductive structure with an upper surface, and having a plurality of second conductive structures electrically coupled with the upper surface of the first conductive structure and spaced from one another by intervening regions. Air gap/spacer insulative structures are within the intervening regions. The air gap/spacer insulative structures have dielectric spacers along sidewalls of the second conductive structures and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps. | 2016-01-07 |
20160005694 | SEMICONDUCTOR PACKAGE STRUCTURE, ALIGNMENT STRUCTURE, AND ALIGNMENT METHOD - A semiconductor package structure includes a first wafer and a second wafer. The first wafer has a concave portion. The concave portion has a bottom surface and at least one sidewall adjacent to the bottom surface. An obtuse angle is formed between the bottom surface and the sidewall. The second wafer is disposed on the first wafer and has a protruding portion. When the protruding portion enters an opening of the concave portion, the protruding portion slides along the sidewall to the bottom surface, such that the protruding portion is coupled to the concave portion. | 2016-01-07 |
20160005695 | PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A method for fabricating a package structure is provided, which includes the steps of: providing a base portion having at least an electronic element embedded therein and at least a positioning unit formed around a periphery of the electronic element, wherein the positioning unit protrudes from or is flush with a surface of the base portion; and forming at least a circuit layer on the surface of the base portion and the electronic element. The circuit layer is aligned and connected to the electronic element through the positioning unit. | 2016-01-07 |
20160005696 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - One semiconductor device includes a wiring substrate, a semiconductor chip layered on one face of the wiring substrate and having a first face facing the wiring substrate and a second face positioned on a reverse side from the first face, a circuit being formed on at least the second face, a non-circuit-incorporating chip in which a circuit is not formed, the non-circuit-incorporating chip being layered on the second face of the semiconductor chip, and a sealing resin disposed between at least the wiring substrate and the non-circuit-incorporating chip. | 2016-01-07 |
20160005697 | SEMICONDUCTOR CHIP, SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF - Provided are a semiconductor chip, a semiconductor package and a fabricating method thereof, which can reduce or prevent cracks from being generated or propagated due to an external pressure. The semiconductor chip includes a semiconductor substrate including a first region and a second region, a plurality of interlayer insulation layers formed on the semiconductor substrate, a first crack stopper formed in the plurality of interlayer insulation layers of the first region, an interconnector formed in the plurality of interlayer insulation layers of the second region, a pad wire formed on the plurality of interlayer insulation layers, electrically connected to the interconnector in the second region and extending to the first region, a bonding pad on the plurality of interlayer insulation layers of the first region, electrically connected to the pad wire, and a protection layer covering the pad wire and exposing the bonding pad. The first crack stopper is positioned at a lower level than the bonding pad and is formed to completely surround the bonding pad while not overlapping with the bonding pad and not being connected to the pad wire. | 2016-01-07 |
20160005698 | SEMICONDUCTOR PACKAGES HAVING RESIDUAL STRESS LAYERS AND METHODS OF FABRICATING THE SAME - A semiconductor package is provided. The semiconductor includes a lower package and an upper package stacked on the lower package. The lower package includes a package substrate, a semiconductor chip, a mold layer and a residential stress layer. The package substrate has upper and lower surfaces. The semiconductor chip is disposed on the upper surface of the package substrate. The mold layer encapsulates the semiconductor chip. The residual stress layer is disposed on the semiconductor chip. The residual stress layer includes a plastically deformed surface. The residual stress layer has a residual stress to counterbalance warpage of the lower package. | 2016-01-07 |
20160005699 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The method includes the steps of: providing a lead frame, including providing a concaved part in an upper face of a joint part of a die-pad-support lead of a lead frame for setting down a die pad and a tie-bar; bonding a semiconductor chip to a first principal face of the die pad via an adhesive-member layer; then, setting the lead frame between first and second molding dies having first and second cavities respectively so that the first and second cavities are opposed to each other, and the second principal face of the die pad faces toward the second cavity; and forming first and second resin sealed bodies on the sides of the first and second principal faces of the die pad respectively by resin sealing with the first and second molding dies clamping the tie-bar and a part of the lead frame surrounding the tie-bar. | 2016-01-07 |
20160005700 | PROCESSING TECHNIQUES FOR SILICON-BASED TRANSIENT DEVICES - Provided are methods of making a transient electronic device by fabricating one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components supported by a mother substrate. The components may independently comprise a selectively transformable material and, optionally, further have a preselected transience profile. The components are transfer printed, thereby decoupling the component fabrication step from additional processing to provide desired device functionality and transient properties. A substrate layer is provided on top of the components and used to facilitate handling, processing, and/or device functionality. | 2016-01-07 |
20160005701 | CHIP WITH SHELF LIFE - A semiconductor structure including a recess within a silicon substrate of an integrated circuit (IC) chip, wherein the recess is located near a circuit of the IC chip, and a metal layer in a bottom portion of the recess, wherein a portion of the silicon substrate is located below the metal layer in the bottom portion of the recess and above the circuit. | 2016-01-07 |
20160005702 | Fan-Out Package and Methods of Forming Thereof - An embodiment is a package including a molding compound laterally encapsulating a chip with a contact pad. A first dielectric layer is formed overlying the molding compound and the chip and has a first opening exposing the contact pad. A first metallization layer is formed overlying the first dielectric layer, in which the first metallization layer fills the first opening. A second dielectric layer is formed overlying the first metallization layer and the first dielectric layer and has a second opening over the first opening. A second metallization layer is formed overlying the second dielectric layer and formed in the second opening. | 2016-01-07 |
20160005703 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An element electrode is located on a surface of a semiconductor element. A metal film is located on the element electrode and includes an inner region and an outer region located around the inner region. The metal film has an opening that exposes the element electrode between the inner region and the outer region. The element electrode has solder wettability lower than solder wettability of the metal film. An external electrode is solder-bonded to the inner region of the metal film. | 2016-01-07 |
20160005704 | Methods and Apparatus of Packaging Semiconductor Devices - Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface. | 2016-01-07 |
20160005705 | Structure and Method of Batch-Packaging Low Pin Count Embedded Semiconductor Chips - A method for fabricating packaged semiconductor devices in panel format. A flat panel sheet dimensioned for a set of contiguous chips includes a stiff substrate of an insulating plate, and a tape having a surface layer of a first adhesive releasable at elevated temperatures, a core base film, and a bottom layer with a second adhesive attached to the substrate. Attaching a set onto the first adhesive layer, the chip terminals having terminals with metal bumps facing away from the first adhesive layer. Laminating low CTE insulating material to fill gaps between the bumps and to form an insulating frame surrounding the set. Grinding lamination material to expose the bumps. Plasma-cleaning assembly, sputtering uniform metal layer across assembly, optionally plating metal layer, and patterning metal layer to form rerouting traces and extended contact pads. | 2016-01-07 |
20160005706 | SEMICONDUCTOR DEVICES HAVING THROUGH ELECTRODES, METHODS OF MANUFACTURING THE SAME, AND SEMICONDUCTOR PACKAGES INCLUDING THE SAME - A semiconductor device includes a semiconductor layer having a first surface and a second surface, a through electrode penetrating the semiconductor layer and having a protruding portion that protrudes over the second surface of the semiconductor layer, a front-side bump disposed on the first surface of the semiconductor layer and electrically coupled to the through electrode, a passivation pattern including a first insulation pattern that surrounds a sidewall of the protruding portion of the through electrode and extends onto the second surface of the semiconductor layer and a second insulation pattern that covers the first insulation pattern and has an etch selectivity with respect to the first insulation pattern, and a back-side bump covering an end surface of the protruding portion of the through electrode and extending onto the passivation pattern. | 2016-01-07 |
20160005707 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes a package board that includes an circuit pattern and a plurality of contact pads electrically connected to the circuit pattern; a semiconductor chip having a plurality of chip pads; and a bump structure including a plurality of connecting bumps electrically connected with the semiconductor chip and the circuit pattern and a plurality of gap adjusting bumps bonded to the semiconductor chip and shaped into a slender bar between the semiconductor chip and the package board, the gap adjusting bumps spacing the semiconductor chip from the package board such that a gap space, S, is maintained between the package board and the semiconductor chip. A method of fabrication and a memory unit are disclosed. | 2016-01-07 |
20160005708 | SEMICONDUCTOR DEVICE AND METHOD FOR MAKING SEMICONDUCTOR DEVICE - A semiconductor device includes: a substrate including a base member having a main surface and a back surface facing opposite in a thickness direction; a semiconductor element mounted on the main surface of the substrate and having at least one element pad; a wire having a bonding portion bonded to the element pad; and a sealing resin formed on the main surface of the substrate for covering the wire and at least a portion of the semiconductor element. The semiconductor element has an element exposed side surface that faces in a direction crossing the thickness direction of the substrate and is exposed from the sealing resin. | 2016-01-07 |
20160005709 | METHODS OF OPERATING BONDING MACHINES FOR BONDING SEMICONDUCTOR ELEMENTS, AND BONDING MACHINES - A method of operating a bonding machine for bonding semiconductor elements is provided. The method includes the steps of: (a) measuring a time based z-axis height measurement characteristic of a bond head assembly during a model bonding process; (b) determining a z-axis adjustment profile for a subsequent bonding process based on the measured time based z-axis height measurement characteristic; and (c) adjusting a z-axis position of the bond head assembly with a z-axis motion system during the subsequent bonding process using the z-axis adjustment profile. | 2016-01-07 |
20160005710 | METHODS OF ATTACHING ELECTRONIC COMPONENTS - A method of attaching an electronic component to a metal substrate, wherein the electronic component comprises solder provided on an exposed solder region. The method comprising: forming a metal-based compound layer on the substrate; placing the electronic component on the metal substrate such that the solder region is in contact with a contact region of the metal-based compound layer; and heating the solder region such that the contact region of the metal-based compound layer dissolves and the solder region forms an electrical connection between the electronic component and the metal substrate. The metal-based compound layer can have a minimum thickness of 10 nm. | 2016-01-07 |