01st week of 2016 patent applcation highlights part 58 |
Patent application number | Title | Published |
20160005711 | SEMICONDUCTOR CHIP ASSEMBLY AND METHOD FOR MAKING SAME - A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly. | 2016-01-07 |
20160005712 | STRUCTURE AND METHOD OF PACKAGED SEMICONDUCTOR DEVICES WITH BENT-LEAD QFN LEADFRAMES - A method for fabricating a semiconductor device package provides a metallic leadframes with a plurality of device sites. Each site including a pad and a plurality of leads with solderable surfaces. At least one set of leads are aligned in a row and are connected by rails to respective leads of an adjacent site. The leads and rails of the row having a surface in a common plane. The strip with the assembled sites and connecting rails are encapsulated in a packaging material, leaving the common-plane lead and rail surfaces un-encapsulated. Trenches are cut between adjacent sites by removing packaging material until reaching the rails. Thus, creating sidewalls of device packages connected by rails. Device packages are singulated from the strip by severing the connecting rails between adjacent sites in approximate halves, leaving a respective rail half as a straight protrusion attached to each lead. The protrusions are bent at an angle away from the common plane towards the package sidewall. | 2016-01-07 |
20160005713 | THREE DIMENSIONAL STACKED MULTI-CHIP STRUCTURE AND MANUFACTURING METHOD OF THE SAME - A three dimensional stacked multi-chip structure including M chips, a first conductive pillar, and N second conductive pillars is provided. Each chip has a common connection area and a chip-enable area, and includes a substrate and a patterned circuit layer disposed on the substrate. The patterned circuit layer includes an active element, at least one common conductive structure in the common connection area, and N chip-enable conductive structures in the chip-enable area. The first conductive pillar connects the common conductive structure of the M chips. Each second conductive pillar connects one of the N chip-enable conductive structures of the M chips. The chip-conductive areas of the M chips have different conducting states. N is large than 1, M is large than 2, and M is smaller than or equal to 2 | 2016-01-07 |
20160005714 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes a first package having a first package substrate mounted with a lower semiconductor chip, and a second package having a second package substrate mounted with upper semiconductor chips. The second package substrate includes a chip region on which the upper semiconductor chips are mounted, and a connection region provided therearound. The chip region includes a first surface defining a first recess region and a second surface defining a first protruding portion. The upper semiconductor chips are mounted on opposite edges of the second surface and spaced apart from each other to have portions protruding toward the connection region beyond the chip region. | 2016-01-07 |
20160005715 | POWER MANAGEMENT INTEGRATED CIRCUIT (PMIC) INTEGRATION INTO A PROCESSOR PACKAGE - A hybrid package having a processor module disposed on a substrate and an auxiliary module disposed on a patterned lid. The auxiliary module may be a memory module, a power management integrated circuit (PMIC) module, and/or other suitable module, that are located in the package along with the processor module. Having the auxiliary module in the package with the processor module reduces the noise at the solder bump between the processor module and the substrate. Having the auxiliary module in the package with the processor module also allows other modules to be added to the package without increasing the area of the package. | 2016-01-07 |
20160005716 | Semiconductor Package and Method - A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks. | 2016-01-07 |
20160005717 | SEMICONDUCTOR DEVICE WITH FACE-TO-FACE CHIPS ON INTERPOSER AND METHOD OF MANUFACTURING THE SAME - A method of making a semiconductor device with face-to-face chips on interposer includes the step of attaching a chip-on-interposer subassembly on a heat spreader with the chip inserted into a cavity of the heat spreader so that the heat spreader provides mechanical support for the interposer. The heat spreader also provides thermal dissipation, electromagnetic shielding and moisture barrier for the enclosed chip. In the method, a second chip is also electrically coupled to a second surface of the interposer and an optional second heat spreader is attached to the second chip. | 2016-01-07 |
20160005718 | MULTI-DIE SEMICONDUCTOR STRUCTURE WITH INTERMEDIATE VERTICAL SIDE CHIP AND SEMICONDUCTOR PACKAGE FOR SAME - Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (MSD) structure having a first substantially horizontal arrangement of semiconductor dies. A second MSD structure having a second substantially horizontal arrangement of semiconductor dies is also included. An intermediate vertical side chip (i-VSC) is disposed between and electrically coupled to the first and second MSD structures. | 2016-01-07 |
20160005719 | LED LAMP DEVICE HAVING A FLUORESCENT ELEMENT SHAPED FOR UNIFORM LIGHT CONVERSION - An LED lamp device includes a plurality of LED elements separately mounted on a substrate and effective to emit light having a first wavelength. A fluorescent element includes a fluorescent material excitable by light emitted from the LED elements to emit light of a second wavelength, and is arranged to cover each LED element with no gaps provided between the fluorescent element and the substrate. The fluorescent element is shaped in accordance with the positioning of the LED elements and the spaces defined there-between such that a proportion of light of the first wavelength with respect to light of the second wavelength is substantially uniform irrespective of light exit direction. | 2016-01-07 |
20160005720 | Method for Producing an Optoelectronic Device and Optoelectronic Device - A method for producing an optoelectronic device is specified. A housing base body is formed with a self-healing polymer material. A recess is found in the housing base body. The recess is confined by a bottom surface and at least one side wall which are formed at least in places by the plastic material of the base body. An optoelectronic semiconductor chip has a first main surface, a second main surface facing away from the first main surface and at least one side surface connecting the first main surface and the second main surface with each other. The optoelectronic semiconductor chip is placed in the recess, so that the first main surface is brought in contact with the bottom surface and the at least one side surface is brought in contact with the at least one side wall. | 2016-01-07 |
20160005721 | MICRO ASSEMBLED LED DISPLAYS AND LIGHTING ELEMENTS - The disclosed technology provides micro-assembled micro-LED displays and lighting elements using arrays of micro-LEDs that are too small (e.g., micro-LEDs with a width or diameter of 10 μm to 50 μm), numerous, or fragile to assemble by conventional means. The disclosed technology provides for micro-LED displays and lighting elements assembled using micro-transfer printing technology. The micro-LEDs can be prepared on a native substrate and printed to a display substrate (e.g., plastic, metal, glass, or other materials), thereby obviating the manufacture of the micro-LEDs on the display substrate. In certain embodiments, the display substrate is transparent and/or flexible. | 2016-01-07 |
20160005722 | Optoelectronic Semiconductor Component and Method for Producing Same - An optoelectronic semiconductor component includes an optoelectronic semiconductor chip with a first surface and a second surface. The component also includes a protective chip which has a protective diode, a first surface and a second surface. The semiconductor chip and the protective chip are embedded in a molded body. A first electrical contact and a second electrical contact are arranged on the first surface of the semiconductor chip. A third electrical contact and a fourth electrical contact are arranged on the first surface of the protective chip. The first electrical contact is electrically connected to the third electrical contact. In addition, the second electrical contact is electrically connected to the fourth electrical contact. | 2016-01-07 |
20160005723 | LIGHT EMITTING DEVICE PACKAGE AND LIGHT UNIT INCLUDING THE SAME - Disclosed are a light emitting device package. The light emitting device package includes a body having recess; a first lead frame including a first and second portions on a first region of the body; a second lead frame including a third and fourth portions on a second region of the body; a third lead frame between the first and second lead frame. The body has a length of the first direction greater than a width of the second direction, wherein the second portion of the first lead frame extends toward the second lead frame and has a small width, and wherein the fourth portion of the second lead frame extends toward the first lead frame. A first light emitting device is disposed on the first portion of the first lead frame and a second light emitting device is disposed on the third portion of the second lead frame. | 2016-01-07 |
20160005724 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes first, second, and third molded bodies. The first molded body covers a first light emitting element, a part of a lead electrically connected to the first light emitting element, a first light receiving element configured to detect a light emitted from the first light emitting element, and a part of a lead electrically connected to the first light receiving element with a first resin. The second molded body covers a second light emitting element, a part of a lead electrically connected to the second light emitting element, a second light receiving element configured to detect a light emitted from the second light emitting element, and a part of a lead electrically connected to the second light receiving element with the first resin. The third molded body molds the first and the second molded bodies as one body using a second resin. | 2016-01-07 |
20160005725 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes a normally off transistor having a first source, a first drain, a first gate connected to a common gate terminal, and a body diode, a normally on transistor having a second source connected to the first drain, a second drain, and a second gate, a capacitor provided between the common gate terminal and the second gate, a first diode having a first anode connected to between the capacitor and the second gate and a first cathode connected to the first source, and a second diode having a second anode connected to the first source and a second cathode connected to the second drain. | 2016-01-07 |
20160005726 | SYSTEM-IN-PACKAGE - A system-in-package includes a package carrier; a first semiconductor die having a die face and a die edge, the first semiconductor die being assembled face-down to a chip side of the package carrier, wherein a plurality of contact pads are situated on the die face; a second semiconductor die mounted on the package carrier and adjacent to the first semiconductor die; a rewiring laminate structure between the first semiconductor die and the package carrier, the rewiring laminate structure comprising a re-routed metal layer, wherein at least a portion of the re-routed metal layer projects beyond the die edge; and a plurality of copper pillar bumps arranged on the rewiring laminate structure for electrically connecting the first semiconductor die with the package carrier. | 2016-01-07 |
20160005727 | SEMICONDUCTOR DEVICE - This invention can reduce heat that is generated in a first semiconductor chip and transfers to a second semiconductor chip through through-silicon vias. The first semiconductor chip has the first through-silicon vias. Each of the first through-silicon vias is arranged on any of grid points arranged in m rows and n columns (m>n). The first semiconductor chip also has a first circuit formation area. A first circuit is formed in the first circuit formation area. The first circuit performs signal processing while communicating with the second semiconductor chip. In plan view, the first circuit formation area does not overlap with a through-silicon via area that is defined by coupling the outermost grid points arranged in m rows and n columns. In plan view, some of connection terminals are located between the first circuit formation area and the through-silicon via area. | 2016-01-07 |
20160005728 | Integrated System and Method of Making the Integrated System - A system and method of manufacturing a system are disclosed. An embodiment of the system includes a first packaged component comprising a first component and a first redistribution layer (RDL) disposed on a first main surface of the first packaged component, wherein the first RDL includes first pads. The system further includes a second packaged component having a second component disposed at a first main surface of the second packaged component, the first main surface having second pads and a connection layer between the first packaged component and the second packaged component, wherein the connection layer connects a first plurality of the first pads with the second pads. | 2016-01-07 |
20160005729 | RADIO FREQUENCY TRANSISTOR STACK WITH IMPROVED LINEARITY - A RF transistor stack is described. The RF transistor stack comprises a first transistor having a T-gate layout configuration. The first transistor has a body region; a plurality of drain regions; and a plurality of source regions. A second transistor is provided which has a T-gate layout configuration. The second transistor has a body region; a plurality of drain regions; and a plurality of source regions. An interconnect operably couples the source regions of the first transistor with the source regions of the second transistor such that the distortion due to asymmetry in the division of RF voltage between the drain to source and the source to body terminals of first transistor is cancelled by reversing the asymmetry in the division of the RF voltage in the second transistor. | 2016-01-07 |
20160005730 | ESD Protection with Asymmetrical Bipolar-Based Device - An ESD protection device is fabricated in a semiconductor substrate that includes a semiconductor layer having a first conductivity type. A first well implantation procedure implants dopant of a second conductivity type in the semiconductor layer to form inner and outer sinker regions. The inner sinker region is configured to establish a common collector region of first and second bipolar transistor devices. A second well implantation procedure implants dopant of the first conductivity type in the semiconductor layer to form respective base regions of the first and second bipolar transistor devices. Conduction of the first bipolar transistor device is triggered by breakdown between the inner sinker region and the base region of the first bipolar transistor device. Conduction of the second bipolar transistor device is triggered by breakdown between the outer sinker region and the base region of the second bipolar transistor device. | 2016-01-07 |
20160005731 | GATE STRUCTURE WITH HARD MASK STRUCTURE FORMED THEREON AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first capacitor structure. The first capacitor structure includes a fin structure formed over a substrate and a first gate structure formed over the substrate. In addition, a first portion of the first gate structure overlaps with a portion of the fin structure. The first capacitor structure further includes a first hard mask structure formed over the first portion of the first gate structure and a first conductive structure formed on the first hard mask structure over the first portion of the first gate structure. The first capacitor structure further includes a first contact formed on a second portion of the first gate structure. In addition, the first contact is in direct contact with the second portion of the first gate structure. | 2016-01-07 |
20160005732 | BIPOLAR JUNCTION TRANSISTOR STRUCTURE - We disclose a bi-directional bipolar junction transistor (BJT) structure, comprising: a base region of a first conductivity type, wherein said base region constitutes a drift region of said structure; first and second collector/emitter (CE) regions, each of a second conductivity type adjacent opposite ends of said base region; wherein said base region is lightly doped relative to said collector/emitter regions; the structure further comprising: a base connection to said base region, wherein said base connection is within or adjacent to said first collector/emitter region. | 2016-01-07 |
20160005733 | INTEGRATED CIRCUIT PRODUCT WITH A GATE HEIGHT REGISTRATION STRUCTURE - One illustrative device disclosed includes, among other things, first and second active regions that are separated by an isolation region, first and second replacement gate structures positioned above the first and second active regions, respectively, and a gate registration structure positioned above the isolation region, wherein the gate registration structure comprises a layer of insulating material positioned above the isolation region and a polish-stop layer and wherein a first end surface of the first replacement gate structure abuts and engages a first side surface of the gate registration structure and a second end surface of the second replacement gate structure abuts and engages a second side surface of the gate registration structure. | 2016-01-07 |
20160005734 | INTEGRATED CIRCUIT PRODUCT COMPRISED OF MULTIPLE P-TYPE SEMICONDUCTOR DEVICES WITH DIFFERENT THRESHOLD VOLTAGES - Disclosed is an integrated circuit product comprised of a semiconductor substrate with a first PMOS active region and a second PMOS active region, of which only the second PMOS active region has a silicon germanium layer formed thereon, a first PMOS device formed in and above the first PMOS active region, the first PMOS device having a first gate structure, and a second PMOS device formed in and above the second PMOS active region, the second PMOS device having a second gate structure disposed on the silicon germanium layer. | 2016-01-07 |
20160005735 | PROTECTION OF SEMICONDUCTOR-OXIDE-CONTAINING GATE DIELECTRIC DURING REPLACEMENT GATE FORMATION - Semiconductor-oxide-containing gate dielectrics can be formed on surfaces of semiconductor fins prior to formation of a disposable gate structure. A high dielectric constant (high-k) dielectric spacer can be formed to protect each semiconductor-oxide-containing gate dielectric. Formation of the high-k dielectric spacers may be performed after formation of gate cavities by removal of disposable gate structures, or prior to formation of disposable gate structures. The high-k dielectric spacers can be used as protective layers during an anisotropic etch that vertically extends the gate cavity, and can be removed after vertical extension of the gate cavities. A subset of the semiconductor-oxide-containing gate dielectrics can be removed for formation of high-k gate dielectrics for first type devices, while another subset of the semiconductor-oxide-containing gate dielectrics can be employed as gate dielectrics for second type devices. The vertical extension of the gate cavities increases channel widths in the fin field effect transistors. | 2016-01-07 |
20160005736 | INGAAS FINFET ON PATTERNED SILICON SUBSTRATE WITH INP AS A BUFFER LAYER - A method for manufacturing a semiconductor device includes providing a substrate having an array of cavities. Each of the cavities has a plurality of lateral sides, and each lateral side has a lateral direction matching a lateral crystal plane of the substrate. The method also includes forming a buffer layer on the substrate and filling the cavities, and forming a fin-type channel layer on the buffer layer. Because the independently grown crystals in the cavities have a lateral direction in line with the direction of the lateral crystal plane, the dislocation defect density is significantly reduced, thereby greatly improving the device performance. | 2016-01-07 |
20160005737 | TRANSISTOR DEVICE AND A METHOD OF MANUFACTURING SAME - A transistor device is provided that includes a substrate, a first channel region formed in a first portion of the substrate and being doped with a dopant of a first type of conductivity, a second channel region formed in a second portion of the substrate and being doped with a dopant of a second type of conductivity, a gate insulating layer formed on the first channel region and on the second channel region, a dielectric capping layer formed on the gate insulating layer, a first gate region formed on the dielectric capping layer over the first channel region, and a second gate region formed on the dielectric capping layer over the second channel region, wherein the first gate region and the second gate region are made of the same material, and wherein one of the first gate region and the second gate region comprises an ion implantation. | 2016-01-07 |
20160005738 | SEMICONDUCTOR DEVICE HAVING A FIN STRUCTURE AND METHOD OF MANUFACTURE THE SAME - A semiconductor device is provided. In some examples, the semiconductor device includes: a substrate, a fin structure disposed with the substrate, a source and a drain that are formed in the fin structure, a channel area disposed between the source and the drain, a gate dielectric layer disposed on the channel area, and a gate line disposed on the gate dielectric layer. The fin structure may include an anti-punch through layer, an upper fin structure disposed on the anti-punch through layer, the upper fin structure including a material having a lattice constant to receive a compressive strain. The fin structure may also include a lower fin structure disposed under the anti-punch through layer, and may comprise the same material as the substrate. | 2016-01-07 |
20160005739 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device includes a first insulating layer covering a substrate, a first contact plug and a second contact plug each penetrating the first insulating layer, a first data storage element disposed on the first contact plug, and a second data storage element disposed on the second contact plug. The first contact plug includes a vertically extending portion and a horizontally extending portion arranged between the vertically extending portion and the first data storage element, and the second contact plug extends substantially vertically from a top surface of the substrate. The first data storage element is laterally spaced apart from the vertically extending portion when viewed in plan view. The first data storage element is disposed on the horizontally extending portion. | 2016-01-07 |
20160005740 | MEMORY DEVICE AND MANUFACTURING METHOD THE SAME - A semiconductor device that can transmit and receive data without contact is popular partly as some railway passes, electronic money cards, and the like; however, it has been a prime task to provide an inexpensive semiconductor device for further popularization. In view of the above current conditions, a semiconductor device of the present invention includes a memory with a simple structure for providing an inexpensive semiconductor device and a manufacturing method thereof. A memory element included in the memory includes a layer containing an organic compound, and a source electrode or a drain electrode of a TFT provided in the memory element portion is used as a conductive layer which forms a bit line of the memory element. | 2016-01-07 |
20160005741 | Compact Semiconductor Memory Device Having Reduced Number of Contacts, Methods of Operating and Methods of Making - An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or siring includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link. | 2016-01-07 |
20160005742 | Semiconductor Constructions, and Semiconductor Processing Methods - Some embodiments include methods in which a pair of spaced-apart adjacent features is formed over a substrate. The features have silicon dioxide surfaces. Silicon nitride is deposited between the features. A first region of the silicon nitride is protected with a mask while a second region is not. The second region is removed to form an opening between the features. Some embodiments include semiconductor constructions that contain a pair of spaced-apart adjacent features. The features are lines extending along a first direction, and are spaced from one another by a trench. Alternating plugs and intervening materials are within the trench, with the plugs and intervening materials alternating along the first direction. The intervening materials consist of silicon nitride, and the plugs have lateral peripheries that directly contact silicon dioxide of the features, and that directly contact silicon nitride of the intervening regions. | 2016-01-07 |
20160005743 | SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a first conductive structure including a first conductive pattern that is formed over a substrate, a second conductive structure formed adjacent to a sidewall of the first conductive structure, and an insulation structure including an air gap that is formed between the first conductive structure and the second conductive structure, wherein the second conductive structure includes a second conductive pattern, an ohmic contact layer that is to formed over the second conductive pattern, and a third conductive pattern that is formed over the ohmic contact layer and is separated from the first conductive pattern through the air gap. | 2016-01-07 |
20160005744 | ULTRAVIOLET-ERASABLE NONVOLATILE SEMICONDUCTOR DEVICE - In order to provide an ultraviolet-erasable nonvolatile semiconductor device that has a high water resistance and is capable of erasing data by ultraviolet rays, a protective film includes a silicon nitride film ( | 2016-01-07 |
20160005745 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate having a cell region, wherein a contact region, page buffer regions, and a scribe lane region are defined around the cell region; a cell structure located in the cell region, including first conductive layers and first insulating layers which are alternately stacked, and having a non-stepped shape; a contact structure located in the contact region, including second conductive layers and second insulating layers which are alternately stacked, and having a stepped shape; a first dummy structure located in the page buffer region, including first sacrificial layers and third insulating layers which are alternately stacked, and having the non-stepped shape; and a second dummy structure located in the scribe lane region, including second sacrificial layers and fourth insulating layers which are alternately stacked, and having the stepped shape. | 2016-01-07 |
20160005746 | MEMORY ARCHITECTURE OF 3D ARRAY WITH INTERLEAVED CONTROL STRUCTURES - A 3D memory device includes a first plurality and a second plurality of stacks of semiconductor material strips on a substrate. The second plurality of stacks of gate material strips on the substrate is interleaved with, and coplanar with, the first plurality of stacks. The second plurality of stacks is configured as gates for the first plurality of stacks. A first plurality of word lines is arranged orthogonally over, and having surfaces conformal with, the first plurality of stacks, such that a 3D array of memory elements is established at cross-points between surfaces of the first plurality of stacks and the plurality of word lines. | 2016-01-07 |
20160005747 | three dimensional semiconductor device - A semiconductor device includes alternately stacked conductive layers and the insulating layers, an opening passing through the conductive layers and insulating layers, a first semiconductor layer formed in the opening, a second semiconductor layer formed in the first semiconductor layer, a capping layer formed in the opening and disposed over the first semiconductor layer and the second semiconductor layer, and a liner layer interposed between the first semiconductor layer and the second semiconductor layer and protruding through the capping layer relative to the first semiconductor layer and the second semiconductor layer. | 2016-01-07 |
20160005748 | 3D NAND ARRAY ARCHITECTURE - Roughly described, a memory device has a multilevel stack of conductive layers which are divided laterally into word lines. Vertically oriented pillars each include series-connected memory cells at cross-points between the pillars and the layers. String select lines run above the conductive layers and define select gates of the pillars. Bit lines run above the SSLs. The pillars are arranged on a regular grid having a unit cell area α, and adjacent ones of the string select lines have respective widths in the bit line direction which are at least as large as (α/pBL). Ground select lines run below the conductive layers and define ground select gates of the pillars. The ground select lines, too, may have respective widths in the bit line direction which are at least as large as (α/pBL). | 2016-01-07 |
20160005749 | SERIES FERROELECTRIC NEGATIVE CAPACITOR FOR MULTIPLE TIME PROGRAMMABLE (MTP) DEVICES - Implementations of the technology described herein provide a Multiple Time Programmable (MTP) device, such as a Flash memory device, that implements a coupling gate in series with a floating gate. The coupling gate includes a ferroelectric capacitor and a conventional capacitor. The ferroelectric capacitor in combination with the coupling gate provides a negative capacitance such that the total capacitance of the combination of the floating gate and the coupling gate is larger than it would be if the coupling gate included only a conventional capacitor. One advantage of this device is that the effective coupling ratio between the coupling gate and the floating gate is increased. Another advantage is that the floating gate drops more voltage than conventional Multiple Time Programmable (MTP) devices. | 2016-01-07 |
20160005750 | Semiconductor Device Having Electrically Floating Body Transistor, Semiconductor Device Having Both Volatile and Non-Volatile Functionality and Method of Operating - A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided. | 2016-01-07 |
20160005751 | STRUCTURE AND METHOD FOR SINGLE GATE NON-VOLATILE MEMORY DEVICE - The present disclosure provides an integrated circuit. The integrated circuit includes a substrate; a field effect transistor disposed in a periphery region of the substrate, the field effect transistor including a gate electrode, a first source, a first drain; a floating gate non-volatile memory device disposed in a memory region of the substrate, the floating gate non-volatile memory device including a second source, a third source, and a second drain, wherein the second source, the third source, and the second drain are disposed along an axis; and a floating gate electrode in the memory region including a first portion, a second portion, and a third portion, wherein the first portion, the second portion, and the third portion are electrically connected, wherein the first portion, the second portion and the third portion extend perpendicular to the axis. | 2016-01-07 |
20160005752 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes a semiconductor substrate, a first region that is provided on the semiconductor substrate and has a line-and-space pattern extending in a first direction, and a second region that is provided adjacent to the first region on the semiconductor substrate and has a dummy pattern. The surface area per unit area of the second region is greater than the surface area per unit area of the first region. | 2016-01-07 |
20160005753 | Three Dimensional Semiconductor Memory Devices - A semiconductor memory device includes a semiconductor substrate including a common source region and a drain region, a lower structure provided on the semiconductor substrate and including a plurality of lower transistors connected in series between the common source region and the drain region, a stack including a plurality of word lines stacked on the lower structure, and semiconductor pillars penetrating the stack and controlling gate electrodes of respective ones of the lower transistors. | 2016-01-07 |
20160005754 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device having a plurality of unit cells, each of the plurality of unit cells includes a first transistor suitable for having a fixed threshold voltage, and a second transistor suitable for coupling to the first transistor in parallel and having a variable threshold voltage. | 2016-01-07 |
20160005755 | NON-VOLATILE MEMORY DEVICE - According to one embodiment, a non-volatile memory device includes first electrodes, at least one first semiconductor layer, a first memory film, second electrodes, at least one second semiconductor layer, and a second memory film. The first electrodes are stacked in a first direction. The one first semiconductor layer extends in the first direction through the first electrodes. The first memory film is provided between each of the first electrodes and the one first semiconductor layer. The second electrodes are stacked in the first direction and provided together with the first electrodes in a second direction orthogonal to the first direction. The one second semiconductor layer extends in the first direction through the second electrodes. The second memory film is provided between each of the second electrodes and the one second semiconductor layer. An outer diameter of the first memory film is larger than that of the second memory film. | 2016-01-07 |
20160005756 | HKMG HIGH VOLTAGE CMOS FOR EMBEDDED NON-VOLATILE MEMORY - The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-κ metal gate) integrated circuit which includes a high voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size. | 2016-01-07 |
20160005757 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a stacked layer structure including first to n-th semiconductor layers (n is a natural number equal to or larger than 2) stacked in a first direction which is perpendicular to a surface of a semiconductor substrate, and an upper insulating layer stacked on the n-th semiconductor layer, the stacked layer structure extending in a second direction which is parallel to the surface of the semiconductor substrate, and first to n-th NAND strings provided on surfaces of the first to n-th semiconductor layers in a third direction which is perpendicular to the first and second directions respectively. | 2016-01-07 |
20160005758 | THREE-DIMENSIONAL VERTICAL GATE NAND FLASH MEMORY INCLUDING DUAL-POLARITY SOURCE PADS - A memory includes a three-dimensional array including a plurality of levels is described. Each level includes a bit line pad, a source line pad, and a plurality of strips of semiconductor material extending between the bit line pad and the source line pad. The source line pad includes at least one n-type region and at least one p-type region. The memory includes word lines coupled to the plurality of strips in the plurality of levels. The memory includes data storage elements between the word lines and the strips of semiconductor material, whereby memory cells are disposed at cross-points of the strips and the word lines. The memory also includes circuitry coupled to the n-type region and the p-type region of the source line pad, configured to selectively enable current flow in the strips extending from the source line pad and one of the n-type region and the p-type region. | 2016-01-07 |
20160005759 | THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - A three-dimensional semiconductor memory device is provided. A stacked structure is formed on a substrate. The stacked structure includes conductive patterns vertically stacked on the substrate. A selection structure including selection conductive patterns is stacked on the stacked structure. A channel structure penetrates the selection structure and the stacked structure to connect to the substrate. An upper interconnection line crosses the selection structure. A conductive pad is disposed on the channel structure to electrically connect the upper interconnection line to the channel structure. A bottom surface of the conductive pad is positioned below a top surface of the uppermost selection conductive pattern of the selection conductive patterns. | 2016-01-07 |
20160005760 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a lower stack structure including lower gate electrodes and lower insulating layers that are alternately and repeatedly stacked on a substrate. The semiconductor device includes an upper stack structure including upper gate electrodes and upper insulating layers that are alternately and repeatedly stacked on the lower stack structure. A lower channel structure penetrates the lower stack structure. An upper channel structure penetrates and is connected to the upper stack structure. A lower vertical insulator is disposed between the lower stack structure and the lower channel structure. The lower channel structure includes a first vertical semiconductor pattern connected to the substrate, and a first connecting semiconductor pattern disposed on the first vertical semiconductor pattern. The upper channel structure includes a second vertical semiconductor pattern electrically connected to the first vertical semiconductor pattern with the first connecting semiconductor pattern disposed therebetween. | 2016-01-07 |
20160005761 | Data Line Arrangement and Pillar Arrangement in Apparatuses - Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern which has at least portions of 7 different pillars. Each of the different pillars in a respective one of the repeating pillar patterns is capable of being electrically coupled to a different data line of a plurality of data lines. Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern having at least portions of 7 different pillars. All 7 different pillars of a repeating pillar pattern are encompassed by a single drain-side select gate (SGD). | 2016-01-07 |
20160005762 | MULTIPLE-BIT-PER-CELL, INDEPENDENT DOUBLE GATE, VERTICAL CHANNEL MEMORY HAVING SPLIT CHANNEL - A vertical channel 3D NAND array is configured for independent double gate operation, establishing two memory sites per frustum of a vertical channel column, and in addition, for multiple-bit-per-cell operation. The memory device can comprise even and odd stacks of conductive strips. Active pillars are arranged between corresponding even and odd stacks of conductive strips. A 3D array includes even memory cells accessible via the active pillars and conductive strips in the even stacks and odd memory cells accessible via the active pillars and conductive strips in the odd stacks of conductive strips. Control circuitry is configured to apply different bias voltages to the even and odd conductive strips, and execute a program operation by which more than one bit of data is stored in both the even memory cell and odd memory cell in a given frustum of a selected active strip. | 2016-01-07 |
20160005763 | SEMICONDUCTOR DEVICE WITH SIX TRANSISTORS FORMING A NAND CIRCUIT - A semiconductor device has a small area and constitutes a CMOS 3-input NAND circuit by using surrounding gate transistors (SGTs) that are vertical transistors. In a 3-input NAND circuit including six MOS transistors arranged in a line, the MOS transistors constituting the NAND circuit have the following configuration. Planar silicon layers are disposed on a substrate. The drain, gate, and source of the MOS transistors are arranged in a vertical direction, and the gate surrounds a silicon pillar. The planer silicon layers include a first active region having a first conductivity type and a second active region having a second conductivity type. The first and second active regions are connected to each other via a silicide layer disposed on surfaces of the planar silicon layers. In this way, a semiconductor device constituting a NAND circuit with a small area is provided. | 2016-01-07 |
20160005764 | SEMICONDUCTOR DEVICE WITH SIX TRANSISTORS FORMING A NOR CIRCUIT - A semiconductor device has a small area and constitutes a CMOS 3-input NOR circuit by using surrounding gate transistors (SGTs) which are vertical transistors. In the 3-input NOR circuit including six MOS transistors arranged in a line, the MOS transistors constituting the NOR circuit have the following configuration: Planar silicon layers are disposed on a substrate. The drain, the gate, and the source of the MOS transistors are arranged in a vertical direction, and the gate surrounds a silicon pillar. The planar silicon layers include a first active region having a first conductivity type and a second active region having a second conductivity type. The first and second active regions are connected to each other via a silicide layer disposed on surfaces of the planar silicon layers. In this way, a semiconductor device constituting a NOR circuit with a small area is provided. | 2016-01-07 |
20160005765 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In an SOI substrate having a semiconductor layer formed on the semiconductor substrate via an insulating layer, a MISFET is formed in each of the semiconductor layer in an nMIS formation region and a pMIS formation region. In power feeding regions, the semiconductor layer and the insulating layer are removed. In the semiconductor substrate, a p-type semiconductor region is formed so as to include the nMIS formation region and one of the power feeding regions, and an n-type semiconductor region is formed so as to include a pMIS formation region and the other one of the power feeding regions. In the semiconductor substrate, a p-type well having lower impurity concentration than the p-type semiconductor region is formed so as to contain the p-type semiconductor region, and an n-type well having lower impurity concentration than the n-type semiconductor region is formed so as to contain the n-type semiconductor region. | 2016-01-07 |
20160005766 | ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, DISPLAY DEVICE - The embodiments of the present invention disclose an array substrate, a method for manufacturing the same, and a display device. With the solutions of the embodiments, aperture rate is increased, and gate signal delay caused by increased connection resistance of gate line is alleviated. The array substrate of the present invention includes a thin film transistor; a substrate; a common electrode provided on the substrate; a gate line comprising a plurality of separate segments arranged to be spaced apart from each other and connected with each other through a bridge; and a common electrode line provided to be spaced apart from the gate line, the gate line and the common electrode line being in the same layer, wherein the common electrode line comprises a connection segment extending through a gap between separate segments to electrically connect with the common electrode directly. | 2016-01-07 |
20160005767 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE - An array substrate, a manufacturing method thereof and a display device are provided; in the array substrate, two adjacent rows of the pixel units ( | 2016-01-07 |
20160005768 | THIN FILM TRANSISTOR ARRAY PANEL - A thin film transistor array panel includes: a data line which extends in a column direction and transfers a data voltage; a first pixel electrode and a second pixel electrode connected to the data line and adjacent in a row direction; a first thin film transistor connected to the first pixel electrode and the data line, and including a first source electrode and a first drain electrode; and a second thin film transistor connected to the second pixel electrode and the data line, and including a second source electrode and a second drain electrode. The first pixel electrode is at the right of the data line, the second pixel electrode is at the left of the data line, and relative positions of the first source electrode and the first drain electrode are the same as relative positions of the second source electrode and the second drain electrode. | 2016-01-07 |
20160005769 | LIQUID CRYSTAL DISPLAY DEVICE - The invention provides a high-precision display device having a reliable top- and single-gate TFT causing less current leakage. | 2016-01-07 |
20160005770 | THIN FILM TRANSISTOR SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor substrate includes: a gate insulating film that covers a gate electrode and a common electrode; a transparent oxide film selectively disposed on the gate insulating film; a source electrode and a drain electrode that are spaced from each other on the transparent oxide film; and a light transmissive pixel electrode electrically connected to the drain electrode. The transparent oxide film includes a conductive region and a semiconductor region. The conductive region is disposed in a lower portion of the source electrode and the drain electrode and disposed in a portion that continues from the lower portion of the drain electrode, extends to part of an upper portion of the common electrode, and forms the pixel electrode. The semiconductor region is disposed in a portion corresponding to a lower layer in a region between the source electrode and the drain electrode. | 2016-01-07 |
20160005771 | Millimetre wave integrated circuits with thin film transistors - MMIC circuits with thin film transistors are provided without the need of grinding and etching of the substrate after the fabrication of active and passive components. Furthermore, technology for active devices based on non-toxic compound semiconductors is provided. The success in the MMIC methods and structures without substrate grinding/etching and the use of semiconductors without toxic elements for active components will reduce manufacturing time, decrease economic cost and environmental burden. MMIC structures are provided where the requirements for die or chip attachment, alignment and wire bonding are eliminated completely or minimized. This will increase the reproducibility and reduce the manufacturing time for the MMIC circuits and modules. | 2016-01-07 |
20160005772 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - Embodiments of the invention provide an array substrate, a manufacturing method thereof and a display device. The array substrate comprises: a base substrate; a gate line and a gate electrode formed on the base substrate; a gate insulating layer formed on the gate line and the gate electrode; a source electrode, a drain electrode and a pixel electrode formed on the gate insulating layer, wherein the pixel electrode is directly connected to the drain electrode; and an active layer formed on the gate insulating layer, the source electrode and the drain electrode. | 2016-01-07 |
20160005773 | SUBSTRATE FOR DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A method for a display device is discussed. The method according to one embodiment includes forming a substrate of the display device; forming a thin film transistor on the substrate; and forming a passivation layer of a photosensitive organic material on the thin film transistor, the passivation layer having a contact hole exposing the thin film transistor. The photosensitive organic material comprises an ultraviolet absorber. The method according to the embodiment includes forming a blocking area in a mask above the contact hole; and absorbing, via the ultraviolet absorber, reflected ultraviolet (UV) rays passing by the blocking area in the mask above the contact hole. | 2016-01-07 |
20160005774 | Fractal-Edge Thin Film And Method Of Manufacture - A fractal-edge thin film includes a material layer having a perimeter with a fractal dimension exceeding one, the material layer having greater peel resistance as compared to a thin-film material layer with fractal dimension equaling one. | 2016-01-07 |
20160005775 | PHOTODETECTOR AND METHOD OF FORMING THE PHOTODETECTOR ON STACKED TRENCH ISOLATION REGIONS - Disclosed are structures and methods of forming the structures so as to have a photodetector isolated from a substrate by stacked trench isolation regions. In one structure, a first trench isolation region is in and at the top surface of a substrate and a second trench isolation region is in the substrate below the first. A photodetector is on the substrate aligned above the first and second trench isolation regions. In another structure, a semiconductor layer is on an insulator layer and laterally surrounded by a first trench isolation region. A second trench isolation region is in and at the top surface of a substrate below the insulator layer and first trench isolation region. A photodetector is on the semiconductor layer and extends laterally onto the first trench isolation region. The stacked trench isolation regions provide sufficient isolation below the photodetector to allow for direct coupling with an off-chip optical fiber. | 2016-01-07 |
20160005776 | SOLID-STATE IMAGE PICKUP DEVICE - A solid-state image pickup device capable of suppressing the generation of dark current and/or leakage current is provided. The solid-state image pickup device has a first substrate provided with a photoelectric converter on its primary face, a first wiring structure having a first bonding portion which contains a conductive material, a second substrate provided with a part of a peripheral circuit on its primary face, and a second wiring structure having a second bonding portion which contains a conductive material. In addition, the first bonding portion and the second bonding portion are bonded so that the first substrate, the first wiring structure, the second wiring structure, and the second substrate are disposed in this order. | 2016-01-07 |
20160005777 | SOLID STATE IMAGING DEVICE, METHOD OF PRODUCING SOLID STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS - A solid state imaging device includes: a substrate; a photoelectric conversion unit that is formed on the substrate to generate and accumulate signal charges according to light quantity of incident light; a vertical transmission gate electrode that is formed to be embedded in a groove portion formed in a depth direction from one side face of the substrate according to a depth of the photoelectric conversion unit; and an overflow path that is formed on a bottom portion of the transmission gate to overflow the signal charges accumulated in the photoelectric conversion unit. | 2016-01-07 |
20160005778 | Semiconductor Package and Method for Manufacturing the Same - Provided is a semiconductor package including: a substrate; an image sensor chip disposed on the substrate and including a first surface that faces the substrate and a second surface that is opposed to the first surface; an adhesion layer interposed between the substrate and the image sensor chip; and a first cavity surrounded by the first surface, an upper surface of the substrate and a side surface of the adhesion layer. The first surface includes a first central portion and a first edge portion, the adhesion layer includes a first adhesion part directly contacting the first central portion and a second adhesion part directly contacting the substrate, and the first adhesion part has an area corresponding to about 5% to about 50% of an area of the first surface. | 2016-01-07 |
20160005779 | PHOTODETECTION DEVICE AND SENSOR PACKAGE - A photodetection device of the present invention includes a semiconductor substrate which is defined such that a first light-receiving portion and a second light-receiving portion are spaced from one another, and an optical filter which is formed on the semiconductor substrate, and includes a first filter which is disposed so as to cover the first light-receiving portion, to selectively allow an optic element in a first wavelength band to transmit through, and a second filter which is disposed so as to cover the second light-receiving portion, to selectively allow an optic element in a second wavelength band different from the first wavelength band, to transmit through, and the optical filter has a filter laminated structure which is defined such that edge portions of the first filter and the second filter overlap one another on a boundary region between the first light-receiving portion and the second light-receiving portion. | 2016-01-07 |
20160005780 | IMAGE SENSOR DEVICE AND METHOD OF FORMING SAME - An image sensor device includes a first substrate, an interconnect structure, a conductive layer, a conductive via and a second substrate. The first substrate includes a first region including a pixel array and a second region including a circuit. The interconnect structure is over the pixel array or the circuit. The interconnect structure electrically connecting the circuit to the pixel array. The conductive layer is on the interconnect structure. The conductive via passes through the second substrate and at least partially embedded in the conductive layer. The second substrate is over the conductive layer. | 2016-01-07 |
20160005781 | BACKSIDE ILLUMINATED IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME - A backside illuminated (BSI) image sensor device includes: a first substrate including a front side and a back side; a second substrate bonded with the first substrate on the front side; and a blocking layer between the first substrate and the second substrate. The first substrate includes an image sensor, and the image sensor is configured to collect incident light entering from the back side. The second substrate includes a circuit coupled with the image sensor. The blocking layer is configured to block radiation induced by the circuit. | 2016-01-07 |
20160005782 | SOLID STATE IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - A method of manufacturing a solid state image sensor is provided. The method includes forming electrically conductive layer and an interlayer insulation film above a first region and a second region, performing an annealing process after forming the conductive layer and the interlayer insulation film, and forming a protective film above the interlayer insulation film and the electrically conductive layer. The electrically conductive layer includes a light shielding layer arranged above the second region. The interlayer insulation film includes a first portion located above the first region and a second portion located above the second region and below the light shielding layer. Before performing the annealing process, an average hydrogen concentration of the second portion is higher than an average hydrogen concentration of the first portion. | 2016-01-07 |
20160005783 | SOLID-STATE IMAGING DEVICE AND CAMERA - A solid-state imaging device including is provided. The solid-state imaging device includes: pixels arrayed; a photoelectric conversion element in each of the pixels; a read transistor for reading electric charges photoelectrically-converted in the photoelectric conversion elements to a floating diffusion portion; a shallow trench element isolation region bordering the floating diffusion portion; and an impurity diffusion isolation region for other element isolation regions than the shallow trench element isolation region. | 2016-01-07 |
20160005784 | SOLID-STATE IMAGE PICKUP DEVICE, METHOD OF MANUFACTURING THEREOF, AND ELECTRONIC APPARATUS - Provided is a solid-state image pickup device including: a plurality of pixels, each of which includes a photoelectric conversion portion and a pixel transistor formed in a front surface side of a substrate, wherein a rear surface side of the substrate is set as a light receiving plane of the photoelectric conversion portion; and an element, which becomes a passive element or an active element, which is disposed in the front surface side of the substrate so as to be superimposed on the photoelectric conversion portion. | 2016-01-07 |
20160005785 | IMAGE SENSOR WITH ANTI-BLOOMING GATE - The invention concerns active-pixel electronic image sensors. The pixel comprises a photodiode (PH) designed in a semiconductor active layer ( | 2016-01-07 |
20160005786 | ATOMICALLY PRECISE SURFACE ENGINEERING FOR PRODUCING IMAGERS - High-quality surface coatings, and techniques combining the atomic precision of molecular beam epitaxy and atomic layer deposition, to fabricate such high-quality surface coatings are provided. The coatings made in accordance with the techniques set forth by the invention are shown to be capable of forming silicon CCD detectors that demonstrate world record detector quantum efficiency (>50%) in the near and far ultraviolet (155 nm-300 nm). The surface engineering approaches used demonstrate the robustness of detector performance that is obtained by achieving atomic level precision at all steps in the coating fabrication process. As proof of concept, the characterization, materials, and exemplary devices produced are presented along with a comparison to other approaches. | 2016-01-07 |
20160005787 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a device region disposed in the semiconductor substrate; a dielectric layer disposed on the first surface of the semiconductor substrate; a conducting pad structure disposed in the dielectric layer and electrically connected to the device region, a carrier substrate disposed on the dielectric layer; and a conducting structure disposed in a bottom surface of the carrier substrate and electrically contacting with the conducting pad structure. | 2016-01-07 |
20160005788 | SOLID-STATE IMAGING APPARATUS AND IMAGING SYSTEM - Provided is a solid-state imaging apparatus including plural pixels each including a first pixel connecting transistor and a second pixel connecting transistor each connected at one end to a floating diffusion node, a first pixel connecting line connected to the other end of the first pixel connecting transistor, and a second pixel connecting line connected to the other end of the second pixel connecting transistor. The first pixel connecting line provided in a first pixel of the plural pixels is connected to the second pixel connecting line provided in a second pixel of the plural pixels, and the second pixel connecting line provided in the first pixel is connected to the first pixel connecting line provided in a third pixel of the plural pixels. | 2016-01-07 |
20160005789 | DISPLAY DEVICE USING SEMICONDUCTOR LIGHT EMITTING DEVICE - Discussed is a display device using a semiconductor light emitting device. In a display device including a plurality of semiconductor light emitting devices, each of the plurality of semiconductor light emitting devices includes a first conductive semiconductor layer, a second conductive semiconductor layer overlapped with the first conductive semiconductor layer, an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer, a first electrode deposited on the first conductive semiconductor layer, and a second electrode deposited on the second conductive semiconductor layer, wherein the first electrode is extended toward an adjoining semiconductor light emitting device to be electrically connected to the adjoining semiconductor light emitting device. | 2016-01-07 |
20160005790 | DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE - Embodiments of the present invention disclose a display substrate and a method of manufacturing the same, and a display device comprising the display substrate. The display substrate comprises: a substrate; a black matrix layer and a color filter layer located on the substrate; and at least one main spacer and at least one secondary spacer located on the black matrix layer or the color filter layer and both having direct projections on the substrate within a region where the black matrix layer is located. A sum of thicknesses of portions of the black matrix layer and the color filter layer corresponding to each secondary spacer is smaller than that of portions of the black matrix layer and the color filter layer corresponding to each main spacer, so that a distance from a top end of the secondary spacer to the substrate is smaller than a distance from a top end of the main spacer to the substrate. As a result, a difference between the distance from the top end of the main spacer to the substrate and the distance from the top end of the secondary spacer to the substrate can be varied by adjusting a difference between the sum of thicknesses of the black matrix layer and the color filter layer directly below each main spacer and the sum of thicknesses of the black matrix layer and the color filter layer directly below each secondary spacer, thereby enabling the main spacer and the secondary spacer to provide a good effect of buffering an external force. | 2016-01-07 |
20160005791 | METHOD AND SYSTEM FOR PROVIDING A THIN PINNED LAYER IN A PERPENDICULAR MAGNETIC JUNCTION USABLE IN SPIN TRANSFER TORQUE MAGNETIC RANDOM ACCESS MEMORY APPLICATIONS - A magnetic junction usable in a magnetic device and a method for providing the magnetic junction are described. The magnetic junction includes a free layer, a pinned layer and nonmagnetic spacer layer between the free and pinned layers. The free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. The pinned layer has a perpendicular magnetic anisotropy energy greater than an out-of-plane demagnetization energy. The nonmagnetic spacer layer and the free layer are between the pinned layer and the substrate. The pinned layer has a pinned layer perpendicular magnetic anisotropy energy greater than a pinned layer out-of-plane demagnetization energy and a thickness of not more than thirty Angstroms. | 2016-01-07 |
20160005792 | SEMICONDUCTOR MEMORY DEVICE, AND METHOD FOR PRODUCING THE SAME - Provided is a semiconductor memory device (resistance random access memory element) improved in properties. A Ru film is formed as a film of a lower electrode by sputtering, and a Ta film is formed thereonto by sputtering. Next, the Ta film is oxidized with plasma to oxidize the Ta film. In this way, a compound Ta | 2016-01-07 |
20160005793 | MEMORY ELEMENT WITH A REACTIVE METAL LAYER - A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO | 2016-01-07 |
20160005794 | THREE DIMENSIONAL SEMICONDUCTOR INTEGRATED CIRCUIT HAVING GATE PICK-UP LINE AND METHOD OF MANUFACTURING THE SAME - A 3D semiconductor integrated circuit having a gate pick-up line and a method of manufacturing the same, wherein the semiconductor integrated circuit includes a plurality of active pillars formed in a gate pick-up region, buffer layers formed on the respective active pillars in the gate pick-up region, gates each surrounding an outer circumference of the corresponding active pillar and the corresponding buffer layer, and a gate pick-up line electrically coupled to the gates. | 2016-01-07 |
20160005795 | ORGANIC TANDEM PHOTOVOLTAIC DEVICE AND METHODS - An organic tandem photovoltaic device includes a first electrode, a second electrode spaced apart from said first electrode, first and second photoactive organic bulk heterojunction layers, and an interconnecting layer. The interconnecting layer is between and electrically connects the first and second photoactive organic bulk heterojunction layers. The interconnecting layer includes an electron extracting interface layer of a first inorganic material and a hole extracting interface layer of a second inorganic material. | 2016-01-07 |
20160005796 | ILLUMINATING DEVICE AND MANUFACTURING METHOD THEREOF - An illuminating device is provided, which includes: a substrate ( | 2016-01-07 |
20160005797 | ORGANIC ELECTROLUMINESCENCE DISPLAY PANEL - An organic electroluminescence display panel that includes a plurality of first pixel areas, a plurality of second pixel areas, and a plurality of third pixel areas is provided. The organic electroluminescence display panel includes a first electrode layer, an organic layer including a light-emitting layer made of organic light-emitting material and a second electrode layer. The first electrode layer includes a reflective material. The organic layer is located on the first electrode layer. The second electrode layer is located on the organic layer. The material of the second electrode layer includes a transparent metal oxide conductive material. The thickness of the second electrode layer is a single thickness and is greater than 300 nm. | 2016-01-07 |
20160005798 | EL DISPLAY DEVICE - An EL display device including a light emitter configured to emit at least red, green, and blue light; and a thin film transistor array that controls light emission. The light emitter includes light-emitting layers within areas defined by a bank that emit at least red, green, and blue light. The light emitter further includes electrodes that extend under the bank and hole transport layers that are above the electrodes within the areas defined by the bank, the light-emitting layers being formed on the hole transport layers. The hole transport layers each have a main portion and a peripheral protrusion in contact with a side surface of the bank that protrudes upwards from the main portion. The light-emitting layers each have a peripheral protrusion in contact with a side surface of the bank, formed above a corresponding one of the peripheral protrusions. | 2016-01-07 |
20160005799 | THIN FILM TRANSISTOR, TFT ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE - A TFT, a TFT array substrate, a manufacturing method thereof and a display device are disclosed. A source of the TFT includes a first source portion ( | 2016-01-07 |
20160005800 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE AND FABRICATING METHOD THEREOF - An OLED display device is discussed which can include: a first substrate defined into an emission region and a non-emission region; a first electrode formed on the first substrate; a bank pattern configured to expose a part of the first electrode corresponding to the emission region; an organic emission layer formed on the exposed part of the first electrode corresponding to the emission region; a second electrode which includes a first conductive layer formed on the organic emission layer and a second conductive layer formed on the second conductive layer. The first conductive layer is formed from an alloy of magnesium (Mg) and silver (Ag), and the second conductive layer is formed from silver (Ag). Such an OLED display device allows the second electrode to include the first conductive layer and the second conductive layer. As such, a large-sized display device with low resistance and high transmittance can be realized. | 2016-01-07 |
20160005801 | DISPLAY DEVICE, ELECTRONIC APPARATUS, AND METHOD OF FABRICATING THE DISPLAY DEVICE - It is an object of the invention to provide a technique to manufacture a display device with high image quality and high reliability at low cost with high yield. The invention has spacers over a pixel electrode layer in a pixel region and over an insulating layer functioning as a partition which covers the periphery of the pixel electrode layer. When forming a light emitting material over a pixel electrode layer, a mask for selective formation is supported by the spacers, thereby preventing the mask from contacting the pixel electrode layer due to a twist and deflection thereof. Accordingly, such damage as a crack by the mask does not occur in the pixel electrode layer. Thus, the pixel electrode layer does not have a defect in shapes, thereby a display device which performs a high resolution display with high reliability can be manufactured. | 2016-01-07 |
20160005802 | ORGANIC LIGHT EMITTING DISPLAY DEVICES - An organic light emitting display device may have a pixel region and a transparent region, and may include a substrate, at least one semiconductor device disposed on the substrate in the pixel region, an organic light emitting structure disposed on the at least one semiconductor device, and a capacitor disposed on the substrate in the transparent region. The capacitor may have a sufficient capacitance without substantially reducing a transmittance of the organic light emitting display device. Additionally, the transparent region of the organic light emitting display device may serve as a mirror in accordance with the material included in a lower electrode of the capacitor and/or an upper electrode of the capacitor. | 2016-01-07 |
20160005803 | ORGANIC ELECTROLUMINESCENT DEVICE - Disclosed is an organic electroluminescent device (OELD) includes a first substrate including a pixel region that includes an element region and a light emission region; a storage capacitor disposed at the element region, and including a first storage electrode, a first buffer layer on the first storage electrode, and a second storage electrode on the first buffer layer; a second buffer layer on the storage capacitor; a plurality of TFTs on the second buffer layer at the element region; and a passivation layer on the plurality of TFTs, wherein the storage capacitor overlaps at least one of the plurality of TFTs. | 2016-01-07 |
20160005804 | ORGANIC LIGHT EMITTING DISPLAY AND METHOD OF FABRICATING THE SAME - A subpixel structure for a display device and a method of fabricating the display device are discussed. The subpixel structure can include a light emitting diode, a first switching transistor having a first gate electrode and a first active layer, a driving transistor having a second gate electrode and a second active layer, a second switching transistor including a third gate electrode and a third active layer, and at least one of the first, second and third gate electrodes is disposed between the corresponding first, second and third active layers and a substrate. | 2016-01-07 |
20160005805 | MIM CAPACITORS FOR LEAKAGE CURRENT IMPROVEMENT - The semiconductor device includes a substrate, a bottom electrode, a capacitor dielectric layer, a top electrode, an etching stop layer, a first anti-reflective coating layer and a capping layer. The bottom electrode is on the substrate. The capacitor dielectric layer is on the bottom electrode. The capacitor dielectric layer has a first region and a second region adjacent to the first region. The top electrode is on the first region of the capacitor dielectric layer. The etching stop layer is on the top electrode. The first anti-reflective coating layer is on the etching stop layer, in which the first anti-reflective coating layer, the etching stop layer and the top electrode together have a sidewall. The capping layer overlies the sidewall, the etching stop layer, the second region of the capacitor dielectric layer, in which the capping layer is formed from oxide or nitride. | 2016-01-07 |
20160005806 | SEMICONDUCTOR DEVICE HAVING SUPPORTER - A semiconductor device includes a plurality of lower electrodes having a vertical length greater than a horizontal width on a substrate, a supporter disposed between the lower electrodes, an upper electrode disposed on the lower electrodes, and a capacitor dielectric layer disposed between the lower electrodes and the upper electrode. The supporter includes a first element, a second element, and oxygen, an oxide of the second element has a higher band gap energy than an oxide of the first element, and the content of the second element in the supporter is from about 10 at % to 90 at %. | 2016-01-07 |
20160005807 | Semiconductor Structure with Dielectric-Sealed Doped Region - Leakage current can be substantially reduced by the formation of a seal dielectric in place of the conventional junction between source/drain region(s) and the substrate material. Trenches are formed in the substrate and lined with a seal dielectric prior to filling the trenches with semiconductor material. Preferably, the trenches are overfilled and a CMP process planarizes the overfill material. An epitaxial layer can be grown atop the trenches after planarization, if desired. | 2016-01-07 |
20160005808 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device, includes: a first semiconductor region of a first conductivity type; a second semiconductor region provided on the first semiconductor region, an impurity concentration of the second semiconductor region being lower than an impurity concentration of the first semiconductor region; a third semiconductor region of a second conductivity type provided on the second semiconductor region; and a fourth semiconductor region provided on the third semiconductor region or in a portion of the third semiconductor region. A lattice strain of the fourth semiconductor region is greater than a lattice strain of the third semiconductor region. | 2016-01-07 |
20160005809 | CONFIGURATION AND METHOD TO GENERATE SADDLE JUNCTION ELECTRIC FIELD IN EDGE TERMINATION - This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination. | 2016-01-07 |
20160005810 | SEMICONDUCTOR DEVICE - A highly reliable semiconductor device with high withstand voltage is provided. As means therefor, an impurity concentration in a first JTE region is set to 4.4×10 | 2016-01-07 |