02nd week of 2009 patent applcation highlights part 28 |
Patent application number | Title | Published |
20090010009 | LED FLAT-PLATE TYPE MULTI-CHIP HIGH POWER LIGHT SOURCE - The present invention provides a LED flat-plate type multi-chip high power light source comprising a heat dissipating substrate, a reflecting cover mounted on the heat dissipating substrate, LEDs mounted on the heat dissipating substrate and in the reflecting cover, a circuit board embedded in the heat dissipating substrate connecting to the LEDs, and the circuit board also connecting to a socket set in the heat dissipating substrate. The heat dissipating substrate is made of high heat conduction metal. In the present invention, the heat dissipating substrate is made of high heat conduction metal, and the heat conducting pole is abolished. Comparing with the conventional art, the present invention decreases the heat dissipating path, increases the sectional area, and eliminates the intermediate link of high thermal resistance. | 2009-01-08 |
20090010010 | LED DIRECT-PLUGGING TYPE MULTI-CHIP HIGH POWER LIGHT SOURCE - The present invention provides a LED direct-plugging type multi-chip high power light source, comprising a heat dissipating substrate, a protecting rubber ring mounted at the obverse of the heat dissipating substrate, LEDs fixed on the heat dissipating substrate and in the protecting rubber ring, the heat dissipating substrate being provided with two through holes impenetrating its obverse and inverse, in each of the two through holes separately provided with a pin connecting to the LEDs, one end of the pin inserted into the through hole and the other end of the pin led out from the inverse of the heat dissipating substrate to the outside of the heat dissipating substrate, and the part of the pins inserted in the through holes being separated from the heat dissipating substrate by a dielectric. The heat dissipating substrate is made of high heat conduction metal. In the present invention, the heat dissipating substrate is made of high heat conduction metal, and the heat conducting pole is abolished. Comparing with the conventional art, the present invention decreases the heat dissipating path, increases the sectional area, and eliminates the intermediate link of high thermal resistance. The present invention increases the power of a single light source, decreases the attenuation of light greatly, and increases the useful life greatly. | 2009-01-08 |
20090010011 | Solid state lighting device with heat-dissipating capability - A solid state lighting device includes a heat-dissipating base, a diode chip, and a plurality of conductive terminals. The heat-dissipating base includes a base body formed integrally from a thermally conductive material. The base body has a top side, and is formed with a cavity that is indented from the top side. The base body further has a plurality of terminal channels, each of which extends from the cavity to an exterior of the base body. The diode chip is disposed in the cavity. Each of the conductive terminals extends through a respective one of the terminal channels, and has a first connecting part that is disposed in the cavity and that is coupled electrically to the diode chip, and a second connecting part that is disposed outwardly of the heat-dissipating base. | 2009-01-08 |
20090010012 | METHODS AND SYSTEMS OF ATTACHING A DEOCRATIVE LIGHT MOUNTING DEVICE - A method and system of attaching a decorative light mounting structure. At least some of the illustrative embodiments are decorative light mounting devices comprising a bulb support portion having an aperture and an affixation portion coupled to the bulb support portion. The affixation portion is configured to magnetically affix the decorative light mounting structure to substantially only an upper surface of a metallic roofing material. | 2009-01-08 |
20090010013 | Light for a vehicle, particularly flash warning light for an aircraft - The light for a vehicle, particularly a flash warning light for an aircraft, is provided with at least one LED ( | 2009-01-08 |
20090010014 | Reading light having diffused light suppression - An individual cabin illumination device in an aircraft, the device having a light source associated with a passenger or with a group of passengers and an antidazzle device, wherein the antidazzle device includes a multitude of light-directing units which may be arranged one beside the other. Each light-directing unit includes a light-inlet aperture, a light-outlet aperture and a wall that connects the light-inlet aperture to the light-outlet aperture, wherein the light-directing units allow diffusion of the light that can be given off by the light source essentially only onto the passengers associated with the light source. | 2009-01-08 |
20090010015 | BICYCLE SAFETY LIGHTING - A bicycle or moped lighting system projects light onto a rider's moving legs to make the rider more visible to motor vehicle operators and thereby improve the rider's safety. A single safety light fixture is mounted below the bicycle seat and directs diverging light beams towards the backs of both of the rider's legs. While peddling, the motion of the lighted legs attracts the attention of the motor vehicle operators thereby improving rider visibility. A second light fixture may reside ahead of the rider to direct diverging light beams onto the fronts of the rider's moving legs. | 2009-01-08 |
20090010016 | VEHICLE LIGHTING DEVICE - A vehicle lighting device is mounted in a bicycle. The lighting device includes a cantilever, a light-emitting lamp, and a power generating unit. The cantilever is fixed on a frame of the bicycle, so as to support the power generating unit to urge the power generating unit against a wheel of the bicycle constantly. The power generating unit includes an induction coil winding, a magnetic rotor, and a roller. The induction coil winding is wound around a winding axis. A rotating axis of the magnetic rotor is perpendicular to the winding axis. When wheels of the bicycle rotate, the roller and the magnetic rotor are driven to rotate relative to the induction coil winding, such that the induction coil winding generates an inductive electric power, which is supplied to the light-emitting lamp. Thus, a low-cost and labor-saving vehicle lighting device is developed. | 2009-01-08 |
20090010017 | LIGHT EMITTING DEVICE - A light emitting device comprises; a metal reflecting member, a light emitting element fixed to the metal reflecting member, a glass film that covers the metal reflecting member and has Si—N bonds, and a translucent resin that covers the glass film. The present invention provides a light emitting device with which, even when this device is used in a harsh environment, there will be no deterioration in the light reflecting performance of the metal reflecting member, and light can be emitted at high output over an extended period. | 2009-01-08 |
20090010018 | Fiberoptic Cable Assembly - A fiberoptic cable assembly includes a cable provided as a continuous length of a bundle of optic fibers enclosed within a flexible sheathing and a rigid or semi-rigid protective pistol-grip handle formed about at least a portion of one of the ends of the bundle of optic fibers. The handle includes a grip section, an elongate extension extending from the grip section, and an end fitting connected to an end tip on the extension. The extension extends from the grip section at an angle in a manner forming an elbow therebetween and providing a pistol grip configuration. Preferably, the elongate extension is of a length multiple times greater than its diameter or width. | 2009-01-08 |
20090010019 | Method and apparatus for illuminating tile - Illumination of stationary objects to provide adequate illumination in rooms and/or hallways, along walkways, on stairs, around swimming pools, etc. to prevent accidents and illuminate obstacles, leading people to entrances and/or exits and the like. Similarly, illumination of stationary objects may be for decorative purposes. | 2009-01-08 |
20090010020 | LINEAR LIGHTING APPARATUS AND IMAGE READER USING THE SAME - Conventional methods using two optical waveguide members are disadvantageous in cost because they require two optical waveguide members and pairs of their associated components. A linear lighting apparatus includes a rod-like optical waveguide member ( | 2009-01-08 |
20090010021 | RECREATIONAL APPARATUS AND METHOD OF MAKING THE SAME - A recreational apparatus includes a base layer forming one opposed side of the apparatus. A core layer is established on the base layer, the core layer having a fiber optic sheet assembly integration pocket defined therein. A fiber optic sheet is established in the integration pocket. The fiber optic sheet has a plurality of protrusions therethrough. An illumination source and a power supply are each operatively connected to the fiber optic sheet. A cover layer is established on the fiber optic sheet and the core layer. | 2009-01-08 |
20090010022 | MULTI-FUNCTIONAL LED LAMP - A multi-functional LED lamp is mainly composed of a lamp base, an illuminant device, a light guide device and a lampshade. The illuminant device is provided with plural LED bulbs planted on a laminate that is fixed on the lamp base with a heat-conductive medium spread in between. Heat generated by the illuminant device is dispersed by the lamp base. The light guide device is transparent, placed at a place where the illuminant device is to emit, used to conduct the light beams and promote its brightness. The lampshade is covered on the light guide device and the illuminant device. With features of low energy consumption, long service life and high luminous efficiency for LEDs and a good cooling member, the LED lamp is really energy saving and high-efficient. | 2009-01-08 |
20090010023 | LIGHT SOURCE HAVING TRANSPARENT LAYERS - A system for providing a light source is disclosed. In one embodiment, the apparatus comprises a light guide made of several transparent layers having different refractive indexes. | 2009-01-08 |
20090010024 | OPTICAL PLATE AND BACKLIGHT MODULE USING THE SAME - An exemplary optical plate includes at least one transparent plate unit. The transparent plate unit includes a first surface, a second surface, a plurality of first protrusions, a plurality of second protrusions and a lamp-receiving portion. The second surface is opposite to the first surface. The first protrusions are formed at the first surface, and each first protrusion is a rectangular pyramidal protrusion. The second protrusions are formed at the second surface, and each second protrusion is a conical frustum protrusion. The lamp-receiving portion is defined in one of the first surface and the second surface. A backlight module using the optical plate is also provided. | 2009-01-08 |
20090010025 | Light source device, display apparatus, and optical member - An optical member is disposed between an optical sheet and a pair of middle chassis and top chassis that securely support an edge of an liquid crystal panel and an edge of the optical sheet. The optical member reflects light emitted from light-emitting diodes at high reflectivity so that an amount of light loss through the edge of the optical sheet is reduced. This allows for higher light utilization efficiency, thereby enhancing the brightness. | 2009-01-08 |
20090010026 | Radiating element for light panels and light panel manufactured using said radiating element - A radiating element for light panels includes a face providing a light radiation-emitting surface, a light source for sideward light generation and an element for reflecting and/or scattering the incident light. In one embodiment, the radiating element includes a half-shell shaped plate with a polygonal or round plan shape. A concave reflection and/or scattering side of the half shell faces the emitting surface and a central area opposite thereto defines an opening for receiving a light source, such that the light radiation emitted from the emitting head in a sideward direction is reflected and/or scattered in a predetermined percentage in a direction incident upon a light-emitting surface oriented transversally, preferably perpendicularly, to the central axis of symmetry of the reflection and/or scattering element. A light panel may be manufactured using one or a plurality of such radiating elements, which may arranged individually or in clusters. | 2009-01-08 |
20090010027 | SWITCHING POWER SUPPLY APPARATUS - A switching power supply apparatus which includes a DC power supply, an isolation transformer having primary, secondary and tertiary windings, and a switching element, and in which, by turning the switching element on and off, the high-frequency voltage appearing in the secondary windings of the isolation transformer is rectified to obtain a DC output, power consumption can be decreased during standby (in burst mode) in particular by means of a control circuit which controls the turn-on and turn-off of the element and similar. | 2009-01-08 |
20090010028 | INDUCTIVE POWER SUPPLY, REMOTE DEVICE POWERED BY INDUCTIVE POWER SUPPLY AND METHOD FOR OPERATING SAME - An inductive power supply includes a transceiver for sending information between the remote device and the inductive power supply. The remote device determines the actual voltage and then sends a command to the inductive power supply to change the operating frequency if the actual voltage is different from the desired voltage. In order to determine the actual voltage, the remote device determines a peak voltage and then applies a correction factor. | 2009-01-08 |
20090010029 | POWER CONVERTER - An apparatus to convert a direct current to an alternating current includes a power module disposed between an input terminal of the direct current and output terminal of the alternating current, the power module comprising an on/off switch element, a first smoothing condenser connected in parallel with the power module, a second smoothing condenser connected in parallel with the power module, the second smoothing condenser comprising an electrostatic capacity less than the first smoothing condenser, a first wiring connecting the power module and the first smoothing condenser, and a second wiring connecting the power module and the second smoothing condenser, the second wiring comprising an inductance greater than the first wiring. | 2009-01-08 |
20090010030 | Power supply circuit with feedback circuit - An exemplary power supply circuit ( | 2009-01-08 |
20090010031 | ZERO-VOLTAGE-SWITCHING ELECTRIC CONVERTER - The zero-voltage-switching electric converter comprises a power source configured to provide DC current and having a first terminal and a second terminal, a switching circuit having a third terminal electrically connected to the first terminal of the power source and a fourth terminal, and a resonant load having a fifth terminal electrically connected to the second terminal of the power source and a sixth terminal connected to the fourth terminal of the switching circuit. The power source, the switching circuit and the resonant load are connected to form a loop, and the net energy fed into the switching circuit is zero. | 2009-01-08 |
20090010032 | Power supply capable of reducing secondary-side noise - A switching power supply capable of reducing secondary-side noise mainly has at least one decoupling device for guiding the secondary-side noise to at least a terminal of an AC power supply. Thus, the secondary-side high-frequency noise can be reduced, and the quality in using the electronic apparatus product, which is electrically connected to the output of the switching AC-to-DC power supply, can be greatly enhanced. | 2009-01-08 |
20090010033 | ACTIVE DIODE - An active diode is disclosed. One embodiment provides a method for operating a device. The electronic device includes a transistor connected between a first and a second connection of the electronic device; a control device coupled to a control connection of the transistor; and an energy storage device coupled to the control device. | 2009-01-08 |
20090010034 | START SIGNAL DETECTOR CIRCUIT - A variation of a threshold of diode-connected transistors is compensated for to maintain a constant rectification efficiency of a rectifier circuit, thereby enabling stable detection of a start signal. A constant voltage is applied to DC bias terminal of cascaded half-wave voltage doubler rectifier circuits (including MOS transistors M | 2009-01-08 |
20090010035 | Boost and up-down switching regulator with synchronous freewheeling MOSFET - A freewheeling MOSFET is connected in parallel with the inductor in a switched DC/DC converter. When the freewheeling MOSFET is turned on during the switching operation of the converter, while the low-side and energy transfer MOSFETs are turned off, the inductor current circulates or “freewheels” through the freewheeling MOSFET. The frequency of the converter is thereby made independent of the lengths of the magnetizing and energy transfer stages, allowing far greater flexibility in operating and converter and overcoming numerous problems associated with conventional DC/DC converters. For example, the converter may operate in either step-up or step-down mode and may even transition for one mode to the other as the values of the input voltage and desired output voltage vary. | 2009-01-08 |
20090010036 | SEMICONDUCTOR MEMORY - A semiconductor memory includes a memory cell array area having a memory cell, a word line contact area adjacent to the memory cell array area, a word line arranged straddling the memory cell array area and the word line contact area, a contact hole provided on the word line in the word line contact area, and a word line driver connected to the word line via the contact hole. A size of the contact hole is larger than a width of the word line, and the lowest parts of the contact hole exist on a position lower than a top surface of the word line and higher than a bottom surface of the word line. | 2009-01-08 |
20090010037 | SEMICONDUCTOR MEMORY DEVICE WITH FERROELECTRIC DEVICE - A semiconductor memory device comprises a one-transistor (1-T) field effect transistor (FET) type ferroelectric device connected between a pair of bit lines and controlled by a word line, where a different channel resistance is induced to a channel region depending on a polarity state of a ferroelectric layer; a plurality of access transistors connected between the ferroelectric device and the pair of bit lines; and a plurality of port word lines configured to select the plurality of access transistors. | 2009-01-08 |
20090010038 | LOW RESISTANCE PLATE LINE BUS ARCHITECTURE - An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times. | 2009-01-08 |
20090010039 | NON-VOLATILE MEMORY DEVICE - According to one embodiment, a nonvolatile memory device includes: a memory cell array including memory cells each having a variable resistance element for nonvolatilely storing data identified by an electrically rewritable resistance value; a first data latch storing write and erase data to be written on a given group of memory cells of the memory cell array for a write and erase operation; and a second data latch storing reference data for performing a compensation operation of the given group to compensate write and erase disturbance accompanied by the write or erase operation. | 2009-01-08 |
20090010040 | RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device includes: a memory chip having memory cells of a resistance change type; and a heater so attached to the memory chip as to apply a temperature bias to the memory chip. | 2009-01-08 |
20090010041 | Hybrid DRAM - In one embodiment, a hybrid DRAM is provided that includes: a sense amplifier including a differential amplifier and regenerative latch, wherein the differential amplifier and regenerative latch are constructed using core transistors that have a relatively thin gate oxide; and a plurality of memory cells coupled to the sense amplifier through a pair of bit lines, wherein each memory cell includes an access transistor coupled to a storage cell, the access transistor having a relatively thick gate oxide, whereby the storage capacitor is capable of being charged to a VIO power supply voltage that is greater than a VDD power supply voltage for the core transistors. | 2009-01-08 |
20090010042 | Semiconductor integrated circuit device - In an integrated circuit device, there are various optimum gate lengths, thickness of gate oxide films, and threshold voltages according to the characteristics of circuits. In a semiconductor integrated circuit device in which the circuits are integrated on the same substrate, the manufacturing process is complicated in order to set the circuits to the optimum values. As a result, in association with deterioration in the yield and increase in the number of manufacturing days, the manufacturing cost increases. In order to solve the problems, according to the invention, transistors of high and low thresholds are used in a logic circuit, a memory cell uses a transistor of the same high threshold voltage and a low threshold voltage transistor, and an input/output circuit uses a transistor having the same high threshold voltage and the same concentration in a channel, and a thicker gate oxide film. | 2009-01-08 |
20090010043 | Configurable SRAM System and Method - A static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM cell. In another example, an independent mode includes isolating a first SRAM cell from a second SRAM cell such that they operate independently. | 2009-01-08 |
20090010044 | Toggle Magnetic Random Access Memory and Write Method of Toggle Magnetic Random Access Memory - A toggle magnetic random access memory includes a first memory array, a second memory array and a controller. The first memory array includes a plurality of first memory cells including magnetoresistive elements. The second memory array includes a plurality of second memory cells including magnetoresistive elements and differs from the first memory array in write wirings used for writing. The controller controls the first memory array and the second memory array such that a first state in which a first burst write operation in the first memory array is executed and a second state in which a second burst write operation in the second memory array is executed are alternately executed in a continuous burst write mode. Accordingly, the continuous burst write operation can be executed at the high speed without any drop in the reliability and any increase in the circuit area. | 2009-01-08 |
20090010045 | MAGNETORESISTIVE RANDOM ACCESS MEMORY - A MRAM includes a first magnetoresistive effect (MR) element that takes a low and high resistance states. A second MR element is fixed to a low or high resistance state. First and second MOSFETs are connected to the first and second MR elements, respectively. A sense amplifier amplifies a difference between values of current flowing through the first and second MOSFETs. A current circuit outputs reference current whose value lies between current flowing through the first MR element of the low and high resistance states. A third MOSFET has one end that receives the reference current and is connected to its own gate terminal. The gate terminal of the second MOSFET receives the same potential as the gate terminal of the third MOSFET. A first resistance element is connected to the others end of the third MOSFET and has the same resistance as the second magnetoresistive effect element. | 2009-01-08 |
20090010046 | MAGNETIC MEMORY DEVICE WITH NON-RECTANGULAR CROSS SECTION CURRENT CARRYING CONDUCTORS - Embodiments of the invention magnetic memory device, comprising: a plurality of magnetic memory cells, each comprising: a magnetic memory element capable of being flipped between two stable spin orientations under the influence of an applied magnetic field; and current-carrying conductors proximate the magnetic element to carry a current that induces said applied magnetic field, wherein the current-carrying conductors have a non-rectangular cross section; and a read circuit for reading data from the selected magnetic memory cells. | 2009-01-08 |
20090010047 | WRITING CIRCUIT FOR A PHASE CHANGE MEMORY - A phase change memory writing circuit is provided. The circuit comprises a writing path and a fast write control unit. The writing path further comprises a current driving unit, a first switch device and a phase change memory cell. The current driving unit is coupled to a high voltage source and outputs a driving current. The first switch device is controlled by a first control signal. The fast write control unit is coupled to the writing path to provide a writing voltage to the writing path. When the first switch device is turned off, the fast write control unit outputs the writing voltage to the writing path. When the first switch device is turned on, the fast write control unit stops outputting the writing voltage to the writing path. | 2009-01-08 |
20090010048 | MEMORY DEVICE INCLUDING A PROGRAMMABLE RESISTANCE ELEMENT - Disclosed are a phase change memory with improved retention characteristic of a phase change device, and a method for refreshing the phase change memory. The fact that a memory is a DRAM interface compatible memory is exploited. There are provided dummy cells stressed in accordance with the number of times of read and write operations. Changes in the resistance value of the dummy cells are detected by comparator circuits. If the resistance value have been changed beyond a predetermined reference value (that is, changed to a low resistance), a refresh request circuit requests an internal circuit, not shown, to effect refreshing. The memory cells and the dummy cells are transitorily refreshed and correction is made for variations in the programmed resistance value of the phase change devices to assure the margin as well as to improve retention characteristic. | 2009-01-08 |
20090010049 | Phase change memory device - A phase change memory device is constituted of a plurality of memory cells including a plurality of phase change memory elements, which are arranged at intersecting points formed between a plurality of word lines and a plurality of bit lines. A write circuit which operates based on a write voltage source (Vwrite) is controlled by control signals (e.g. WE, RDIS, SDIS, and DIN) output from a control circuit which operates based on a voltage source (VDD), where Vwrite>VDD. All the control signals based on VDD are applied to the gates of N-channel MOS transistors included in the write circuit. This allows adequately high write currents to be supplied to phase change memory elements; and this eliminates the necessity of arranging a potential switch circuit in the write circuit, thus reducing the scale of the phase change memory device. | 2009-01-08 |
20090010050 | Calibration system for writing and reading multiple states into phase change memory - A memory system includes phase change memory cells. A control module causes one of the phase change memory cells to be written using a write parameter, causes a resistance value of the one of the phase change memory cells to be read back, adjusts the write parameter, and causes the writing, reading and adjusting to be repeated until the resistance value is within a predetermined range of a target resistance value. | 2009-01-08 |
20090010051 | Reading a phase change memory - A phase change memory cell may be read by driving a current through the cell higher than its threshold current. A voltage derived from the selected column may be utilized to read a selected bit of a phase change memory. The read window or margin may be improved in some embodiments. A refresh cycle may be included at periodic intervals. | 2009-01-08 |
20090010052 | One-transistor type dram - A one-transistor type DRAM including a floating body storage element connected between a bit line and a source line and controlled by a word line comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a plurality of clamp bit lines and reference bit lines arranged in a column direction, a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a clamp cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a reference cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, and a sense amplifier and a write driving unit connected to the bit line and configured to receive a clamp voltage and a reference voltage. | 2009-01-08 |
20090010053 | COMBO MEMORY CELL - A combo memory cell comprising a SRAM cell and a mask-ROM code programmer. The SRAM cell comprises first and second inverters. The first inverter comprises a first PMOS transistor and a first NMOS transistor. Gates of the first PMOS and NMOS transistors are commonly connected to a first input node and drains thereof commonly connected to a first output node. The second inverter comprises a second PMOS transistor and a second NMOS transistor. Gates of the second PMOS and NMOS transistors are commonly connected to a second input node and drains thereof commonly connected to a second output node. The first input node and the second output node are connected, as are the second input node and the first output node. The mask-ROM code programmer is coupled to the sources of the first and second PMOS transistors or the first and second NMOS transistors. | 2009-01-08 |
20090010054 | SEMICONDUCTOR MEMORY DEVICE WITH FERROELECTRIC DEVICE - A semiconductor memory device includes a one-transistor (1-T) field effect transistor (FET) type memory cell connected between a pair of bit lines, and controlled by a word line, where a different channel resistance is induced to a channel region depending on a polarity state of a ferroelectric layer. The device comprises a plurality of word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a pair of clamp dummy lines arranged in the column direction, a pair of reference dummy lines arranged in the column direction, a cell array including the memory cell and formed in a region where the word line and the bit line are crossed, a dummy cell array including the memory cell and formed where the word line, the pair of claim dummy lines and the pair of reference dummy lines are crossed, and a sense amplifier and a write driving unit connected to the bit line and configured to receive a clamp voltage and a reference voltage. | 2009-01-08 |
20090010055 | One-transistor type DRAM - A one-transistor type DRAM comprises a floating body storage element configured to store data in a floating body in a SOI wafer, a plurality of access transistors each connected between a bit line and one end of the floating body storage element, a word line configured to control the floating body storage element, and a plurality of port word lines each configured to select one of the plurality of access transistors. | 2009-01-08 |
20090010056 | Method and apparatus for capacitorless double-gate storage - A method and/or system and/or apparatus for a dual gate, capacitor less circuit that can act as a state storage device. Further embodiments describe fabrication methods and methods of operation of such a device. | 2009-01-08 |
20090010057 | SEMICONDUCTOR MEMORY DEVICE WITH MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE AND MEMORY SYSTEM - A semiconductor memory device includes first memory cell transistors, a memory block, and word lines. Each of the first memory cell transistors has a stacked gate including a charge accumulation layer and a control gate and is capable of holding M bits (M≠2 | 2009-01-08 |
20090010058 | MULTI-BIT NON-VOLATILE MEMORY DEVICE, METHOD OF OPERATING THE SAME, AND METHOD OF FABRICATING THE SAME - A multi-bit non-volatile memory device and methods of operating and fabricating the same may be provided. The memory device may include a channel region formed in a semiconductor substrate, and a source and drain that form a Schottky contact with the channel region. Also, a central gate electrode may be located on a portion of the channel region, and first and second sidewall gate electrodes may be formed on the channel region along the outer sides of the central gate electrode. First and second storage nodes may be formed between the channel region and the sidewall gate electrodes. | 2009-01-08 |
20090010059 | Memory Arrangement, Particularly for the Non-Volatile Storage of Uncompressed Video and/or Audio Data - When recording uncompressed video and/or audio data using a digital video recorder, there is the need for a robust memory arrangement based on non-volatile, integrated circuits which is able to be fitted directly on the video camera without a long external cable connection and which is also able to be used for shots under difficult conditions, particularly action shots. The inventive memory arrangement involves the use of a number of non-volatile memory chips which are connected together with a favorable level of circuit complexity. To be able to cope with the high data rate for the incoming video and/or audio data, a plurality of parallel supply buses are provided. Each supply bus has an associated number of memory chips. In this case, the memory word length of the memory chips is greater than the bus width of a data/address bus. A supply bus with high-quality multiplexing has a respective associated number of demultiplexer/driver circuits which match the bus width of the supply bus to the memory word length of the memory chips. There are respectively as many downstream memory chips per demultiplexer/driver circuit as prescribed by a value X, the value X being limited by the memory technology used, namely by the maximum number of circuits which can be connected, also called the “fan-out” value. The memory chips used are preferably NAND Flash EPROM memory chips. | 2009-01-08 |
20090010060 | Bit line decoder architecture for nor-type memory array - A bit line decoder for sensing states of memory cells of a memory array includes D control devices and a control module. The D control devices selectively communicate with (D−1) bit lines of the memory array and are arranged in first and second levels of the bit line decoder. (D−2) of the D control devices are arranged in the first level, and two of the D control devices are arranged in the second level. log | 2009-01-08 |
20090010061 | Bit line decoder architecture for NOR-type memory array - A bit line decoder for sensing states of memory cells of a memory array includes a first sub-decoder, a control module, and an isolation circuit. The first sub-decoder is adjacent to the memory array and includes D control devices arranged in a first of two levels of the bit line decoder. The D control devices selectively communicate with a first set of S of B bit lines of the memory array, where log | 2009-01-08 |
20090010062 | Bit line decoder architecture for NOR-type memory array - A bit line decoder for sensing states of memory cells of a memory array includes R first sub-decoders, R isolation circuits, a second sub-decoder, and a sensing circuit. The R first sub-decoders communicate with R memory sub-arrays of the memory array, respectively, where R is an integer greater than 1. The R isolation circuits each have first ends that communicate with the R first sub-decoders, respectively, and second ends. The second ends of a first of the R isolation circuits communicate with corresponding the second ends of (R- | 2009-01-08 |
20090010063 | NAND TYPE FLASH MEMORY AND WRITE METHOD OF THE SAME - A NAND type flash memory includes first to third memory cell transistors having current paths connected in series between one end of a current path of each of first and second selection transistors, and each having a control gate and a charge storage layer, the first and second memory cell transistors being adjacent to the first and second selection transistors, the third memory cell transistor being positioned between the first and second memory cell transistors, the third memory cell transistor holding data having not less than three bits, the first memory cell transistor holding 2-bit data in which middle and upper pages is written by skipping a lower page, and a lower page verify voltage being set when writing the middle page, and a middle page verify voltage is set when writing the upper page, changing a position of a threshold distribution of the first memory cell transistor. | 2009-01-08 |
20090010064 | NAND FLASH CELL STRUCTURE - NAND architecture Flash memory strings, memory arrays, and memory devices are described that utilize continuous channel enhancement and depletion mode floating gate memory cells. Depletion mode floating gate memory cells allow for increased cell current through lower channel r | 2009-01-08 |
20090010065 | NON-VOLATILE MEMORY USING MULTIPLE BOOSTING MODES FOR REDUCED PROGRAM DISTURB - A non-volatile storage system which reduces program disturb. Multiple boosting modes are implemented while programming non-volatile storage. For example, self-boosting, local self-boosting, erased area self-boosting and revised erased area self-boosting may be used. One or more switching criteria are used to determine when to switch to a different boosting mode. The boosting mode may be used to prevent program disturb in unselected NAND strings while storage elements are being programmed in selected NAND strings. By switching boosting modes, an optimal boosting mode can be used as conditions change. The boosting mode can be switched based on various criteria such as program pulse number, program pulse amplitude, program pass number, the position of a selected word line, whether coarse or fine programming is used, whether a storage element reaches a program condition and/or a number of program cycles of the non-volatile storage device. | 2009-01-08 |
20090010066 | FLASH MEMORY DEVICE AND METHOD IN WHICH TRIM INFORMATION IS STORED IN MEMORY CELL ARRAY - A flash memory device which includes a memory cell array which stores data and trim information, and control logic which controls programming, erasing, and reading modes of the memory cell array. The control logic is operative to receive the trim information from the memory cell array in a power-up mode, and to optimize operational time periods of the programming, erasing, and reading modes in accordance with the trim information. | 2009-01-08 |
20090010067 | COARSE/FINE PROGRAM VERIFICATION IN NON-VOLATILE MEMORY USING DIFFERENT REFERENCE LEVELS FOR IMPROVED SENSING - Coarse/fine programming of non-volatile memory is provided in which memory cells are programmed at a first rate of programming prior to reaching a coarse verify level for their intended state and a second rate of programming after reaching the coarse verify level but before reaching the final verify level for their intended state. Large sub-threshold swing factors associated with smaller memory cells can affect the accuracy of sense operations, particularly when sensing at a fine verify level after sensing at a coarse verify level without pre-charging the bit line between the different sensings. Different reference potentials are utilized when sensing at a coarse verify level and a final verify level. The different between the reference potentials can compensate for any discharge of the bit line during the coarse level sensing. | 2009-01-08 |
20090010068 | Systems for Coarse/Fine Program Verification in Non-Volatile Memory Using Different Reference Levels for Improved Sensing - Coarse/fine programming of non-volatile memory is provided in which memory cells are programmed at a first rate of programming prior to reaching a coarse verify level for their intended state and a second rate of programming after reaching the coarse verify level but before reaching the final verify level for their intended state. Large sub-threshold swing factors associated with smaller memory cells can affect the accuracy of sense operations, particularly when sensing at a fine verify level after sensing at a coarse verify level without pre-charging the bit line between the different sensings. Different reference potentials are utilized when sensing at a coarse verify level and a final verify level. The different between the reference potentials can compensate for any discharge of the bit line during the coarse level sensing. | 2009-01-08 |
20090010069 | SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING A SEMICONDUCTOR DEVICE - The present invention is directed to a semiconductor device having a non-volatile memory cell | 2009-01-08 |
20090010070 | Method of writing to non-volatile semiconductor memory device storing information depending on variation in level of threshold voltage - In a flash memory, after an initial write operation ends, each bit line associated with a memory cell subjected to a write is precharged and each bit line associated with a memory cell that is not subjected to the write is discharged and verified to detect a memory cell low in threshold voltage and a memory cell thus detected is subjected to an additional write. The verification can be verified without being affected by a current flowing through the memory cell that is not subjected to the write. All memory cells can have their respective threshold voltages set accurately. | 2009-01-08 |
20090010071 | NONVOLATILE MEMORY DEVICE AND ERASING METHOD - Disclosed is an erasing method for a nonvolatile memory device that includes erasing selected memory cells and erase-verifying the selected memory cells after increasing their threshold voltage by application of a negative bulk bias voltage. | 2009-01-08 |
20090010072 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of nonvolatile memory cells ( | 2009-01-08 |
20090010073 | Non-Volatile Memory System Including Spare Array and Method of Erasing a Block in the Same - Methods of operating non-volatile memory devices can compensate for threshold voltage disturbances caused by overhead data programming during block erase operations. These methods include erasing a spare array of nonvolatile memory cells and a corresponding main array of nonvolatile memory cells that shares word lines with the spare array. This erasing operation is followed by writing updated overhead data (e.g., an erase count) into the spare array and then performing a soft program operation. This soft program operation is performed on at least a first portion of the main array to thereby narrow a threshold voltage distribution of erased memory cells within the first portion of the main array. The soft program operation is then followed by an operation to verify an erased status of at least the first portion of the main array and an operation to communicate that the main and spare arrays of nonvolatile memory cells have been properly erased to a memory controller. | 2009-01-08 |
20090010074 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a semiconductor layer provided on an insulating substrate or an insulating layer; active areas each defined in the semiconductor layer with a device insulating film buried therein; and NAND cell units formed on the active areas, each NAND cell unit including a plurality of electrically rewritable and non-volatile memory cells connected in series, both ends of each NAND cell unit being coupled to a source line and a bit line, wherein the device has such a carrier discharging mode as to discharge channel carriers in the NAND cell unit to at least one of the source line and the bit line. | 2009-01-08 |
20090010075 | NROM memory cell, memory array, related devices and methods - An array of memory cells configured to store at least one bit per one F | 2009-01-08 |
20090010076 | SEMICONDUCTOR DEVICE AND CONTROLLING METHOD FOR THE SAME - A semiconductor device has a plurality of bit lines BL provided in a memory cell area | 2009-01-08 |
20090010077 | SHIFT REGISTER LATCH WITH EMBEDDED DYNAMIC RANDOM ACCESS MEMORY SCAN ONLY CELL - A hybrid shift register latch which uses static memory cells for system operations and a dynamic memory cell for testing operations only. An L1 storage element and an L2 storage element are provided in an array cell. The L1 storage element comprises a static random access memory cell. The L1 storage element is used during system and testing operation of the array cell. The L2 storage element comprises a dynamic random access memory cell. The L2 storage element is used only during testing operation of the array cell. | 2009-01-08 |
20090010078 | Semiconductor memory device - A semiconductor memory device includes: an input pad set configured to receive an external input signal and a reference voltage; an input buffer set configured to detect and transmit the input signal to an internal circuit of the semiconductor memory device by comparing the input signal with the reference voltage; and a reference voltage generation circuit configured to generate the reference voltage to supply the reference voltage to the input pad set and the input buffer set during a test operation, the reference voltage generation circuit being deactivated after the semiconductor memory device is packaged. | 2009-01-08 |
20090010079 | One-transistor type dram - A one-transistor type DRAM includes a floating body storage element connected between a bit line and a source line and controlled by a word line. The DRAM comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a plurality of reference bit lines arranged in a column direction, a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a reference cell array including the floating body storage element, formed in a region where the source line, the word line and the bit line are crossed and configured to output a reference current having a plurality of levels, a plurality of reference voltage generating units connected to the reference bit lines and configured to generate a plurality of reference voltages corresponding to the reference current having a plurality of levels, and a sense amplifier and a write driving unit connected to the bit line and configured to receive the plurality of reference voltages. | 2009-01-08 |
20090010080 | SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF CONTROLLING THE SAME - An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells. | 2009-01-08 |
20090010081 | OVERDRIVE WRITE METHOD, WRITE AMPLIFIER POWER GENERATING CIRCUIT, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A write amplifier power generating circuit includes a control unit for changing an output voltage. In a first write cycle in which a pair of bit lines are being amplified, a write operation is performed by an overdrive write method in which a high level from a write amplifier is set to a first voltage (for example, a power supply voltage). In a second write cycle after amplification in the pair of the bit lines has been completed, a write operation is performed by a write method in which the high level from the write amplifier is set to a second voltage (for example, an internal voltage). | 2009-01-08 |
20090010082 | DATA TRANSFER APPARATUS IN SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - A data transfer apparatus in a semiconductor memory device includes a DQ pad, a DQS pad, a DQ driver for transferring the data signal to the DQ pad according to a driver select signal, and a DQS driver for transferring data strobe signal to the DQS pad according to the driver select signal. Any one of the DQ driver and the DQS driver is activated by the driver select signal, and the driver select signal is generated by one of EMRS control code, MRS control code and test mode code. | 2009-01-08 |
20090010083 | CLOCK CIRCUITRY FOR DDR-SDRAM MEMORY CONTROLLER - A circuit for providing a delayed clock signal to a synchronous memory controller controlling a synchronous memory device comprises logic delay circuitry for performing synchronous memory device read access, the logic delay circuitry generating delay interval information. A programmable delay line receives a clock signal and the delay interval information, the programmable delay line delaying the clock signal by the delay interval. A 2-input XOR gate receives both the clock signal and the output of the programmable delay line, an output of the XOR gate providing a delayed 2× clock signal. | 2009-01-08 |
20090010084 | APPARATUS FOR CONTROLLING ACTIVATION OF SEMICONDUCTOR INTEGRATED CIRCUIT - An apparatus for controlling an activation of semiconductor integrated circuit includes: an active control unit configured to generate active control signal for determining activation of banks; and a plurality of active signal generating units configured to input the active control signal commonly, and generate active signals for activating the banks to according to the active control signal. According to this structure, it is possible to reduce current consumption to a minimum in a refresh mode, to easily arrange signal lines, and thus to effectively use extra space. | 2009-01-08 |
20090010085 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND REDUNDANCY METHOD THEREOF - A semiconductor integrated circuit device includes a first fuse circuit, a second fuse circuit, and a control signal generating circuit which sends a first control signal and executes program such that the resistance value of the first fuse circuit becomes greater than the resistance value of the second fuse circuit, and sends a second control signal and executes reprogram such that the resistance value of the second fuse circuit becomes greater than the resistance value of the first fuse circuit. | 2009-01-08 |
20090010086 | SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME - A sense amplifier circuit includes a current sense amplifier, a voltage sense amplifier, and an output stabilizing circuit. The current sense amplifier amplifies differential input currents to generate differential output voltages and provides the differential output voltages to a sense amplifier output line pair. The voltage sense amplifier is coupled to the sense amplifier output line pair to amplify the differential output voltages on the sense amplifier output line pair. The voltage sense amplifier is activated at the time later than a time of activation of the current sense amplifier. The output stabilizing circuit is coupled to the sense amplifier output line pair to stabilize the differential output voltages on the sense amplifier output line pair. The output stabilizing circuit has a positive input resistance. Accordingly, the sense amplifier circuit reduces power consumption and an occupied area on a semiconductor chip. | 2009-01-08 |
20090010087 | DATA WRITE IN CONTROL CIRCUIT FOR TOGGLE MAGNETIC RANDOM ACCESS MEMORY - A data write in control circuit for magnetic random access memory is configured with a first transistor, a second transistor connected to the first transistor, a transmission gate connected to the first transistor, a comparator having two input terminal connected to the first transistor, a storage capacitor having one end connected to the first transistor and the other end connected to a power source or a ground, and a logic circuit having one end connected to the output terminal of the comparator and the other end receiving data to be written in. | 2009-01-08 |
20090010088 | DATA READING CIRCUIT OF TOGGLE MAGNETIC MEMORY - A data reading circuit of a magnetic memory applicable for reading data of a magnetic memory includes a first transistor, a second transistor connected to the first transistor in series, a third transistor, a fourth transistor connected to the third transistor in series, a first transmission gate electrically connected to the first transistor, a second transmission gate electrically connected to the first and third transistors, a comparison circuit having two input ends respectively connected to the first transistor, and a storage capacitor having an end electrically connected to the first transistor and the other end connected to a power end. | 2009-01-08 |
20090010089 | APPARATUS AND METHOD TO STORE INFORMATION IN A HOLOGRAPHIC DATA STORAGE MEDIUM - A method is disclosed to store information in a holographic data storage medium. The method supplies a holographic data storage medium and provides information. The method defines an Active storage portion for the holographic data storage medium and establishes a threshold access interval. The method determines if the information was last accessed within the threshold access interval. If the information was last accessed within said threshold access interval, the method then stores that information as one or more holograms encoded in said Active storage portion of the holographic data storage medium. | 2009-01-08 |
20090010090 | BUCKET BRIGADE ADDRESS DECODING ARCHITECTURE FOR CLASSICAL AND QUANTUM RANDOM ACCESS MEMORIES - In an address signal decoder for a RAM memory, address signals are decoded in a “bucket brigade” address decoding architecture in which the address signals or bits are sequentially sent along the same address decoding path. The inventive architecture comprises a set of node switches linked into a binary tree. The address signals enter at the root node of the binary tree. As each address signal reaches a node switch at the end the path, it sets the path direction for that switch node so that subsequent address signals that follow the path will use that path direction. The decoder can be used with classical or quantum RAM memories. | 2009-01-08 |
20090010091 | ADDRESS COUNTER, SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME, AND DATA PROCESSING SYSTEM - An address counter includes FIFO units and first to third command counters that controls the groups. In the FIFO units, latch circuits including input gates and output gates are connected in parallel. The first command counter conducts any one of the input gates in response to a first internal command; the second command counter conducts any one of the output gates in response to a second internal command; and the third command counter conducts any one of the output gates in response to a third internal command. Thereby, the same address signals can be outputted successively at a plurality of timings, and thus, a circuit scale of the address counter can be reduced. | 2009-01-08 |
20090010092 | ADDRESS COUNTER, SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME, AND DATA PROCESSING SYSTEM - An address counter includes FIFO units and first and second command counters that control the groups. The first command counter has a first mode in which any one of input gates is conducted in response to a first internal command and a second mode in which a plurality of input gates are conducted in response to an internal command. The second command counter has a first mode in which any one of output gates is conducted in response to one of second and third internal commands and second mode in which corresponding output gates are each conducted in response to one of the second and third internal commands. Thereby, when tCCD is small, the first mode can be selected, and when the tCCD is large, the second mode can be selected. | 2009-01-08 |
20090010093 | Method of Adding STMP to a Gypsum Slurry - The disclosure relates to a method for effectively and efficiently adding sodium trimetaphosphate to a gypsum slurry. In one exemplary embodiment, the sodium trimetaphosphate is added at the same time as foam is added to the gypsum slurry through the foam waterline. In another exemplary embodiment, the sodium trimetaphosphate is added at the same time as additional water is added to the gypsum slurry through the gauging waterline. The sodium trimetaphosphate can be added to either or both waterlines in its dry form or in a diluted solution. | 2009-01-08 |
20090010094 | KNEADING MACHINE AND KNEADING CONTROL METHOD - An object of the invention is to provide a mixer and a mixing control method that enable to keep the driving efficiency of a motor high, and to flexibly follow a predetermined rotation speed of a mixing rotor pair, which is varied depending on various applications of the mixing rotor pair. A fixed speed motor is rotated at a constant rotation speed, and a variable speed motor is variably rotated at an arbitrary rotation speed. A difference in rotation speed between the fixed speed motor and the variable speed motor is supplied to the mixing rotor pair as the rotation speed by operations of a sun gear, a planetary gear, an internal gear, and a gear retainer of a planetary gear transmission. | 2009-01-08 |
20090010095 | Automatic device for mixing fluids, particularly paints or varnishes - The invention relates to an automatic device for mixing fluids, particularly paints or varnishes, that are to be sent on to one or more mixing containers ( | 2009-01-08 |
20090010096 | BLENDING DEVICE - A blending device for blending objects is provided. The device preferably includes a conveying module, a cleaning module, a receiving module, a blending & liquefaction module, a discharge module, and a control module. The conveying module carries objects into the receiving module. While transferring the objects, the conveying module is being rinsed and dried by the cleaning module. After the blending & liquefaction module blends and liquefies the objects in the receiving module, the discharge module discharges tile blended and liquefied objects. | 2009-01-08 |
20090010097 | System and Method for Heat Treating a Homogenized Fluid Product - A system and method for heat treating a homogenized fluid product, the method comprising the steps of feeding a stream of fluid product ingredients through a local constriction of flow to effectuate high shear mixing of the fluid product ingredients in a high shear mixing zone downstream from the local constriction of flow and thereby form a homogenized fluid product at a first temperature and introducing a sufficient amount of the homogenized fluid product at a second temperature, which is less than the first temperature, into the high shear mixing zone to effectuate mixing of the homogenized fluid product at the first temperature with the homogenized fluid product at the second temperature to thereby heat treat the homogenized fluid product fluid product. | 2009-01-08 |
20090010098 | BULK TRANSPORT SYSTEM - A flexible bulk container capable of transporting a first material and introducing a second material for mixing therewithin is disclosed wherein 1) said container can comprise a component of a bulk transport system further comprising a container assembly, and 2) said container includes a body defining a cavity, at least one opening, at least one vent, and a material delivery system assembly wherein a) the body is flexible and capable of positioning within the container assembly, b) the opening provides communication with the cavity, and c) the material delivery system assembly comprises at least one manifold, a portion of which is positioned within the cavity of the flexible bulk container, and said manifold includes a shell, an interior region, an inlet accessible from outside of the cavity of the flexible bulk container and at least one passageway extending from the internal region, through the shell, to, in turn, place the interior of the manifold in communication with the cavity. | 2009-01-08 |
20090010099 | DEVICE FOR OBTAINING HIGHLY REACTIVE CALCIUM SORBENTS AND/OR OF BINDING MATERIALS - An apparatus is provided for fabrication of highly reactive calcium sorbents and/or binding materials, from powdered calcium carbonate and/or fly-ashes coming from coal combustion, especially in boilers with fluidised bed furnaces. A method is provided in which ashes with chemical by weight containing from 25% up to 45% SiO | 2009-01-08 |
20090010100 | SYNCHRONOUS RE-SAMPLING BASED SIGNAL EXTRACTION - Sampling of a captured signal is synchronized to a tonal which may be unstable in frequency detected in the signal to cause the detected tonal and all of its harmonics, sub-harmonics and fundamental to appear to have a substantially constant frequency relative to the sampling rate to facilitate observation and other signal processing even if some related signals are otherwise undetectable amid noise. By adjusting an integration period of a corresponding output of a fast Fourier transform to extract an intrinsic bandwidth, substantial signal processing gain can be obtained for the tonal and harmonically related components of the signal, even if some harmonically related signals are otherwise undetectable. Signal processing may be performed in either the time domain or the frequency domain. Recursive processing to observe as many unrelated tones as possible by grouping of tones which are harmonically related. Further recursive processing supports detection of relationships between acoustic signal sources by observation of variations from harmonic frequencies of harmonically related signal components. | 2009-01-08 |
20090010101 | Seismic streamer having longitudinally symmetrically sensitive sensors to reduce effects of longitudinally traveling waves - A seismic streamer includes a jacket and at least one seismic sensor disposed in a sensor holder inside the jacket. The at least one sensor is oriented inside the sensor holder such that a response of the at least one sensor is substantially longitudinally symmetric. | 2009-01-08 |
20090010102 | METHOD FOR ADJUSTING A SEISMIC WAVE VELOCITY MODEL ACCORDING TO INFORMATION RECORDED IN WELLS - The invention is a method for defining the development conditions of a hydrocarbon reservoir by updating a velocity model by means of log data. A first seismic depth image representative of the reservoir is established by using seismic data and a velocity model. A series of log data is acquired from wells. Differences between seismic reflector depths observed in the first seismic depth image and depths for these reflectors identified in the wells are measured. The velocity model is modified to minimize these errors, using a prestack kinematic inversion technique allowing constraints to be taken into account. A new seismic depth image from which the development conditions of the hydrocarbon reservoir are determined is deduced therefrom. The invention has application for hydrocarbon reservoir development. | 2009-01-08 |
20090010103 | EFFICIENT SEISMIC DATA ACQUISITION WITH SOURCE SEPARATION - A method for the simultaneous operation of multiple seismic vibrators using unique modified pseudorandom sweeps and recovery of the transmission path response from each vibrator is disclosed. The vibrator sweeps are derived from pseudorandom binary sequences modified to be weakly correlated over a time window of interest, spectrally shaped and amplitude level compressed. Cross-correlation with each pilot signal is used to perform an initial separation of the composite received signal data set. Recordings of the motion of each vibrator are also cross-correlated with each pilot, windowed, and transformed to form a source cross-spectral density matrix in the frequency domain useful for source signature removal and for additional crosstalk-suppression between the separated records. After source signature removal in the frequency domain an inverse transform is applied to produce an estimate of each source-to-receiver earth response in the time domain. The method has application to both land and marine geophysical exploration. | 2009-01-08 |
20090010104 | METHODS AND SYSTEMS FOR PROCESSING MICROSEISMIC DATA - Methods and systems for processing microseismic waveforms. The methods and systems provide determining a measure of waveform fit in the frequency-domain comprising constructing, in the frequency-domain, at least one of an amplitude misfit functional and a cross phase functional between arrivals; and estimating source parameters and/or model parameters. | 2009-01-08 |
20090010105 | SEISMIC DATA PROCESSING METHOD AND SYSTEM FOR MIGRATION OF SEISMIC SIGNALS INCORPORATING AZIMUTHAL VARIATIONS IN THE VELOCITY - A method and system for seismic data processing utilizes azimuthal variations in the velocity of seismic signals. The system and method utilizes a plurality of seismic energy sources that are located at known positions at the surface of the earth. The seismic energy sources generate seismic signals that propagate downward into the earth. Some of the seismic signals are reflected and diffracted by various sub-surface layers and are returned to the surface of the earth. The returned seismic signals are received by a plurality of receivers. The method includes the step of determining the distance from an energy source to an image point. A fast travel time of the seismic signal from the energy source to the image point is determined, and a slow travel time of the seismic signal from the energy source to the image point is determined. The azimuth angle between the energy source and the surface location of the image point is calculated. A first travel time of the seismic signal traveling from the energy source to the image point is calculated. A second travel time of the seismic signal traveling from the image point to the seismic receiver is calculated. The total travel time is calculated by adding the first and second travel time. The amplitudes from the recorded signal at the total travel time are phase adjusted and added into the output image at the image point. The foregoing steps are repeated for a plurality of image points beneath the surface of the earth and the total travel time is calculated. | 2009-01-08 |
20090010106 | Caregiver personal alert device - The present invention relates to a portable caregiver personal alert device to facilitate the improvement in the delivery of bedside patient care. The device assists caregivers in ensuring time-sensitive tasks are performed within a specific time frame and in a specific sequence to ensure efficiency, compliance with standard of care or regulation and patient comfort. The device of the present invention comprises a display, a microprocessor that monitors various tasks for multiple patients, and at least one user input feature and at least one alarm, capable of alerting a caregiver when it is time to perform the task. The device preferably includes various functions such as a bed assignment mode, a task mode for choosing applicable tasks associated with the needs of one or more bed numbers, and at least one clock for coordinating a plurality of alarms to one or more corresponding bed number and associated task. | 2009-01-08 |
20090010107 | TAMPER-RESISTANT TIME REFERENCE AND APPARATUS USING SAME - A tamper-proof reference usable as a time reference and an integrated circuit apparatus using the tamper-proof reference to determine an elapsed time are disclosed. The circuit comprises a reference source ( | 2009-01-08 |
20090010108 | ELECTRONIC DEVICE WITH AN ALARM CLOCK FUNCTION AND METHOD OF CONTROLLING THE FUNCTION - An electronic device with an alarm clock function including a storage unit storing a preset number and a count number inside; a managing unit for performing or disabling an alarm clock function; a random code generating module for generating and outputting a random code; a random code confirming module for receiving inputs and determining whether the input matches the random code; a recording module for adding 1 to the count number when the input matches the random code; and a number confirming module for comparing the count number with the preset number, disabling the alarm clock function when the count number is equal to the preset number, and informing the random code generating module to re-generate a random code when the count number is not equal to the preset number. A method of disabling alarm clock function is also provided. | 2009-01-08 |