02nd week of 2013 patent applcation highlights part 41 |
Patent application number | Title | Published |
20130011940 | METHOD OF REDUCING DAMAGE TO AN ELECTRON BEAM INSPECTED SEMICONDUCTOR SUBSTRATE, AND METHODS OF INSPECTING A SEMICONDUCTOR SUBSTRATE - Methods for reducing electron beam induced damage on semiconductor substrates employ compositions such as small chain organic solvents and non-neutral pH solutions to reduce or eliminate charge imbalances on semiconductor substrates caused by electron beam inspection of the semiconductor substrates. Damage to semiconductor substrates by electron beam inspection processes may also be reduced by generating or otherwise forming passivation films on a semiconductor substrate following electron beam inspection. | 2013-01-10 |
20130011941 | BOND LINE THICKNESS CONTROL FOR DIE ATTACHMENT - A semiconductor die is attached onto a substrate on a process platform during manufacturing of a semiconductor package. A dispenser dispenses an adhesive onto the substrate, and the semiconductor die is bonded onto the adhesive which has been dispensed onto the substrate with a bonding tool. Thereafter, a bond line thickness between a bottom surface of the semiconductor die and a top surface of the substrate on the process platform is measured using a measuring device. | 2013-01-10 |
20130011942 | Method for Manufacturing Light Emitting Device - An object of the present invention to improve reliability of a light emitting device having a mixed layer including an organic compound and metal oxide without reducing productivity. The above object is solved in such a way that after forming the mixed layer including the organic compound and metal oxide, the mixed layer is exposed to a nitrogen gas atmosphere without being exposed to a gas atmosphere including oxygen, and then a stacked film is formed over the mixed layer without exposing the mixed layer to a gas atmosphere including oxygen. | 2013-01-10 |
20130011943 | Film Forming Method - One embodiment of the present invention is a film forming method comprising: arranging a surface of a film formation substrate | 2013-01-10 |
20130011944 | STORAGE OF AN IMAGE IN AN INTEGRATED CIRCUIT - An integrated circuit including a substrate of a semiconductor material and first metal portions of a first metallization level or of a first via level defining pixels of an image. The pixels are distributed in first pixels, for each of which the first metal portion is connected to the substrate, and in second pixels, for each of which the first metal portion is separated from the substrate by at least one insulating portion. | 2013-01-10 |
20130011945 | IMAGE DISPLAYING DEVICE - An image displaying device having multiple photosensing devices have successfully suppressed a leakage current from each photosensing device and improved the S/N ratio. In the image displaying device, pixels and photosensing devices are disposed as pairs in a matrix pattern on a substrate. Each of the pixels and each of the photosensing devices are driven independently. Each photosensing device includes a semiconductor layer that is a photoelectric conversion layer connected to at least a first electrode and a second electrode. The contact surfaces of the first and second electrodes with respect to the semiconductor layer are disposed so that their center axes are separated from each other. | 2013-01-10 |
20130011946 | LED PACKAGE WITH EFFICIENT, ISOLATED THERMAL PATH - Packages for containing one or more light emitting devices, such as light emitting diodes (LEDs), are disclosed with an efficient, isolated thermal path. In one embodiment, LED package can include a thermal element and at least one electrical element embedded within a body. The thermal element and electrical element can have the same and/or substantially the same thickness and can extend directly from a bottom surface of the LED package such that they are substantially flush with or extend beyond the bottom surface of the LED package. The thermal and electrical element have exposed portions which can be substantially flush with lateral sides of the body such that the thermal and electrical element do not have a significant portion extending beyond an outermost edge of the lateral sides of the body. | 2013-01-10 |
20130011947 | METHOD OF FORMING A SAMPLED GRATING AND METHOD OF PRODUCING A LASER DIODE - A method of forming a sampled grating includes the steps of preparing a substrate; preparing a nano-imprinting mold including a pattern surface on which projections and recesses are periodically formed; preparing a mask including a light obstructing portion and a light transmitting portion that are alternately provided; forming a photoresist layer and a resin portion in that order on the substrate; forming a patterned resin portion having projections and recesses by pressing the pattern surface of the mold into contact with the resin portion and hardening the resin portion while maintaining the contact; exposing a portion of the photoresist layer by irradiating the photoresist layer with exposing light through the mask and the patterned resin portion; forming a patterned photoresist layer by developing the photoresist layer; and etching the substrate using the patterned photoresist layer. | 2013-01-10 |
20130011948 | METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE AND PASTE APPLICATION APPARATUS USED FOR THE SAME - There are disclosed a method of manufacturing a semiconductor light emitting device and a paste application apparatus. The method includes preparing a light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; disposing a mask including an opening exposing a part of the light emitting structure on the light emitting structure; applying a paste including a wavelength conversion material to the light emitting structure through the opening of the mask, by using a pressure means; and planarizing the applied paste by using a roller. | 2013-01-10 |
20130011949 | METHOD FOR MANUFACTURING HIGH EFFICIENCY LIGHT-EMITTING DIODES - A method of manufacturing a light-emitting device comprising the steps of cutting a substrate by a laser beam to form a cavity in the substrate and generate a by-product directly on the substrate by the cutting, and removing the by-product by a chemical solution containing an acid under a predetermined cleaning temperature. | 2013-01-10 |
20130011950 | METHOD OF MANUFACTURING INFRARED LIGHT-EMITTING ELEMENT - To provide a method of manufacturing an infrared light-emitting element having a wavelength of 1.57 μm, including: forming a SiO | 2013-01-10 |
20130011951 | PRODUCTION METHOD FOR ORGANIC ELECTROLUMINESCENT ELEMENT - Disclosed is a production method for an organic electroluminescent element that is provided with a substrate, an organic laminate with an organic light emitting layer that was formed by a method involving a wet process, and a pair of electrodes, wherein the method produces an organic electroluminescent element with high luminous efficiency, low driving voltage, and a minimal rise in voltage when continuously driven, by applying the coating liquid for said organic light emitting layer, and thereafter, in a drying process, heating the substrate while applying tension in a manner such that a stress that is less than the yield stress is applied to the substrate. | 2013-01-10 |
20130011952 | METHOD FOR PRODUCING ORGANIC ELECTROLUMINESCENCE ELEMENT - Provided is a method for producing an organic electroluminescence device which contains an anode, a cathode and an organic layer between the anode and the cathode where the organic layer contains a light-emitting layer and an adjacent layer adjacent to the light-emitting layer, the method including: applying to the adjacent layer a coating liquid prepared by dissolving or dispersing a light-emitting material and a host material in a solvent, and heating the coating liquid applied to the adjacent layer at a temperature higher than a melting temperature of the host material and higher than a boiling point of the solvent, to thereby form the light-emitting layer, wherein a difference as an absolute value between contact angle A (°) of the light-emitting layer with respect to pure water and contact angle B (°) of the adjacent layer with respect to pure water is 13 (°) or smaller. | 2013-01-10 |
20130011953 | METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT-EMITTING DEVICE - To improve light emission efficiency and reliability. | 2013-01-10 |
20130011954 | High Power Density Photo-electronic and Photo-voltaic Materials and Methods of Making - A high power density photo-electronic and photo-voltaic material comprising a bio-inorganic nanophotoelectronic material with a photosynthetic reaction center protein encapsulated inside a multi-wall carbon nanotube or nanotube array. The array can be on an electrode. The photosynthetic reaction center protein can be immobilized on the electrode surface and the protein molecules can have the same orientation. A method of making a high power density photo-electronic and photo-voltaic material comprising the steps of immobilizing a bio-inorganic nanophotoelectronic material with a photosynthetic reaction center protein inside a carbon nanotube, wherein the immobilizing is by passive diffusion, wherein the immobilizing can include using an organic linker. | 2013-01-10 |
20130011955 | METHOD FOR MANUFACTURING ENERGY RAY DETECTION DEVICE - In a method for manufacturing an energy ray detection device including a first semiconductor region disposed below a first area on a surface of a semiconductor substrate, a second semiconductor region disposed below a second area on the surface and connected to a contact portion, and a third semiconductor region disposed below a third area on the surface between the first area and the second area, the first semiconductor region and the third semiconductor region are formed on the semiconductor substrate by performing ion implantation through a buffer film that covers the first area and the third area, a portion of the buffer film that covers the third area having a thickness smaller than a portion of the buffer film that covers the first area. | 2013-01-10 |
20130011956 | Method For Texturing A Photovoltaic Cell - A method for texturing an active surface of a photovoltaic cell in single-crystal silicon or poly-crystal silicon includes depositing a resin on the active surface of the cell, texturing the resin on the active surface with geometric patterns, and texturing the active surface of the cell by eliminating the deposited resin. The depositing of the resin is preceded by pre-texturing the resin on a depositing tool. The texturing step of the resin on the active surface is simultaneous with the depositing of the resin on the active surface. | 2013-01-10 |
20130011957 | METAL INKS - Self-reducing metal inks and systems and methods for producing and using the same are disclosed. In an exemplary embodiment, a method may comprise selecting a metal-organic (MO) precursor, selecting a reducing agent, and dissolving the MO precursor and the reducing agent in an organic solvent to produce a metal ink that remains in a liquid phase at room temperature. Metal inks, including self-reducing and fire-through metal inks, are also disclosed, as are various applications of the metal inks. | 2013-01-10 |
20130011958 | PHOTOVOLTAIC DEVICES FABRICATED FROM NANOSTRUCTURED TEMPLATE - Photovoltaic devices, such as solar cells, and methods for their manufacture are disclosed. A device may be characterized by an architecture having a nanostructured template made from an n-type first charge transfer material with template elements between about 1 nm and about 500 nm in diameter with about 10 | 2013-01-10 |
20130011959 | METHOD OF MANUFACTURING SOLAR CELL ELECTRODE AND CONDUCTIVE PASTE - A method of manufacturing a solar cell electrode comprising steps of: applying onto a semiconductor substrate a conductive paste comprising (i) a conductive powder, (ii) a glass frit, (iii) an organic polymer and (iv) an organic solvent comprising 30 to 85 weight percent (wt %) of 1-phenoxy-2-propanol based on the weight of the organic solvent; and firing the conductive paste. | 2013-01-10 |
20130011960 | Doped Graphene Films with Reduced Sheet Resistance - Techniques for increasing conductivity of graphene films by chemical doping are provided. In one aspect, a method for increasing conductivity of a graphene film includes the following steps. The graphene film is formed from one or more graphene sheets. The graphene sheets are exposed to a solution having a one-electron oxidant configured to dope the graphene sheets to increase a conductivity thereof, thereby increasing the overall conductivity of the film. The graphene film can be formed prior to the graphene sheets being exposed to the one-electron oxidant solution. Alternatively, the graphene sheets can be exposed to the one-electron oxidant solution prior to the graphene film being formed. A method of fabricating a transparent electrode on a photovoltaic device from a graphene film is also provided. | 2013-01-10 |
20130011961 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object is to provide a semiconductor device having excellent characteristics, in which a channel layer includes an oxide semiconductor with high crystallinity. In addition, a semiconductor device including a base film with improved planarity is provided. CMP treatment is performed on the base film of the transistor and plasma treatment is performed thereon after the CMP treatment, whereby the base film can have a center line average roughness Ra | 2013-01-10 |
20130011962 | SPUTTERING TARGET, METHOD FOR MANUFACTURING SPUTTERING TARGET, AND METHOD FOR FORMING THIN FILM - There have been cases where transistors formed using oxide semiconductors are inferior in reliability to transistors formed using amorphous silicon. Thus, in the present invention, a semiconductor device including a highly reliable transistor formed using an oxide semiconductor is manufactured. An oxide semiconductor film is deposited by a sputtering method, using a sputtering target including an oxide semiconductor having crystallinity, and in which the direction of the c-axis of a crystal is parallel to a normal vector of the top surface of the oxide semiconductor. The target is formed by mixing raw materials so that its composition ratio can obtain a crystal structure. | 2013-01-10 |
20130011963 | PROCESS FOR PRODUCING ZINC OXIDE VARISTOR - A process for producing zinc oxide varistors possessed a property of breakdown voltage (V1mA) ranging from 230 to 1,730 V/mm is to perform the doping of zinc oxide and the sintering of zinc oxide grains with a high-impedance sintered powder through two independent procedures, so that the doped zinc oxide and the high-impedance sintered powder are well mixed in a predetermined ratio and then used to make the zinc oxide varistors through conventional technology by low-temperature sintering (lower than 900° C.); the resultant zinc oxide varistors may use pure silver as inner electrode and particularly possess breakdown voltage ranging from 230 to 1,730 V/mm. | 2013-01-10 |
20130011964 | THERMAL ENHANCED PACKAGE - A method of manufacturing an integrated circuit package. The method includes attaching a first surface of a semiconductor die to a thermally and/or electrically conductive substrate, forming a plurality of die connectors on a second surface of the semiconductor die, and encapsulating the semiconductor die and the plurality of die connectors in an encapsulant material. The method also includes removing a portion of the encapsulant material to expose one or more of the plurality of die connectors, thereby forming a routing surface. The method further includes forming a plurality of conductive traces on the routing surface. Each of the plurality of conductive traces is characterized by a first portion in electrical communication with one of the plurality of die connectors and a second portion in electrical communication with a package connector. | 2013-01-10 |
20130011965 | DISTRIBUTING POWER WITH THROUGH-SILICON-VIAS - An integrated circuit with distributed power using through-silicon-vias (TSVs) is presented. The integrated circuit has conducting pads for providing power and ground located within the peripheral region of the top surface. A number of through-silicon-vias are distributed within the peripheral region and a set of TSVs are formed within the non-peripheral region of the integrated circuit. Conducting lines on the bottom surface are coupled between each peripheral through-silicon-via and a corresponding non-peripheral through-silicon-via. Power is distributed from the conducting pads to the TSVs within the non-peripheral region through the TSVs within the peripheral region, thus supplying power and ground to circuits located within the non-peripheral region of the integrated circuit chip. | 2013-01-10 |
20130011966 | STACKABLE SEMICONDUCTOR ASSEMBLIES AND METHODS OF MANUFACTURING SUCH ASSEMBLIES - Stacked semiconductor devices and assemblies including attached lead frames are disclosed herein. One embodiment of a method of manufacturing a semiconductor assembly includes forming a plurality of first side trenches to a first intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes forming a plurality of lateral contacts at sidewall portions of the trenches and electrically connecting first side bond-sites of the dies with corresponding lateral contacts of the trenches. The method further includes forming a plurality of second side channels to a second intermediate depth in the molded portion such that the channels intersect the trenches. The method also includes singulating and stacking the first and second dies with the channels associated with the first die aligned with channels associated with the second die. | 2013-01-10 |
20130011967 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips. | 2013-01-10 |
20130011968 | HYBRID BONDING TECHNIQUES FOR MULTI-LAYER SEMICONDUCTOR STACKS - A circuit arrangement and method utilize hybrid bonding techniques that combine wafer-wafer bonding processes with chip-chip and/or chip-wafer bonding processes to form a multi-layer semiconductor stack, e.g., by bonding together one or more sub-assemblies formed by wafer-wafer bonding together with other sub-assemblies and/or chips using chip-chip and/or chip-wafer bonding processes. By doing so, the advantages of wafer-wafer bonding techniques, such as higher interconnect densities, may be leveraged with the advantages of chip-chip and chip-wafer bonding techniques, such as mixing and matching chips with different sizes, aspect ratios, and functions. | 2013-01-10 |
20130011969 | METHOD FOR FABRICATING THE FLEXIBLE ELECTRONIC DEVICE - The disclosure provides a method for fabricating the flexible electronic devices, including: providing a first rigid carrier substrate and a second rigid carrier substrate, wherein at least one flexible electronic device is formed between the first rigid carrier substrate and the second rigid carrier substrate, and a plurality of first de-bonding areas, a first flexible substrate, the flexible electronic device, a second flexible substrate, a plurality of second de-bonding areas and the second rigid carrier substrate are formed on the first rigid carrier substrate; performing a first cutting step to cut through the first de-bonding areas; separating the first rigid carrier substrate from the first de-bonding areas; removing the first rigid carrier substrate from the first de-bonding areas; and performing a second cutting step to cut through the second de-bonding areas; separating and removing the second rigid carrier substrate from the second de-bonding areas. | 2013-01-10 |
20130011970 | MANUFACTURING METHOD OF MOLDED PACKAGE - In a manufacturing method of a molded package, a lead frame including an island portion and a support portion is prepared. A circuit chip is mounted on the island portion, and the sensor chip is arranged such that a first end section having an electric connecting portion is adjacent to the circuit chip and a second end section having a sensing portion is supported by the support portion. The circuit chip and the electric connecting portion of the first end section is electrically connected through a connection member. The circuit chip, the island portion, the connection member and the first end section are sealed with a resin while maintaining the support state. After the sealing, the support portion is cut from the lead frame and separated from the second end section. | 2013-01-10 |
20130011971 | FABRICATING METHOD OF SEMICONDUCTOR PACKAGE STRUCTURE - A fabricating method of a semiconductor package structure is provided. A dielectric layer having a first surface and a second surface is provided. A patterned metal layer has been formed on the first surface of the dielectric layer. An opening going through the first and the second surfaces is formed. A carrier having a third surface and a fourth surface is formed at the second surface. A portion of the third surface is exposed by the opening of the dielectric layer. A semiconductor die having a joining surface and a side-surface is joined in the opening. At least a through hole going through the third and the fourth surfaces is formed. A metal layer having at least a heat conductive post extending from the fourth surface of the carrier to the through hole and disposed in the through hole and a containing cavity is formed on the fourth surface. | 2013-01-10 |
20130011972 | METHOD OF PRODUCING LAMINATED DEVICE - A method of producing a laminate insert package includes providing a first metal layer, printing a first dielectric layer on the first metal layer, providing a second metal layer, printing a second dielectric layer on the second metal layer, and printing a dielectric spacer layer on the first dielectric layer. At least one semiconductor chip is attached to either the first or the second metal layer. A first layer assembly comprising the first metal layer, the first dielectric layer, the dielectric spacer layer and a second layer assembly comprising the second metal layer and the second dielectric layer are brought together. The first and second layer assemblies are laminated to form a laminate insert package, whereby the at least one semiconductor chip is embedded within the laminate insert package. | 2013-01-10 |
20130011973 | LEADFRAME STRIP AND MOLD APPARATUS FOR AN ELECTRONIC COMPONENT AND METHOD OF ENCAPSULATING AN ELECTRONIC COMPONENT - A leadframe strip comprises a plurality of units arranged in a line. Each unit provides two component positions, each having a chip support substrate. The chip support substrates of the two component positions are mechanically linked by at least one support bar. The two component positions of a unit are molded at essentially the same time to produce a plastic housing for a package in each component position. The central portion of the first support bars remains outside of the plastic housing of the two packages. | 2013-01-10 |
20130011974 | Thyristor-Based Memory Cells, Devices and Systems Including the Same and Methods for Forming the Same - Semiconductor devices including a plurality of thyristor-based memory cells, each having a cell size of 4F | 2013-01-10 |
20130011975 | RAISED SOURCE/DRAIN STRUCTURE FOR ENHANCED STRAIN COUPLING FROM STRESS LINER - A gate stack is formed on a silicon layer that is above a buried oxide layer. The gate stack comprises a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A first nitride layer is formed on the silicon layer and the gate stack. An oxide layer is formed on the first nitride layer. A second nitride layer is formed on the oxide layer. The first nitride layer and the oxide layer are etched so as to form a nitride liner and an oxide liner adjacent to the gate stack. The second nitride layer is etched so as to form a first nitride spacer adjacent to the oxide liner. A faceted raised source/drain region is epitaxially formed adjacent to the nitride liner, the oxide liner, and first nitride spacer. Ions are implanted into the faceted raised source/drain region using the first nitride spacer. | 2013-01-10 |
20130011976 | FABRICATING METHOD OF PIXEL STRUCTURE - A fabricating method of a pixel structure is provided. A substrate has an array of pixel areas. The common electrode wire is positioned only in a portion of the pixel area. A first capacitance storage electrode is formed in each of the pixel areas and electrically connected between two adjacent common electrode wires. A gate insulation layer covers the scan line, the gate electrode, the common electrode wire and the first capacitance storage electrode. A semiconductor layer is formed on the gate insulation layer above the gate electrode. The source and the drain is formed on two sides of the semiconductor layer. A passivation layer is formed on the substrate to cover the data line, the source and the drain. A pixel electrode is formed in each of the pixel areas, and the pixel electrode is electrically connected with the drain through the contact window. | 2013-01-10 |
20130011977 | Floating Body Cell Structures, Devices Including Same, and Methods for Forming Same - Floating body cell structures including an array of floating body cells disposed on a back gate and source regions and drain regions of the floating body cells spaced apart from the back gate. The floating body cells may each include a volume of semiconductive material having a channel region extending between pillars, which may be separated by a void, such as a U-shaped trench. The floating body cells of the array may be electrically coupled to another gate, which may be disposed on sidewalls of the volume of semiconductive material or within the void therein. Methods of forming the floating body cell devices are also disclosed. | 2013-01-10 |
20130011978 | Methods of Forming Memory Arrays and Semiconductor Constructions - Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory. | 2013-01-10 |
20130011979 | SELF-ALIGNED SEMICONDUCTOR DEVICES WITH REDUCED GATE-SOURCE LEAKAGE UNDER REVERSE BIAS AND METHODS OF MAKING - A vertical junction field effect transistor (VJFET) having a self-aligned pin, a p+/n/n+ or a p+/p/n+ gate-source junction is described. The device gate can be self-aligned to within 0.5 μm to the source in order to maintain good high voltage performance (i.e. low DIBL) while reducing gate-source junction leakage under reverse bias. The device can be a wide-bandgap semiconductor device such as a SiC vertical channel junction field effect. Methods of making the device are also described. | 2013-01-10 |
20130011980 | FABRICATION METHOD OF VERTICAL SILICON NANOWIRE FIELD EFFECT TRANSISTOR - The present invention discloses a fabrication method of a vertical silicon nanowire field effect transistor having a low parasitic resistance, which relates to a field of an ultra-large-integrated-circuit fabrication technology. As compared with a conventional planar field effect transistor, on one hand the vertical silicon nanowire field effect transistor fabricated by the present invention can provide a good ability for suppressing a short channel effect due to the excellent gate control ability caused by the one-dimensional structure, and reduce a leakage current and a drain-induced barrier lowering (DIBL). On the other hand, an area of the transistor is further reduced and an integration degree of an IC system is increased. | 2013-01-10 |
20130011981 | HIGH PERFORMANCE MOSFET - A semiconductor structure which exhibits high device performance and improved short channel effects is provided. In particular, a metal oxide semiconductor field effect transistor (MOFET) is provided that includes a low dopant concentration within an inversion layer of the structure; the inversion layer is an epitaxial semiconductor layer that is formed atop a portion of the semiconductor substrate. The structure also includes a well region of a first conductivity type beneath the inversion layer, wherein the well region has a central portion and two horizontally abutting end portions. The central portion has a higher concentration of a first conductivity type dopant than the two horizontally abutting end portions. | 2013-01-10 |
20130011982 | LAYOUT METHOD OF SEMICONDUCTOR DEVICE WITH JUNCTION DIODE FOR PREVENTING DAMAGE DUE TO PLASMA CHARGE - A layout method of junction diodes for preventing damage caused by plasma charge includes forming an active layer to form a plurality of active regions in a unit layout pattern; forming a gate layer to form a plurality of gate regions on the active regions; forming a first conductive type doping region in at least one of the plurality of active regions within a well layer where a second conductive type well region is formed to form a first conductive type active region; forming a second conductive type doping region in at least one of the plurality of active regions outside of the second conductive type well region to form a second conductive type active region; and forming a second conductive type doping region connected with the gate regions to form a junction diode in at least one active region between the first and second conductive type active regions. | 2013-01-10 |
20130011983 | In-Situ Doping of Arsenic for Source and Drain Epitaxy - A method includes forming a gate stack over a semiconductor region, and recessing the semiconductor region to form a recess adjacent the gate stack. A silicon-containing semiconductor region is epitaxially grown in the recess to form a source/drain stressor. Arsenic is in-situ doped during the step of epitaxially growing the silicon-containing semiconductor region. | 2013-01-10 |
20130011984 | Using Hexachlorodisilane as a Silicon Precursor for Source/Drain Epitaxy - A method includes forming a gate stack over a semiconductor region, and recessing the semiconductor region to form a recess adjacent the gate stack. A silicon-containing semiconductor region is epitaxially grown in the recess to form a source/drain region, wherein the step of epitaxially growing is performed using hexachlorodisilane as a precursor. | 2013-01-10 |
20130011985 | SHALLOW-TRENCH CMOS-COMPATIBLE SUPER JUNCTION DEVICE STRUCTURE FOR LOW AND MEDIUM VOLTAGE POWER MANAGEMENT APPLICATIONS - A novel lateral super junction device compatible with standard CMOS processing techniques using shallow trench isolation is provided for low- and medium-voltage power management applications. The concept is similar to other lateral super junction devices having N- and P-type implants to deplete laterally to sustain the voltage. However, the use of shallow trench structures provides the additional advantage of reducing the Rdson without the loss of the super junction concept and, in addition, increasing the effective channel width of the device to form a “FINFET” type structure, in which the conducting channel is wrapped around a thin silicon “fin” that forms the body of the device. The device is manufactured using standard CMOS processing techniques with the addition of super junction implantation steps, and the addition of polysilicon within the shallow trench structures to form fin structures. | 2013-01-10 |
20130011986 | Method for Manufacturing Full Silicide Metal Gate Bulk Silicon Multi-Gate Fin Field Effect Transistors - The present application discloses a method for manufacturing a full silicide metal gate bulk silicon multi-gate fin field effect transistor, which comprises the steps of: forming at least one fin on the semiconductor substrate; forming a gate stack structure on top and side surfaces of the fin; forming a source/drain extension area in the fin on both sides of the gate stack structure; forming a source/drain area on both sides of the source/drain extension area; forming silicide on the source/drain area; forming a full silicide metal gate electrode; and forming contact and implementing metalization. The present invention eliminates the self-heating effect and the floating body effect of SOI devices, then has a much lower cost, overcomes such defects as the polysilicon gate depletion effect, Boron penetration effect, and large series resistance of polysilicon gate electrodes, and has good compatibility with the planar COMS technology, thus it can be easily integrated. | 2013-01-10 |
20130011987 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH VERTICAL GATE - A method for fabricating a semiconductor device includes forming a plurality of pillars by etching a semiconductor substrate, forming a conductive layer over a semiconductor substrate structure including the pillars, forming preliminary gates on sidewalls of each pillar by performing a first etch process on the conductive layer, and forming vertical gates by performing a second etch process on upper portions of the preliminary gates. | 2013-01-10 |
20130011988 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A LAMINATED STRUCTURE COMPRISING A BORON-DOPED SILICON GERMANIUM FILM AND A METAL FILM - A semiconductor device has memory cell portions and compensation capacitance portions on a single substrate. The memory cell portion and the compensation capacitance portion have mutually different planar surface areas. The memory cell portion and the compensation capacitance portion include capacitance plate electrodes of the same structure. The capacitance plate electrode has a laminated structure including a boron-doped silicon germanium film and a metal film. | 2013-01-10 |
20130011989 | METHODS OF MANUFACTURING A DRAM DEVICE - In methods of manufacturing a DRAM device, a buried-type gate is formed in a substrate. A capping insulating layer pattern is formed on the buried-type gate. A conductive layer pattern filling up a gap between portions of the capping insulating layer pattern, and an insulating interlayer covering the conductive layer pattern and the capping insulating layer pattern are formed. The insulating interlayer, the conductive layer pattern, the capping insulating layer pattern and an upper portion of the substrate are etched to form an opening, and a first pad electrode making contact with a first pad region. A spacer is formed on a sidewall of the opening corresponding to a second pad region. A second pad electrode is formed in the opening. A bit line electrically connected with the second pad electrode and a capacitor electrically connected with the first pad electrode are formed. | 2013-01-10 |
20130011990 | Methods of Making Crystalline Tantalum Pentoxide - There is disclosed a method of forming crystalline tantalum pentoxide on a ruthenium-containing material having an oxygen-containing surface wherein the oxygen-containing surface is contacted with a treating composition, such as water, to remove at least some oxygen. Crystalline tantalum pentoxide is formed on at least a portion of the surface having reduced oxygen content. | 2013-01-10 |
20130011991 | METHOD OF FORMING A MEMORY DEVICE INCORPORATING A RESISTANCE VARIABLE CHALCOGENIDE ELEMENT - A method of forming a memory device, such as a PCRAM, including selecting a chalcogenide glass backbone material for a resistance variable memory function and devices formed using such a method. | 2013-01-10 |
20130011992 | CIRCUIT, BIASING SCHEME AND FABRICATION METHOD FOR DIODE ACCESSED CROSS-POINT RESISTIVE MEMORY ARRAY - Methods, systems, structures and arrays are disclosed, such as a resistive memory array which includes access devices, for example, back-to-back Zener diodes, that only allow current to pass through a coupled resistive memory cell when a voltage drop applied to the access device is greater than a critical voltage. The array may be biased to reduce standby currents and improve delay times between programming and read operations. | 2013-01-10 |
20130011993 | PLANAR PHASE- CHANGE MEMORY CELL WITH PARALLEL ELECTRICAL PATHS - A method of manufacturing a phase change memory cell on a substrate. The method includes: etching a first trench in the substrate; depositing a first conductor layer in the first trench; depositing a first insulator layer over the first conductor layer in the first trench; etching a second trench in the substrate at an angle to the first trench; depositing a second insulator layer in the second trench; depositing a second conductor layer over the second insulator layer in the second trench; and depositing phase change material. The deposited phase change material is in contact with the first conductor layer and the second conductor layer. | 2013-01-10 |
20130011994 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device includes the following steps. Firstly, a lower electrode is formed over a substrate (semiconductor substrate). Successively, the lower electrode is primarily crystallized. Successively, a capacitance dielectric layer is formed over the lower electrode after primarily crystallized. Successively, the capacitance dielectric layer is secondarily crystallized. Then, an upper electrode is formed over the capacitance dielectric layer. | 2013-01-10 |
20130011995 | SEMICONDUCTOR DEVICE HAVING WIRING MADE BY DAMASCENE METHOD AND CAPACITOR AND ITS MANUFACTURE METHOD - A wiring trench is formed in an interlayer insulating film partway in the depth direction of the interlayer insulating film. A via hole is formed extending from the bottom of the wiring trench to the bottom of the interlayer insulating film. A capacitor recess is formed reaching the bottom of the interlayer insulating film. A conductive member is embedded in the wiring trench and via hole. A capacitor is embedded in the capacitor recess, including a lower electrode, a capacitor dielectric film and an upper electrode. The lower electrode is made of the same material as that of the conductive member and disposed along the bottom and side surface of the capacitor recess. A concave portion is formed on an upper surface of the lower electrode, and the capacitor dielectric film covers an inner surface of the concave portion. The upper electrode is embedded in the concave portion. | 2013-01-10 |
20130011996 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To provide a semiconductor device having improved reliability at an improved production yield. | 2013-01-10 |
20130011997 | METHOD FOR PRODUCING A WAFER PROVIDED WITH CHIPS - A method for producing a product wafer having chips thereon, comprising the steps of:
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20130011998 | Resin Film Forming Sheet for Chip, and Method for Manufacturing Semiconductor Chip - A sheet for forming a resin film for a chip, with which a semiconductor device is provided with a gettering function, is obtained without performing special treatment to a semiconductor wafer and the chip. The sheet has a release sheet, and a resin film-forming layer, which is formed on the releasing face of the release sheet, and the resin film-forming layer contains a binder polymer component, a curing component, and a gettering agent. | 2013-01-10 |
20130011999 | COATING ADHESIVES ONTO DICING BEFORE GRINDING AND MICRO-FABRICATED WAFERS - A method for preparing a semiconductor wafer into individual semiconductor dies uses both a dicing before grinding step and/or via hole micro-fabrication step, and an adhesive coating step. | 2013-01-10 |
20130012000 | SUBSTRATE DIVIDING METHOD - A substrate dividing method which can thin and divide a substrate while preventing chipping and cracking from occurring. This substrate dividing method comprises the steps of irradiating a semiconductor substrate | 2013-01-10 |
20130012001 | METHOD FOR PRODUCING SEMICONDUCTOR OPTICAL DEVICE - A method for producing a semiconductor optical device includes the steps of growing a semiconductor stacked layer including an etch stop layer and a plurality of semiconductor layers on a major surface of a substrate; forming a mask layer on a top surface of the semiconductor stacked layer so that a tip portion of each of protrusions that protrude from the top surface among protrusions generated in the step of growing the semiconductor stacked layer is exposed; etching the protrusion by wet etching using the mask layer; after etching the protrusion by wet etching, removing the protrusion by dry etching; and removing the mask layer from the top surface, after removing the protrusion by dry etching. | 2013-01-10 |
20130012002 | METHOD FOR PRODUCING SEMICONDUCTOR OPTICAL INTEGRATED DEVICE - A method for producing a semiconductor optical integrated device includes the steps of forming a substrate product including first and second stacked semiconductor layer portions; forming a first mask on the first and second stacked semiconductor layer portions, the first mask including a stripe-shaped first pattern region and a second pattern region, the second pattern region including a first end edge; forming a stripe-shaped mesa structure; removing the second pattern region of the first mask; forming a second mask on the second stacked semiconductor layer portion; and selectively growing a buried semiconductor layer with the first and second masks. The second mask includes a second end edge separated from the first end edge of the first mask, the second end edge being located on the side of the second stacked semiconductor layer portion in the predetermined direction with respect to the first end edge of the first mask. | 2013-01-10 |
20130012003 | METHODS FOR DEPOSITING THIN FILMS COMPRISING GALLIUM NITRIDE BY ATOMIC LAYER DEPOSITION - Atomic layer deposition (ALD) processes for forming thin films comprising GaN are provided. In some embodiments, ALD processes for forming doped GaN thin films are provided. The thin films may find use, for example, in light-emitting diodes. | 2013-01-10 |
20130012004 | MANUFACTURING METHOD OF SEMICONDUCTOR SUBSTRATE - A manufacturing method of a semiconductor substrate includes: forming a trench in a semiconductor board by a dry etching method; etching a surface portion of an inner wall of the trench by a chemical etching method so that a first damage layer is removed, wherein the surface portion has a thickness equal to or larger than 50 nanometers; and performing a heat treatment at temperature equal to or higher than 1050° C. in non-oxidizing and non-azotizing gas so that crystallinity of a second damage layer is recovered, wherein the second damage layer is disposed under the first damage layer. The crystallinity around the trench is sufficiently recovered | 2013-01-10 |
20130012005 | SILICON ON GERMANIUM - A monolayer or partial monolayer sequencing processing, such as atomic layer deposition (ALD), can be used to form a semiconductor structure of a silicon film on a germanium substrate. Such structures may be useful in high performance electronic devices. A structure may be formed by deposition of a thin silicon layer on a germanium substrate surface, forming a hafnium oxide dielectric layer, and forming a tantalum nitride electrode. The properties of the dielectric may be varied by replacing the hafnium oxide with another dielectric such as zirconium oxide or titanium oxide. | 2013-01-10 |
20130012006 | PLASMA TREATMENT APPARATUS, METHOD FOR FORMING FILM, AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR - A structure of the plasma treatment apparatus is employed in which an upper electrode has projected portions provided with first introduction holes and recessed portions provided with second introduction holes, the first introduction hole of the upper electrode is connected to a first cylinder filled with a gas which is not likely to be dissociated, the second introduction hole is connected to a second cylinder filled with a gas which is likely to be dissociated, the gas which is not likely to be dissociated is introduced into a reaction chamber from an introduction port of the first introduction hole provided on a surface of the projected portion of the upper electrode, and the gas which is likely to be dissociated is introduced into the reaction chamber from an introduction port of the second introduction hole provided on a surface of the recessed portion. | 2013-01-10 |
20130012007 | METHODS OF IMPLANTING DOPANT IONS - Methods of implanting dopant ions in a substrate include depositing a sacrificial material on a substrate. Dopant ions are implanted into the substrate while sputtering the sacrificial material, without substantially sputtering the substrate. Substantially no sacrificial material remains on the substrate after the implanting of the dopant ions. Some methods include forming a sacrificial material over a substrate, and implanting dopant ions into the substrate while removing substantially all the sacrificial material from the substrate. Substantially no sputtering of the substrate occurs during the implanting of the dopant ions. Methods of doping a substrate include implanting dopant ions into a substrate having a sacrificial material thereon, and sputtering the sacrificial material while implanting the dopant ions without substantially sputtering the substrate. Substantially no sacrificial material remains on the substrate after implanting the dopant ions. | 2013-01-10 |
20130012008 | METHOD OF PRODUCING SOI WAFER - The present invention provides a method of producing a high quality SOI wafer having a thin BOX layer with high productivity. In the method of producing an SOI wafer by performing heat treatment on a silicon wafer after implanting oxygen ions into silicon wafer, first ion implantation is performed on the silicon wafer to a high dose of 2×10 | 2013-01-10 |
20130012009 | METHOD FOR SELF ALIGNED METAL GATE CMOS - A semiconductor device is formed by first providing a dual gate semiconductor device structure having FET pair precursors, which includes an nFET precursor and a pFET precursor, wherein each of the nFET precursor and the pFET precursor includes a dummy gate structure. At least one protective layer is deposited across the FET pair precursors, leaving the dummy gate structures exposed. The dummy gate structure is removed from one of the nFET precursor and the pFET precursor to create therein one of an nFET gate hole and a pFET gate hole, respectively. A fill is deposited into the formed one of the nFET gate hole and the pFET gate. | 2013-01-10 |
20130012010 | SEMICONDUCTOR DEVICE EXHIBITING REDUCED PARASITICS AND METHOD FOR MAKING SAME - A semiconductor device includes a substrate and a gate stack disposed on the substrate. An upper layer of the gate stack is a metal gate conductor and a lower layer of the gate stack is a gate dielectric. A gate contact is in direct contact with the metal gate conductor. | 2013-01-10 |
20130012011 | INTERCONNECTION STRUCTURE FOR N/P METAL GATES - This description relates to a method for fabricating an interconnection structure in a complementary metal-oxide-semiconductor (CMOS). The method includes forming a first opening in a dielectric layer over a substrate and partially filling the first opening with a second work-function metal layer, wherein a top surface of the second work-function metal layer is below a top surface of the first opening. The method further includes forming a second opening adjoining the first opening in the dielectric layer over the substrate and depositing a first work-function metal layer in the first and second openings, whereby the first work-function metal layer is over the second work-function metal layer in the first opening. The method further includes depositing a signal metal layer over the first work-function metal layer in the first and second openings and planarizing the signal metal layer. | 2013-01-10 |
20130012012 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A substrate having an oxide layer thereon is provided. A high temperature process higher than 1000° C. is performed to form a melting layer between the substrate and the oxide layer. A removing process is performed to remove the oxide layer and the melting layer. | 2013-01-10 |
20130012013 | Methods Of Forming Transistor Gates - Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures. | 2013-01-10 |
20130012014 | UBM Etching Methods for Eliminating Undercut - A method includes forming an under-bump metallurgy (UBM) layer overlying a substrate, and forming a mask overlying the UBM layer. The mask covers a first portion of the UBM layer, and a second portion of the UBM layer is exposed through an opening in the mask. A metal bump is formed in the opening and on the second portion of the UBM layer. The mask is then removed. A laser removal is performed to remove a part of the first portion of the UBM layer and to form an UBM. | 2013-01-10 |
20130012015 | SEMICONDUCTOR DEVICE FOR IMPROVING ELECTRICAL AND MECHANICAL CONNECTIVITY OF CONDUCTIVE PILLERS AND METHOD THEREFOR - A semiconductor device has a semiconductor die having a first surface and a second surface wherein at least one bond pad is formed on the first surface. A passivation layer is formed on the first surface of the semiconductor device, wherein a central area of the at least one bond is exposed. A seed layer is formed on exposed portions of the bond pad and the passivation layer. A conductive pillar is formed on the seed layer. The conductive pillar has a base portion wherein the base portion has a diameter smaller than the seed layer and a stress relief portion extending from a lateral surface of a lower section of the base portion toward distal ends of the seed layer. A solder layer is formed on the conductive pillar. | 2013-01-10 |
20130012016 | ENHANCING METAL/LOW-K INTERCONNECT RELIABILITY USING A PROTECTION LAYER - A protection layer is coated or otherwise formed over the interconnect structure. The interconnect structure includes a metal line (such as top and bottom metal layers connected by a metal via) and a low-K material. The protection layer includes a vertically aligned dielectric or other material dispersed with carbon nanotubes. The protection layer could include one or multiple layers of carbon nanotubes, and the carbon nanotubes could have any suitable dispersion, alignment, and pattern in each layer of the protection layer. Among other things, the carbon nanotubes help to reduce or prevent damage to the interconnect structure, such as by reducing or preventing the collapse of the low-K material or delamination between the metal line and the low-K material. | 2013-01-10 |
20130012017 | MICROELECTRONIC STRUCTURE INCLUDING AIR GAP - A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure. | 2013-01-10 |
20130012018 | ON-CHIP COOLING FOR INTEGRATED CIRCUITS - A semiconductor structure fabrication method. A provided structure includes: a semiconductor substrate, a transistor on the semiconductor substrate, N interconnect layers on the semiconductor substrate, and a temporary filling region within the N layers. N is at least 2. The temporary filling region is heated at a high temperature sufficiently high to result in the temporary filling material being replaced by a cooling pipes system that does not include any solid or liquid material. A first portion and a second portion of the cooling pipes system are each in direct physical contact with a surrounding ambient at a first interface and a second interface respectively such that a first direction perpendicular to the first interface is perpendicular to a second direction perpendicular to the second interface. A totality of interfaces between the cooling pipes system and the ambient consists of the first interface and the second interface. | 2013-01-10 |
20130012019 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes (a) depositing an insulating film on a semiconductor substrate; (b) forming a recess in the insulating film; (c) depositing a conductive film on the insulating film while filling the recess with the conductive film; and (d) polishing the conductive film. Step (d) includes a first polishing substep of using a first polisher pad conditioned with a first dresser and a second polishing substep of using a second polisher pad conditioned with a second dresser different from the first dresser. | 2013-01-10 |
20130012020 | USE OF EPITAXIAL NI SILICIDE - An epitaxial Ni silicide film that is substantially non-agglomerated at high temperatures, and a method for forming the epitaxial Ni silicide film, is provided. The Ni silicide film of the present disclosure is especially useful in the formation of ETSOI (extremely thin silicon-on-insulator) Schottky junction source/drain FETs. The resulting epitaxial Ni silicide film exhibits improved thermal stability and does not agglomerate at high temperatures. | 2013-01-10 |
20130012021 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming an interlayer dielectric film that has first and second trenches on first and second regions of a substrate, respectively, forming a first metal layer along a sidewall and a bottom surface of the first trench and along a top surface of the interlayer dielectric film in the first region, forming a second metal layer along a sidewall and a bottom surface of the second trench and along a top surface of the interlayer dielectric film in the second region, forming a first sacrificial layer pattern on the first metal layer such that the first sacrificial layer fills a portion of the first trench, forming a first electrode layer by etching the first metal layer and the second metal layer using the first sacrificial layer pattern, and removing the first sacrificial layer pattern. | 2013-01-10 |
20130012022 | METHOD FOR FABRICATING SILICON NANOWIRE ARRAYS - A method for larger-area fabrication of uniform silicon nanowire arrays is disclosed. The method includes forming a metal layer with a predetermined thickness on a substrate whose surface has a silicon material by a coating process, the metal layer selected from the group consisting of Ag, Au and Pt; and performing a metal-induced chemical etching for the silicon material by using an etching solution. Accordingly, a drawback that Ag nanoparticles are utilized to perform the metal-induced chemical etching in prior art is solved. | 2013-01-10 |
20130012023 | METHOD OF FORMING MICROPATTERN, METHOD OF FORMING DAMASCENE METALLIZATION, AND SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE FABRICATED USING THE SAME - According to example embodiments, a method of forming micropatterns includes forming dummy patterns having first widths on a dummy region of a substrate, and forming cell patterns having second widths on an active line region of the substrate. The active line region may be adjacent to the dummy region and the second widths may be less than the first widths. The method may further include forming damascene metallization by forming a seed layer on the active line region and the dummy region, forming a conductive material layer on a whole surface of the substrate, and planarizing the conductive material layer to form metal lines. | 2013-01-10 |
20130012024 | STRUCTURE FOR MICROELECTRONICS AND MICROSYSTEM AND MANUFACTURING PROCESS - A process for making cavities in a multilayer structure by providing a multilayer structure that includes a surface layer, a planar support substrate and a buried layer between the layer and the support substrate, wherein the buried layer comprises areas of first and second materials with the first material having a higher etching rate than the second material; producing an opening in the surface layer that extends to the area(s) of the first material of the buried layer; and etching the first material to form at least one cavity in the buried layer. | 2013-01-10 |
20130012025 | DEVICE HAVING AND METHOD FOR FORMING FINS WITH MULTIPLE WIDTHS - A method for fabrication of features for an integrated circuit includes patterning a mandrel layer to include structures having a plurality of different widths on a surface of an integrated circuit device. Exposed sidewalls of the structures are reacted to integrally form a new compound in the sidewalls such that the new compound extends into the exposed sidewalls by a controlled amount to form pillars. One or more layers below the pillars are etched using the pillars as an etch mask to form features for an integrated circuit device. | 2013-01-10 |
20130012026 | METHODOLOGY FOR FABRICATING ISOTROPICALLY RECESSED SOURCE AND DRAIN REGIONS OF CMOS TRANSISTORS - A method for fabricating recessed source and recessed drain regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the source and the drain in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed source region; an isotropically recessed drain region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer. | 2013-01-10 |
20130012027 | Method for the supply of fluorine - Elemental fluorine is used as etching agent for the manufacture of electronic devices, especially semiconductor devices, micro-electromechanical devices, thin film transistors, flat panel displays and solar panels, and as chamber cleaning agent mainly for plasma-enhanced vapor deposition (PECVD) apparatus. For this purpose, fluorine often is produced on-site. The invention provides a process wherein the contamination of the elemental fluorine with gaseous impurities, such as air or moisture, is prevented by producing it on site and delivering it to the point of use under a pressure higher than ambient pressure. | 2013-01-10 |
20130012028 | High purity, environmentally clean method and apparatus, for high rate, liquid anisotropic etching of single crystal silicon or etching of polycrystalline silicon, using an overpressure of ammonia gas above aqueous ammonium hydroxide - A high purity, non-toxic, environmentally friendly method for anisotropically etching single crystal silicon and etching polysilicon, suitable for microelectronics, optoelectronics and microelectromechanical (MEMS) device fabrication, using high purity aqueous ammonium hydroxide (NH | 2013-01-10 |
20130012029 | METHOD AND DEVICE FOR LAYER DEPOSITION - Method for depositing a layer on a surface of a substrate. The method comprises injecting a precursor gas from a precursor supply into a deposition cavity for contacting the substrate surface, draining part of the injected precursor gas from the deposition cavity, and positioning the deposition cavity and the substrate relative to each other along a plane of the substrate surface. The method further comprising providing a first electrode and a second electrode, positioning the first electrode and the substrate relative to each other, and generating a plasma discharge near the substrate for contacting the substrate by generating a high-voltage difference between the first electrode and the second electrode. The method comprises generating the plasma discharge selectively, for patterning the surface by means of the plasma. A portion of the substrate contacted by the precursor gas selectively overlaps with a portion of the substrate contacted by the plasma. | 2013-01-10 |
20130012030 | METHOD AND APPARATUS FOR REMOTE PLASMA SOURCE ASSISTED SILICON-CONTAINING FILM DEPOSITION - An apparatus and methods for depositing amorphous and microcrystalline silicon films during the formation of solar cells are provided. In one embodiment, a method and apparatus is provided for generating and introducing hydrogen radicals directly into a processing region of a processing chamber for reaction with a silicon-containing precursor for film deposition on a substrate. In one embodiment, the hydrogen radicals are generated by a remote plasma source and directly introduced into the processing region via a line of sight path to minimize the loss of energy by the hydrogen radicals prior to reaching the processing region. | 2013-01-10 |
20130012031 | HAFNIUM TANTALUM OXIDE DIELECTRICS - A dielectric layer containing a hafnium tantalum oxide film and a method of fabricating such a dielectric layer produce a dielectric layer for use in a variety of electronic devices. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing a hafnium tantalum oxide film structured as one or more monolayers. | 2013-01-10 |
20130012032 | NH3 CONTAINING PLASMA NITRIDATION OF A LAYER ON A SUBSTRATE - Methods and apparatus for forming nitrogen-containing layers are provided herein. In some embodiments, a method includes exposing a first layer of a substrate to a plasma formed from a process gas comprising predominantly a mixture of ammonia (NH | 2013-01-10 |
20130012033 | SILICON OXIDE FILM FORMING METHOD AND PLASMA OXIDATION APPARATUS - A silicon oxide film forming method includes forming a silicon oxide film by allowing a plasma of a processing gas to react on a silicon exposed on a surface of a target object to be processed in a processing chamber of a plasma processing apparatus. The processing gas includes an ozone-containing gas having a volume ratio of O | 2013-01-10 |
20130012034 | ZIRCONIUM-DOPED TANTALUM OXIDE FILMS - Dielectric layers containing a zirconium-doped tantalum oxide layer, where the zirconium-doped tantalum oxide layer can be formed of one or more monolayers of tantalum oxide doped with zirconium, provide an insulating layer in a variety of structures for use in a wide range of electronic devices. | 2013-01-10 |
20130012035 | Substrate Processing Apparatus and Method of Manufacturing Semiconductor Device - A substrate processing apparatus capable of increasing the life span of a lamp for heating a substrate is provided. The substrate processing apparatus includes: a light receiving chamber for processing a substrate; a substrate support unit inside the light receiving chamber; a lamp including an electrical wire, and a seal accommodating the electrical wire to hermetically seal the lamp with a gas therein, the lamp irradiating the substrate with a light; a lamp receiving unit outside the light receiving chamber to accommodate the lamp therein, the lamp receiving unit including a lamp connector connected to the lamp to supply an electric current through the electrical wire, a heat absorption member including a material having a thermal conductivity higher than that of the seal, and a base member fixing the heat absorption member; and an external electrical wire connected to the lamp connector to supply current to the lamp connector. | 2013-01-10 |
20130012036 | LINE SCAN SEQUENTIAL LATERAL SOLIDIFICATION OF THIN FILMS - A system for preparing a semiconductor film, the system including: a laser source; optics to form a line beam, a stage to support a sample capable of translation; memory for storing a set of instructions, the instructions including irradiating a first region of the film with a first laser pulse to form a first molten zone, said first molten zone having a maximum width (W | 2013-01-10 |
20130012037 | CONTACT DEVICE - A contact device includes a contact point block, a drive unit, and permanent magnets. The contact point block includes fixed terminals having fixed contact points and a movable contactor having movable contact points arranged side by side on one surface of the movable contactor. The movable contact points are configured to come into contact and out of contact with the fixed contact points. The drive unit drives the movable contactor such that the movable contact points come into contact and out of contact with the fixed contact points. The permanent magnets are arranged in a mutually opposing relationship across the contact point block along a direction orthogonal to an arrangement direction of the movable contact points and to a direction in which the movable contact points come into contact and out of contact with the fixed contact points. The permanent magnets are provided with mutually-opposing surfaces having the same polarity. | 2013-01-10 |
20130012038 | HIGH PERFORMANCE, SMALL FORM FACTOR CONNECTOR - Techniques for improving electrical performance of a connector. The techniques are compatible with the form factor of a standardized connector, such as an SFP connector or stacked SFP. The resulting connector has reduced insertion loss for high speed signals. Such techniques, which can be used separately or together, include shaping of conductive elements within the connector while still retaining the same mating contact arrangement. Changes may be made at the contact tail portions or in the intermediate portions where engagement to a connector housing occurs. The techniques also include the incorporation of lossy bridging members between conductive elements designated to be ground conductors. For connectors according to the stacked SFP configuration, multiple bridging members may be incorporated at multiple locations within the connector. | 2013-01-10 |
20130012039 | CONNECTOR - Provided is a connector mountable on a board. The connector comprises a plurality of contacts, a housing holding the contacts, and a monitored member attached to the housing. The monitored member comprises a marker portion and an abutment portion brought into abutment with the board when the connector is mounted on the board in a vertical direction. The abutment portion is apart from the marker portion by a predetermined distance in the vertical direction. The height of the housing is indirectly measured by investigating a position of the marker portion. | 2013-01-10 |