02nd week of 2018 patent applcation highlights part 50 |
Patent application number | Title | Published |
20180012731 | BLANKING APERTURE ARRAY, METHOD FOR MANUFACTURING BLANKING APERTURE ARRAY, AND MULTI-CHARGED PARTICLE BEAM WRITING APPARATUS - In one embodiment, a blanking aperture array is for a multi-charged particle beam writing apparatus. The blanking aperture array includes a substrate and a plurality of blankers. Each of the plurality of blankers includes a blanking electrode and a ground electrode that are formed on a first surface of the substrate. The plurality of blankers includes at least a normal blanker which is capable of applying a predetermined voltage between the blanking electrode and the ground electrode and for which a through hole bored through the substrate is formed, and a defective blanker which is not capable of applying the predetermined voltage between the blanking electrode and the ground electrode and for which the through hole bored through the substrate is filled with a beam shield. | 2018-01-11 |
20180012732 | APPARATUS FOR DEPOSITING METAL FILMS WITH PLASMA TREATMENT - Embodiments of a gas delivery apparatus for use in a radio frequency (RF) processing apparatus are provided herein. In some embodiments, a gas delivery apparatus for use in a radio frequency (RF) processing apparatus includes: a conductive gas line having a first end and a second end; a first flange coupled to the first end; a second flange coupled to the second end, wherein the conductive gas line extends through and between the first and second flanges; and a block of ferrite material surrounding the conductive gas line between the first and second flanges. | 2018-01-11 |
20180012733 | COLLAR, CONICAL SHOWERHEADS AND/OR TOP PLATES FOR REDUCING RECIRCULATION IN A SUBSTRATE PROCESSING SYSTEM - A substrate processing system includes a processing chamber and a showerhead including a faceplate, a stem portion and a cylindrical base portion. A collar connects the showerhead to a top surface of the processing chamber. The collar defines a gas channel to receive secondary purge gas and a plurality of gas slits to direct the secondary purge gas from the gas channel in a radially outward and downward direction. A conical surface is arranged adjacent to the cylindrical base and around the stem portion of the showerhead. An inverted conical surface is arranged adjacent to a top surface and sidewalls of the processing chamber. The conical surface and the inverted conical surface define an angled gas channel from the plurality of gas slits to a gap defined between a radially outer portion of the cylindrical base portion and the sidewalls of the processing chamber. | 2018-01-11 |
20180012734 | SUBSTRATE PROCESSING DEVICE - A substrate processing device includes a housing connected to ground, a cathode stage that supports a substrate, an anode unit, and a gas feeding unit that feeds gas toward the first plate. The cathode stage is applied with voltage for generating plasma. The anode unit includes a first plate including first through holes and a second plate including second through holes that are larger than the first through holes. The second plate is located between the first plate and the cathode stage. The first plate produces a flow of the gas through the first through holes. The gas that has passed through the first through holes flows through the second through holes into an area between the second plate and the cathode stage. A distance between the first plate and the second plate is 10 mm or greater and 50 mm or less. | 2018-01-11 |
20180012735 | GAS SUPPLY SYSTEM, SUBSTRATE PROCESSING SYSTEM AND GAS SUPPLY METHOD - A gas supply system includes: a first flow channel connecting a first gas source and a chamber; a second flow channel connecting a second gas source and the first flow channel; a control valve, provided in the second flow channel, configured to control a flow rate of the second gas; an orifice provided downstream of the control valve and at a terminus of the second flow channel; a switching valve, provided at a connection point between the first flow channel and the terminus of the second flow channel, configured to control a supply timing of the second gas; an exhaust mechanism, connected to a flow channel between the control valve and the orifice in the second flow channel, configured to exhaust the second gas; and a controller configured to bring the control valve, the switching valve and the exhaust mechanism into operation. | 2018-01-11 |
20180012736 | PLASMA PROCESSING APPARATUS - At a time point T | 2018-01-11 |
20180012737 | Plasma Monitoring Device - A plasma monitoring device includes a fixing unit, a plasma measuring unit disposed to be in contact with the fixing unit, and measuring a luminous intensity of emitted light of a plasma to output a luminous intensity measurement value, a reference light source unit irradiating reference light having a uniform luminous intensity to the plasma measuring unit, and a control unit receiving the luminous intensity measurement value to calculate a luminous intensity value of the emitted light, controlling a voltage applied to the reference light source unit to uniformly control a luminous intensity of the reference light, comparing a luminous intensity of the reference light irradiated to the plasma measuring unit with a previously stored luminous intensity reference value to detect a correction factor, and applying the correction factor to a luminous intensity value of the emitted light to correct the luminous intensity measurement value. | 2018-01-11 |
20180012738 | MAGNETRON PLASMA APPARATUS - A magnetron plasma apparatus boosted by hollow cathode plasma includes at least one electrically connected pair of a first hollow cathode plate and a second hollow cathode plate placed opposite to each other at a separation distance of at least 0.1 mm and having an opening following an outer edge of a sputter erosion zone on a magnetron target so that a magnetron magnetic field forms a perpendicular magnetic component inside a hollow cathode slit between plates and, wherein the plates and are connected to a first electric power generator together with the magnetron target to generate a magnetically enhanced hollow cathode plasma in at least one of a first working gas distributed in the hollow cathode slit and a second working gas admitted outside the slit in contact with a magnetron plasma generated in at least one of the first working gas and the second working gas. | 2018-01-11 |
20180012739 | SPUTTERING TARGET AND METHOD FOR MANUFACTURING THE SAME - A novel metal oxide or a novel sputtering target is provided. A sputtering target includes a conductive material and an insulating material. The insulating material includes an oxide, a nitride, or an oxynitride including an element M | 2018-01-11 |
20180012740 | MASS SPECTROMETER - In a device adjustment process, when a solenoid valve is opened, a gas resulting from vaporization of PFTBA held in a container is drawn into an ion source, a relationship between ambient temperature and a correction coefficient for actual signal values is experimentally determined beforehand. In an actual adjustment process, an ambient temperature acquirer reads the ambient temperature and refers to the correction information to determine the correction coefficient corresponding to the ambient temperature at that moment. A signal value corrector multiplies an actually measured peak area value by the correction coefficient to correct the actual signal value. A device adjustment controller adjusts a voltage applied to an ion detector so that the corrected actual signal value matches with a reference signal value. The voltage applied to the ion detector can be thereby adjusted so that the detector has the same level of gain independent of the ambient temperature. | 2018-01-11 |
20180012741 | SUPPRESSING HARMONIC SIGNALS IN ION CYCLOTRON RESONANCE MASS SPECTROMETRY - The invention relates to reducing harmonic signals in FT-ICR spectra. Since harmonic signals in quadrupolar 2ω-detection can be more abundant for the same ion motion in the ICR cell as compared to harmonic signals in classical dipolar 1ω-detection, they could hitherto not be reduced to satisfactory levels by any known method, such as gated deflection during ion introduction into, and correcting for an offset electric field axis in the ICR cell. The present disclosure foresees, in addition to other methods carried out for improving the measurement conditions as the case may be, performing the quadrupolar 2ω-detection at least twice, where the phase of the ion excitation radio frequency is turned by 180° in the second measurement. From the sum transient, a Fourier-transformed spectrum is derived. As a result, the broad band spectra of complex substance mixtures like crude oil become cleaner, and misinterpretations of false (harmonic) peaks are minimized. | 2018-01-11 |
20180012742 | Rapid Scanning of Wide Quadrupole RF Windows While Toggling Fragmentation Energy - A sample is ionized using an ion source and the ion beam is received using a tandem mass spectrometer. An m/z range is divided into two or more precursor ion isolation windows. Two or more values for a fragmentation parameter are selected. A first value of the two or more values for the fragmentation parameter has a level that fragments a minimal amount of ions of the ion beam. The one or more additional values have increasingly aggressive levels that produce increasingly more fragmentation of the ions of the ion beam. For each precursor ion isolation window, the tandem mass spectrometer is instructed to perform a selection and fragmentation of the ion beam using the precursor ion isolation window and the first value and is instructed to perform one or more additional selections and fragmentations of the ion beam using the precursor ion isolation window and using the one or more additional values. | 2018-01-11 |
20180012743 | Method of Charge Reduction of Electron Transfer Dissociation Product Ions - A mass spectrometer is disclosed wherein highly charged fragment ions resulting from Electron Transfer Dissociation fragmentation of parent ions are reduced in charge state within a Proton Transfer Reaction cell by reacting the fragment ions with a neutral superbase reagent gas such as Octahydropyrimidolazepine. | 2018-01-11 |
20180012744 | Device for Improved Detection of Ions in Mass Spectrometry - An electron multiplier is positioned relative to at least one dynode to direct a beam of secondary particles from the at least one dynode to a collector area of the electron multiplier and not to a channel area of the electron multiplier for a range of electron multiplier voltages applied by one or more voltage sources to the electron multiplier and for a dynode voltage applied by the one or more voltage sources to the at least one dynode. The electron multiplier includes an aperture with an entrance cone and walls of the entrance cone comprise the collector area and an apex of the entrance cone comprises the channel area. An electron multiplier voltage of the range of electron multiplier voltages is applied to the electron multiplier and the dynode voltage is applied to the at least one dynode using the one or more voltage sources. | 2018-01-11 |
20180012745 | MASS SPECTROMETRY USING LASERSPRAY IONIZATION - Disclosed herein are systems and methods for mass spectrometry using laserspray ionization (LSI). LSI can create multiply-charged ions at atmospheric pressure for analysis and allows for analysis of high molecular weight molecules including molecules over 4000 Daltons. The analysis can be solvent-based or solvent-free. Solvent-free analysis following LSI allows for improved spatial resolution beneficial in surface and/or tissue imaging. | 2018-01-11 |
20180012746 | PROBES, SYSTEMS, CARTRIDGES, AND METHODS OF USE THEREOF - The invention generally relates to probes, systems, cartridges, and methods of use thereof. In certain embodiments, the invention provides a probe including a porous material and a hollow member coupled to a distal portion of the porous material. | 2018-01-11 |
20180012747 | METHODS FOR TRANSFERRING IONS IN A MASS SPECTROMETER - A method for transporting ions includes: providing an ion transfer tube having an axis and an internal bore having a width and a height less than the width; and providing an apparatus comprising a plurality of electrodes, each having a respective ion aperture having an aperture center, the apertures defining an ion channel configured to receive the ions from the ion transfer tube and to transport the ions to an outlet end of the apparatus, wherein at least a subset of the apertures progressively decrease in size in a direction towards the apparatus outlet end, wherein the ion transfer tube is configured such that the ion transfer tube axis is non-coincident with an axis of the ion channel or such that the width dimension of the ion transfer tube bore is parallel to a plane defined by the ion transfer tube axis and the ion channel axis. | 2018-01-11 |
20180012748 | SYSTEMS AND METHODS FOR BUBBLE BASED ION SOURCES - The present disclosure describes embodiments directed to a bubble based ion source system comprising an ion source configured to generate a plurality of ions, an ion channel, an electrode, and/or any other components. The ion source can include a container at least partially comprising a solvent or solution, a bubble generator coupled to the container configured to generate a plurality of bubbles within the solvent, and/or any other component. The ion channel can receive ions that are generated based on solvent from the bubbles. | 2018-01-11 |
20180012749 | SYSTEM AND METHOD FOR TESTING THE CHEMICAL CONTENT OF PLASTIC CONTAINERS MOVING ALONG A TEST LINE - A system for testing the chemical content of a plurality of plastic containers continuously moving along a test line. The system includes a detector maintained at a first vacuum level for sequentially receiving a sample of air from each of the plurality of plastic containers as they move along the test line and for detecting the chemical content of each of the samples. There is a conduit including a first end proximate the plurality of plastic containers and a second, remote end. There is a sensor module interfacing the conduit between its first end and the second ends. There is also a vacuum pump interconnected to the second end of the conduit to maintain the interior of the conduit at a second, lower vacuum level and to establish an airflow rate to sequentially withdraw and transport air samples from the plastic containers to the sensor module. | 2018-01-11 |
20180012750 | LIGHT SOURCE DEVICE - In a light source device, a control unit causes an energy density of a laser light in a lighting start region RS when a laser support light is maintained to be lower than an energy density of the laser light in the lighting start region RS when the laser support light is put on. For this reason, when the laser support light is maintained, a laser light L is radiated to the lighting start region RS at an energy density of a degree where sputtering does not occur. Therefore, in the light source device, because sputtering in a light emission sealing body can be suppressed, a sufficiently long life can be realized. | 2018-01-11 |
20180012751 | KIT AND LAMINATE - Provided are a kit and a laminate which are capable of suppressing residues derived from a temporary adhesive in manufacture of a semiconductor. The kit for manufacturing a semiconductor device includes a composition which contains a solvent A; a composition which contains a solvent B; and a composition which contains a solvent C, in which the kit is used when a temporary adhesive layer is formed on a first substrate using a temporary adhesive composition containing a temporary adhesive and the solvent A, at least some of an excessive amount of the temporary adhesive on the first substrate is washed using the composition containing the solvent B, a laminate is manufactured by bonding the first substrate and a second substrate through the temporary adhesive layer, one of the first substrate and the second substrate is peeled off from the laminate at a temperature of lower than 40° C., and then the temporary adhesive remaining on at least one of the first substrate or the second substrate is washed using the composition containing the solvent C, and the solvent A, the solvent B, and the solvent C respectively satisfy a predetermined vapor pressure and a predetermined saturated solubility. | 2018-01-11 |
20180012752 | METHOD AND APPARATUS FOR SELECTIVE FILM DEPOSITION USING A CYCLIC TREATMENT - A method is provided for selective film deposition on a substrate. According to one embodiment, the method includes providing a substrate containing a first material having a first surface and second material having a second surface, where the first material includes a dielectric material and the second material contains a semiconductor material or a metal-containing material that excludes a metal oxide, reacting the first surface with a reactant gas containing a hydrophobic functional group to form a hydrophobic first surface, and depositing, by gas phase deposition, a metal oxide film on the second surface, where deposition of the metal oxide film is hindered on the hydrophobic first surface. | 2018-01-11 |
20180012753 | METHOD FOR PRODUCING A PASSIVATED SEMICONDUCTOR STRUCTURE BASED ON GROUP III NITRIDES, AND ONE SUCH STRUCTURE - The invention relates to a method for producing a semiconductor structure, characterised in that the method comprises a step ( | 2018-01-11 |
20180012754 | WET ETCHING METHOD, SUBSTRATE LIQUID PROCESSING APPARATUS, AND STORAGE MEDIUM - This wet etching method comprises rotating a substrate (W), supplying an etching chemical to a first surface (a surface for forming a device) of the rotating substrate, and supplying an etching inhibitor (DIW) to a second surface (a surface which is not used for forming a device) during the supplying the etching chemical to the substrate. The etching inhibitor moves past an edge (WE) of the substrate to swirl onto the first surface and reaches a first region extending from the edge of the substrate on the periphery of the first surface to a first radial position located radially inward from the edge on the first surface. Thus, it is possible to perform an excellent bevel etching treatment on the upper layer of the substrate having a two-layered film formed thereon. | 2018-01-11 |
20180012755 | APPARATUS AND METHOD FOR TREATING SUBSTRATE - A method for treating a substrate, in which a supercritical fluid is supplied into a chamber, in which the substrate is carried, to treat the substrate, the method including a supply step of supplying the supercritical fluid into the chamber until a pressure of the interior of the chamber reaches a preset pressure, and a substrate treating step of performing a supercritical process while repeating supply and exhaust of the supercritical fluid into and out of the interior of the chamber after the supply step, wherein a flow rate of the supercritical fluid supplied into the chamber in the supply step is variable. | 2018-01-11 |
20180012756 | Method of Forming Insulating Film - There is provided a method of forming an insulating film which includes providing a workpiece having a base portion and a protuberance portion formed to protrude from the base portion; and forming an insulating film on the workpiece by sputtering. The forming an insulating film includes forming the insulating film while changing an angle defined between the workpiece and a target. | 2018-01-11 |
20180012757 | SEMICONDUCTOR STRUCTURE HAVING A GROUP III-V SEMICONDUCTOR LAYER COMPRISING A HEXAGONAL MESH CRYSTALLINE STRUCTURE - A semiconductor structure ( | 2018-01-11 |
20180012758 | EPITAXIAL WAFER MANUFACTURING METHOD, EPITAXIAL WAFER, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE - A method for manufacturing an epitaxial wafer comprising a silicon carbide substrate and a silicon carbide voltage-blocking-layer, the method includes: epitaxially growing a buffer layer on the substrate, doping a main dopant for determining a conductivity type of the buffer layer and doping an auxiliary dopant for capturing minority carriers in the buffer layer at a doping concentration less than the doping concentration of the main dopant, so that the buffer layer enhances capturing and extinction of the minority carriers, the minority carriers flowing in a direction from the voltage-blocking-layer to the substrate, so that the buffer layer has a lower resistivity than the voltage-blocking-layer, and so that the buffer layer includes silicon carbide as a main component; and epitaxially growing the voltage-blocking-layer on the buffer layer. | 2018-01-11 |
20180012759 | TIN OXIDE THIN FILM SPACERS IN SEMICONDUCTOR DEVICE MANUFACTURING - Thin tin oxide films are used as spacers in semiconductor device manufacturing. In one implementation, thin tin oxide film is conformally deposited onto a semiconductor substrate having an exposed layer of a first material (e.g., silicon oxide or silicon nitride) and a plurality of protruding features comprising a second material (e.g., silicon or carbon). For example, 10-100 nm thick tin oxide layer can be deposited using atomic layer deposition. Next, tin oxide film is removed from horizontal surfaces, without being completely removed from the sidewalls of the protruding features. Next, the material of protruding features is etched away, leaving tin oxide spacers on the substrate. This is followed by etching the unprotected portions of the first material, without removal of the spacers. Next, underlying layer is etched, and spacers are removed. Tin-containing particles can be removed from processing chambers by converting them to volatile tin hydride. | 2018-01-11 |
20180012760 | DEVICES AND METHODS OF FORMING SADP ON SRAM AND SAQP ON LOGIC - Devices and methods of fabricating integrated circuit devices with reduced cell height are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a logic area and an SRAM area, a fin material layer, and a hardmask layer; depositing a mandrel over the logic area; depositing a sacrificial spacer layer; etching the sacrificial spacer layer to define a sacrificial set of vertical spacers; etching the hardmask layer; leaving a set of vertical hardmask spacers; depositing a first spacer layer; etching the first spacer layer to define a first set of vertical spacers over the logic area; depositing an SOH layer; etching an opening in the SOH layer over the SRAM area; depositing a second spacer layer; and etching the second spacer layer to define a second set of spacers over the SRAM area. | 2018-01-11 |
20180012761 | Lithography Using High Selectivity Spacers for Pitch Reduction - A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer. | 2018-01-11 |
20180012762 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Plural sessions of proton irradiation are performed by differing ranges from a substrate rear surface side. After first to fourth n-type layers of differing depths are formed, the protons are activated. Next, helium is irradiated to a position deeper than the ranges of the proton irradiation from the substrate rear surface, introducing lattice defects. When the amount of lattice defects is adjusted by heat treatment, protons not activated in a fourth n-type layer are diffused, forming a fifth n-type layer contacting an anode side of the fourth n-type layer and having a carrier concentration distribution that decreases toward the anode side by a more gradual slope than that of the fourth n-type layer. The fifth n-type layer that includes protons and helium and the first to fourth n-type layers that include protons constitute an n-type FS layer. Thus, a semiconductor device having improved reliability and lower cost may be provided. | 2018-01-11 |
20180012763 | DOPING METHOD, DOPING APPARATUS, AND SEMICONDUCTOR ELEMENT MANUFACTURING METHOD - Provided is a doping method for doping by injecting a dopant into a processing target substrate. According to this doping method, a value of bias electric power supplied during a plasma doping processing is set to a predetermined value on premise of a washing processing to be performed after a plasma doping, and plasma is generated within a processing vessel using microwaves so as to perform the plasma doping processing on the processing target substrate hold on a holding pedestal in the processing vessel. | 2018-01-11 |
20180012764 | Bipolar Transistor Device With an Emitter Having Two Types of Emitter Regions - Disclosed is a bipolar semiconductor device, comprising a semiconductor body having a first surface; and a base region of a first doping type and a first emitter region in the semiconductor body, wherein the first emitter region adjoins the first surface and comprises a plurality of first type emitter regions of a second doping type complementary to the first doping type, a plurality of second type emitter regions of the second doping type, a plurality of third type emitter regions of the first doping type, and a recombination region comprising recombination centers, wherein the first type emitter regions and the second type emitter regions extend from the first surface into the semiconductor body, wherein the first type emitter regions have a higher doping concentration and extend deeper into the semiconductor body from the first surface than the second type emitter regions, wherein the third type emitter regions adjoin the first type emitter regions and the second type emitter regions, and wherein the recombination region is located at least in the first type emitter regions and the third type emitter regions. | 2018-01-11 |
20180012765 | SEMICONDUCTOR DEVICE, RELATED MANUFACTURING METHOD, AND RELATED ELECTRONIC DEVICE - A semiconductor device may include the following elements: a first doped region; a second doped region, which contacts the first doped region; a third doped region, which contacts the first doped region; a first dielectric layer, which contacts the above-mentioned doped regions; a first gate member, which is conductive and comprises a first gate portion, a second gate portion, and a third gate portion, wherein the first gate portion contacts the first dielectric layer, wherein the second gate portion is positioned between the first gate portion and the third gate portion, and wherein a width of the second portion is unequal to a width of the third gate portion; a doped portion, which is positioned between the third gate portion and the third doped region; a second gate member; and a second dielectric layer, which is positioned between the third gate portion and the second gate member. | 2018-01-11 |
20180012766 | METHOD OF FORMING SPACERS FOR A GATE OF A TRANSISTOR - A method for forming spacers of a gate of a field effect transistor is provided, the gate including sides and a top and being located above a layer of a semiconductor material, the method including a step of forming a dielectric layer that covers the gate; after the step of forming the dielectric layer, at least one step of modifying the dielectric layer by ion implantation while retaining non-modified portions of the dielectric layer covering sides of the gate and being at least non-modified over their entire thickness; the ions having a hydrogen base and/or a helium base; at least one step of removing the modified dielectric layer using a selective etching of the dielectric layer, wherein the removing includes a wet etching with a base of a solution including hydrofluoric acid diluted to x % by weight, with x≦0.2, and having a pH less than or equal to 1.5. | 2018-01-11 |
20180012767 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor wafer serving as a treatment target has a stack structure in which a high-dielectric-constant gate insulating film is formed on a silicon base material with an interface layer film of silicon dioxide sandwiched therebetween, and a metal gate electrode containing fluorine is further formed thereon. A heat treatment apparatus radiates flash light from a flash lamp to the semiconductor wafer in an atmosphere containing hydrogen to carry out heating treatment for an extremely short period of time of 100 milliseconds or less. As a result, diffusion of nitrogen contained in the metal gate electrode is inhibited, at the same time, only the fluorine is diffused from the high-dielectric-constant gate insulating film to an interface between the interface layer film and the silicon base material to reduce an interface state, and reliability of the gate stack structure can be improved. | 2018-01-11 |
20180012768 | Plasma Processing Apparatus and Plasma Processing Method - A plasma processing, apparatus of an embodiment includes a chamber, an introducing part, a first power source, a holder, an electrode, and a second power source. The introducing pat introduces gas into the chamber. The first power source outputs a first voltage for generating ions from the gas. The holder holds a substrate. The electrode is opposite to the ions across the substrate, and has a surface not parallel to the substrate. The second power source applies a second voltage to the electrode. The second voltage has a frequency lower than the frequency of the first voltage and Introduces die ions to the substrate. | 2018-01-11 |
20180012769 | STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE - Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure. The semiconductor device structure further includes a spacer element over a sidewall of the gate stack. The spacer element includes a first layer and a second layer over the first layer. The dielectric constant of the first layer is greater than the dielectric constant of the second layer. A gate dielectric layer of the gate stack adjoins the first layer and the second layer. | 2018-01-11 |
20180012770 | GaN-on-Si SEMICONDUCTOR DEVICE STRUCTURES FOR HIGH CURRENT/ HIGH VOLTAGE LATERAL GaN TRANSISTORS AND METHODS OF FABRICATION THEREOF - A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions. | 2018-01-11 |
20180012771 | METHOD OF PLANARIZING SUBSTRATE SURFACE - A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer. | 2018-01-11 |
20180012772 | METHOD OF PLANARIZING SUBSTRATE SURFACE - A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer. | 2018-01-11 |
20180012773 | POWER SEMICONDUCTOR DEVICE WITH THICK TOP-METAL-DESIGN AND METHOD FOR MANUFACTURING SUCH POWER SEMICONDUCTOR DEVICE - The present application contemplates a method for manufacturing a power semiconductor device. The method comprises: providing a wafer of a first conductivity type, the wafer having a first main side and a second main side opposite to the first main side, and the wafer including an active cell area, which extends from the first main side to the second main side, in a central part of the wafer and a termination area surrounding the active cell area in an orthogonal projection onto a plane parallel to the first main side; forming a metallization layer on the first main side to electrically contact the wafer in the active cell area, wherein the surface of the metallization layer, which faces away from the wafer, defines a first plane parallel to the first main side; forming an isolation layer on the first main side in the termination area, wherein the surface of the isolation layer facing away from the wafer defines a second plane parallel to the first main side; after the step of forming the metallization layer and after the step of forming the isolation layer, mounting the wafer with its first main side to a flat surface of a chuck; and thereafter thinning the wafer from its second main side by grinding while pressing the second main side of the wafer onto a grinding wheel by applying a pressure between the chuck and the grinding wheel, wherein the first plane is further away from the wafer than a third plane, which is parallel to the second plane and arranged at a distance of 1 μm from the second plane in a direction towards the wafer. | 2018-01-11 |
20180012774 | ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF - An electronic package including a middle patterned conductive layer, a first redistribution circuitry disposed on a first surface of the middle patterned conductive layer and a second redistribution circuitry disposed on a second surface of the middle patterned conductive layer is provided. The middle patterned conductive layer has a plurality of middle conductive pads. The first redistribution circuitry includes a first patterned conductive layer having a plurality of first conductive elements. Each of the first conductive elements has a first conductive pad and a first conductive via that form a T-shaped section. The second redistribution circuitry includes a second patterned conductive layer having a plurality of second conductive elements. Each of the second conductive elements has a second conductive pad and a second conductive via that form an inversed T-shaped section. | 2018-01-11 |
20180012775 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - In a method of manufacturing a semiconductor memory device, a plurality of first conductive structures including a first conductive pattern and a hard mask are sequentially stacked on a substrate. A plurality of preliminary spacer structures including first spacers, sacrificial spacers and second spacers are sequentially stacked on sidewalls of the conductive structures. A plurality of pad structures are formed on the substrate between the preliminary spacer structures, and define openings exposing an upper portion of the sacrificial spacers. A first mask pattern is formed to cover surfaces of the pad structures, and expose the upper portion of the sacrificial spacers. The sacrificial spacers are removed to form first spacer structures having respective air spacers, and the first spacer structures include the first spacers, the air spacers and the second spacers sequentially stacked on the sidewalls of the conductive structures. | 2018-01-11 |
20180012776 | VACUUM ASSISTED SEALING PROCESSES & SYSTEMS FOR INCREASING AIR CAVITY PACKAGE MANUFACTURING RATES - The present disclosure describes a sealing processes and structure for sealing air cavity electronic packages using a thermosetting, thermal plastic, other known or as yet unknown adhesives, or hybrid combinations of such adhesive(s). Processes disclosed comprise steps of providing a base and a lid, with at least one of the base and the lid having a mating surface coated with the adhesive. Initially, an air gap is maintained between the base, the lid, and the adhesive and a vacuum is generated around the base, the lid, and the adhesive. Once the vacuum has been generated, the base and the lid are mated to create a mated package assembly with a vacuum therein. After the mating, the mated package assembly is heated to a curing temperature to cure the adhesive, and pressure may be applied as well. Because the air within the mated package assembly has been evacuated prior to heating, there is no air pressure build-up therein, reducing or eliminating the presence of blowouts and pin holes. | 2018-01-11 |
20180012777 | SUBSTRATE LIQUID PROCESSING APPARATUS, SUBSTRATE LIQUID PROCESSING METHOD AND STORAGE MEDIUM - A substrate liquid processing apparatus includes a liquid processing unit configured to process a substrate by a processing liquid, and a controller. The controller processes the substrate in the liquid processing unit, and switches the processing liquid discharged from a discharge line, from a recycling line, to a waste line in which the processing liquid is discarded through the discharge line to the outside, according to a concentration of an elution component eluted from the substrate. | 2018-01-11 |
20180012778 | SUBSTRATE PROCESSING APPARATUS - In a substrate processing apparatus, a cup part is moved in an up-down direction to cause a cup exhaust port to selectively overlap a first chamber exhaust port or a second chamber exhaust port. In the state in which the cup exhaust port overlaps the first chamber exhaust port, gas in the cup part is discharged through the cup exhaust port and the first chamber exhaust port by a first exhaust mechanism. In the state in which the cup exhaust port overlaps the second chamber exhaust port, the gas in the cup part is discharged through the cup exhaust port and the second chamber exhaust port by a second exhaust mechanism. In this way, an exhaust mechanism for exhausting gas from the cup part can be easily switched between the first exhaust mechanism and the second exhaust mechanism. | 2018-01-11 |
20180012779 | PURGE MODULE JIG AND PURGE MODULE HAVING THE SAME - A purge module jig and a purge module including the purge module jig are provided. The purge module jig and the purge module include a plate having a recessed groove and an opening formed therein, a gas transfer pipe having an elliptical cross section, and a fixing part fixing the plate and the gas transfer pipe with each other, so that leakage of cleaning gas is prevented, thickness thereof is reduced, the interference between the jig and a wafer cassette is reduced, the purge module jig and the purge module can be applied to various load ports of various manufactures, and performance thereof can be improved. | 2018-01-11 |
20180012780 | SUBSTRATE PROCESSING APPARATUS - Disclosed is a substrate processing apparatus that includes: a polishing table; an atomizer configured to spray a fluid to a polishing surface; a polishing liquid supply nozzle configured to drop a slurry at a position that corresponds to a slurry dropping position set on the polishing table and is lower than the top surface of the atomizer; a nozzle moving mechanism configured to move the polishing liquid supply nozzle above the atomizer between the retreat position set outside the polishing table and the slurry dropping position; and a nozzle tip retreating mechanism configured to bring the tip end of the polishing liquid supply nozzle into a retreated position above the top surface of the atomizer when the polishing liquid supply nozzle moves between the slurry dropping position and the retreat position. | 2018-01-11 |
20180012781 | SUBSTRATE PROCESSING APPARATUS - A throughput in processing a substrate can be improved and a running cost thereof can be reduced. A substrate processing apparatus | 2018-01-11 |
20180012782 | PHOTOVOLTAIC CELL WITH POROUS SEMICONDUCTOR REGIONS FOR ANCHORING CONTACT TERMINALS, ELECTROLITIC AND ETCHING MODULES, AND RELATED PRODUCTION LINE - A photovoltaic cell is proposed. The photovoltaic cell includes a substrate of semiconductor material, and a plurality of contact terminals each one arranged on a corresponding contact area of the substrate for collecting electric charges being generated in the substrate by the light. For at least one of the contact areas, the substrate includes at least one porous semiconductor region extending from the contact area into the substrate for anchoring the whole corresponding contact terminal on the substrate. In the solution according to an embodiment of the invention, each porous semiconductor region has a porosity decreasing moving away from the contact area inwards the substrate. An etching module and an electrolytic module for processing photovoltaic cells, a production line for producing photovoltaic cells, and a process for producing photovoltaic cells are also proposed. | 2018-01-11 |
20180012783 | TRANSPORTING SYSTEM AND TRANSPORTING UNIT INCLUDED THEREIN - A transporting system includes a first rail including a first region and a second region, the first region being a region where the first rail extends linearly and the second region being a region where the first rail is curved. A second rail includes a third region, separated from the first region, and a fourth region overlapping the second region, wherein the first and second rails merge at a joining location that includes the second region and the fourth region. Optical lines are disposed in the second region and the fourth region, wherein the optical lines are parallel to each other in the fourth region. A first transporting unit travels on the first rail. A second transporting unit travels on the second rail. A first controller controls the traveling of the first and second transporting units using light transmitted or received through the optical lines. | 2018-01-11 |
20180012784 | PLASMA PROCESSING-APPARATUS PROCESSING OBJECT SUPPORT PLATFORM, PLASMA PROCESSING APPARATUS, AND PLASMA PROCESSING METHOD - According to one embodiment, a plasma processing-apparatus processing object support platform includes a lower plate, an upper plate, and a variable condenser. The lower plate is electrically conductive. The upper plate is provided on the lower plate. A processing object is placed on an upper surface of the upper plate. The variable condenser is provided along a circumferential direction of the lower plate in a region at an upper outer circumferential vicinity of the lower plate. The region has an annular configuration. The variable condenser includes a first capacitance element and a second capacitance element disposed respectively on an inner circumferential side and an outer circumferential side in the region having the annular configuration. Mutually-different control voltages are suppliable to the first capacitance element and the second capacitance element. | 2018-01-11 |
20180012785 | ELECTROSTATIC CHUCK WITH FEATURES FOR PREVENTING ELECTRICAL ARCING AND LIGHT-UP AND IMPROVING PROCESS UNIFORMITY - A substrate support for a substrate processing system includes a baseplate, a bond layer provided on the baseplate, and a ceramic layer arranged on the bond layer. The ceramic layer includes a first region and a second region located radially outward of the first region, the first region has a first thickness, the second region has a second thickness, and the first thickness is greater than the second thickness. | 2018-01-11 |
20180012786 | METHOD FOR REALIZING ULTRA-THIN SENSORS AND ELECTRONICS WITH ENHANCED FRAGILILTY - A method of fabricating ultra-thin semiconductor devices includes forming an array of semiconductor dielets mechanically suspended on a frame with at least one tether connecting each semiconductor dielet of the array of semiconductor dielets to the frame. | 2018-01-11 |
20180012787 | METHOD OF PROCESSING A SEMICONDUCTOR WAFER, SEMICONDUCTOR CHIP, AND SURFACE PROTECTIVE TAPE - A method of processing a semiconductor wafer, in which a mask is formed: by cutting, with CO | 2018-01-11 |
20180012788 | WAFER-FIXING TAPE, METHOD OF PROCESSING A SEMICONDUCTOR WAFER, AND SEMICONDUCTOR CHIP - A wafer-fixing tape, having: an temporary-adhesive layer provided on a substrate film, wherein the substrate film contains an ionomer resin comprising a terpolymer crosslinked by a metal ion, and wherein an arithmetic average roughness Ra of a surface of the substrate film opposite to the temporary-adhesive layer | 2018-01-11 |
20180012789 | ROBOTIC APPARATUS AND METHOD FOR TRANSPORT OF A WORKPIECE - A robotic apparatus for transporting a workpiece includes a first arm that pivots about a first axis and a second arm that is pivotably connected to the first arm. The second arm has a surface upon which the workpiece can be received. A first drive unit of the robotic apparatus drives the first arm member to pivot about the first axis. The robotic apparatus includes a controller that controls the first drive unit to move the surface of the second arm member to transport the workpiece. The control unit also controls the first drive unit such that the surface is not moved at an acceleration value that exceeds a predetermined acceleration limit during the transport of the workpiece. | 2018-01-11 |
20180012790 | SUBSTRATE CARRIER - Embodiments of substrate carriers and method of making the same are provided herein. In some embodiments, a substrate carrier includes a substantially planar body; and a plurality of holding elements arranged on a surface of the substantially planar body, wherein the plurality of holding elements are configured to hold a plurality of substrates on the surface of the substantially planar body, and wherein the plurality of holding elements includes at least three holding elements disposed around a corresponding position of each of the plurality of substrates. | 2018-01-11 |
20180012791 | INTERCONNECTS WITH INNER SACRIFICIAL SPACERS - Interconnect structures and methods of forming such interconnect structures. A spacer is formed inside an opening in a dielectric layer. After the spacer is formed, a conductive plug is formed inside the opening in the dielectric layer. After the conductive plug is formed, the spacer is removed to define an air gap located inside the opening in the dielectric layer. The air gap is located between the conductive plug and the opening in the dielectric layer. | 2018-01-11 |
20180012792 | SELECTIVE FILM DEPOSITION METHOD TO FORM AIR GAPS - A method for depositing a film to form an air gap within a semiconductor device is disclosed. An exemplary method comprises pulsing a metal halide precursor onto the substrate and pulsing an oxygen precursor onto a selective deposition surface. The method can be used to form an air gap to, for example, reduce a parasitic resistance of the semiconductor device. | 2018-01-11 |
20180012793 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a stop layer between the dielectric layer and the substrate, wherein the stop layer contacts the substrate directly and the dielectric layer covers the top surface of the stop layer; forming an opening in the dielectric layer, wherein the dielectric layer comprises a damaged layer adjacent to the opening; forming a dielectric protective layer in the opening; forming a metal layer in the opening; removing the damaged layer and the dielectric protective layer to form a void, wherein the void exposes a top surface of the substrate; and forming a cap layer on and covering the dielectric layer, the void, and the metal layer. | 2018-01-11 |
20180012794 | WIRING STRUCTURE AND METHOD OF FORMING A WIRING STRUCTURE - A method of forming a mask layout includes forming a layout of a first mask including a lower wiring structure pattern and a dummy lower wiring structure pattern. A layout of a second mask overlapping the first mask and including an upper wiring structure pattern and a dummy upper wiring structure pattern is formed. A layout of a third mask including a first via structure pattern and a first dummy via structure pattern is formed. A layout of a fourth mask including a second via structure pattern and a second dummy via structure pattern is formed. The second via structure pattern may commonly overlap the lower wiring structure pattern and the upper wiring structure pattern, and the second dummy via structure pattern may commonly overlap the dummy lower wiring structure pattern and the dummy upper wiring structure pattern. The fourth mask may overlap the third mask. | 2018-01-11 |
20180012795 | DESIGN-AWARE PATTERN DENSITY CONTROL IN DIRECTED SELF-ASSEMBLY GRAPHOEPITAXY PROCESS - A method for local pattern density control of a device layout used by graphoepitaxy directed self-assembly (DSA) processes includes importing a multi-layer semiconductor device design into an assist feature system and determining overlapping regions between two or more layers in the multi-layer semiconductor device design using at least one Boolean operation. A fill for assist features is generated to provide dimensional consistency of device features by employing the overlapping regions to provide placement of the assist features. An updated device layout is stored in a memory device. | 2018-01-11 |
20180012796 | INTERCONNECT STRUCTURE FORMED WITH A HIGH ASPECT RATIO SINGLE DAMASCENE COPPER LINE ON A NON-DAMASCENE VIA - An interconnect structure and a method to form an interconnect structure utilizes a high-aspect ratio single-damascene line and a non-damascene via. The interconnect includes a first single-damascene interconnect line disposed in a first interlayer dielectric layer, and a non-damascene via on the first single-damascene interconnect line that may be formed from cobalt, titanium and/or tungsten. A first SiCN layer may be formed on one or more sidewalls of the non-damascene via. A second single-damascene layer may be formed on the non-damascene via in which the second single-damascene layer may be disposed in a second interlayer dielectric layer. A second SiCN layer may be formed on at least part of an upper surface of the first single-damascene layer, and a third SiCN layer may be formed on at least part of an upper surface of the second single-damascene layer. | 2018-01-11 |
20180012797 | METHOD FOR REDUCING VIA RC DELAY - A method for manufacturing an interconnect structure includes providing a substrate structure including a substrate, a first metal layer on the substrate, a dielectric layer on the substrate and covering the first metal layer, and an opening extending to the first metal layer; forming a first barrier layer on a bottom and sidewalls of the opening with a first substrate bias; forming a second barrier layer on the first barrier layer with a second substrate bias, the second substrate bias being greater than the first substrate bias, the first and second barrier layers forming collectively a barrier layer; removing a portion of the barrier layer on the bottom and on the sidewalls of the opening by bombarding the barrier layer with a plasma with a vertical substrate bias; and forming a second metal layer filling the opening. | 2018-01-11 |
20180012798 | METHOD AND APPARATUS FOR PLACING A GATE CONTACT INSIDE A SEMICONDUCTOR ACTIVE REGION HAVING HIGH-K DIELECTRIC GATE CAPS - A method provides a structure having a FinFET in an Rx region, the FinFET including a channel, source/drain (S/D) regions and a gate, the gate including gate metal. A cap is formed over the gate having a high-k dielectric liner and a core. Trench silicide (TS) is disposed on sides of the gate. The TS is recessed to a level above a level of the gate and below a level of the cap. An oxide layer is disposed over the structure. A CB trench is patterned into the oxide layer within the Rx region to expose the core and liner at an intermediate portion of the CB trench. The core is selectively etched relative to the liner to extend the CB trench to a bottom at the gate metal. The CB trench is metalized to form a CB contact. | 2018-01-11 |
20180012799 | INTEGRATED ANTENNA ON INTERPOSER SUBSTRATE - Some embodiments relate to a semiconductor module having an integrated antenna structure. The semiconductor module has an excitable element and a first ground plane disposed between a substrate and the excitable element. A second ground plane is separated from the first ground plane by the substrate. The second ground plane is coupled to the first ground plane by one or more through-substrate vias (TSVs) that extend through the substrate. | 2018-01-11 |
20180012800 | DEVICE WITHOUT ZERO MARK LAYER - Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through silicon via (TSV) opening is formed in the substrate. The TSV opening extends through the first and second surfaces of the substrate. An alignment trench corresponding to an alignment mark is formed in the substrate. The alignment trench extends from the first surface of the substrate to a depth shallower than a depth of the TSV opening. A dielectric liner layer is provided over the substrate. The dielectric liner layer at least lines sidewalls of the TSV opening. A conductive layer is provided over the substrate. The conductive layer fills at least the TSV opening to form TSV contact. A redistribution layer (RDL) is formed over the substrate. The RDL layer is patterned using a reticle to form at least one opening which corresponds to a TSV contact pad. The reticle is aligned using the alignment mark in the substrate. | 2018-01-11 |
20180012801 | METHOD FOR PRODUCING A PLURALITY OF SEMICONDUCTOR CHIPS AND SEMICONDUCTOR CHIP - According to the present disclosure, a method for producing a plurality of semiconductor chips is provided with the following steps: a) providing a composite assembly, including a carrier, a semiconductor layer sequence and a functional layer; b) severing the functional layer by means of coherent radiation along a singulation pattern; c) forming separating trenches in the carrier along the singulation pattern; and d) applying a protective layer, which delimits the functional layer toward the separating trenches, on in each case at least one side surface of the semiconductor chips to be singulated. The singulated semiconductor chips each includes a part of the semiconductor layer sequence, of the carrier and of the functional layer. | 2018-01-11 |
20180012802 | ELEMENT CHIP MANUFACTURING METHOD - A semiconductor chip manufacturing method includes preparing a semiconductor wafer including a front surface on which a bump is exposed, a rear surface located at a side opposite to the front surface, a plurality of element regions in each of which the bump is formed, and a dividing region defining each of the element regions, forming a mask which covers the bump and has an opening exposing the dividing region on the surface of the semiconductor wafer by spraying liquid which contains raw material of the mask along the bump by a spray coating method, and singulating the semiconductor wafer by exposing the surface of the semiconductor wafer to first plasma and etching the dividing region, which is exposed to the opening, until the rear surface is reached in a state where the bump is covered by the mask. | 2018-01-11 |
20180012803 | INTEGRATED DEVICE DIES AND METHODS FOR SINGULATING THE SAME - Integrated device dies and methods for forming one or more of the integrated device dies are disclosed. The integrated device dies can be formed using two step sawing process; a first sawing step partially sawing a substrate comprising metal and a second sawing step sawing through a remaining thickness of the substrate. | 2018-01-11 |
20180012804 | SEMICONDUCTOR DEVICE CHIP MANUFACTURING METHOD - Disclosed herein is a semiconductor device chip manufacturing method including a chipping prevention layer forming step of forming a chipping prevention layer at each intersection of a plurality of crossing division lines formed on the front side of a wafer, a modified layer forming step of applying a laser beam having a transmission wavelength to the wafer to the back side thereof along each division line in the condition where the focal point of the laser beam is set inside the wafer, thereby forming a modified layer inside the wafer along each division line, and a dividing step of grinding the back side of the wafer after performing the modified layer forming step, thereby reducing the thickness of the wafer and also dividing the wafer into individual semiconductor device chips along each division line where the modified layer is formed as a break start point. | 2018-01-11 |
20180012805 | SEMICONDUCTOR STRUCTURE WITH SELF-ALIGNED WELLS AND MULTIPLE CHANNEL MATERIALS - Embodiments of the present invention provide a semiconductor structure having a strain relaxed buffer, and method of fabrication. A strain relaxed buffer is disposed on a semiconductor substrate. A silicon region and silicon germanium region are disposed adjacent to each other on the strain relaxed buffer. An additional region of silicon or silicon germanium provides quantum well isolation. | 2018-01-11 |
20180012806 | SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME - In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A first insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so as to form a gate space in the first insulating layer. A first conductive layer is formed in the gate space so as to form a reduced gate space. The reduced gate space is filled with a second conductive layer made of a different material from the first conductive layer. The filled first conductive layer and the second conductive layer are recessed so as to form a first gate recess. A third conductive layer is formed over the first conductive layer and the second conductive layer in the first gate recess. After recessing the filled first conductive layer and the second conductive layer, the second conductive layer protrudes from the first conductive layer. | 2018-01-11 |
20180012807 | SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF - A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling. | 2018-01-11 |
20180012808 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device is provided. A substrate having a dummy gate thereon is prepared. A spacer is disposed on a sidewall of the dummy gate. A source/drain region is disposed adjacent to the dummy gate. A sacrificial layer is then formed on the source/drain region. A cap layer is then formed on the sacrificial layer. A top surface of the cap layer is coplanar with a top surface of the dummy gate. A replacement metal gate (RMG) process is performed to transform the dummy gate into a replacement metal gate. An opening is then formed in the cap layer to expose a top surface of the sacrificial layer. The sacrificial layer is removed through the opening, thereby forming a lower contact hole exposing a top surface of the source/drain region. A lower contact plug is then formed in the lower contact hole. | 2018-01-11 |
20180012809 | FINFET DEVICE - The present disclosure provides many different embodiments of a FinFET device that provide one or more improvements over the prior art. In one embodiment, a FinFET includes a semiconductor substrate and a plurality of fins having a first height and a plurality of fin having a second height on the semiconductor substrate. The second height may be less than the first height. | 2018-01-11 |
20180012810 | SEMICONDUCTOR STRUCTURES AND FABRICATION METHODS THEREOF - A method for fabricating a semiconductor structure includes providing a base structure including a substrate, a dielectric layer formed on the substrate, a plurality of first openings formed in the dielectric layer in a first transistor region, and a plurality of second openings formed in the dielectric layer in a second transistor region. The method also includes forming a first work function layer an the dielectric layer covering bottom and sidewall surfaces of the first and the second openings, forming a first sacrificial layer in each first opening and each second opening with a top surface lower than the top surface of the dielectric layer, removing a portion of the first work function layer exposed by the first sacrificial layer, removing the first work function layer formed in each first opening, and forming a second work function layer and a gate electrode in each first opening and each second opening. | 2018-01-11 |
20180012811 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - Semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes forming an interlayer dielectric layer on a base substrate; forming a plurality of first openings and second openings in the interlayer dielectric layer, one first opening connecting to a second opening, the one first opening being between the second opening and the base substrate; forming a high-K gate dielectric layer on side and bottom surfaces of the first openings and on side surfaces of the second openings; forming a cap layer, containing oxygen ions, on the high-K gate dielectric layer; forming an amorphous silicon layer on the cap layer at least on the bottoms of the first openings; performing a thermal annealing process on the amorphous silicon layer, the cap layer and the high-K dielectric; removing the amorphous silicon layer; and forming a metal layer, in the first openings and the second openings. | 2018-01-11 |
20180012812 | HETEROGENEOUS INTEGRATION OF 3D SI AND III-V VERTICAL NANOWIRE STRUCTURES FOR MIXED SIGNAL CIRCUITS FABRICATION - A method of forming Si or Ge-based and III-V based vertically integrated nanowires on a single substrate and the resulting device are provided. Embodiments include forming first trenches in a Si, Ge, III-V, or Si | 2018-01-11 |
20180012813 | ADVANCED PROCESS CONTROL METHODS FOR PROCESS-AWARE DIMENSION TARGETING - Disclosed are methods of advanced process control (APC) for particular processes. A particular process (e.g., a photolithography or etch process) is performed on a wafer to create a pattern of features. A parameter is measured on a target feature and the value of the parameter is used for APC. However, instead of performing APC based directly on the actual parameter value, APC is performed based on an adjusted parameter value. Specifically, an offset amount (which is previously determined based on an average of a distribution of parameter values across all of the features) is applied to the actual parameter value to acquire an adjusted parameter value, which better represents the majority of features in the pattern. Performing this APC method minimizes dimension variations from pattern to pattern each time the same pattern is generated on another region of the same wafer or on a different wafer using the particular process. | 2018-01-11 |
20180012814 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second pads separated from each other, first and second test elements connected to the first and second pads and connected to each other in parallel between the first and second pads, a first diode connected to the first test element in series, and a second diode connected to the second test element in series. | 2018-01-11 |
20180012815 | SEMICONDUCTOR DEVICE PACKAGE AND METHODS OF MANUFACTURE THEREOF - A method of manufacturing a packaged semiconductor device includes forming an assembly by placing a semiconductor die over a substrate with a die attach material between the semiconductor die and the substrate. A conformal structure which includes a pressure transmissive material contacts at least a portion of a top surface of the semiconductor die. A pressure is applied to the conformal structure and in turn, the pressure is transmitted to the top surface of the semiconductor die by the pressure transmissive material. While the pressure is applied, concurrently encapsulating the assembly with a molding compound and exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. | 2018-01-11 |
20180012816 | Circuit Package - A circuit package comprises a circuit device in a first epoxy mold compound and a second epoxy mold compound of different compositions. | 2018-01-11 |
20180012817 | PASSIVATION STRUCTURE AND METHOD OF MAKING THE SAME - A passivation structure includes a bottom dielectric layer. The passivation structure further includes a doped dielectric layer over the bottom dielectric layer. The doped dielectric layer includes a first doped layer and a second doped layer. The passivation structure further includes a top dielectric layer over the doped dielectric layer. | 2018-01-11 |
20180012818 | SYSTEMS AND METHODS TO ENHANCE PASSIVATION INTEGRITY - Some embodiments relate to a semiconductor device. The semiconductor device includes a layer disposed over a substrate. A conductive body extends through the layer. A plurality of bar or pillar structures are spaced apart from one another and laterally surround the conductive body. The plurality of bar or pillar structures are generally concentric around the conductive body. | 2018-01-11 |
20180012819 | Semiconductor Devices and Methods of Formation Thereof - In one embodiment, a semiconductor device includes a first contact pad disposed at a top side of a workpiece, a second contact pad disposed at the top side of the workpiece. An isolation region is disposed between the first contact pad and the second contact pad. A metal strip is disposed at least partially within the isolation region. The metal strip is not coupled to an external potential node. | 2018-01-11 |
20180012820 | HEAT SPREADERS WITH INTEGRATED PREFORMS - Embodiments of heat spreaders with integrated preforms, and related devices and methods, are disclosed herein. In some embodiments, a heat spreader may include: a frame formed of a metal material, wherein the metal material is a zinc alloy or an aluminum alloy; a preform secured in the frame, wherein the preform has a thermal conductivity higher than a thermal conductivity of the metal material; and a recess having at least one sidewall formed by the frame. The metal material may have an equiaxed grain structure. In some embodiments, the equiaxed grain structure may be formed by squeeze-casting or rheocasting the metal material. | 2018-01-11 |
20180012821 | PLACEMENT BASE FOR SEMICONDUCTOR DEVICE AND VEHICLE EQUIPMENT - A placement base ( | 2018-01-11 |
20180012822 | A SEMICONDUCTOR MODULE - A semiconductor module includes a baseplate, a cover element attached to the baseplate so that detaching the cover element from the baseplate requires material deformations, and a semiconductor element in a room defined by the baseplate and the cover element. The semiconductor element is in a heat conductive relation with the baseplate and an outer surface of the baseplate is provided with laser machined grooves suitable for conducting heat transfer fluid. The laser machining makes it possible to make the grooves after the semiconductor module has been assembled. Therefore, regular commercially available semiconductor modules can be modified, with the laser machining, to semiconductor modules as disclosed. | 2018-01-11 |
20180012823 | SEMICONDUCTOR DEVICES, VIA STRUCTURES AND METHODS FOR FORMING THE SAME - A semiconductor device includes a via structure penetrating through a substrate, a top metal layer and an electronic component over the via structure, and a bottom metal layer and another electronic component below the via structure. The via structure includes a through hole penetrating from a first surface to an opposite second surface of a substrate, a filling insulating layer within the through hole, a first conductive layer, which is within the through hole and surrounds the filling insulating layer, wherein a portion of the first conductive layer is below the filling insulating layer and at the bottom of the through hole. The via structure further includes a first insulating layer, which is on the sidewalls of the through hole and surrounds the first conductive layer. | 2018-01-11 |
20180012824 | CAPPED THROUGH-SILICON-VIAs FOR 3D INTEGRATED CIRCUITS - The present disclosure relates to a chip including a wafer, a back-end-of-line (BEOL) layer deposited on the wafer, a chip TSV in the wafer containing a conductive material, and a chip cap layer disposed between the chip TSV and the BEOL layer, and configured to reduce via extrusion of conductive material in the chip TSV during operation of the chip. The present disclosure further includes a 3D integrated circuit including a plurality of electrically connected chips, at least one of which is a chip as described above. The disclosure further relates to a 3D integrated circuit with an interposer, a TSV in the interposer containing a conductive material, and an interposer cap layer configured to reduce via extrusion of the conductive material located in the interposer TSV during operation of the circuit. The present disclosure further includes methods of forming such chips and 3D integrated circuits. | 2018-01-11 |
20180012825 | Self-Alignment for Redistribution Layer - An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the electronic devices. Dummy TSVs each extend through the substrate and form an alignment mark on a second side of the substrate. Functional TSVs each extend through the substrate and electrically connect to the electronic devices. A redistribution layer (RDL) formed on the second side of the substrate interconnects ones of the dummy TSVs with ones of the functional TSVs. Step heights of the RDL over the functional TSVs are less than a predetermined value, whereas step heights of the RDL over the dummy TSVs are greater than the predetermined value. | 2018-01-11 |
20180012826 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - An aspect of the present disclosure provides a method of manufacturing a semiconductor device. The method includes: preparing a first semiconductor element and a second semiconductor element, each of the first semiconductor element and the second semiconductor element having an element main surface and an element back surface that face opposite sides to each other; die bonding the element back surface of the first semiconductor element to a pad main surface by using a first solder; and die bonding the element back surface of the second semiconductor element to the pad main surface by using a second solder having a melting point lower than a melting point of the first solder, after die bonding the element back surface of the first semiconductor element to the pad main surface by using the first solder. | 2018-01-11 |
20180012827 | Electronic Components with Integral Lead Frame and Wires - An electronic component includes one or more circuits having electrical connections coupled therewith. The electrical connections include a lead frame as well as electrical wires coupling the circuit or circuits to respective portions of the lead frame. The electrical wires may be formed as one piece with the respective portion of the lead frame without joints therebetween, e.g., by 3D printing. | 2018-01-11 |
20180012828 | LEAD FRAME AND METHOD OF FABRICATING THE SAME - A lead frame is provided, including one or more power terminals and one or more control terminals, wherein at least one of the control terminals is externally terminated with a press-fit contact member, and wherein at least one of the control terminals and at least one power terminals are formed from different materials. With the disclosed lead frame of the invention, lower material cross sections in the power terminals will be provided because of the better electrical conductivity when using pure copper compared to alloys with higher mechanical strengths. Also specific/different plating could be added to the individual needs of the different pin types without using masks in the plating process. | 2018-01-11 |
20180012829 | SEMICONDUCTOR PACKAGE WITH CLIP ALIGNMENT NOTCH - An electronic component includes a leadframe and a first semiconductor die. The leadframe includes a leadframe top side, a leadframe bottom side opposite the leadframe top side, and a top notch at the leadframe top side. The top notch includes a top notch base located between the leadframe top side and the leadframe bottom side, and defining a notch length of the top notch, and can also include a top notch first sidewall extended, along the notch length, from the leadframe top side to the top notch base. The first semiconductor die can include a die top side a die bottom side opposite the die top side and mounted onto the leadframe top side, and a die perimeter. The top notch can be located outside the die perimeter. Other examples and related methods are also disclosed herein. | 2018-01-11 |
20180012830 | Semiconductor Devices, Methods of Manufacture Thereof, and Semiconductor Device Packages - Semiconductor devices, methods of manufacture thereof, and semiconductor device packages are disclosed. In one embodiment, a semiconductor device includes an insulating material layer having openings on a surface of a substrate. One or more insertion bumps are disposed over the insulating material layer. The semiconductor device includes signal bumps having portions that are not disposed over the insulating material layer. | 2018-01-11 |