02nd week of 2012 patent applcation highlights part 27 |
Patent application number | Title | Published |
20120008397 | MEMORY SYSTEM AND METHOD OF OPERATING THE SAME - A memory system includes a flash memory device including a first memory block group on which a least significant bit (LSB) program operation has been performed and a program operation on another bit has not been performed and a second memory block group on which both the LSB program operation and a most significant bit (MSB) program operation have been performed and a memory controller configured to check which of the first and second memory block groups a memory block selected for an LSB data read operation belongs to and set a level of a read voltage for the LSB data read operation of the selected memory block. | 2012-01-12 |
20120008398 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a plurality of global word lines, a plurality of transistors configured to transfer voltages of the global word lines to a plurality of local word lines inside a cell block, and a voltage control unit configured to supply a first negative voltage to a global word line of the plurality of global word lines and configured to charge a bulk region of the plurality of transistors with a second negative voltage. | 2012-01-12 |
20120008399 | METHODS OF OPERATING MEMORIES INCLUDING CHARACTERIZING MEMORY CELL SIGNAL LINES - Methods of operating memories facilitate compensating for memory cell signal line propagation delays, such as to increase the overall threshold voltage range and non-volatile memory cell states available. Methods include selecting a memory cell signal line of a memory and characterizing the memory cell signal line by determining an RC time constant of the memory cell signal line. | 2012-01-12 |
20120008400 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device includes: a memory string; a select transistor; and a carrier selection element. The select transistor has one end connected to one end of the memory string. The carrier selection element has one end connected to the other end of the select transistor, and selects a majority carrier flowing through respective bodies of the memory transistors and the select transistor. The carrier selection element includes: a third semiconductor layer; a metal layer; a second gate insulation layer; and a third conductive layer. The metal layer extends in the vertical direction. The metal layer extends in the vertical direction from the top of the third semiconductor layer. The second gate insulation layer surrounds the third semiconductor layer and the metal layer. The third conductive layer surrounds the third semiconductor layer and the metal layer via the second gate insulation layer and extends in a parallel direction. | 2012-01-12 |
20120008401 | SYSTEMS AND METHODS FOR STORING, RETRIEVING, AND ADJUSTING READ THRESHOLDS IN FLASH MEMORY STORAGE SYSTEM - A method, system and computer-readable medium are provided for reading information from a memory unit. A request may be received to read information from a set of memory cells in the memory unit. At least one read threshold in an initial set of read thresholds may be perturbed to generate a perturbed set of read thresholds. The set of memory cells may be read using the perturbed set of read thresholds to provide a read result. The performance of said reading may be evaluated using the perturbed set of read thresholds. The at least one read threshold may be iteratively perturbed for each sequential read operation that the read performance is evaluated to be sub-optimal. | 2012-01-12 |
20120008402 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A method of operating a semiconductor memory device includes performing an LSB program operation for selected memory cells while raising a program voltage, when the threshold voltages of some of the selected memory cells reach a target level, storing data, corresponding to a relevant program voltage, in a first flag cell, performing the LSB program operation for some of the selected memory cells, having threshold voltages not reached the target level, until the threshold voltages of all the selected memory cells reach the target level, and after the LSB program operation is completed, performing an MSB program operation for the selected memory cells by using a program voltage, set based on the data stored in the first flag cell, as a start program voltage. | 2012-01-12 |
20120008403 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a boost circuit configured to boost a power supply voltage so as to generate first and second voltages, the second voltage being lower than the first voltage, a load circuit supplied with the first voltage, and a capacitor. The capacitor has first and second diffusion regions, a first insulating film formed on a channel region, a first electrode formed on the first insulating film, a second insulating film formed on the first electrode, and a second electrode formed on the second insulating film. The second voltage is applied to the first electrode. The first voltage is applied to the second electrode. The power supply voltage is applied to at least one of the first and second diffusion regions. | 2012-01-12 |
20120008404 | SYSTEM AND METHOD FOR REDUCING PIN-COUNT OF MEMORY DEVICES, AND MEMORY DEVICE TESTERS FOR SAME - Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output terminals that receive address signals and write data signals and transmit read data signals. The input/output terminals are connected to a multiplexer, which is responsive to a received mode control signal to couple the input/output terminals to either a command bus or an input/output bus. A latch in the memory device latches the command signals when the mode control signal causes the input/output terminals to be coupled to the input/output bus. As a result, the command signals continue to be applied to the command bus. When the mode control signal causes the input/output terminals to be coupled to the input/output bus, write data signals are clocked into the memory device and read data signals are clocked out of the memory device responsive to a received clock signal. | 2012-01-12 |
20120008405 | Detection of Broken Word-Lines in Memory Arrays - Techniques and corresponding circuitry are presented for the detection of broken wordlines in a memory array. In an exemplary embodiment, a program operation of the memory circuit is performed on a first plurality of memory cells along a word-line, where the programming operation includes a series of alternating programming pulses and verify operations, with the memory cells individually locking out from further programming pulses as verified. The determination of whether the word-line is defective based on the number of programming pulses for the memory cells of a first subset of the first plurality to verify as programmed relative to the number of programming pulses for the memory cells of a second subset of the first plurality to verify as programmed, where the first and second subsets each contain multiple memory cells and are not the same. | 2012-01-12 |
20120008406 | NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A method of operating a nonvolatile memory device includes programming first memory cells to make threshold voltages of the first memory cells to reach a verification voltage determined based on program data of second memory cells to be programmed, and programming the second memory cells. | 2012-01-12 |
20120008407 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A method of programming a semiconductor memory device includes a first program step for performing a program by supplying a first program voltage, having a specific amount, to a selected word line of the semiconductor memory device for a set time and a second program step for performing a program by supplying, to the selected word line, a second program voltage which is a step pulse gradually rising from a start voltage lower than the first program voltage. | 2012-01-12 |
20120008408 | NON-VOLATILE MEMORY DEVICE AND OPERATING METHOD OF THE SAME - A non-volatile memory device and an operation method of the same are provided. A method for operating a non-volatile memory device includes programming a plurality of memory cells based on a target voltage level, verifying threshold voltage levels of the plurality of memory cells based on a correction voltage level higher than the target voltage level and selecting a memory cell programmed lower than the correction voltage level, and programming the selected memory cell based on the correction voltage level. | 2012-01-12 |
20120008409 | REDUCTION OF QUICK CHARGE LOSS EFFECT IN A MEMORY DEVICE - Methods for reducing quick charge loss effects, methods for programming, memory devices, memory devices, and memory systems are disclosed. In one such method, a programming pulse is applied to the word line to increase the threshold voltage of the memory cells being programmed. A negative voltage pulse is applied to the word line after the programming pulse to force any electrons trapped in the tunnel oxide of memory cells being programmed back into the tunnel region. After the negative pulse, a program verify operation is performed. | 2012-01-12 |
20120008410 | Detection of Word-Line Leakage in Memory Arrays: Current Based Approach - Techniques and corresponding circuitry are presented for the detection of wordline leakage in a memory array. In an exemplary embodiment, a capacitive voltage divider is used to translate the high voltage drop to low voltage drop that can be compared with a reference voltage to determine the voltage drop due to leakage. An on-chip self calibration method can help assure the accuracy of this technique for detecting leakage limit. In other embodiments, the current drawn by a reference array, where a high voltage is applied to the array with all wordlines non-selected, is compared to the current drawn by an array where the high voltage is applied and one or more selected wordlines. In these current based embodiments, the reference array can be a different array, or the same array as that one selected for testing. | 2012-01-12 |
20120008411 | MEMORY APPARATUS INCLUDING PROGRAMMABLE NON-VOLATILE MULTI-BIT MEMORY CELL, AND APPARATUS AND METHOD FOR DEMARCATING MEMORY STATES OF THE CELL - Memory states of a multi-bit memory cell are demarcated by generating read reference signals having levels that constitute boundaries of the memory states. The read reference signals may be dependent upon the levels of programming reference signals used for controlling the programming of the memory cell. The memory cell can thus be programmed without reading out its memory state during the programming process, with programming margins being assured by the dependence of the read reference signals on the programming reference signals. Both sets of reference signals may be generated by reference cells which track variations in the operating characteristics of the memory cell with changes in conditions, such as temperature and system voltages, to enhance the reliability of memory programming and readout. | 2012-01-12 |
20120008412 | NONVOLATILE MEMORY DEVICE AND METHOD OF ERASING THE SAME - A method of erasing a nonvolatile memory device includes the steps of supplying an erase voltage to the P well of a semiconductor substrate having a memory cell block disposed therein; performing a first erase verification operation for verifying the erase state of memory cells coupled to the even bit lines of the memory cell block; making a determination of success or failure for the first erase verification operation; and if, as a result of the determination for the first erase verification operation, all the memory cells coupled to the even bit lines are determined to be erased, performing a second erase verification operation for verifying the erase state of memory cells coupled to odd bit lines of the memory cell block. | 2012-01-12 |
20120008413 | METHOD FOR OPERATING SEMICONDUCTOR MEMORY DEVICE - A method for operating a semiconductor memory device includes the steps of: erasing memory cells of a memory block to set the memory cells in a first erased state, programming a part of the memory cells of the memory block to convert them into a programmed state, raising threshold voltages of selected memory cells of the memory block and converting the selected memory cells from the programmed state to a second erased state, and reading data from the memory cells in the first erased state, the programmed state, and the second erased state, and outputting the data read from the memory cells in the first and second erased states with the same value. | 2012-01-12 |
20120008414 | SYSTEMS AND METHODS FOR STORING, RETRIEVING, AND ADJUSTING READ THRESHOLDS IN FLASH MEMORY STORAGE SYSTEM - A method, system and computer-readable medium are provided for reading information from a memory unit. A read instruction may be received to read information from a set of memory cells in the memory unit. A data structure storing sets of read thresholds may be searched for a set of read thresholds based on one or more characteristic value(s) of the set of memory cells. If the set of read thresholds is found, the set of memory cells may be read to execute the read instruction using the found set of read thresholds. The set of read thresholds may be thresholds which were previously used to successfully read a set of cells having the same or similar characteristic value(s). | 2012-01-12 |
20120008415 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF ERASING THE SAME - A method of erasing a semiconductor memory device includes precharging a channel of a selected memory cell of a selected string including memory cells; boosting a channel of the selected string by supplying a positive voltage to word lines of the respective memory cells of the selected string; and erasing the selected memory cell by supplying an erase voltage lower than the positive voltage to a selected word line associated with the selected memory cell. | 2012-01-12 |
20120008416 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a memory cell array comprising a plurality of cell strings and a page buffer group comprising a plurality of page buffers coupled to the respective cell string through bit lines. Each of the page buffers includes a latch unit for storing data to be programmed into memory cells included in the cell string or for storing data read from the memory cells. Each of the page buffers is coupled to a pad for the test operation of the memory cells according to data stored in the latch unit in the test operation. | 2012-01-12 |
20120008417 | NONVOLATILE MEMORY AND OPERATION METHOD OF THE SAME - A nonvolatile memory includes a first bit line coupled to a first cell string, a second bit line coupled to a second cell string, and a bit line precharge unit configured to precharge the first bit line and the second bit line before a program operation. A bit line selected from among the first bit line and the second bit line is precharged to a lower voltage level than a target voltage level, and an unselected bit line is precharged to the target voltage level. | 2012-01-12 |
20120008418 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes even page buffers coupled to even memory cells through respective even bit lines, odd page buffers coupled to odd memory cells through respective odd bit lines, first BL selectors, each configured to couple each of the even bit lines to the respective even page buffers and to couple each of the even page buffers to respective odd bit lines so that the even and odd page buffers precharge the odd bit lines in a precharge operation for the odd bit lines, and second BL selectors, each configured to couple each of the odd bit lines to the respective odd page buffers and to couple each of the odd page buffers to respective even bit lines so that the even and odd page buffers precharge the even bit lines in a precharge operation for the even bit lines. | 2012-01-12 |
20120008419 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes cells strings including memory cells and coupled between a common source line and bit lines, respectively, a peripheral circuit configured to store data in the memory cells or read data stored in the memory cells, a main voltage supply unit configured to generate operating voltages to be supplied to the peripheral circuit, a precharge voltage supply unit configured to generate a precharge voltage for precharging the bit lines, and a switching circuit configured to transfer the precharge voltage to the common source line and one of the bit lines when a bit line precharge operation is performed. | 2012-01-12 |
20120008420 | Command Generation Circuit And Semiconductor Memory Device - There is provided a command generation circuit. The command generation circuit includes a first driving unit driving an output node in response to an internal MRS command and a RAS idle signal; a second driving unit driving the output node in response to an off-signal; and a latch unit latching a signal at the output node in response to a power-up signal and generating an SRR command. | 2012-01-12 |
20120008421 | DATA OUTPUTING METHOD OF MEMORY CIRCUIT AND MEMORY CIRCUIT AND LAYOUT THEREOF - A data outputting method of a memory circuit is illustrated. The memory circuit having at least 16 data buffers DQ[0]˜DQ[15] for storing at least 16 batches of data is provided. If a quadruple data outputting mode is selected for the memory circuit, when the clock signal triggers the 16 data buffers DQ[0]˜DQ[15], the 4 batches of the data stored in the 4 data buffers DQ[0], DQ[1], DQ[8], DQ[9] via 4 input/output pins connected to the 4 data buffers DQ[0], DQ[1], DQ[8], DQ[9], the batch of data stored in the data buffer DQ[2n+2] is transferred to be stored in the data buffer DQ[2n], and the batch of the data stored in the data buffer DQ[2n+3] is transferred to be stored in the data buffer DQ[2n+1], for n is an integer from 0 through 2, and from 4 through 6. | 2012-01-12 |
20120008422 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes a memory bank configured to output stored data in response to a column selection signal, a plurality of data latching units configured to latch the data outputted from the memory bank in response to an input control signal which is generated according to the column selection signal, and output the latched data in response to an output control signal, a time measurement unit configured to measure a time from an activation of the input control signal to an activation of the output control signal and generate a delay control signal, and an activation control unit configured to control an activation time of the column selection signal in response to the delay control signal. | 2012-01-12 |
20120008423 | SETTING CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME - A setting circuit includes a selection unit configured to select one of a predefined code and an external code in response to a test signal, and a setting information generation unit configured to generate setting information in response to the code selected by the selection unit. | 2012-01-12 |
20120008424 | NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile memory device includes a plurality of latches for storing data, a set/reset circuit for transferring data, stored in a selected latch of the latches, to a common node, a transmission circuit for transferring the data of the common node to a first sense node, a bit line transmission circuit for transferring the data of the first sense node to a bit line, a sense circuit for transferring the data of the first sense node to a second sense node, and a discharge circuit for changing a voltage level of the common node based on the data of the second sense node. | 2012-01-12 |
20120008425 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a memory cell array including a plurality of memory cells, circuits configured to receive program data when a program operation is performed and output a random signal in response to the program data, and a page buffer configured to logically combine the program data and the random signal and to store the logically combined data in the memory cells. | 2012-01-12 |
20120008426 | HIGH SPEED DRAM ARCHITECTURE WITH UNIFORM ACCESS LATENCY - A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time. | 2012-01-12 |
20120008427 | Semiconductor Memory Device To Reduce Off-Current In Standby Mode - A semiconductor memory device capable of reducing off-current in a standby mode is provided. The semiconductor memory device includes an enable signal generating unit configured to receive a plurality of address decoding signals and generate a first enable signal to select a first cell block and a second enable signal to select a second cell block, and an internal voltage generating unit for generating an internal voltage by controlling a supply of a first voltage in accordance with the first or second enable signals. | 2012-01-12 |
20120008428 | DATA OUTPUT CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE - A data output circuit for a semiconductor memory device includes a first driver configured to output a first drive control signal in response to a data signal, a drive controller configured to compare a voltage level of the first drive control signal with a reference voltage and output a second drive control signal, and a second driver configured to drive an output terminal in response to the first drive control signal and additionally drive the output terminal in response to the second drive control signal. | 2012-01-12 |
20120008429 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a data coding logic for generating converted data groups and a inverted flag data from original data groups received by the semiconductor memory device. The number of zeros in the converted data groups is less than or equal to the number of zeros in the original data groups. The semiconductor memory device also includes data decoding logic for generating the original data groups from the converted data groups and the inverted flag data. A peripheral circuit may be enabled to program the converted data groups and the inverted flag data into the memory cells and read the converted data groups and the inverted flag data from the memory cells. A control logic may be enabled to generate control signals for the data coding logic, the data decoding logic, and the peripheral circuit. | 2012-01-12 |
20120008430 | SEMICONDUCTOR STORAGE DEVICE - According to the embodiments, a memory cell stores therein data, a dummy cell replicates an operation of the memory cell, a write control unit makes the dummy cell to perform writing in synchronization with write timing of the memory cell, and a row decoder performs opening and closing of a word line that performs a row selection of the memory cell based on a monitored result of a write condition of the dummy cell. | 2012-01-12 |
20120008431 | INTEGRATED CIRCUIT USING METHOD FOR SETTING LEVEL OF REFERENCE VOLTAGE - An integrated circuit includes a reference voltage level setting circuit and a reference voltage generation circuit. The reference voltage level setting circuit is configured to set a level of an input reference voltage to a preset level in a power-up period or a self-refresh mode. The reference voltage generation circuit is configured to select one of a plurality of reference voltages and output the selected reference voltage as the input reference voltage when the power-up period is ended and an operation mode is not in the self-refresh mode. | 2012-01-12 |
20120008432 | MEMORY CELL HAVING REDUCED CIRCUIT AREA - The present invention relates to a memory cell having a reduced circuit area, which comprises a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor is coupled to a readline and controlled by a wordline. The second transistor is coupled between the first transistor and a low-voltage power supply. The third transistor is coupled to the second transistor and controlled by a bitline. The third transistor controls turn-on and cutoff of the second transistor. Besides, the fourth transistor is coupled to the third transistor and a writeline, and is controlled by the wordline. Thereby, according to the present invention, four transistors form a memory cell, and the objective of saving circuit area can be achieved. | 2012-01-12 |
20120008433 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes an open-loop-type delay locked loop (DLL) configured to generate a clock signal locked by reflecting a first delay amount which actually occurs in a data path and a second delay amount which is required for locking the clock signal, a latency control unit configured to shift an inputted command according to a latency code value corresponding to the first delay amount and latency information, and output the shifted command, and an additional delay line configured to delay the shifted command according to a delay code value corresponding to the second delay amount, and output the command of which operation timing is controlled. | 2012-01-12 |
20120008434 | SEMICONDUCTOR SYSTEM AND DEVICE, AND METHOD FOR CONTROLLING REFRESH OPERATION OF STACKED CHIPS - A system for controlling a refresh operation of a plurality of stacked semiconductor chips includes a first semiconductor configured to output a refresh signal for performing a refresh operation, and a semiconductor chip discrimination signal, and a plurality of second semiconductor chips configured to perform a refresh operation at different timings in response to the refresh signal, and the semiconductor chip discrimination signal. | 2012-01-12 |
20120008435 | DELAY LOCKED LOOP - A delay locked loop includes a closed loop circuit configured to generate preliminary delay information, a control unit configured to update the preliminary delay information into delay information in response to a control signal, and a first delay unit configured to delay an input clock signal by a first delay value determined by the delay information and generate an output clock signal. | 2012-01-12 |
20120008436 | SIMULATING A REFRESH OPERATION LATENCY - A memory apparatus includes multiple memory circuits an interface circuit having one or more first components of a first type and one or more second components of a second type different from the first type, each of the one or more first components and second components being electrically couplable to a host system. The interface circuit is operable to present to the host system a simulated memory circuit where there is a difference in at least one aspect between the simulated memory circuit and at least one memory circuit of the plurality of memory circuits. The at least one aspect includes a timing that relates to a refresh operation latency, in which each memory circuit of the plurality of memory circuits is electrically coupled to at least one first component and to at least one second component. | 2012-01-12 |
20120008437 | COUNTER CIRCUIT, LATENCY COUNTER, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND DATA PROCESSING SYSTEM - To provide a counter circuit capable of accurately counting a high-frequency signal in which hazard or the like is easily generated. There are provided: a frequency dividing circuit that generates first and second frequency dividing clocks, which differ in phase to each other, based on a clock signal; a first counter that counts the first frequency dividing clock; a second counter that synchronizes with the second frequency dividing clock to fetch a count value of the first counter; and a selection circuit that exclusively selects count values of the first and second counters. According to the present invention, a relation of the count values between the first and second counters is kept always constant, and thus, even when hazard occurs, the count values are only made to jump and the count values do not fluctuate. | 2012-01-12 |
20120008438 | EFFICIENT WORD LINES, BIT LINE AND PRECHARGE TRACKING IN SELF-TIMED MEMORY DEVICE - A memory device for efficient word line, bit line and precharge tracking is provided. The memory device includes a memory array, one or more address decoders, a word line driver, a plurality of sense amplifiers, a reference word line column, a reference bit line column, and a control circuit. The control circuit generates a control signal to perform read and write operations on the memory device. The address decoder selects a bit line and a word line. The selected word line is activated by the word line driver. While the reference word line column is used for vertical tracking of the word line, the reference bit line column is used for vertical tracking of the bit line. The sense amplifiers are activated to read the bit line. | 2012-01-12 |
20120008439 | DELAY LOCKED LOOP CIRCUIT AND METHOD - Delay locked loop circuits and methods are disclosed. In the embodiments, a delay locked loop may include a phase detector to detect a phase difference between a clock signal and a reference clock signal, and a charge pump that receives the detected phase difference. A low pass filter may filter an output from the charge pump. The delay locked loop may further include a delay line having a plurality of delay elements, the plurality of delay elements including a first selectable group and a second selectable group that is larger than the first selectable group. A first clock signal from the first group of delay elements may be provided to the phase detector to first synchronize the delay locked loop, and following the synchronization, a second clock signal from the second group may be employed to synchronize the delay locked loop. | 2012-01-12 |
20120008440 | DATA RETENTION KILL FUNCTION - Various data protection techniques are provided. In one embodiment, a memory device is provided. The memory device may initiate a security measure upon occurrence of one or more triggering events. The one or more triggering events may include receipt of a command signal. Various additional methods, devices, and systems are also provided. | 2012-01-12 |
20120008441 | SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF - A semiconductor memory device includes a repair control signal generation unit configured to compare a repair target address programmed corresponding to a repair target memory cell with an external address, and generate a repair control signal. an address decoding unit configured to control a normal memory cell or a redundancy memory cell corresponding to the external address to be accessed in response to the repair control signal and an internal active signal, and an activation interval detection unit configured to generate an interval detection signal by detecting a time interval between an activation timing of the repair control signal and an activation timing of the internal active signal in a test operation mode. | 2012-01-12 |
20120008442 | SEMICONDUCTOR DEVICE AND METHOD OF TESTING THE SAME - A semiconductor device according to an aspect of the present disclosure includes a test mode signal generator configured to generate a test mode setup signal, and a controller configured to set a separated test operation in response to the test mode setup signal. | 2012-01-12 |
20120008443 | IMPLEMENTING SMART SWITCHED DECOUPLING CAPACITORS TO EFFICIENTLY REDUCE POWER SUPPLY NOISE - A method and circuit are provided for implementing smart switched decoupling capacitors to efficiently reduce power supply noise in a logic circuit, and a design structure on which the subject circuit resides. The logic circuit includes a logic macro, a high-current event control signal activating a logic function, and a switched decoupling capacitor circuit integrated within the logic macro. The switched decoupling capacitor circuit uses the high-current event control signal to control capacitor switching to discharge to a voltage supply rail responsive to activating the logic function, and to charge the capacitors. | 2012-01-12 |
20120008444 | DUAL BIT LINE PRECHARGE ARCHITECTURE AND METHOD FOR LOW POWER DYNAMIC RANDOM ACCESS MEMORY (DRAM) INTEGRATED CIRCUIT DEVICES AND DEVICES INCORPORATING EMBEDDED DRAM - A dual bit line precharge architecture and method for low power DRAM which provides the low operating voltage of a non-half supply voltage (VCC/2) precharge with the low memory array current consumption and low memory array noise spike of VCC/2 precharge techniques. The architecture and technique of the present invention provides both reference voltage (VSS) precharged sub arrays and VCC precharged sub arrays on the same DRAM memory either with or without the novel charge sharing or charge recycling circuitry between these two different sub arrays as disclosed herein. | 2012-01-12 |
20120008445 | DUAL BIT LINE PRECHARGE ARCHITECTURE AND METHOD FOR LOW POWER DYNAMIC RANDOM ACCESS MEMORY (DRAM) INTEGRATED CIRCUIT DEVICES AND DEVICES INCORPORATING EMBEDDED DRAM - A dual bit line precharge architecture and method for low power DRAM which provides the low operating voltage of a non-half supply voltage (VCC/2) precharge with the low memory array current consumption and low memory array noise spike of VCC/2 precharge techniques. The architecture and technique of the present invention provides both reference voltage (VSS) precharged sub arrays and VCC precharged sub arrays on the same DRAM memory either with or without the novel charge sharing or charge recycling circuitry between these two different sub arrays as disclosed herein. | 2012-01-12 |
20120008446 | PRECHARGING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A semiconductor memory device includes a write driver for transmitting data loaded on a global line to a local line pair, a read driver for transmitting data loaded on the local line pair to the global line, a core region for storing data loaded on the local line pair or provide stored data to the local line pair, and a precharging circuit configured to precharge the local line pair by selectively using a first voltage and a second voltage in response to a precharge control signal and an operation mode signal, wherein the second voltage is lower than the first voltage. | 2012-01-12 |
20120008447 | SEMICONDUCTOR DEVICE HAVING VARIABLE PARAMETER SELECTION BASED ON TEMPERATURE - A semiconductor device that may include temperature sensing circuits is disclosed. The temperature sensing circuits may be used to control various parameters, such as internal regulated supply voltages, internal refresh frequency, a word line low voltage, or the like. In this way, operating specifications of a semiconductor device at worse case temperatures may be met without compromising performance at normal operating temperatures. Each temperature sensing circuit may include a selectable temperature threshold value as well as a selectable temperature hysteresis value. In this way, temperature performance characteristics may be finely tuned. Furthermore, a method of testing the temperature sensing circuits is disclosed in which a current value may be monitored an temperature threshold values and temperature hysteresis values may be thereby determined. | 2012-01-12 |
20120008448 | ANTI-FUSE CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME - An anti-fuse circuit includes an anti-fuse coupled to a sensing node, a driving unit configured to rupture the anti-fuse in response to a rupture enable signal, an anti-fuse status detecting unit configured to output an anti-fuse status detecting signal in response to a voltage at the sensing node corresponding to a rupture status of the anti-fuse, and a sensing current supplying unit configured to supply sensing current to the sensing node in response to a rupture sensing signal. | 2012-01-12 |
20120008449 | LOW POWER STATIC RANDOM ACCESS MEMORY - A SRAM that keeps the memory cell array under a low voltage in the Standby mode and Write mode, and raises the memory cell array supply voltage to a high voltage in the Read mode. A SRAM comprising: at least one memory cell circuit, comprising a latch circuit with at least two inverters, and comprising two power receiving terminals for receiving power; and a power supplying circuit, for providing the power to the memory cell circuit, such that the voltages at the power receiving terminals of the latch circuit is below a predetermined voltage level when data is written to the latch circuit. In one embodiment, the memory cell circuit includes a plurality of data accessing terminals and the data accessing terminals are respectively controlled by at least two pass-transistor switch devices. | 2012-01-12 |
20120008450 | FLEXIBLE MEMORY ARCHITECTURE FOR STATIC POWER REDUCTION AND METHOD OF IMPLEMENTING THE SAME IN AN INTEGRATED CIRCUIT - A memory for an integrated circuit, a method of designing a memory and an integrated circuit manufactured by the method. In one embodiment, the memory includes: (1) one of: (1a) at least one data input register block and at least one bit enable input register block and (1b) at least one data and bit enable merging block and at least one merged data register block, (2) one of: (2a) at least one address input register block and at least one binary to one-hot address decode block and (2b) at least one binary to one-hot address decode block and at least one one-hot address register block and (3) a memory array, at least one of the blocks having a timing selected to match at least some timing margins outside of the memory. | 2012-01-12 |
20120008451 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first group configured to include a first bank and a second bank; a second group configured to include a third bank and a fourth bank; an address strobe pulse generating unit configured to generate an address strobe pulse signal for activating the first group and the second group in response to a first bank address and a command signal; and a strobe signal generating unit configured to generate a strobe signal that selects a bank from the first group and the second group in response to the address strobe pulse signal and a second bank address. | 2012-01-12 |
20120008452 | SEMICONDUCTOR INTEGRATED CIRCUIT CAPABLE OF CONTROLLING READ COMMAND - The semiconductor integrated circuit includes a command decoder, a shift register unit and a command address latch unit. The command decoder is responsive to an external command defining write and read modes and configured to provide a write command or a read command according to the external command using a rising or falling clock. The shift register unit is configured to shift an external address and the write command by a write latency in response to the write command. The column address latch unit is configured to latch and provide the external address as a column address in the read mode, and to latch a write address, which is provided from the shift register unit, and provide the write address as the column address in the write mode. | 2012-01-12 |
20120008453 | Method and System for Calculating and Reporting Slump in Delivery Vehicles - A system for managing a concrete delivery vehicle having a mixing drum | 2012-01-12 |
20120008454 | MULTIPURPOSE MANUAL MIXER - The disclosed multipurpose manual mixer is a new kitchen utensil in one piece comprised of a handle attached to a mixer to the other end, resembling a helicopter with propeller like plates. A multipurpose manual mixer with its entire structure in one piece made up of a long and uneven handle at one end and flat rectangular pieces with rounded corners, propellers like big and small, holed and un-holed attached vertically to a tubular body to the other end in continuous rows, parallel and separated from each other at equal distance. The multi flat rectangular pieces as mentioned and described above are all called plates. The body comprised of all plates big and small and attached vertically along to the cylindrical tubular part in the middle, is called ‘the mixer.’ In other words, ‘the mixer’ consists of multiple flat rectangular plates rounded in corners on one side, big and small, holed and un-holed and bound to each other by a receiving tubular part that also fits the handle. This invention called ‘multipurpose manual mixer’ has been specially designed in order to provide an improved manual mixer of simple, cheap, effective and readily reusable construction. It adds quality to the finishing product—food simple or complex and ends up to being a very useful tool in the kitchen. | 2012-01-12 |
20120008455 | Systems and Methods for Mixing and Dispensing Flowable Materials - Disclosed herein are systems and methods for mixing materials together and transferring the materials into other instruments, particularly for use in the medical field. | 2012-01-12 |
20120008456 | INTENSE GLASS BATCH MIXER - A continuous-action intense glass batch mixer comprising a horizontal cylindrical mixing chamber with an inlet fitting for loading batch and scrap glass, a water nozzle, and a steam nozzle. A chamber has loading, accumulation and unloading zones and a rotor central shaft. The mixer has a hole for unloading the mixture of batch and scrap glass, with magnetic separators installed under it, wherein in order to clean the chamber walls, scrapers are installed on the rotor shaft, and mixing cutting tools are installed on the shaft in the loading and unloading zones and uniformly distributed around the circumference at a 90° angle to the shaft, except that the second cutting tool is installed at a 60° angle to the first cutting tool (the intensive stirring zone). The total width of the work surface of the cutting tools is 15-30% larger than the length of the zone they are installed in. | 2012-01-12 |
20120008457 | AGRICULTURAL MIXER WITH DRIVE SYSTEM AND METHOD OF USING SAME - An agricultural mixer includes a hydraulic drive system. The mixer includes an automatic jam-resolving feature, whereby if an auger becomes jammed, the drive system will cause the auger to rotate in a reverse direction for a period of time to resolve the jam. The hydraulic drive system will maintain a speed of rotation of the auger at a relatively constant rate during mixing while choosing an efficient displacement setting for the hydraulic motor. The auger is maintained at a constant speed during a discharge mode by maintaining the motor in a maximum displacement setting. A clean-out mode is provided wherein the auger is rotated at a maximum speed to aid in cleaning out the last remaining feed mixture in the mixer. | 2012-01-12 |
20120008458 | METHOD TO ATTENUATE STRONG MARINE SEISMIC NOISE - Methods to attenuating strong marine seismic noises using singular value decomposition, determining noisiest traces and estimating noise components only from these traces, iteratively estimating the noise and protecting signal behind the noise. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72( | 2012-01-12 |
20120008459 | SIMULTANEOUS OR NEAR-SIMULTANEOUS ACQUISITION FOR BOREHOLE SEISMIC - A technique facilitates performance of seismic profiling, such as three-dimensional vertical seismic profiling. A downhole acquisition system is provided with acoustic receivers designed to receive acoustic source signals. The firing of acoustic source signals is synchronized with the downhole acquisition system. Additionally, the firing of two or more acoustic source signals is controlled to provide simultaneous or nearly simultaneous timing of one acoustic source signal with respect to another acoustic source signal. A processing system is used to acquire and process a data stream of the initial shot and a data stream of the additional shot occurring simultaneously or nearly simultaneously. | 2012-01-12 |
20120008460 | DATA ACQUISITION SYSTEM WITH REMOVABLE - Data acquisition modules and systems including batteries with integrated data storage. The battery with integrated data storage can be selectively removed from the data acquisition module. This allows for reduced logistical effort associated with data retrieval and battery charging. For instance, the entire data acquisition module need not be transported to a central location for data recovery and charging, but rather the removable battery with integrated storage may be removed and transported. Also facilitated is extended surveys in that the battery or storage module may be replaced, such that survey design limitations such as storage capacity or battery life may be eliminated. | 2012-01-12 |
20120008461 | METHOD FOR ACCENTUATING SPECULAR AND NON-SPECULAR SEISMIC EVENTS FROM WITHIN SHALLOW SUBSURFACE ROCK FORMATIONS - A method for evaluating subsurface formations includes deploying at least two intersecting seismic transducer lines above an area of the subsurface to be surveyed. Each line includes spaced apart seismic transmitters on one side of the intersection and spaced apart seismic receivers on the other side. On each line, one of the transmitters is actuated and signals are detected at one of the receivers. The foregoing is repeated for each of the remaining receivers. The foregoing is then repeated for each of the remaining transmitters on each line. The detected signals are processed to enhance both specular and non-specular seismic events in the subsurface. The enhanced events may be stored and/or displayed. | 2012-01-12 |
20120008462 | Vibroseis Acquisition Technique and System Using Dynamic Source Control - A technique includes during a seismic acquisition, selectively forming groups of at least one seismic source from a plurality of seismic sources as the seismic sources become available based at least in part on a minimum source spacing distance. The technique also includes selectively activating the groups. Each group responds to being activated by substantially simultaneously initiating a sweep for the seismic source(s) of the group. The technique further includes regulating a timing of the group activations based at least in part on a slip time and a minimum group spacing distance. | 2012-01-12 |
20120008463 | HIGH DATA RATE ACOUSTIC MULTIPLE-INPUT/MULTIPLE-OUTPUT (MIMO) COMMUNICATION APPARATUS AND SYSTEM FOR SUBMERSIBLES - Underwater multiple input/multiple output (MIMO) communication apparatus, systems, and methods are disclosed. An underwater MIMO apparatus includes a submersible housing having a water impermeable section, a data acquisition system located within the water impermeable section of the submersible housing, and at least two transmission communication elements electrically connected to the data acquisition system. The MIMO communication apparatus may be used in a communication system including a communication array for communicating with the MIMO communication apparatus using a MIMO communication method. | 2012-01-12 |
20120008464 | ELECTRONIC WILDLIFE CALL - An electronic wildlife call has electronics and a housing. The electronics includes an electronic sound generator, memory containing at least one sound call, and at least one speaker connected with the sound generator. The housing contains the electronics and has an upper portion and a lower portion. Legs are coupled to the lower portion of the housing. The legs are movable between a deployed position and a stowed position, wherein when the legs are in the deployed position, the housing is elevated above the ground. The housing has a docking port for receiving a remote control. When the remote control is located in the docking port, the power supply in the remote control is recharged and calls are synced. | 2012-01-12 |
20120008465 | Multiple display clock - A multiple display clock includes date and month timing units mounted on a clock body, and each including a needle, and a stepper motor to drive the needle. A controller is coupled to a digital display and the stepper motors of the date and month timing units, and includes a processor controlling a digital time counter to count a calendar time. The processor controls the digital display to display digital time information, and activates the stepper motors of the date and month timing units to drive the date and month needles for display of analog calendar time information. A main timing unit is disposed on the clock body and has a stepper motor that is used to drive minute and hour needles, and that is disconnected from the controller. | 2012-01-12 |
20120008466 | TIME INFORMATION ACQUIRING APPARATUS AND RADIO CONTROLLED TIMEPIECE - A time information acquiring apparatus for acquiring time information from a time code signal included in a standard radio wave, including: a pulse measuring section which detects a degree of proximity of an individual pulse signal constituting the time code signal to a predetermined code value; a grouping section which groups pulse signals into one group; a code string estimating section which estimates a code string having a possibility of emerging in a portion of the group in a frame of the time code signal; a code string determining section which determines a probability that the code string indicated by the grouped pulse signals corresponds to the estimated code string based on the degree of proximity; and a time information generating section which generates the time information based on the code string for which the code string determining section determines that the probability is high. | 2012-01-12 |
20120008467 | BALANCE SPRING WITH FIXED CENTRE OF MASS - The invention relates to a balance spring ( | 2012-01-12 |
20120008468 | HAIRSPRING FOR TIMEPIECE HAIRSPRING-BALANCE OSCILLATOR, AND METHOD OF MANUFACTURE THEREOF - The present invention relates to a hairspring for a timepiece hairspring-balance oscillator, which can be produced, in particular, from a low-density material such as silicon, diamond or quartz, and to a method of manufacturing such a hairspring. According to the invention, this hairspring comprises at least one leaf ( | 2012-01-12 |
20120008469 | Processing Electromagnetic Films Using a Symmetric Head Assembly - Methods and systems for presensitizing film, including providing an assembly of heads comprising N left heads, a center head, and N right heads, each head being configured to effect a corresponding process P, on one or more regions of a film, activating the left heads and the center head sequentially over a first region of the film, in response to the head assembly moving from left to right with respect to the film, and activating the right heads and the center head sequentially over a second region of the film, in response to the head assembly moving from right to left with respect to the film. | 2012-01-12 |
20120008470 | MAGNETIC RECORDING HEAD CAPABLE OF MONITORING LIGHT FOR THERMAL ASSIST - Provided is a thermally-assisted magnetic recording head in which a slider including an optical system is joined with a light source unit. The light source unit comprises: a unit substrate including a joining surface joined with the slider and a source-installation surface adjacent to the joining surface; a light source provided in the source-installation surface and emits light for thermal assist; and a photodetector section formed inside the unit substrate, a light-receiving portion of the photodetector section for receiving light emitted from a rear light-emission center being located on the source-installation surface side. The light source unit includes the photodetector section that enables constant monitoring of light output from the light source. Accordingly, feedback adjustment of the light output can be accomplished. Further, since the rear light-emission center and the light-receiving portion can be located sufficiently close to each other, the light output can be monitored with a higher efficiency. | 2012-01-12 |
20120008471 | RECORDING MEDIUM, RECORDING APPARATUS, REPRODUCTION APPARATUS, RECORDING METHOD AND REPRODUCTION METHOD - The present invention allows the usability of a write-once recording medium to be enhanced. The write-once recording medium is provided with an ordinary recording/reproduction area, an alternate area, a first alternate-address management information area (DMA) and a second alternate-address management information area (TDMA). In addition, written/unwritten state indication information (a space bitmap) is also recorded. The second alternate-address management information area is an area allowing alternate-address management information recorded therein to be renewed by adding alternate-address management information thereto. In addition, the written/unwritten state indication information indicates whether or not data has been recorded in each data unit (cluster) on the recording medium. Thus, it is possible to correctly execute management of defects and properly implement renewal of data in the write-once recording medium. | 2012-01-12 |
20120008472 | PROVIDING DEVICE-LEVEL FUNCTIONALITY WITHOUT ALTERING INSTRUCTIONS STORED IN DEVICE MEMORY - Systems, methods, and machine-readable media provide device-level functionality without altering device memory. A non-transitory machine-readable medium can store a first set of instructions that are executed by the machine to provide device-level functionality unsupported by a second set of instructions stored in device memory associated with the machine without altering the second set of instructions stored in the device memory. For example, the machine can be an optical disc player and the medium can be an optical disc. | 2012-01-12 |
20120008473 | PLAYBACK METHOD FOR OPTICAL DISC, PLAYBACK APPARATUS FOR OPTICAL DISC, NON-TRANSISTORY COMPUTER PROGRAM PRODUCT - Address information that has been error correction encoded is recorded on a second version of a recording medium after being transformed such that such that the address decoding cannot be performed by a playback device that is not compatible with the second version of the recording medium. The address decoding for the second version of the recording medium cannot be performed by the incompatible playback device (for example, a playback device that was manufactured to be compatible only with a first version of the recording medium). In other words, in the playback device that is not compatible with the second version of the recording medium, a state is created in which address errors cannot be corrected, so access is impossible (recording and playback are impossible). | 2012-01-12 |
20120008474 | RECORDING MEDIUM, RECORDING METHOD, REPRODUCTION METHOD, RECORDING APPARATUS AND REPRODUCTION APPARATUS - A recording medium comprising a recording area, the recording area includes a first area and a second area, the first area includes a frame area, the frame area includes an area in which a second synchronization code sequence and at least a portion of data are to be recorded, and the second area includes an area of linking frames in which a third synchronization code sequence and a fourth synchronization code sequence are to be recorded. | 2012-01-12 |
20120008475 | METHOD OF CONTROLLING LIGHT, AND OPTICAL PICKUP DEVICE AND OPTICAL DISK DRIVE ADOPTING THE METHOD - An optical pickup device, an optical disk drive and method of controlling light performed by the optical pickup device are provided. The optical pickup device includes: a light transmitting system including an object lens for facing a medium having a multi recording layer for storing information, a light source system for providing a plurality of beams used to record information on or reproduce information from the multi recording layer via the light transmitting system, a light-receiving system disposed on a path of a beam reflected from the medium, and a light controller including a light control device for controlling stray light generated in the medium such that the stray light does not reach the light-receiving device. | 2012-01-12 |
20120008476 | INFORMATION REPRODUCTION APPARATUS AND METHOD FOR CONTROLLING SAME - According to one embodiment, an information reproduction apparatus includes an information acquisition unit, an error detection unit, and a control unit. The information acquisition unit is configured to irradiate a reference beam, convert the reference beam into a luminance signal, and output the luminance signal when reproducing an information recording Medium. The error detection unit is configured to detect at least one selected from a first error and a second error by extracting a feature extraction quantity from the luminance signal. The first error is of an irradiation angle of the reference beam. The second error is of at least one selected from a temperature and a wavelength of the reference beam. The control unit is configured to control at least one selected from the irradiation angle and the at least one selected from the reproduction temperature and the wavelength of the reference beam using the second error. | 2012-01-12 |
20120008477 | OPTICAL DISC DRIVE AND METHOD OF CONTROLLING LASER LIGHT POWER IN OPTICAL DISC DRIVE - This invention provides an optical disc drive with more accurate and stable power control for a laser light source. An optical disc drive in an embodiment of this invention includes a monitor photodetector for receiving laser light emitted by a laser light source to monitor the laser light power. The monitor diode is a photodetector for generating an electric signal corresponding to the laser light power. A laser light controller controls drive current to the laser light source based on a result of measurement by the monitor diode. The optical disc drive measures output variations of the monitor diode and controls the gain of the monitor diode based on the result of the measurement. This gain control improves accuracy and stability in laser light control so that stability in recording/reading can be attained. | 2012-01-12 |
20120008478 | OPTICAL DISC DRIVE AND METHOD OF CONTROLLING POWER OF LASER LIGHT IN RECORDING TO OPTICAL DISC - This invention provides accurate control of laser light power in a recording operation to achieve more stable recording operation. An optical disc drive in an embodiment of this invention monitors the power of laser light with a monitor diode and controls the laser light power based on the result of monitoring. The optical disc drive changes data transfer rate (recording frequency) depending on the disc radial position. The optical disc drive controls the gain of the monitor diode across the recording surface depending on the recording frequency. This control improves the accuracy in laser light power control to achieve stable recording operations by precise servo control. | 2012-01-12 |
20120008479 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND PROGRAM - An information processing apparatus includes a data processing unit which executes a copy process for recording data recorded on a first medium onto a second medium, and the data processing unit executes a questionable data discrimination process for discriminating questionable data which is highly likely to be not normally reproduced in a reproduction process in which a reproduction program different from a dedicated reproduction program to the data recorded on the first medium is applied, and executes at least any of processes, which include a questionable data deletion process for deleting the questionable data from a copy target or a warning notification process for notifying a user of a possibility that copied data will not be normally reproduced, according to the discrimination result in the questionable data discrimination process. | 2012-01-12 |
20120008480 | INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND PROGRAM - An information processing device including a data processing section which executes control of a copying process where recording data on a first medium is recorded onto a second medium, and a data conversion section which executes data conversion in the copying process, where the data processing section acquires position information of a packet, which corresponds to an angle change point, based on conversion data generated by the data conversion section and executes an updating process on a reproduction control information file where angle change point position information of data before conversion which is recorded in the reproduction control information file included in copy target data is changed to angle change point position information of data after conversion. | 2012-01-12 |
20120008481 | OPTICAL PICKUP APPARATUS - The present invention provides an electronic equipment which includes an optical member including a first adhesive application portion, wherein a support member is provided in which a second adhesive application portion is provided on a support surface of the optical member, a cross-sectional surface of the first adhesive application portion is opposite to a cross-sectional surface of the second adhesive application portion, a separation portion is provided between the first cross-sectional surface and the second cross-sectional surface, and a approximately spherical adhesive is fixed around an approximately center of the separation portion to include a part of the first and second adhesive application portions. Thus, an object is to provide electronic equipment that reduces deviation in the relative position between the optical member and the support member generated after the curing of the ultraviolet-curable adhesive. | 2012-01-12 |
20120008482 | SYSTEM FOR HOLOGRAPHY - The present invention provides systems of recording holograms that reduce the writing time, increase the diffraction efficiency, improve the resolution, or restitute color. These systems are well suited for use with an updateable 3D holographic display using integral holography and photorefractive polymer. | 2012-01-12 |
20120008483 | OPTICAL HEAD AND OPTICAL DISC APPARATUS - Reference light for interference with signal light from an optical information recording medium is displaced and reflected by a corner cube prism or the like with high accuracy. The signal light and the displaced reference light are made parallel with each other with high accuracy. The signal light and the reference light are each split using a polarization splitter to generate interference light. Thus, regeneration signals are stabilized. Accordingly, an interference-type optical head and optical disc apparatus of higher quality than conventional ones can be provided. | 2012-01-12 |
20120008484 | OPTICAL INFORMATION RECORDING REPRODUCTION APPARATUS AND OPTICAL INFORMATION RECORDING REPRODUCTION METHOD - An optical information recording reproduction apparatus includes: a first light beam source; a second light beam source emitting a beam with a wavelength shorter than that of the first light beam source; and an object lens condensing the beams from the first and second light beam sources to an optical information recording medium. When information is recorded in the optical information recording medium, a recording beam is emitted from the first light beam source and a beam used to generate a signal for controlling a position of the object lens is emitted from the second light beam source. When the information of the optical information recording medium is reproduced, a reproduction beam is emitted from the second light beam source. | 2012-01-12 |
20120008485 | Objective Lens, Optical Pickup Apparatus, and Optical Information Recording Reproducing Apparatus - An objective lens relating to the present invention includes a first optical path difference providing structure in which a first basic structure and a second basic structure are overlapped with each other. The first basic structure is a blaze-type structure which emits a Xth-order diffracted light flux, when the first light flux passes through the first basic structure, where the value of X is an odd integer. At least a part of the first basic structure arranged around an optical axis includes a step facing an opposite direction to the optical axis. The second basic structure is a blaze-type structure which emits a Lth-order diffracted light flux, when the first light flux passes through the second basic structure, where the value of L is an even integer. At least a part of the second basic structure arranged around the optical axis includes a step facing the optical axis. | 2012-01-12 |
20120008486 | RECORDING DEVICE AND APC CORRECTION METHOD - A recording device includes a light irradiation portion which irradiates an optical recording medium with laser light emitted from a light source via a field lens, a light emission drive portion which drives and causes the light source to emit light, a front monitor which receives the laser light emitted from the light source, a light receiving portion which receives reflected light which is obtained from the optical recording medium in response to the laser light irradiation, a focus servo control portion which controls a focus servo of the field lens on the basis of a light receiving signal by the light receiving portion, a surface jump controller which controls the focus servo control portion so as to perform a focus jump operation to a surface of the optical recording medium, and a surface APC corrector which performs a process as an auto power control (APC) correction process. | 2012-01-12 |
20120008487 | OPTICAL RECORDING DEVICE AND RECORDING METHOD - A recording device includes a plurality of channels configured to record data to an optical recording medium, a reception unit configured to receive data transmitted from an external device, a storage unit configured to temporarily store the data that is received by the reception unit, and a distribution control unit configured to read the data that is stored in the storage unit and distribute the data by a block unit to the plurality of channels based on transfer time of the data and recording time to the optical recording medium so that record processing of the plurality of channels are simultaneously ended. | 2012-01-12 |
20120008488 | TURNTABLE - An improved turntable is described with inherent properties for reducing noise generated by external sources or by the parts of the turntable. The plinth of the turntable is comprised of an elastomeric layer and at least one stiffening layer that adds rigidity to the plinth. The support feet, spindle bearing, and armboard only come into contact with the elastomeric layer, which dampens energy, allowing the turntable produce the audio on the record without excessive noise. | 2012-01-12 |
20120008489 | BASE STATION APPARATUS AND METHOD FOR USE IN MOBILE COMMUNICATION SYSTEM - One aspect of the present invention relates to a base station apparatus in a mobile communication system, comprising: an acquisition unit configured to receive an uplink signal from a user equipment and acquire channel condition information and an average value of the channel condition information for each of one or more frequency resource blocks; a reference metric calculation unit configured to calculate a reference metric indicative of priority of assignment of the frequency resource blocks to the user equipment based on the channel condition information and the average value of the channel condition information acquired by the acquisition unit; a modification unit configured to modify the reference metric calculated by the reference metric calculation unit with a first parameter to generate a modified metric; a scheduler configured to compare the modified metrics of the individual frequency resource blocks generated by the modification unit and determine an assignment plan of radio resources; and a transmitting unit configured to transmit a downlink signal in accordance with the assignment plan determined by the scheduler, wherein the modification unit modifies the reference metric with the first parameter, the first parameter having a first value for a predefined first frequency resource block and a second value for a predefined second frequency resource block if the user equipment belongs to a group differentiated based on a path loss. | 2012-01-12 |
20120008490 | METHOD AND SYSTEM FOR COMMUNICATION IN MULTI-USER MULTIPLE-INPUT-MULTIPLE-OUTPUT WIRELESS NETWORKS - Wireless communication in a wireless system using a multiple user transmission opportunity is provided. The data blocks are organized in order of transmission priority based on access categories. Contention for access to the communication medium during a transmission opportunity period is based on a backoff timer of each access category and the transmission priority. Upon successful contention for a transmission opportunity period, during the transmission opportunity period, a data block of a primary access category is wirelessly transmitted from the wireless station to one or more primary destination wireless receivers. Simultaneously, a data block of a secondary access category is wirelessly transmitted from the wireless station to one or more secondary destination wireless receivers. Contending for the transmission opportunity period includes each access category contending for access to the wireless communication medium and a secondary access category selectively invoking communication medium access backoff based on one or more backoff events. | 2012-01-12 |
20120008491 | RELAY APPARATUS FOR COMMUNICATION FRAMES AND RELAY METHOD - A layer 2 switch (L2SW) includes (i) a leaned information management unit for recording learned information that associates a receiving port, an address of another L2SW, and a source address specified in the original communication frame, when an encapsulated frame, in which a communication frame has been encapsulated by data containing the address of the another L2SW, is received from the backbone network and (ii) a status monitoring unit. The learned information management unit determines the update extent of the learned information, in accordance with a check result of the connection status and thus the occurrence of flooding transfer to a backbone networks side is suppressed. | 2012-01-12 |
20120008492 | METHODS AND SYSTEMS FOR ENABLING END-USER EQUIPMENT AT AN END-USER PREMISE TO EFFECT COMMUNICATIONS HAVING CERTAIN ORIGINS WHEN AN ABILITY OF THE END-USER EQUIPMENT TO COMMUNICATE VIA A COMMUNICATION LINK CONNECTING THE END-USER EQUIPMENT TO A COMMUNICATIONS NETWORK IS DISRUPTED - A method for effecting communications, such as telephone calls, accesses to data network sites, alarm system communications, and/or other communications, having certain origins over a communications network. The method comprises: receiving a request for a communication originated by first end-user equipment at a first end-user premise when an ability of the first end-user equipment to communicate via a first communication link connecting the first end-user equipment to the communications network is disrupted; determining, based on an origin of the communication, that the communication is to be effected over the communications network; and causing information pertaining to the communication to be exchanged between the first end-user equipment and the communications network via a wireless communication link established between the first end-user equipment and second end-user equipment at a second end-user premise and a second communication link connecting the second end-user equipment to the communications network. Also provided are apparatus and computer-readable media containing a program element executable by a computing system to perform such a method. | 2012-01-12 |
20120008493 | Bi-Directional Ring Network Having Minimum Spare Bandwidth Allocation and Corresponding Connection Admission Controls - The present invention provides for a method for reserving spare bandwidth for a link in a communication network including a plurality of links. The method provides for monitoring the volume of traffic routed through each link of the communication network. A single link failure for each link is then simulated and the volume of traffic which would be rerouted through each link for maintaining communication and the volume of traffic removed from each link are determined for each simulated single link failure. The difference between the volume of traffic which would need to be rerouted through each link and the corresponding volume of traffic removed from each link is then computed, and a maximum difference value is determined for each link for all simulated single link failures. An amount of spare bandwidth equivalent to the determined maximum difference is then reserved for each link. | 2012-01-12 |
20120008494 | Offering Incentives under a Flat Rate Charging System - The invention describes a method of providing incentives to users via supporting mechanisms and algorithms for facilitating the move of DT traffic to off-peak hours. It proposes an efficient utilization of the network resources during peak hour under a flat-rate pricing scheme with the cooperation and blessing of the users and without adding complexity to billing. | 2012-01-12 |
20120008495 | Methods And Systems For Controlling SIP Overload - Techniques for controlling Session Initiation Protocol (SIP) overload between a sending entity and a receiving entity includes receiving a message at a send buffer at the sending entity and forwarding the message to a receive buffer at the receiving entity if the send buffer is empty of other messages or rejecting the message if the send buffer is not empty of other messages. | 2012-01-12 |
20120008496 | SYSTEM, METHOD AND COMPUTER PROGRAM FOR INTELLIGENT PACKET DISTRIBUTION - The present invention provides a system, method and computer program for intelligent packet distribution over a plurality of potentially diverse links. The system includes an intelligent packet distribution engine (“IPDE”) that incorporates or is linked to means for executing a decision tree. The IPDE, in real time, obtains data traffic parameters and, based on the data traffic parameters and performance criteria, selectively applies one or more techniques to alter the traffic over selected communication links to conform to the data traffic parameters. | 2012-01-12 |