02nd week of 2022 patent applcation highlights part 59 |
Patent application number | Title | Published |
20220013371 | MOLD TOOL FOR MOLDING A SEMICONDUCTOR POWER MODULE WITH TOP-SIDED PIN CONNECTORS AND METHOD OF MANUFACTURING SUCH A SEMICONDUCTOR POWER MODULE - A mold tool | 2022-01-13 |
20220013372 | SUBSTRATE TREATING APPARATUS AND SUBSTRATE TREATING METHOD - The inventive concept provides an apparatus for treating a substrate by using a supercritical fluid. In an embodiment, the apparatus may include a process chamber that provides a treatment space, and including a chamber heater that increases a temperature of an interior of the treatment space, a substrate support provided in the treatment space and that supports the substrate, and a substrate heating member that heats a lower surface of the substrate while contacting the lower surface of the substrate. | 2022-01-13 |
20220013373 | SUBSTRATE SUPPORT ASSEMBLIES AND COMPONENTS - Exemplary substrate support assemblies may include a platen characterized by a first surface configured to support a semiconductor substrate. The assemblies may include a first stem section coupled with a second surface of the platen opposite the first surface of the platen. The assemblies may include a second stem section coupled with the first stem section. The second stem section may include a housing and a rod holder disposed within the housing. The second stem section may include a connector seated within the rod holder at a first end of the connector. The second stem section may include a heater rod disposed within the first end of the connector and a heater extension rod coupled with the connector at a second end of the connector. The second stem section may include an RF rod and an RF strap coupling the RF rod with an RF extension rod. | 2022-01-13 |
20220013374 | TEMPERATURE CONTROLLED SUBSTRATE SUPPORT ASSEMBLY - Implementations described herein provide a substrate support assembly which enables both lateral and azimuthal tuning of the heat transfer between an electrostatic chuck and a heater assembly. The substrate support assembly comprises an upper surface and a lower surface; one or more main resistive heaters disposed in the substrate support; and a plurality of heaters in column with the main resistive heaters and disposed in the substrate support. A quantity of the heaters is an order of magnitude greater than a quantity of the main resistive heaters and the heaters are independently controllable relative to each other as well as the main resistive heater. | 2022-01-13 |
20220013375 | HIGH PRESSURE AND HIGH TEMPERATURE ANNEAL CHAMBER - Embodiments of the disclosure relate to an apparatus and method for annealing one or more semiconductor substrates. In one embodiment, a processing chamber is disclosed. The processing chamber includes a chamber body enclosing an internal volume, a substrate support disposed in the internal volume and configured to support a substrate during processing, a gas panel configured to provide a processing fluid into the internal volume, and a temperature-controlled fluid circuit configured to maintain the processing fluid at a temperature above a condensation point of the processing fluid. The temperature-controlled fluid circuit includes a gas conduit fluidly coupled to a port on the chamber body at a first end and to the gas panel at a second end. | 2022-01-13 |
20220013376 | SPOT HEATING BY MOVING A BEAM WITH HORIZONTAL ROTARY MOTION - Embodiments of the present disclosure generally relate to apparatus and methods for semiconductor processing, more particularly, to a thermal process chamber. In one or more embodiments, a process chamber comprises a first window, a second window, a substrate support disposed between the first window and the second window, and a motorized rotatable radiant spot heating source disposed over the first window and configured to provide radiant energy through the first window. | 2022-01-13 |
20220013377 | OPTICAL HEATING DEVICE - An optical heating device for heating a substrate includes:
| 2022-01-13 |
20220013378 | APPARATUS FOR FILLING WAFER WITH GLASS POWDER - An apparatus for filling a wafer with glass powder includes a supporting device for supporting a wafer, a feeding device and a scraping device, where the feeding device and the scraping device are both provided on an upper side of the supporting device; a lower side of the feeding device is provided with a fetching part, and the feeding device drives the fetching part to move; a lower side of the scraping device is provided with a scraper, and the scraping device drives the scraper to move. After the feeding device evenly applies the glass powder to the wafer through the fetching part, the scraping device removes an excess of the glass powder on the wafer through the scraper to ensure an appropriate amount of glass powder on the wafer, avoiding complex subsequent processing due to excessive glass powder, and avoiding uneven glass powder distribution. | 2022-01-13 |
20220013379 | High Density Pick and Sequential Place Transfer Process and Tool - Mass transfer tools and methods for high density transfer of arrays of micro devices are described. In an embodiment, a mass transfer tool includes a micro pick up array with an array of transfer heads arranged in clusters. The clusters of transfer heads can be used to pick up a high density group of micro devices followed by sequential placement onto a receiving substrate. | 2022-01-13 |
20220013380 | HIGH DENSITY PICK AND SEQUENTIAL PLACE TRANSFER PROCESS AND TOOL - Mass transfer tools and methods for high density transfer of arrays of micro devices are described. In an embodiment, a mass transfer tool includes a micro pick up array with an array of transfer heads arranged in clusters. The clusters of transfer heads can be used to pick up a high density group of micro devices followed by sequential placement onto a receiving substrate. | 2022-01-13 |
20220013381 | MASS TRANSFER APPARATUS, METHOD, AND DEVICE - A mass transfer apparatus, method, and device are provided. The mass transfer apparatus includes a rotating disk, a drive member, a first transfer head, a second transfer head, and a third transfer head. The rotating disk has a first surface and a second surface opposite to the first surface. The first surface is divided into a first region, a second region, a third region, and a fourth region. The drive member is connected to the second surface and configured to drive the rotating disk to move or rotate. The first transfer head is located in the first region, the second transfer head is located in the second region, and the third transfer head is located in the third region. The first transfer head and the second transfer head is symmetric about the first line, and the second transfer head and the third transfer head is symmetric about the second line. | 2022-01-13 |
20220013382 | TRANSFER CAROUSEL WITH DETACHABLE CHUCKS - A transfer apparatus for use in a multiple processing region system is disclosed that includes a carousel that includes a hub having a plurality of transfer arms extending therefrom. Each of the transfer arms include a first end coupled to the hub and a second end, the second end comprising a component supporting region, and a plurality of electrical interface connections distributed about the component supporting region. | 2022-01-13 |
20220013383 | SUBSTRATE PROCESSING MODULE AND METHOD OF MOVING A WORKPIECE - Embodiments disclosed herein include a substrate processing module and a method of moving a workpiece. The substrate processing module includes a shutter stack and two process stations. The shutter stack is disposed between the process stations. The method of moving a workpiece includes moving a supporting portion from a first location to a shutter stack in a first direction, retrieving the workpiece from the shutter stack, and moving the supporting portion to a second location. The transfer chamber assembly and method allows for moving workpieces to and from the shutter stack to the two process stations. A central transfer robot of the substrate processing module is configured to grip both substrates and shutter discs, allowing for one robot when typically two robots would be required. | 2022-01-13 |
20220013384 | DECENTRALIZED SUBSTRATE HANDLING AND PROCESSING SYSTEM - An electronics manufacturing system includes a first substrate transfer via having position detection sensors to detect a position of a substrate in the first substrate transfer via and flow-controlled valves to inject inert gas through a floor and move the substrate in a predetermined direction with reference to the position within the first substrate transfer via by adjusting a pressure of the inert gas underneath the substrate. A processing chamber is coupled to the first substrate transfer via and having a pedestal with apertures and flow-controlled devices to inject inert gas through the apertures to receive the substrate from the first substrate transfer via and move the substrate into a second substrate transfer via after processing of the substrate. | 2022-01-13 |
20220013385 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE TRANSPORT METHOD - A substrate processing apparatus includes a load port, a load lock chamber, a processing module, a substrate transport mechanism, and a controller. The substrate transport mechanism includes a plurality of substrate holders, each of which is configured hold one substrate. The controller is configured to control, when the processing module is configured to process one substrate at a time, the substrate transport mechanism such that a first substrate holder transports the substrate between the load port and the processing module and a second substrate holder transports the substrate between the load lock chamber and the processing module. The controller is further configured to control, when the processing module is configured to simultaneously process the plurality of substrates, the substrate transport mechanism such that the plurality of substrate holders simultaneously transport the plurality of substrates between the load port, the load lock chamber, and the processing module. | 2022-01-13 |
20220013386 | ANNEALING CHAMBER - Embodiments disclosed herein generally include annealing chambers. The annealing chambers allow for high throughput without sacrificing wafer-to-wafer and within wafer uniformity. The annealing chamber includes a transport system, a substrate carrier, and a plurality of thermal sources. The transport system is magnetically coupled to the substrate carrier. The transport system moves the substrate carrier along a path. A substrate supported by the substrate carrier is annealed by the thermal sources. The annealing chamber described herein allows for a higher throughput of substrate (alternatively referred to as a wafer) annealing compared to furnace annealing chambers. | 2022-01-13 |
20220013387 | SUBSTRATE PROCESSING SYSTEM AND TEMPERATURE CONTROL METHOD - A substrate processing system includes a substrate processing apparatus and a control device. The substrate processing apparatus includes a chamber, and a placing table provided inside the chamber. The placing table places a substrate thereon, and includes a base and an electrostatic chuck provided on an upper surface of the base. The electrostatic chuck has a plurality of division regions each provided with a heater therein. The substrate processing system also includes a control device that includes a measuring unit that measures a resistance value of the heater for each of the division regions, an estimating unit that estimates a temperature of each of the division regions based on the resistance value of the heater measured by the measuring unit, and a power controller that controls a power supplied to the heater for each of the division regions based on the temperature estimated by the estimating unit. | 2022-01-13 |
20220013388 | PIN-LIFTER TEST SUBSTRATE - Various embodiments include apparatuses to provides an in-situ, non-intrusive verification of substrate pin-lifters while a substrate is in a substrate-processing location on a process tool. The disclosed subject matter can also verify any unexpected substrate movement prior to or while the substrate is being removed from the process tool. In an exemplary embodiment, a pin-lifter test substrate includes a number of motion sensors and at least one force sensor. The motion sensors including at least one type of sensor selected from sensor types including inclinometers and accelerometers. A memory device on the pin-lifter test substrate records data received from the motion sensors. Instead of or in addition to the memory device, a wireless communications device transmits data received from the motion sensors to a remote receiver. Other apparatuses and systems are disclosed. | 2022-01-13 |
20220013389 | CRANE MONITORING SYSTEM AND METHOD - A crane monitoring system includes: a first detection apparatus configured to detect a position of a crane, to send a first detection signal when the crane is located above a Front Opening Unified Pod (FOUP) load port of a semiconductor device, and to send a second detection signal when the crane leaves a space above the FOUP load port; a processing apparatus configured to generate a start control signal responsive to receiving the first detection signal, and to generate a stop control signal responsive to receiving the second detection signal; and a second detection apparatus configured to start a detection of whether there is a foreign matter between the crane and the FOUP load port after receiving the start control signal, and to stop the detection after receiving the stop control signal. | 2022-01-13 |
20220013390 | PATTERNED CARRIER ASSEMBLIES HAVING AN INTEGRATED ADHESIVE FILM - Introduced here are carrier assemblies that include a rigid tray having a deck area with a patterned surface of cavities for receiving semiconductor components. The cavities can be designed to accommodate semiconductor components of different form factors (e.g., having different shapes, sizes, etc.). Moreover, an adhesive film can be affixed to the deck area to ensure that the semiconductor components are securely held against the top surface of the rigid tray. In some instances the adhesive film substantially conforms to the deck area, while in other instances the adhesive film extends across the opening of each cavity located in the deck area. Semiconductor component(s) can be secured to the carrier assembly based on the adhesiveness provided by the adhesive film, mechanical force provided the cavities, electrostatic force provided by the cavities, or any combination thereof. | 2022-01-13 |
20220013391 | SUBSTRATE CARRIER LATCHING STRUCTURE - The invention discloses a substrate carrier latching structure, which mainly comprises a top portion, a cover and a detachable module. The top portion is disposed on the enclosure of a substrate carrier, and the cover is connected to the top portion via a detachable module. As such, the excessive stress on the substrate carrier is avoided to maintain the integrity of substrates stored in the inner portion of the substrate carrier. | 2022-01-13 |
20220013392 | CEILING TRAVELING VEHICLE, CEILING TRAVELING VEHICLE SYSTEM, AND METHOD FOR DETECTING OBSTACLE - A ceiling traveling vehicle includes a traveler to travel along a grid-shaped track, a main body coupled to the traveler and below the track, and a detector on a rear side of a center of the main body in a traveling direction of the traveler and below the main body to apply detection light forward in the traveling direction and downward and receive reflected light of the detection light to detect an obstacle. | 2022-01-13 |
20220013393 | APPARATUS FOR TRANSFERRING SUBSTRATE, AND APPARATUS AND METHOD FOR TREATING SUBSTRATE - An apparatus for treating a substrate is provided. The apparatus for treating the substrate includes a first process chamber to perform a liquid treatment process with respect to the substrate, a second process chamber to perform a drying treatment process with respect to the substrate which is liquid treated in the first process chamber, a first hand to introduce the substrate to the first process chamber, before the liquid treatment process is performed, a second hand to withdraw the substrate from the first process chamber after the liquid treatment process is performed and to introduce the substrate into the second process chamber, and a third hand to withdraw the substrate from the second process chamber after the drying treatment process is performed. | 2022-01-13 |
20220013394 | SUBSTRATE HANDLING SYSTEMS - An apparatus for transferring a substrate is disclosed herein. More specifically, the apparatus relates to substrate handling systems used in semiconductor device manufacturing, and more particularly, to substrate handling systems having a substrate handler with enclosed moving elements and increased compatibility with post-CMP cleaning modules. The apparatus includes one or more indexing assemblies. Each of the indexing assemblies including an enclosure, an actuator assembly disposed within the enclosure, and two handling blades disposed outside of the disclosure. Each of the two blades are moveable in either of a translational or a rotating manner. | 2022-01-13 |
20220013395 | SYSTEM FOR A SEMICONDUCTOR FABRICATION FACILITY AND METHOD FOR OPERATING THE SAME - A system for a semiconductor fabrication facility (FAB) and operation method thereof are provided. The system includes an orientation tool and a transporting tool configured to transport at least one customized part. The orientation tool includes a port configured to receive the workpiece, a sensor configured to detect an orientation of the workpiece received in the port and a rotation mechanism configured to turn the workpiece received in the port. | 2022-01-13 |
20220013396 | ALIGNMENT MASK, METAL MASK ASSEMBLY, AND PREPARATION METHOD THEREFOR - Disclosed are an alignment mask, a metal mask assembly, and a preparation method therefor. The alignment mask includes a mask body. The mask body includes: multiple alignment holes; and, separating parts surrounding at least some alignment holes and used for separating the areas at where the at least some alignment holes are located from other areas, where the separation parts include at least one semi-etched line. | 2022-01-13 |
20220013397 | PLASMA PROCESSING APPARATUS AND SEMICONDUCTOR FABRICATION METHOD USING THE SAME - Disclosed is a plasma processing apparatus comprising a plasma electrode, an electrostatic chuck, and a diode board. The electrostatic chuck includes a microheater layer and a chuck electrode. The microheater layer includes an inner heater part and an outer heater part. The inner heater part includes a first inner heater in a first inner region that circumferentially surrounds a center of the microheater layer, and a second inner heater in a second inner region that circumferentially surrounds the first inner region. The outer heater part includes a first outer heater in a first outer region that circumferentially surrounds the second inner region, and a second outer heater in a second outer region that circumferentially surrounds the first outer region. A distance between centers of the first and second outer heaters is less than that between centers of the first and second inner heaters. | 2022-01-13 |
20220013398 | MICRO-LED TRANSFER METHOD AND DISPLAY PANEL - A micro-LED transfer method, including: moving a passing substrate to a position above a donor substrate and moving the pasting substrate in a direction approaching the donor substrate to paste up LED grains so that the LED grains are separated from the bearing substrate; moving the pasting substrate with the LED grains to a position above a target substrate with the LED grains being closer to the target substrate than the pasting substrate, and conducting an alignment so that the LED grains are directly opposite to positions on the target substrate where the LED grains are to be arranged; and heating the pasting substrate with the LED grains to a first temperature greater than or equal to a melting temperature of the hot melt adhesive film to melt the hot melt adhesive film, so that the LED grains are separated from the pasting substrate and transferred to the target substrate. | 2022-01-13 |
20220013399 | ULTRAVIOLET RADIATION SHIELD LAYER - A method is provided to fabricate a wafer including a bonding layer interposed between a device wafer and a handle wafer. The method includes performing a first deposition process to deposit an ultraviolet (UV) shield layer on a backside surface of the handle wafer. A second deposition process is performed to deposit a stress compensation layer on an exposed surface of the UV shield layer. The UV shield layer blocks UV energy generated while performing the second deposition process from reaching the bonding layer. | 2022-01-13 |
20220013400 | WET ALIGNMENT METHOD FOR MICRO-SEMICONDUCTOR CHIP AND DISPLAY TRANSFER STRUCTURE - A wet alignment method for a micro-semiconductor chip and a display transfer structure are provided. The wet alignment method for a micro-semiconductor chip includes: supplying a liquid to a transfer substrate including a plurality of grooves; supplying the micro-semiconductor chip onto the transfer substrate; scanning the transfer substrate by using an absorber capable of absorbing the liquid. According to the wet alignment method, the micro-semiconductor chip may be transferred onto a large area. | 2022-01-13 |
20220013401 | METHOD FOR SEMICONDUCTOR DIE EDGE PROTECTION AND SEMICONDUCTOR DIE SEPARATION - Methods for protecting edges of semiconductor dies are disclosed. Further, the disclosed methods provide for separating the semiconductor dies without using a dicing technique. In one embodiment, a plurality of trenches may be formed on a front side of a substrate including a plurality of semiconductor dies. Individual trenches may correspond to scribe lines of the substrate where each trench includes a depth greater than a final thickness of the semiconductor dies. A dielectric layer may be formed on sidewalls of the trenches, thereby protecting the edges of the semiconductor dies, prior to filling the trenches with an adhesive material. Subsequently, the substrate may be thinned from a back side such that the adhesive material in the trenches may be exposed from the back side. The adhesive material may be removed to singulate individual semiconductor dies of the plurality from the substrate. | 2022-01-13 |
20220013402 | STAGE DEVICE AND SUBSTRATE PROCESSING APPARATUS - A stage device includes: a stage having a pin hole provided therein and a placement surface on which a substrate is placed; and at least one lift pin configured to move up and down through the pin hole; and a lifter configured to raise and lower the at least one lift pin, wherein the stage includes a first heating part provided therein and configured to heat the stage, and the at least one lift pin includes a second heating part provided therein or therearound and configured to heat the at least one lift pin. | 2022-01-13 |
20220013403 | INTEGRATED CHIP WITH CAVITY STRUCTURE - The present disclosure relates to an integrated chip. The integrated chip comprises a dielectric layer over a substrate. A first metal feature is over the dielectric layer. A second metal feature is over the dielectric layer and is laterally adjacent to the first metal feature. A first dielectric liner segment extends laterally between the first metal feature and the second metal feature along an upper surface of the dielectric layer. The first dielectric liner segment extends continuously from along the upper surface of the dielectric layer, to along a sidewall of the first metal feature that faces the second metal feature, and to along a sidewall of the second metal feature that faces the first metal feature. A first cavity is laterally between sidewalls of the first dielectric liner segment and is above an upper surface of the first dielectric liner segment. | 2022-01-13 |
20220013404 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method for example manufacturing a semiconductor device, which includes: forming a hole in a region of an insulating film laminated on a substrate; embedding a first conductive material in the hole to a position lower than a height of a sidewall of the hole; further embedding a second conductive material through a selective growth in the hole in which the first conductive material has been embedded; and etching the second conductive material to form a contact pad at a position above the hole. | 2022-01-13 |
20220013405 | SPACER-DEFINED PROCESS FOR LITHOGRAPHY-ETCH DOUBLE PATTERNING FOR INTERCONNECTS - One or more embodiments described herein include systems, and/or methods that facilitate fabrication of a semiconductor device using a spacer lithography-etch process. According to an embodiment, a method can comprise performing a first lithography exposure and etch over a first layer of a semiconductor device, where the first lithography exposure and etch comprises forming one or more mandrels on a first region of a second layer by employing a first photoresist layer. The method can further comprise forming one or more spacers on a sidewall of the one or more mandrels and covering a second region of the second layer, where the second region is adjacent to the one or more mandrels. The method can further comprise forming a cut over a third region of the second layer and filling the third region with first material. | 2022-01-13 |
20220013406 | Trapezoidal Interconnect at Tight BEOL Pitch - Techniques for forming trapezoidal-shaped interconnects are provided. In one aspect, a method for forming an interconnect structure includes: patterning a trench(es) in a dielectric having a V-shaped profile with a rounded bottom; depositing a liner into the trench(es) using PVD which opens-up the trench(es) creating a trapezoidal-shaped profile in the trench(es); removing the liner from the trench(es) selective to the dielectric whereby, following the removing, the trench(es) having the trapezoidal-shaped profile remains in the dielectric; depositing a conformal barrier layer into and lining the trench(es) having the trapezoidal-shaped profile; depositing a conductor into and filling the trench(es) having the trapezoidal-shaped profile over the conformal barrier layer; and polishing the conductor and the conformal barrier layer down to the dielectric. An interconnect structure is also provided. | 2022-01-13 |
20220013407 | SEMICONDUCTOR STRUCTURE AND METHODS OF FORMING THE SAME - A semiconductor structure and method of forming the same are provided. The method includes: forming a plurality of mandrel patterns over a dielectric layer; forming a first spacer and a second spacer on sidewalls of the plurality of mandrel patterns, wherein a first width of the first spacer is larger than a second width of the second spacer; removing the plurality of mandrel patterns; patterning the dielectric layer using the first spacer and the second spacer as a patterning mask; and forming conductive lines laterally aside the dielectric layer. | 2022-01-13 |
20220013408 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device ( | 2022-01-13 |
20220013409 | METHOD FOR MANUFACTURING WIRING SUBSTRATE - A method for manufacturing a wiring substrate includes forming multiple conductor pads on an insulating layer such that the conductor pads include multiple first conductor pads and multiple second conductor pads, forming multiple protruding parts on surfaces of the first conductor pads of the conductor pads, respectively, forming a resin layer such that the resin layer covers the insulating layer and the conductor pads, exposing, from the resin layer, end portions of the protruding parts on the opposite side with respect to the insulating layer, forming, in the resin layer, multiple openings such that the openings expose surfaces of the second conductor pads of the conductor pads, respectively; and forming a coating film on the surfaces of the second conductor pads exposed in the openings. | 2022-01-13 |
20220013410 | SELF-ALIGNED METAL GATE FOR MULTIGATE DEVICE AND METHOD OF FORMING THEREOF - Devices and methods that a first gate structure wrapping around a channel layer disposed over the substrate, a second gate structure wrapping around another channel layer disposed over the substrate and a dielectric fin structure formed over a shallow trench isolation (STI) feature and between the first and second gate structures. At least one metallization layer is formed on the first gate structure, the dielectric fin structure, and the second gate structure and contiguously extends from the first gate structure to the second gate structure. | 2022-01-13 |
20220013411 | SEMICONDUCTOR DEVICE WITH REDUCED LOADING EFFECT - The present disclosure relates to a method for forming a semiconductor structure includes depositing a dielectric layer on a substrate and depositing a patterning layer on the dielectric layer. The method also includes performing a first etching process on the patterning layer to form a first region including a first plurality of blocks at a first pattern density and a second region including a second plurality of blocks at a second pattern density that is lower than the first pattern density. The method also includes performing a second etching process on the second plurality of blocks to decrease a width of each block of the second plurality of blocks and etching the dielectric layer and the substrate using the first and second pluralities of blocks to form a plurality of fin structures. | 2022-01-13 |
20220013412 | PATTERNING METHOD AND STRUCTURES RESULTING THEREFROM - A method includes depositing a first work function layer over a gate dielectric layer, forming a first hard mask layer over the first work function layer, forming a photoresist mask over the first hard mask layer, where forming the photoresist mask includes depositing a bottom anti-reflective coating (BARC) layer over the first hard mask layer, etching a portion of the BARC layer, etching a portion of the first hard mask layer using the BARC layer as a mask, etching a portion of the first work function layer to expose a portion of the gate dielectric layer through the first hard mask layer and the first work function layer, removing the first hard mask layer, and depositing a second work function layer over the first work function layer and over the portion of the gate dielectric layer. | 2022-01-13 |
20220013413 | FINFET DEVICES - FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures. | 2022-01-13 |
20220013414 | METHODS RELATED TO RADIO-FREQUENCY SWITCHING DEVICES HAVING IMPROVED VOLTAGE HANDLING CAPABILITY - Methods related to radio-frequency (RF) switching devices having improved voltage handling capability. In some embodiments, a method for fabricating an RF switching device can include: providing a semiconductor substrate; forming a plurality of field-effect transistors (FETs) on the semiconductor substrate such that the FETs have a non-uniform distribution of a parameter; and connecting the FETs to form a stack, such that the non-uniform distribution results in the stack having a first voltage handling capacity that is greater than a second voltage handling capacity corresponding to a similar stack having a substantially uniform distribution of the parameter. | 2022-01-13 |
20220013415 | RADIO-FREQUENCY SWITCHING DEVICES HAVING IMPROVED VOLTAGE HANDLING CAPABILITY - Radio-frequency (RF) switching devices having improved voltage handling capability. In some embodiments, a switching device can include a first terminal and a second terminal, and a plurality of switching elements connected in series to form a stack between the first terminal and the second terminal. The switching elements can have a non-uniform distribution of a parameter that results in the stack having a first voltage handling capacity that is greater than a second voltage handling capacity corresponding to a similar stack having a substantially uniform distribution of the parameter. | 2022-01-13 |
20220013416 | Apparatus and Methods for Wafer to Wafer Bonding - A method includes having a first wafer bonding recipe and a model of a wafer bonding process, the model comprising an input indicative of a physical parameter of a first wafer to be bonded to a second wafer and configured to output a wafer bonding recipe based on the physical parameter of the first wafer; obtaining measurements of the first wafer to obtain the physical parameter of the first wafer; generating, by the model, the first wafer bonding recipe based on the physical parameter of the first wafer; and bonding the first wafer to the second wafer in accordance with the first wafer bonding recipe to produce a first post-bond wafer. | 2022-01-13 |
20220013417 | SYSTEM AND METHOD FOR MODIFICATION OF SUBSTRATES - Various embodiments of the present technology generally relate to substrate planarization. More specifically, some embodiments of the present technology relate a versatile systems and methods for precision surface topography optimization known as planarization on nominally planar substrates. In some embodiments, a method for planarization of a patterned substrate using inkjets can determine the global and nanoscale topography and pattern information of the patterned substrate. Based upon the global and nanoscale topography and pattern information, a drop pattern can be determined and then dispensed on the patterned substrate. A gap between the patterned substrate and a superstrate causing the dispensed drops can be closed to form a substantially contiguous film. The substantially contiguous film can be cured and the superstrate can be separated from the patterned substrate with substantially contiguous film on the patterned substrate. | 2022-01-13 |
20220013418 | SEMICONDUCTOR WAFER, METHOD FOR SEPARATING THE SEMICONDUCTOR WAFER, SEMICONDUCTOR CHIP, AND SEMICONDUCTOR PACKAGE INCLUDING THE SEMICONDUCTOR CHIP - A semiconductor wafer includes a first chip region and a second chip region spaced apart from each other by a scribe lane region. The semiconductor wafer also includes a test pad disposed in the scribe lane region. The semiconductor wafer additionally includes a protective layer partially covering the first chip region, the second chip region, and the scribe lane region, wherein the protective layer covers a portion of the test pad adjacent to the first chip region and leaves a remaining portion of the first test pad exposed. | 2022-01-13 |
20220013419 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor chip with a normal connection electrode and a measurement connection electrode, formed on a first surface, and a substrate with a normal substrate pad, connected to the normal connection electrode, and a measurement substrate pad, connected to the measurement connection electrode. The normal substrate pad and the measurement substrate pad are formed on a surface that faces the first surface. The measurement connection electrode includes first and second edge measurement connection electrodes and first and second center measurement connection electrodes. The measurement substrate pad includes a center measurement substrate pad, a first edge measurement substrate pad, and a second edge measurement substrate pad. The first edge measurement connection electrode and the first center measurement connection electrode are electrically connected to each other, and the second edge measurement connection electrode and the second center measurement connection electrode are electrically connected to each other. | 2022-01-13 |
20220013420 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a frame having a first surface, a second surface opposite the first surface, and a through-hole, a first semiconductor chip in the through-hole of the frame, a second semiconductor chip on the frame, a first connection structure on the first surface of the frame and including a first redistribution structure electrically connected to the first semiconductor chip and having a third surface contacting the first surface of the frame, the first redistribution structure including a first redistribution layer and a first redistribution via, a first pad on a center portion of a fourth surface of the first redistribution structure opposite the third surface, a second pad on an edge portion of the fourth surface, a second connection structure on the second surface and comprising a second redistribution structure electrically connected to the second semiconductor chip and including a second redistribution layer and a second redistribution via, and an electrical connection metal on the first pad on the fourth surface, wherein the electrical connection metal is not on the second pad. | 2022-01-13 |
20220013421 | SHIELDED FAN-OUT PACKAGED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING - Several aspects of the present technology are directed toward fan-out packaged semiconductor devices having an integrated shield. The shield can include a conductive wall and a conductive cap over a redistribution structure. The shield can surround or at least partially enclose circuits placed or formed on the redistribution structure. The circuits and/or the conductive cap can be covered by an encapsulant, and the conductive cap can be on an upper surface of an encapsulant. | 2022-01-13 |
20220013422 | PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME - Provided is a package structure including a composite wafer, a plurality of dies, an underfill, and a plurality of dam structures. The composite wafer has a first surface and a second surface opposite to each other. The composite wafer includes a plurality of seal rings dividing the composite wafer into a plurality of packages; and a plurality of through holes respectively disposed between the seal rings and penetrating through the first and second surfaces. The dies are respectively bonded onto the packages at the first surface by a plurality of connectors. The underfill laterally encapsulates the connectors. The dam structures are disposed on the first surface of the composite wafer to separate the underfill from the through holes. | 2022-01-13 |
20220013423 | ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF - Some embodiments of the disclosure provide an electronic device. The electronic device comprises: a substrate; a first nitride semiconductor layer on the substrate; a second nitride semiconductor layer on the first nitride semiconductor layer, and having a band gap greater than a band gap of the first nitride semiconductor layer; a group III-V dielectric layer disposed on the second nitride semiconductor layer; a gate electrode disposed on the second nitride semiconductor layer; and a first passivation layer disposed on the group III-V dielectric layer, wherein the group III-V dielectric layer is separated from the gate electrode by the first passivation layer. | 2022-01-13 |
20220013424 | Apparatus Having a Functional Structure Delimited by a Frame Structure and Method for Producing Same - An apparatus includes a semiconductor-based substrate with a functional structure that is formed in or on the semiconductor-based substrate. The apparatus includes a frame structure surrounding the functional structure and includes a coating that covers the functional structure and is delimited by the frame structure. | 2022-01-13 |
20220013425 | SEMICONDUCTOR DEVICE WITH PROTECTION LAYERS AND METHOD FOR FABRICATING THE SAME - The present application discloses a semiconductor device with protection layers for reducing the metal to silicon leakage and a method for fabricating the semiconductor device. The semiconductor device includes a first die, a first conductive feature positioned in the first die, a second die positioned on the first die, a first mask layer positioned on the second die, a conductive filler layer positioned along the first mask layer and the second die, extending to the first die, and contacting the first conductive feature, isolation layers positioned between the conductive filler layer and the first die and between the conductive filler layer and the second die, and protection layers positioned between the conductive filler layer and the first mask layer and covering upper portions of the isolation layers. | 2022-01-13 |
20220013426 | THREE-DIMENSIONAL MEMORY DEVICES HAVING HYDROGEN BLOCKING LAYER AND FABRICATION METHODS THEREOF - Embodiments of three-dimensional (3D) memory devices have a blocking layer and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, an array of NAND memory strings each extending vertically through the memory stack, a plurality of logic devices above the array of NAND memory strings, a semiconductor layer above and in contact with the logic devices, a pad-out interconnect layer above the semiconductor layer, and a blocking layer vertically between the semiconductor layer and the pad-out interconnect layer and configured to block outgassing of hydrogen. | 2022-01-13 |
20220013427 | SEMICONDUCTOR DEVICE - Semiconductor device (A | 2022-01-13 |
20220013428 | ELECTRONIC DEVICE - An electronic device includes an upper package, a lower package and a printed circuit board. The upper package includes an upper chip. The lower package includes a lower chip. The upper package and the lower package are stacked on the printed circuit board. The thermal diffusion layer is disposed in a vicinity of the lower chip at the lower package. | 2022-01-13 |
20220013429 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor element; a submount on which the semiconductor element is mounted, wherein the submount has a first surface on which the semiconductor element is mounted, a second surface located on a side opposite the first surface, and a lateral surface located between the first surface and the second surface, and wherein the submount comprises: a groove located at the second surface, a heat dissipation portion located at the second surface, and an electrode pattern located at the first surface; a package substrate on which the submount is mounted; a first joint member that physically joins the heat dissipation portion to the package substrate; and a connection portion located on the side surface, wherein the connection portion electrically connects the electrode pattern and the package substrate, and the connection portion comprises a second joint member. | 2022-01-13 |
20220013430 | SEMICONDUCTOR STRUCTURE AND METHOD OF WAFER BONDING - A semiconductor structure includes a glass substrate and a device wafer. The glass substrate includes a glass layer, a heat dissipation layer and a silicon nitride layer stacked from bottom to top. The device wafer includes at least one semiconductor device integrated in a device layer situated over the silicon nitride layer of the glass substrate. Or, the glass substrate includes a glass layer and a silicon nitride layer stacked from bottom to top. The device wafer includes at least one semiconductor device integrated in a device layer, and a heat dissipation layer is stacked on the device layer, wherein the heat dissipation layer is bonded with the silicon nitride layer of the glass substrate. The present invention also provides a method of wafer bonding for manufacturing said semiconductor structure. | 2022-01-13 |
20220013431 | AUTOMOTIVE POWER DEVICES ON DIRECT BOND COPPER EMBEDDED IN PCB DRIVER BOARDS - A power device embedded PCB includes a printed circuit board having a first major surface separated by a thickness and opposite a second major surface and an embedded power device. The embedded power device may include a power semiconductor device, an electrically and thermally conductive substrate bonded to the power semiconductor device along a first surface of the electrically and thermally conductive substrate and bonded to an electrical insulation layer on a second surface of the electrically and thermally conductive substrate opposite the first surface and a thermally conductive substrate bonded to the electrical insulation layer on a surface opposite the bonded electrically and thermally conductive substrate. The power semiconductor device, the electrically and thermally conductive substrate, the electrical insulation layer, and the thermally conductive substrate are disposed within the printed circuit board. The thermally conductive substrate forms a bondable surface adjacent the second major surface of the printed circuit board. | 2022-01-13 |
20220013432 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device includes an insulating substrate on which a first conductor layer is arranged on one surface, a first conductor that is connected to the first conductor layer via a first connecting material, and a semiconductor element that is connected to the first conductor via a first connecting material. When viewed from a direction perpendicular to an electrode surface of the semiconductor element, the first conductor includes a peripheral portion formed larger than the semiconductor element. A first recess is formed in the peripheral portion so that a thickness of the first connecting material becomes thicker than other portions. | 2022-01-13 |
20220013433 | Semiconductor Device Package Comprising a Thermal Interface Material with Improved Handling Properties - A semiconductor device package comprises an electrically conductive carrier, a semiconductor die disposed on the carrier, an encapsulant encapsulating part of the carrier and the semiconductor die, an electrically insulating and thermally conductive interface structure, in particular covering an exposed surface portion of the carrier and a connected surface portion of the encapsulant, wherein the interface structure comprises a glass transition temperature in a range between −40° C. to 150° C. | 2022-01-13 |
20220013434 | METHODS OF MANUFACTURING STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH HIGH EFFICIENCY THERMAL PATHS - Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material. | 2022-01-13 |
20220013435 | INTEGRATED CIRCUIT WITH A RING-SHAPED HOT SPOT AREA AND MULTIDIRECTIONAL COOLING - Methods, systems, and apparatus, including an integrated circuit (IC) with a ring-shaped hot spot area. In one aspect, an IC includes a first area along an outside perimeter of a surface of the IC. The first area defines a first inner perimeter. The IC includes a second area that includes a center of the IC and that includes a first set of components. The second area defines a first outer. The IC includes a ring-shaped hot spot area between the first area and the second area. The ring-shaped hot spot area defines a ring outer perimeter that is juxtaposed with the first inner perimeter. The ring-shaped hot spot area defines a ring inner perimeter that is juxtaposed with the first outer perimeter. The ring-shaped hot spot area includes a second set of components that produce more heat than the first set of components. | 2022-01-13 |
20220013436 | Electronic device - An electronic device includes: a flexible substrate including a through hole; a connecting element disposed in the through hole; a semiconductor disposed on the flexible substrate; and a first conductive element disposed under the flexible substrate, wherein the first conductive element electrically connects to the semiconductor through the connecting element, wherein a distance between the semiconductor and the connecting element ranges from 5 μm to 500 μm | 2022-01-13 |
20220013437 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device in which the reliability of the gate insulating film in a trench gate is improved. The semiconductor device includes a semiconductor substrate, a plurality of trench gates, and a gate electrode. The semiconductor substrate includes an active region and a wiring region. The trench gates extend from the first active region to the wiring region. The trench gates form parts of transistors in the active region. The gate electrode is provided in the wiring region and is electrically connected to the trench gates. The end portions of the trench gates are located in the wiring region. The gate electrode is provided so as to cover gate contact portions formed at the end portions of the trench gates. The gate electrode is electrically connected to trench gates via the gate contact portions. The plurality of trench gates extend only in one direction. | 2022-01-13 |
20220013438 | POWER CONVERTER - To provide a technique of reducing gate oscillation while suppressing reduction in switching speed. A semiconductor device according to the technique disclosed in the present description includes: a first gate electrode in an active region; a gate pad in a first region different from the active region in a plan view; and a first gate line electrically connecting the first gate electrode and the gate pad to each other. The first gate line is formed into a spiral shape. The first gate line is made of a different type of material from the first gate electrode. | 2022-01-13 |
20220013439 | PACKAGED HIGH VOLTAGE MOSFET DEVICE WITH CONNECTION CLIP AND MANUFACTURING PROCESS THEREOF - An HV MOSFET device has a body integrating source conductive regions. Projecting gate structures are disposed above the body, laterally offset with respect to the source conductive regions. Source contact regions, of a first metal, are arranged on the body in electric contact with the source conductive regions, and source connection regions, of a second metal, are arranged above the source contact regions and have a height protruding with respect to the projecting gate structures. A package includes a metal support bonded to a second surface of the body, and a dissipating region, above the first surface of the semiconductor die. The dissipating region includes a conductive plate having a planar face bonded to the source connection regions and spaced from the projecting gate structures. A package mass of dielectric material is disposed between the support and the dissipating region and incorporates the semiconductor die. The dissipating region is a DBC-type insulation multilayer. | 2022-01-13 |
20220013440 | MOUNTING BOARD AND SEMICONDUCTOR DEVICE - A mounting board includes an electrode pad and an insulating protective film on an insulating resin layer. In a plan view, the electrode pad includes first and second sides running parallel in a first direction. The insulating protective film includes an opening including first and second regions adjoining each other in the first direction. The first region lies over the electrode pad to expose part of the electrode pad. The second region exposes part of the insulating resin layer. The first region is defined by third and fourth sides that are between the first and second sides in a second direction perpendicular to the first direction and run parallel in the first direction. The maximum dimension of the second region in the second direction is greater than the distance between respective ends of the third and fourth sides at which the first region adjoins the second region. | 2022-01-13 |
20220013441 | SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure includes a frontside redistribution layer, a stacking structure, a backside redistribution layer, a first intellectual property (IP) core, and a second IP core. The stacking structure is disposed over the frontside redistribution layer and comprises a first semiconductor die and a second semiconductor die over the first semiconductor die. The backside redistribution layer is disposed over the stacking structure. The first IP core is disposed in the stacking structure and is electrically coupled to the frontside redistribution layer through a first routing channel. The second IP core is disposed in the stacking structure and is electrically coupled to the backside redistribution layer through a second routing channel, wherein the second routing channel is separated from the first routing channel and electrically insulated from the frontside redistribution layer. | 2022-01-13 |
20220013442 | APPARATUS AND METHOD FOR PROVIDING A SCALABLE BALL GRID ARRAY (BGA) ASSIGNMENT AND A PCB CIRCUIT TRACE BREAKOUT PATTERN FOR RF CHIP INTERFACES - A pin map covers a surface area of a layer of a printed circuit board (PCB). The pin map includes a plurality of electrical designations for each pin in the pin map and a plurality of empty spaces within the pin map. Each electrical designation may be assigned to a pin on the pin map. Each electrical designation includes a positive polarity (P+) pin, a negative polarity (P−) pin, or an electrical ground (G) pin. If a space in the pin map does not have an electrical designation, then it may include an empty space/plain portion of the printed circuit board (PCB). The pin map may include a plurality of rows and a first repeating pin polarity pattern. The first repeating pin polarity pattern may include a lane unit tile. The pin map may help couple two circuit elements together that are attached to one layer of a PCB. | 2022-01-13 |
20220013443 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device package includes a first substrate, a second substrate, a conductive structure, a first solder and a second solder. The second substrate is disposed over the first substrate. The conductive structure is disposed between the first substrate and the second substrate. The conductive structure includes a first wetting portion, a second wetting portion, and a non-wetting portion disposed between the first wetting portion and the second wetting portion. The first solder covers the first wetting portion and connects the conductive structure to the first substrate. The second solder covers the second wetting portion and connects the conductive structure to the second substrate. The first solder is spaced apart from the second solder by the non-wetting portion. | 2022-01-13 |
20220013444 | SUBSTRATE COMPRISING AN INDUCTOR AND A CAPACITOR LOCATED IN AN ENCAPSULATION LAYER - A package that includes a power amplifier and a substrate coupled to the power amplifier. The substrate includes an encapsulation layer, a capacitor device located in the encapsulation layer, an inductor located in the encapsulation layer, at least one first dielectric layer coupled to a first surface of the encapsulation layer, and a plurality of first interconnects coupled to the first surface of the encapsulation layer. The plurality of first interconnects is located at least in the at least one first dielectric layer. The plurality of first interconnects is coupled to the capacitor device and the inductor. The inductor and the capacitor device are configured to be electrically coupled together to operate as elements of a matching network for the power amplifier. The capacitor device is configured to be coupled to ground. | 2022-01-13 |
20220013445 | INTERPOSER AND SEMICONDUCTOR PACKAGE INCLUDING SAME - An interposer including a base layer, a redistribution structure on a first surface of the base layer and including a conductive redistribution pattern, a first lower protection layer on a second surface of the base layer, a lower conductive pad on the first lower protection layer, a through electrode connecting the conductive redistribution pattern and the lower conductive pad, a second lower protection layer on the first lower protection layer, including a different material than the first lower protection layer, and contacting at least a portion of the lower conductive pad, and an indentation formed in an outer edge region of the interposer to provide a continuous angled sidewall extending entirely through the second lower protection layer and through at least a portion of the first protection layer. | 2022-01-13 |
20220013446 | High Temperature Barrier Film For Molten Wafer Infusion - A metallized via structure may comprise a via hole, a barrier layer deposited within the via hole, and a metallic plug disposed within the via hole. The via hole may be formed in a device package, and the via hole may be defined by at least one interior wall of the device package. The barrier layer may be disposed upon the at least one interior wall to form a barrier layer lined via hole. The metallic plug may be disposed within the barrier lined via hole by pressurized injection of a molten metal, such that the barrier layer is situated between the metallic plug and the at least one interior wall. The barrier layer may be situated to prevent the metallic plug from contacting the interior wall. | 2022-01-13 |
20220013447 | SEMICONDUCTOR PACKAGE - A semiconductor package includes an upper substrate having a first surface and a second surface which are opposite to each other, a semiconductor chip on the first surface of the upper substrate, a buffer layer on the second surface of the upper substrate, a mold layer between the second surface of the upper substrate and the buffer layer, a plurality of through-electrodes penetrating the upper substrate and the mold layer, an interconnection layer between the first surface of the upper substrate and the semiconductor chip and configured to electrically connect the semiconductor chip to the plurality of through-electrodes, and a plurality of bumps disposed on the buffer layer, spaced apart from the mold layer, and electrically connected to the plurality of through-electrodes. The mold layer includes an insulating material of which a coefficient of thermal expansion is greater than that of the upper substrate. | 2022-01-13 |
20220013448 | WIRING SUBSTRATE AND METHOD FOR MANUFACTURING WIRING SUBSTRATE - A wiring substrate includes a resin insulating layer, a via conductor formed in the resin insulating layer such that the via conductor is penetrating through the resin insulating layer, a conductor pad formed on the resin insulating layer and connected to the via conductor, a coating insulating layer formed on the resin insulating layer such that the coating insulating layer is covering the conductor pad, and a metal post formed on the conductor pad and protruding from the coating insulating layer. The conductor pad is formed such that a central axis of the conductor pad is shifted in a predetermined direction with respect to a central axis of the via conductor, and the metal post is formed such that a central axis of the metal post is shifted in the predetermined direction with respect to the central axis of the conductor pad. | 2022-01-13 |
20220013449 | Assemblies having Conductive Interconnects which are Laterally and Vertically Offset Relative to One Another - Some embodiments include an integrated assembly having a base which includes first circuitry. Memory decks are over the base. Each of the memory decks has a sense/access line coupled with the first circuitry. The memory decks and base are vertically spaced from one another by gaps. The gaps alternate in a vertical direction between first gaps and second gaps. Overlapping conductive paths extend from the sense/access lines to the first circuitry. The conductive paths include first conductive interconnects within the first gaps and second conductive interconnects within the second gaps. The first and second conductive interconnects are laterally offset relative to one another. | 2022-01-13 |
20220013450 | Integrated Assemblies Having Conductive-Shield-Structures Between Linear-Conductive-Structures - Some embodiments include an assembly having channel-material-structures, and having memory cells along the channel-material-structures. The memory cells include charge-storage-material. Linear-conductive-structures are vertically offset from the channel-material-structures and are electrically coupled with the channel-material-structures. Intervening regions are between the linear-conductive-structures. Conductive-shield-structures are within the intervening regions. The conductive-shield-structures are electrically coupled with a reference-voltage-source. | 2022-01-13 |
20220013451 | COMPACT TRANSISTOR UTILIZING SHIELD STRUCTURE ARRANGEMENT - A transistor includes a semiconductor substrate having a first terminal and a second terminal. An interconnect structure is formed on an upper surface of the semiconductor substrate, the interconnect structure being formed of multiple layers of dielectric material and electrically conductive material. The electrically conductive material of the interconnect structure includes a pillar in electrical contact with the first terminal, a first runner electrically connected to the pillar, a tap interconnect in electrical contact with the second terminal, a second runner electrically connected to the tap interconnect, a shield structure positioned between the pillar and the tap interconnect, and a shield runner electrically connected to the shield structure, the shield runner overlying the second runner in a direction perpendicular to the upper surface of the semiconductor substrate. | 2022-01-13 |
20220013452 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device package and a method for manufacturing the semiconductor device package are provided. The semiconductor device package includes a carrier, an electronic component, a first encapsulant and a conductive via. The carrier has a first surface and a second surface opposite to the first surface. The semiconductor device is mounted at the second surface of the carrier. The first encapsulant encapsulates the first surface of the carrier and has a surface facing away from the first surface of the carrier. The conductive via extends from the surface of the first encapsulant into the carrier. | 2022-01-13 |
20220013453 | Method for Manufacturing an Anchor-Shaped Backside Via - A method includes providing a fin, an isolation structure, and first and second source/drain (S/D) features over the fin; forming an etch mask covering a first portion and exposing a second portion of the fin; removing the second portion of the fin, resulting in a first trench; filling the first trench with a first dielectric feature; removing the etch mask; and applying etching process(es) to remove the first portion of the fin and to partially recess the first S/D feature. The etching process(es) includes an isotropic etching tuned selective to materials of the first S/D feature and not materials of the isolation structure and the first dielectric feature, resulting in a second trench under the first S/D feature and having a gap between a bottom surface of the first S/D feature and a top surface of the isolation structure. The method further includes forming a via in the second trench. | 2022-01-13 |
20220013454 | SEMICONDUCTOR PACKAGE - A semiconductor package includes: a first redistribution structure having a first surface and a second surface opposing the first surface, and including a first insulating layer and a first redistribution layer disposed on the first insulating layer; a semiconductor chip disposed on the first surface of the first redistribution structure, and including a connection pad electrically connected to the first redistribution layer and embedded in the first insulating layer; a vertical connection structure disposed on the first surface and electrically connected to the first redistribution layer; an encapsulant encapsulating at least a portion of each of the semiconductor chip and the vertical connection structure; a second redistribution structure disposed on the encapsulant and including a second redistribution layer electrically connected to the vertical connection structure; and a connection bump disposed on the second surface and electrically connected to the first redistribution layer. | 2022-01-13 |
20220013455 | WIRING SUBSTRATE AND METHOD FOR MANUFACTURING WIRING SUBSTRATE - A wiring substrate includes a resin insulating layer, a via conductor formed in the resin insulating layer such that the via conductor is penetrating through the resin insulating layer, a conductor pad formed on the resin insulating layer and connected to the via conductor, a coating insulating layer formed on the resin insulating layer such that the coating insulating layer is covering the conductor pad, and a metal post formed on the conductor pad and protruding from the coating insulating layer. The via conductor is formed such that the via conductor is increased in diameter toward the conductor pad, and the metal post is formed such that the metal post is increased in diameter toward the conductor pad. | 2022-01-13 |
20220013456 | INTERCONNECT STRUCTURES - Representative techniques and devices, including process steps may be employed to mitigate undesired dishing in conductive interconnect structures and erosion of dielectric bonding surfaces. For example, an embedded layer may be added to the dished or eroded surface to eliminate unwanted dishing or voids and to form a planar bonding surface. Additional techniques and devices, including process steps may be employed to form desired openings in conductive interconnect structures, where the openings can have a predetermined or desired volume relative to the volume of conductive material of the interconnect structures. Each of these techniques, devices, and processes can provide for the use of larger diameter, larger volume, or mixed-sized conductive interconnect structures at the bonding surface of bonded dies and wafers. | 2022-01-13 |
20220013457 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, a semiconductor element, and a multilayer wiring. The semiconductor element is formed on the semiconductor substrate. The multilayer wiring includes a wiring electrically connected with the semiconductor element, and a first inductor. The multilayer wiring is formed on the semiconductor substrate such that the multilayer wiring covers the semiconductor element. The first inductor is formed such that the first inductor electrically isolated from the wiring and is magnetically connected with the wiring. | 2022-01-13 |
20220013458 | VERTICAL ELECTRICAL FUSE DEVICE AND METHOD FOR FORMING THE SAME - The present disclosure relates to an electrical fuse (e-fuse) device and a method for forming the electrical fuse device. The vertical e-fuse device includes a fuse link disposed over a semiconductor base. A material of the fuse link and a material of the semiconductor base are the same. The vertical e-fuse device also includes a first bottom anode/cathode region and a second bottom anode/cathode region disposed over the semiconductor base. A bottom portion of the fuse link is sandwiched between the first bottom anode/cathode region and the second anode/cathode region. The vertical e-fuse device further includes a top anode/cathode region disposed over the fuse link. | 2022-01-13 |
20220013459 | 3D NAND MEMORY DEVICE AND METHOD OF FORMING THE SAME - In a method for fabricating a semiconductor device, an initial stack of sacrificial word line layers and insulating layers is formed over a substrate of the semiconductor device. The sacrificial word line layers and the insulating layers are disposed over the substrate alternately. A first staircase is formed in a first staircase region of a connection region of the initial stack. A second staircase is formed in a second staircase region of the connection region of the initial stack. The connection region of the initial stack includes a separation region between the first and second staircases, and the connection region is positioned between array regions of the initial stack at opposing sides of the initial stack. | 2022-01-13 |
20220013460 | PACKAGED SEMICONDUCTOR ASSEMBLIES AND METHODS FOR MANUFACTURING SUCH ASSEMBLIES - Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites. | 2022-01-13 |
20220013461 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a bridge and a plurality of dies. The bridge is free of active devices and includes a substrate, an interconnect structure, a redistribution layer structure and a plurality of conductive connectors. The interconnect structure includes at least one dielectric layer and a plurality of first conductive features in the at least one dielectric layer. The redistribution layer structure includes at least one polymer layer and a plurality of second conductive features in the at least one polymer layer, wherein a sidewall of the interconnect structure is substantially flush with a sidewall of the redistribution layer structure. The conductive connectors are electrically connected to one another by the redistribution layer structure and the interconnect structure. The bridge electrically connects the plurality of dies. | 2022-01-13 |
20220013462 | PACKAGE SUBSTRATE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a package substrate, includes: providing a glass frame having a through hole and a chip embedding cavity; fixing an electronic component in the chip embedding cavity; coating a dielectric layer to an upper surface of the glass frame, the through hole and the chip embedding cavity and curing the dielectric layer; photoetching the dielectric layer to form an opening window arranged above the through hole; depositing metal through the opening window and patterning the metal to form a metal pillar and a circuit layer, the metal pillar passing through the through hole, the circuit layer being arranged on the upper surface and/or a lower surface of the glass frame and being connected to the electronic component and the metal pillar; forming a solder mask on a surface of the circuit layer, patterning the solder mask to form a pad connected to the circuit layer. | 2022-01-13 |
20220013463 | SEMICONDUCTOR PACKAGES AND FORMING METHODS THEREOF - A semiconductor package includes a redistribution layer structure, a first semiconductor chip, a circuit board structure and an encapsulation layer. The redistribution layer structure has a first side and a second side opposite to the first side. The first semiconductor chip is electrically connected to the first side of the redistribution layer structure. The circuit board structure is electrically connected to the first side of the redistribution layer structure, and the circuit board structure includes a first mask layer having an opening pattern that corresponds to first semiconductor chip. The encapsulation layer laterally encapsulates the circuit board structure and fills in a space between the semiconductor chip and the opening pattern of the first mask layer of the circuit board structure. | 2022-01-13 |
20220013464 | SEMICONDUCTOR PACKAGE INCLUDING INTERPOSER AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A semiconductor package comprises a package substrate, a semiconductor chip on the package substrate, and an interposer substrate on the semiconductor chip. The interposer substrate comprises a first surface facing the semiconductor chip and a trench in the first surface, the trench vertically overlapping the semiconductor chip. An insulating filler is provided between the semiconductor chip and the interposer substrate, and at least partially fills the trench of the interposer substrate. | 2022-01-13 |
20220013465 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a first redistribution structure having a first surface in which a first pad and a second pad are embedded and including a first redistribution layer thereon, and a vertical connection structure including a land layer and a pillar layer. The land layer is embedded in the first surface of the first redistribution structure, and a width of an upper surface of the land layer is narrower than a width of a lower surface of the pillar layer. | 2022-01-13 |
20220013466 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a wiring layer; a titanium nitride layer deposited on the wiring layer; a titanium oxynitride layer deposited on the titanium nitride layer; a titanium oxide layer deposited on the titanium oxynitride layer; and a surface passivation film deposited on the titanium oxide layer, wherein an opening penetrating the titanium nitride layer, the titanium oxynitride layer, the titanium oxide layer, and the surface passivation film is provided to expose a part of the wiring layer so as to serve as a pad. | 2022-01-13 |
20220013467 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THEREOF - A semiconductor device and a method for fabricating the same. The semiconductor device comprising: a first level wiring disposed at a first metal level, and includes a first line wiring, a first insulating capping film and a first side wall graphene film, the first insulating capping film extending along an upper surface of the first line wiring, and the first side wall graphene film extending along a side wall of the first line wiring; an interlayer insulating film covering the side wall of the first line wiring and a side wall of the first insulating capping film; and a second level wiring disposed at a second metal level higher than the first metal level, and includes a second via connected to the first line wiring, and a second line wiring connected to the second via, wherein the second via penetrates the first insulating capping film. | 2022-01-13 |
20220013468 | Misregistration Target Having Device-Scaled Features Useful in Measuring Misregistration of Semiconductor Devices - A target and method for using the same in the measurement of misregistration between at least a first layer and a second layer formed on a wafer in the manufacture of functional semiconductor devices on the wafer, the functional semiconductor devices including functional device structures (FDSTs), the target including a plurality of measurement structures (MSTs), the plurality of MSTs being part of the first layer and the second layer and a plurality of device-like structures (DLSTs), the plurality of DLSTs being part of at least one of the first layer and the second layer, the DLSTs sharing at least one characteristic with the FDSTs and the MSTs not sharing the at least one characteristic with the FDSTs. | 2022-01-13 |
20220013469 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a semiconductor wafer with a chip region and an edge region and with an identification mark formed on one surface of the semiconductor wafer in the edge region; conductive connectors formed on the one surface of the semiconductor wafer in the chip region; and dummy conductive connectors formed on the one surface of the semiconductor wafer in the edge region, wherein the dummy conductive connectors do not overlap with the identification mark. | 2022-01-13 |
20220013470 | SEMICONDUCTOR DEVICE AND TEMPLATE - A semiconductor device includes: a semiconductor substrate having a first surface; a device area that is formed on the semiconductor substrate and includes a semiconductor element; and a conductive member that surrounds the device area and extends in a first direction perpendicularly intersecting the first surface. The conductive member is formed on the semiconductor substrate, and includes a first pattern and a second pattern, the second pattern overlapping the first pattern in the first direction. A pitch of the first pattern in a second direction intersecting the first direction is different from a pitch of the second pattern in the second direction. | 2022-01-13 |