02nd week of 2010 patent applcation highlights part 40 |
Patent application number | Title | Published |
20100009459 | METHOD AND MICROFLUIDIC DEVICE FOR COMBINING REACTION COMPONENTS CONTAINED IN LIQUIDS - The invention relates to a method and a microfluidic device for combining reaction components contained in liquids. The method comprises the steps: application of at least one first liquid filament containing a first reaction component on a first carrier substrate; application of at least one second liquid filament containing a second reaction component on a second carrier substrate; positioning of the two carrier substrates relative to each other at a predetermined distance such that the liquid filaments face each other; and bringing at least one of the at least one first liquid filament into contact with at least one of the at least one second liquid filament by creating at least one connecting point of the respective first and second liquid filaments. A microfluidic device for combining reaction components contained in liquids comprises two carrier substrates each being adapted for accommodating at least one first and at least one second liquid filament, wherein the liquid filaments are preferably each accommodated in a receiving means which is comprised in the carrier substrate. | 2010-01-14 |
20100009460 | Multifunctional vacuum manifold - A laboratory device design particularly for a multiplate format that includes a manifold wherein the position of the plate is not a function of gasket compression or vacuum rate applied. In one embodiment, the device has a modular design, wherein one or more removable inserts, preferably with different functionalities can be positioned between a base component and a collar component. The particular insert(s) chosen depend on the desired sample preparation or assay to be carried out. The insert(s) are stacked and are positioned between the base and collar as a unit, so that the stack within the manifold does not move during evacuation of the vacuum chamber. The consistent position of the insert(s) facilitates using vacuum sample processing with automated liquid handlers. | 2010-01-14 |
20100009461 | Npcil1 (Npc3) And Methods Of Identifying Ligands Thereof - The present invention provides human, rat and mouse NPCIL1 polypeptides and polynucleotides encoding the polypeptides. Methods for detecting ligands which bind to NPC1L1 and block intestinal cholesterol absorption are provided. Also included is a method of identifying ligands which bind to NPCILI using membranes derived from brush border membrane preparations. Compounds that bind to NPCILI can be used for inhibiting intestinal cholesterol absorption in a subject. | 2010-01-14 |
20100009462 | Timp-2 as target/marker of beta cell failure - The present invention relates to the monitoring of disease progression and diagnosis of beta-cell failure in diabetes by measuring levels of TIMP-2 in a liquid sample, and to screening for novel compounds for the prevention and/or treatment of diabetes. | 2010-01-14 |
20100009463 | Reagents for the detection of protein phosphorylation in signaling pathways - The invention discloses novel phosphorylation sites identified in signal transduction proteins and pathways, and provides phosphorylation-site specific antibodies and heavy-isotope labeled peptides (AQUA peptides) for the selective detection and quantification of these phosphorylated sites/proteins, as well as methods of using the reagents for such purpose. Among the phosphorylation sites identified are sites occurring in the following protein types: adaptor/scaffold proteins, adhesion/extracellular matrix protein, apoptosis proteins, calcium binding proteins, cell cycle regulation proteins, chaperone proteins, chromatin, DNA binding/repair/replication proteins, cytoskeletal proteins, endoplasmic reticulum or golgi proteins, enzyme proteins, G/regulator proteins, inhibitor proteins, motor/contractile proteins, phosphatase, protease, Ser/Thr protein kinases, protein kinase (Tyr)s, receptor/channel/cell surface proteins, RNA binding proteins, transcriptional regulators, tumor suppressor proteins, ubiquitan conjugating system proteins and proteins of unknown function. | 2010-01-14 |
20100009465 | METHOD FOR THE ANALYSIS OF CIRCULATING ANTIBODIES - There is provided a method for the analysis of circulating antibodies comprising the steps:
| 2010-01-14 |
20100009466 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - An interlayer insulating film ( | 2010-01-14 |
20100009467 | Novel magnetic tunnel junction (MTJ) to reduce spin transfer magnetization switching current - A MTJ that minimizes spin-transfer magnetization switching current (Jc) in a Spin-RAM to <1×10 | 2010-01-14 |
20100009468 | METHOD OF MANUFACTURE FOR SEMICONDUCTOR PACKAGE WITH FLOW CONTROLLER - A semiconductor package can comprise a die stack attached to a substrate, with bond wires electrically connecting the two. Often multiple die stacks are adhered to a single substrate so that several semiconductor packages can be manufactured at once. A molding compound flow controller is optimally associated with the substrate or semiconductor package at one or more various locations. Flow controllers can control or direct the flow of the molding compound during the encapsulation process. Flow controllers can be sized, shaped, and positioned in order to smooth out the flow of the molding compound, such that the speed of the flow is substantially equivalent over areas of the substrate containing dies and over areas of the substrate without dies. In this manner, defects such as voids in the encapsulation, wire sweeping, and wire shorts can be substantially avoided during encapsulation. | 2010-01-14 |
20100009469 | PLASMA DOPING METHOD AND APPARATUS - During a plasma discharging process, a laser beam having a certain exciting wavelength is applied to a surface of a process substrate, so as to measure, using scattered light, an impurity density and a crystal state on the surface of the process substrate. | 2010-01-14 |
20100009470 | WITHIN-SEQUENCE METROLOGY BASED PROCESS TUNING FOR ADAPTIVE SELF-ALIGNED DOUBLE PATTERNING - An apparatus for adaptive self-aligned dual patterning and method thereof. The method includes providing a substrate to a processing platform configured to perform an etch process and a deposition process and a metrology unit configured for in-vacuo critical dimension (CD) measurement. The in-vacuo CD measurement is utilized for feedforward adaptive control of the process sequence processing platform or for feedback and feedforward adaptive control of chamber process parameters. In one aspect, a first layer of a multi-layered masking stack is etched to form a template mask, an in-vacuo CD measurement of the template mask is made, and a spacer is formed, adjacent to the template mask, to a width that is dependent on the CD measurement of the template mask. | 2010-01-14 |
20100009471 | Adapter board and method for manufacturing same, probe card, method for inspecting semiconductor wafer, and method for manufacturing semiconductor device - An adapter board includes a package substrate having a first surface and a second surface and further including a board having wirings formed therein, pads disposed in the device side, and the pads disposed in the bump side, an insulating resin layer joined to the first surface, through holes formed in the positions corresponding to the pads in the insulating resin layer, vias formed in the through holes, and pads covering the through holes, wherein the pads are electrically coupled to the pads through the wirings, and the pads are electrically coupled to the pads through the vias. | 2010-01-14 |
20100009472 | Edge Exclusion Zone Patterning For Solar Cells And The Like - The edge profile (and optionally the physical and electrical characteristics) of a wafer is determined. Useful regions of the wafer in an edge exclusion zone may then be identified. A customized grid array layout is created specific to that wafer from an analysis of the edge profile, for example having a grid array with interconnection lines located within the useful portions of the edge exclusion zone. This working file is then used by a system, such as a digital lithography system, to form the grid array on the surface of the wafer. The grid array is specific to that wafer. Various aspects of the grid array may also be controlled in the process. For example, the line width, inter-line spacing, and position of the lines comprising the grid array are configurable on a wafer-by-wafer basis. | 2010-01-14 |
20100009473 | Method for manufacturing semiconductor device - A method for manufacturing a semiconductor device includes preparing two substrates having a first and a second surface and having first and second pads and a second testing-dedicated pad, the first pads in the first surface, the second pads in the second surface and arranged with an inter-pad distance that is larger than that for the first pad, and the second testing-dedicated pad being in the second surface; coupling a wafer with a apparatus, and inspecting the wafer with a probe card, the wafer having a LSI, which is an object of an inspection, the apparatus applicable signal to the LSI formed in the wafer, and measurable electrical characteristics of the LSI formed in the wafer, and the probe card having one of the two substrates; dicing the wafer into semiconductor elements containing the LSI; and packaging the semiconductor element over the other of the two substrates. | 2010-01-14 |
20100009474 | METHOD OF GROWING CARBON NANOTUBES AND METHOD OF MANUFACTURING FIELD EMISSION DEVICE USING THE SAME - A method of growing carbon nanotubes and a method of manufacturing a field emission device using the same is provided. The method of growing carbon nanotubes includes steps of preparing a substrate, forming a catalyst metal layer on the substrate to promote growing of carbon nanotubes, forming an inactivation layer on the catalyst metal layer to reduce the activity of the catalyst metal layer, and growing carbon nanotubes on a surface of the catalyst metal layer. Because the inactivation layer partially covers the catalyst metal layer, carbon nanotubes are grown on a portion of the catalyst metal layer that is not covered by the inactivation layer. Thus, density of the carbon nanotubes can be controlled. This method for growing carbon nanotubes can be used to make an emitter of a field emission device. The field emission device having carbon nanotube emitter made of this method has superior electron emission characteristics. | 2010-01-14 |
20100009475 | Disk Laser Including an Amplified Spontaneous Emission (ASE) Suppression Feature - A laser system may include a first portion of laser host material adapted for amplification of laser radiation and a second portion of laser host material surrounding the first portion which may be adapted for suppression of ASE. The first portion of laser host material and the second portion of laser host material may be respectively doped at a different predetermined concentration of laser ions. A heat exchanger may be provided to dissipate heat from the first portion and the second portion. | 2010-01-14 |
20100009476 | SUBSTRATE STRUCTURE AND METHOD OF REMOVING THE SUBSTRATE STRUCTURE - A method of removing a substrate structure is described. A plurality of pillars is formed on a substrate by using a photolithography etching process. A group III nitride semiconductor layer is grown on the plurality of pillars. The plurality of pillars is etched to separate the group III nitride semiconductor layer from the substrate by using a chemical etching process. | 2010-01-14 |
20100009477 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor light emitting device and a method of manufacturing the semiconductor light emitting device. The semiconductor light emitting device includes a substrate, at least two light emitting cells located on the substrate and formed by stacking semiconductor material layers, a reflection layer and a transparent insulating layer sequentially stacked between the light emitting cells, and a transparent electrode covering the upper surface of the light emitting cells. | 2010-01-14 |
20100009478 | IPS MODE LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR FABRICATING THEREOF - An IPS mode LCD device and a method for fabricating the same are disclosed. A switching device is formed at each unit pixel and then a passivation layer is formed thereon. A first concave pattern and a second concave pattern at each unit pixel by using one mask are formed, and a common electrode is formed in the first concave pattern and a pixel electrode is formed in the second concave pattern. Accordingly, the entire fabrication process is simplified. | 2010-01-14 |
20100009479 | LIQUID CRYSTAL DISPLAY AND THIN FILM TRANSISTOR PANEL THEREFOR - A thin film transistor panel for a liquid crystal display includes a substrate, a plurality of data lines formed over the substrate and extending in a first direction, and a plurality of gate lines formed over the substrate and extending in a second direction. The plurality of gate lines cross the plurality of data lines to form a plurality of pixel areas, each of the plurality of pixel areas having a multi-bent band shape. Each of a plurality of pixel electrodes are formed in a corresponding pixel area. | 2010-01-14 |
20100009480 | Method for fabricating liquid crystal display device - A thin film transistor including: an active layer on a substrate, the active layer having at least two unit channels; and source and drain electrodes on the active layer, wherein an interval D between each of the channels is larger than a unit channel width W. | 2010-01-14 |
20100009481 | METHOD FOR FABRICATING THIN FILM TRANSISTOR ARRAY SUBSTRATE - A method for fabricating a TFT array substrate includes following steps. A gate pattern and a first pad pattern are formed on a substrate. A gate insulation layer and a semiconductor layer covering the two patterns are sequentially formed. A patterned photoresist layer having different resist blocks is formed, and patterns and thicknesses of the resist blocks in different regions are adjusted. The semiconductor layer and the gate insulation layer above the first pad pattern are removed through performing an etching process and reducing a thickness of the patterned photoresist layer. After removing the patterned photoresist layer, a source pattern, a drain pattern, and a second pad pattern electrically connected to the first pad pattern are formed. A patterned passivation layer is formed on the gate insulation layer and has a second opening exposing the source pattern or the drain pattern and a third opening exposing the second pad pattern. | 2010-01-14 |
20100009482 | PHOTORESIST COMPOSITION, METHOD OF FORMING A METAL PATTERN, AND METHOD OF MANUFACTURING A DISPLAY SUBSTRATE USING THE SAME - A photoresist composition includes 5% to 50% by weight of an alkali-soluble resin, 0.5% to 30% by weight of a quinone diazide compound, 0.1% to 15 % by weight of a curing agent, and a remainder of an organic solvent. A method of forming a metal pattern includes coating a photoresist composition on a base substrate having a metal layer, and forming a first photoresist film. The photoresist composition includes 5% to 50% by weight of an alkali-soluble resin, 0.5% to 30% by weight of a quinone diazide compound, 0.1% to 15% by weight of a curing agent, and a remainder of an organic solvent. The first photoresist film is patterned, and forms a first photo pattern. The base substrate having the first photo pattern is heated, and forms a first baked pattern. The metal layer is patterned using the first baked pattern, and forms a metal pattern. | 2010-01-14 |
20100009483 | METHOD FOR FABRICATING A NITRIDE-BASED SEMICONDUCTOR LIGHT EMITTING DEVICE - An exemplary method includes the following steps. First, a substrate is provided. Second, a nitride-based multi-layered structure is epitaxially grown on the substrate. The multi-layered structure includes a first-type layer, an active layer, and a second-type layer arranged one on the other in that order along a direction away from the substrate. A crystal growth orientation of the multi-layered structure intersects with a <0001> crystal orientation thereof. Thirdly, the multi-layered structure is patterned to form a mesa structure thereof, wherein the first-type layer is partially exposed to form an exposed portion. The mesa structure has a top surface facing away from the substrate, and side surfaces adjacent to the top surface. Fourthly, a first-type electrode and a second-type electrode are formed in ohmic contact with the first-type layer and the second-type layer, respectively. Finally, the top and side surfaces of the patterned multi-layered structure are wet etched. | 2010-01-14 |
20100009484 | METHOD OF FABRICATING QUANTUM WELL STRUCTURE - In the method of fabricating a quantum well structure which includes a well layer and a barrier layer, the well layer is grown at a first temperature on a sapphire substrate. The well layer comprises a group III nitride semiconductor which contains indium as a constituent. An intermediate layer is grown on the InGaN well layer while monotonically increasing the sapphire substrate temperature from the first temperature. The group III nitride semiconductor of the intermediate layer has a band gap energy larger than the band gap energy of the InGaN well layer, and a thickness of the intermediate layer is greater than 1 nm and less than 3 nm in thickness. The barrier layer is grown on the intermediate layer at a second temperature higher than the first temperature. The barrier layer comprising a group III nitride semiconductor and the group III nitride semiconductor of the barrier layer has a band gap energy larger than the band gap energy of the well layer. | 2010-01-14 |
20100009485 | SEMICONDUCTOR LIGHT EMITTING DEVICE, METHOD OF MANUFACTURING SAME, AND OPTICAL MODULE - A semiconductor light emitting device capable of realizing a long life, and a method of manufacturing the same. The impurity concentration of hydrogen in the active layer is 3×10 | 2010-01-14 |
20100009486 | LIGHT EMITTING DIODE AND METHOD OF MAKING THE SAME - A light emitting diode (LED) and a method of making the same are disclosed. The present invention uses a metal layer of high conductivity and high reflectivity to prevent the substrate from absorbing the light emitted. This invention also uses the bonding technology of dielectric material thin film to replace the substrate of epitaxial growth with high thermal conductivity substrate to enhance the heat dissipation of the chip, thereby increasing the performance stability of the LED, and making the LED applicable under higher current. | 2010-01-14 |
20100009487 | ONO Spacer Etch Process to Reduce Dark Current - A method of forming a CMOS image sensor device. The method includes providing a semiconductor substrate having a P-type impurity characteristic. The semiconductor substrate includes a surface region. The method includes forming a gate oxide layer overlying the surface region and forming a first gate structure overlying a first portion of the gate oxide layer, the first gate structure has a top surface region and at least a side region. The method forms an N-type impurity region in a portion of the semiconductor substrate to form a photodiode device region from the N-type impurity region and the P-type impurity. The method includes forming a blanket spacer layer including an oxide on nitride on oxide structure overlying at least the first gate structure; and forming one or more spacer structures using the blanket spacer layer for the first gate structure while maintaining a portion of the oxide layer from the oxide on nitride on oxide overlying at least the photo-diode device region | 2010-01-14 |
20100009488 | METHOD TO FORM A PHOTOVOLTAIC CELL COMPRISING A THIN LAMINA - A very thin photovoltaic cell is formed by implanting gas ions below the surface of a donor body such as a semiconductor wafer. Ion implantation defines a cleave plane, and a subsequent step exfoliates a thin lamina from the wafer at the cleave plane. A photovoltaic cell, or all or a portion of the base or emitter of a photovoltaic cell, is formed within the lamina. In preferred embodiments, the wafer is affixed to a receiver before the cleaving step. Electrical contact can be formed to both surfaces of the lamina, or to one surface only. | 2010-01-14 |
20100009489 | METHOD AND SYSTEM FOR PRODUCING A SOLAR CELL USING ATMOSPHERIC PRESSURE PLASMA CHEMICAL VAPOR DEPOSITION - A process and system for producing a thin-film solar cell using atmospheric pressure plasma chemical vapor deposition is disclosed. A plasma at substantially atmospheric pressure is used to deposit P-type layers, intrinsic layers and N-type layers to form one or more P-N junctions for use in a solar cell. The surface onto which a P-N junction is deposited may be prepared or cleaned using the plasma at substantially atmospheric pressure. Alternatively, the plasma at substantially atmospheric pressure may be used to deposit other layers of the solar cell such as conductive layers in contact with a P-N junction. | 2010-01-14 |
20100009490 | METHOD FOR FABRICATING A SOLID-STATE IMAGING DEVICE - A method for manufacturing a solid-state imaging device. A solid-state image sensor is mounted on the semiconductor package support and electrically connected to first terminals and second terminals by bonding wires. The second terminals to which the bonding wires are connected are sealed with a sealing member. The optically-transparent member is thereafter disposed on the support member and the sealing member. The sealing member is cured to fix the optically transparent member. | 2010-01-14 |
20100009491 | Joined wafer, fabrication method thereof, and fabrication method of semiconductor devices - A method of fabricating a joined wafer has an exposure process which comprises a device formed-area exposure process of exposing by a stepper such that parts of the photosensitive adhesive layer formed over a surface of the transparent wafer or the device formed wafer are removed, the parts corresponding to the device formed areas when the transparent wafer and the device formed wafer are stuck together; and a wafer periphery exposure process of exposing such that a portion of the photosensitive adhesive layer over the periphery of the transparent wafer is left. | 2010-01-14 |
20100009492 | METHOD FOR PRODUCTION OF THIN SEMICONDUCTOR SOLAR CELLS AND INTEGRATED CIRCUITS - The invention relates to the formation of thin-film crystalline silicon using a zone-melting recrystallization process in which the substrate is a ceramic material. Integrated circuits and solar cells are fabricated in the recrystallized silicon thin film and lifted off the substrate. Following lift-off, these circuits and devices are self-sustained, lightweight and flexible and the released ceramic substrate can be reused making the device fabrication process cost effective. | 2010-01-14 |
20100009493 | Methods of manufacturing an image sensor - The method of manufacturing an image sensor includes providing a semiconductor substrate including a first pixel region, first forming a first pattern on the first pixel region, first performing a reflow of the first pattern to form a sub-micro lens on the first pixel region, second forming a second pattern on the sub-micro lens, and second performing a reflow of the second pattern to form a first micro lens covering the sub-micro lens. | 2010-01-14 |
20100009494 | Dye-Sensitized Solar Cell and Fabrication Method Thereof - Disclosed is a dye-sensitized solar cell with enhanced photoelectric conversion efficiency. The dye-sensitized solar cell includes a first electrode of a light transmission material, a second electrode facing the first electrode, and a dye-absorbed porous layer formed on the first electrode. An electrolyte is injected between the first and the second electrodes. The porous layer contains first and second materials differing from each other in conduction band energy level. | 2010-01-14 |
20100009495 | Anti-reflective device having an anti-reflective surface formed of silicon spikes with nano-tips - Described is a device having an anti-reflection surface. The device comprises a silicon substrate with a plurality of silicon spikes formed on the substrate. A first metallic layer is formed on the silicon spikes to form the anti-reflection surface. The device further includes an aperture that extends through the substrate. A second metallic layer is formed on the substrate. The second metallic layer includes a hole that is aligned with the aperture. A spacer is attached with the silicon substrate to provide a gap between an attached sensor apparatus. Therefore, operating as a Micro-sun sensor, light entering the hole passes through the aperture to be sensed by the sensor apparatus. Additionally, light reflected by the sensor apparatus toward the first side of the silicon substrate is absorbed by the first metallic layer and silicon spikes and is thereby prevented from being reflected back toward the sensor apparatus. | 2010-01-14 |
20100009496 | Structuring Device for Structuring Plate-Like Elements, in Particular Thin-Film Solar Modules - A structuring device is for structuring a plate-like element. A solar module and/or a thin-film solar module comprises a plurality of structuring tools which are configured respectively for introducing a track into the plate-like element, characterised by a first structuring unit which has a plurality of these structuring tools, at least two structuring tools of this first structuring unit being configured such that two first tracks which extend parallel to each other and at a constant spacing from each other can be introduced into the plate-like element with said structuring tools (first track group SG | 2010-01-14 |
20100009497 | PERFORMANCE IMPROVEMENTS OF OFETS THROUGH USE OF FIELD OXIDE TO CONTROL INK FLOW - An OFET includes a thick dielectric layer with openings in the active region of a transistor. After the field dielectric layer is formed, semiconductor ink is dropped in the active region cavities in the field dielectric layer, forming the semiconductor layer. The ink is bounded by the field dielectric layer walls. After the semiconductor layer is annealed, dielectric ink is dropped into the same cavities. As with the semiconductor ink, the field dielectric wall confines the flow of the dielectric ink. The confined flow causes the dielectric ink to pool into the cavity, forming a uniform layer within the cavity, and thereby decreasing the probability of pinhole shorting. After the dielectric is annealed, a gate layer covers the active region thereby completing a high performance OFET structure. | 2010-01-14 |
20100009498 | PLANAR INTERCONNECT STRUCTURE FOR HYBRID CIRCUITS - Described herein is an electronic device in which one or more planar interconnect structure are interposed between two substrates each incorporating a hybrid circuit. The planar interconnect structure has a plurality of conductive traces formed on one of its faces for electrically connecting sets of interconnection points of each of the hybrid circuits. | 2010-01-14 |
20100009499 | STACKED MICROELECTRONIC LAYER AND MODULE WITH THREE-AXIS CHANNEL T-CONNECTS - A method for interconnecting stacked layers containing integrated circuit die and a device built from the method is disclosed. The stacked layers are bonded together to form a module whereby individual I/O pads of the integrated circuit die are rerouted to at least one edge of the module. The rerouted leads terminate at the edge. Channels are formed in a surface of the module or on the surface of a layer whereby the rerouted leads are disposed within the channel. The entire surface of the edge or layer is metalized and a predetermined portion of the metalization removed such that the rerouted leads within each channel are electrically connected to each other. | 2010-01-14 |
20100009500 | Aluminum Leadframes for Semiconductor QFN/SON Devices - A post-mold plated semiconductor device has an aluminum leadframe ( | 2010-01-14 |
20100009501 | Packaging structure, method for manufacturing the same, and method for using the same - A packaging structure applied for a surface mounting process, comprising: a chip module having a packaging surface; and a pre-cured layer formed on the packaging surface of the chip module. As above-mentioned, the structure is employed for protecting the external surface of the wafer. The pre-cured layer is formed on pre-curing a gluing material and the gluing material is uniformly filled with the space between the connecting protrusions on the packaging surface. The pre-cured later is post-curing in a connecting process for mounting the connecting protrusions to the substrate so that the connecting strength is improved. Moreover, the rate of the packaging process is increasing. | 2010-01-14 |
20100009502 | Semiconductor Fabrication Process Including An SiGe Rework Method - A method for fabricating a semiconductor device includes forming an SiGe region. The SiGe region can be an embedded source and drain region, or a compressive SiGe channel layer, or other SiGe regions within a semiconductor device. The SiGe region is exposed to an SC1 solution and excess surface portions of the SiGe region are selectively removed. The SC1 etching process can be part of a rework method in which overgrowth regions of SiGe are selectively removed by exposing the SiGe to and SC1 solution maintained at an elevated temperature. The etching process is carried out for a period of time sufficient to remove excess surface portions of SiGe. The SC1 etching process can be carried out at elevated temperatures ranging from about 25° C. to about 65° C. | 2010-01-14 |
20100009503 | METHOD OF FORMING DIELECTRIC LAYER ABOVE FLOATING GATE FOR REDUCING LEAKAGE CURRENT - A method of fabricating a memory system is disclosed that includes a set of non-volatile storage elements. The method includes forming a floating gate having a top and at least two sides. A dielectric cap is formed at the top of the floating gate. An inter-gate dielectric layer is formed around the at least two sides of the floating gate and over the top of the dielectric cap. A control gate is formed over the top of the floating gate, the inter-gate dielectric layer separates the control gate from the floating gate. In one aspect, forming the dielectric cap includes implanting oxygen in the top of the floating gate and heating the floating gate to form the dielectric cap from the implanted oxygen and silicon from which the floating gate was formed. | 2010-01-14 |
20100009504 | SYSTEMS AND METHODS FOR A HIGH DENSITY, COMPACT MEMORY ARRAY - A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi-level charge techniques can be used to increase the number of bit per cell and achieve further increased density for the memory array. | 2010-01-14 |
20100009505 | SEMICONDUCTOR DEVICE HAVING A VERTICAL TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having a vertical transistor comprises a silicon substrate; a drain region, a channel region and a source region vertically stacked on the silicon substrate; a buried type bit line formed under the drain region in the silicon substrate to contact with the drain region and to extend in one direction; and gates respectively formed on both side walls of the stacked drain region, channel region and source region. | 2010-01-14 |
20100009506 | DOPANT IMPLANTATION METHOD AND INTEGRATED CIRCUITS FORMED THEREBY - A method of forming a dopant implant region in a MOS transistor device having a dopant profile having a target dopant concentration includes implanting a first concentration of dopants into a region of a substrate, where the first concentration of dopants is less than the target dopant concentration, and without annealing the substrate after the implanting step, performing at least one second implanting step to implant at least one second concentration of dopants into the region of the substrate to bring the dopant concentration in the region to the target dopant concentration. | 2010-01-14 |
20100009507 | METHOD OF CONSTRUCTING CMOS DEVICE TUBS - The present invention provides a method of fabricating an integrated circuit comprising at least one bipolar transistor and at least one field effect transistor. The method includes implanting a dopant species of a first type in a semiconductor layer that is doped with a dopant of a second type opposite the first type to form at least one sinker that contacts at least one collector of said at least one bipolar transistor. The method also includes applying heat to cause the dopant species to diffuse outwards to form at least one doped extension of said at least one sinker and forming said at least one field effect transistor in the doped extension. | 2010-01-14 |
20100009508 | Methods of fabricating stack type capacitors of semiconductor devices - Provided are methods of fabricating capacitors of semiconductor devices, the methods including: forming a lower electrode on a semiconductor substrate, performing a pre-process operation on the lower electrode for suppressing deterioration of the lower electrode during a process, forming a dielectric layer on the lower electrode using a source gas and an ozone gas, and forming an upper electrode on the dielectric layer, wherein the pre-process operation and the forming of the dielectric layer may be performed in one device capable of atomic layer deposition. | 2010-01-14 |
20100009509 | DUAL-DAMASCENE PROCESS TO FABRICATE THICK WIRE STRUCTURE - A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer. | 2010-01-14 |
20100009510 | Method of manufacturing semiconductor device - A method of manufacturing a semiconductor device including implanting an impurity ion into a predetermined region of a semiconductor layer using a resist film as a mask, wherein in case when a mask data ratio for implanting the impurity ion only into the predetermined region in the resist film is less than a first reference value, a dummy ion implantation region, into which the impurity ion is also implanted in addition to the predetermined region, is added in a region other than the predetermined region so that a mask data ratio becomes larger than a second reference value which is equal to or larger than the first reference value, the mask data ratio indicating a ratio of an opening with respect to an entire region of a reticle region corresponding to the reticle. | 2010-01-14 |
20100009511 | PROGRAMMABLE CAPACITOR ASSOCIATED WITH AN INPUT/OUTPUT PAD - The present invention provides a method and apparatus for a programmable capacitor associated with an input/output pad in the semiconductor device. The apparatus includes a semiconductor die having an upper surface, a first capacitor deployed above the upper surface of the semiconductor die, a separation layer deployed above the first capacitor, and a bond pad deployed above the separation layer such that at least a portion of the bond pad lies above the first capacitor. | 2010-01-14 |
20100009512 | METHODS OF FORMING A PLURALITY OF CAPACITORS - A method of forming a plurality of capacitors includes forming a plurality of individual capacitor electrodes using two masking steps. An earlier of the two masking steps is used to form an array of first openings over a plurality of storage node contacts. A later of the two masking steps is used to form an array of second openings received partially over and partially offset from the array of first openings. Overlapping portions of the first and second openings are received over the storage node contacts. After both of the two masking steps, conductive material of the individual capacitor electrodes is deposited into the overlapping portions of each of the first and second openings. The individual capacitor electrodes are incorporated into a plurality of capacitors. Other aspects and implementations are contemplated. | 2010-01-14 |
20100009513 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes forming a gate insulating film on a semiconductor substrate, forming a gate electrode film on the gate insulating film, and forming a plurality of trenches by etching the gate electrode film, the gate insulating film and the semiconductor substrate so that an upper portion of the gate electrode film includes a tapered side surface and a lower portion of the gate electrode film includes a side surface perpendicular to a surface of the semiconductor substrate. The method also includes forming an element isolation insulating film in the trenches, including forming a deposition type insulating film in the trenches and forming a coating type insulating film on the deposition type insulating film, and removing the element isolation insulating film by a dry etching method so that the tapered side surfaced of the gate electrode film is exposed and the perpendicular side surface of the gate electrode film is covered by the element isolation insulating film. | 2010-01-14 |
20100009514 | METHOD OF FABRICATING MICRO-VERTICAL STRUCTURE - A method of fabricating a micro-vertical structure is provided. The method includes bonding a second crystalline silicon (Si) substrate onto a first crystalline Si substrate by interposing an insulating layer pattern and a cavity, etching the second crystalline Si substrate using a deep reactive ion etch (DRIE) process along a [111] crystal plane vertical to the second crystalline Si substrate, and etching an etched vertical surface of the second crystalline Si substrate using a crystalline wet etching process to improve the surface roughness and flatness of the etched vertical surface. As a result, no morphological defects occur on the etched vertical surface. Also, footings do not occur at an etch end-point due to the insulating layer pattern. In addition, the micro-vertical structure does not float in the air but is fixed to the first crystalline Si substrate, thereby facilitating subsequent processes. | 2010-01-14 |
20100009515 | LASER LIFT-OFF METHOD - The present invention discloses a laser lift-off method, which applies to lift off a transient substrate from an epitaxial layer grown on the transient substrate after a support substrate having an adhesion metal layer is bonded to the epitaxial layer. Firstly, the epitaxial layer is etched to define separation channels around each chip section, and the epitaxial layer between two separation channels is not etched but preserved to form a separation zone. Each laser illumination area only covers one illuminated chip section, the separation channels surrounding the illuminated chip section, and the separation zones surrounding the illuminated chip section. Thus, the adhesion metal layer on the separation channels is only heated once. Further, the outward stress generated by the illuminated chip section is counterbalanced by the outward stress generated by the illuminated separation zones, and the stress-induced structural damage on the chip section is reduced. | 2010-01-14 |
20100009516 | METHOD FOR GROWTH OF GaN SINGLE CRYSTAL, METHOD FOR PREPARATION OF GaN SUBSTRATE, PROCESS FOR PRODUCING GaN-BASED ELEMENT, AND GaN-BASED ELEMENT - A GaN-based thin film (thick film) is grown using a metal buffer layer grown on a substrate. (a) A metal buffer layer ( | 2010-01-14 |
20100009517 | Process for Inhibiting Corrosion and Removing Contaminant from a Surface During Wafer Dicing and Composition Useful Therefor - Adherence of contaminant residues or particles is suppressed, corrosion of exposed surfaces is substantially reduced or eliminated during the process of dicing a wafer by sawing. A fluoride-free aqueous composition comprising a dicarboxylic acid and/or salt thereof; a hydroxycarboxylic acid and/or salt thereof or amine group containing acid, a surfactant and deionized water is employed. | 2010-01-14 |
20100009518 | Particle Free Wafer Separation - A method for singulating semiconductor wafers is disclosed. A preferred embodiment comprises forming scrub lines on one side of the wafer and filling the scrub lines with a temporary fill material. The wafer is then thinned by removing material from the opposite side of the wafer from the scrub lines, thereby exposing the temporary fill material on the opposite side. The temporary fill material is then removed, and the individual die are removed from the wafer. | 2010-01-14 |
20100009519 | METHOD OF THINNING A SEMICONDUCTOR WAFER - A method for manufacturing a thin semiconductor wafer. A semiconductor wafer is thinned from its backside followed by the formation of a cavity in a central region of the backside of the semiconductor wafer. Forming the cavity also forms a ring support structure in a peripheral region of the semiconductor wafer. An electrically conductive layer is formed in at least the cavity. The front side of the semiconductor wafer is mated with a tape that is attached to a film frame. The ring support structure of the semiconductor wafer is thinned to form the thinned semiconductor wafer. A backside tape is coupled to semiconductor wafer and to the film frame and the tape coupled to the front side of the semiconductor wafer is removed. The thinned semiconductor wafer is singulated. | 2010-01-14 |
20100009520 | WAFER PROCESSING METHOD FOR IMPROVING GETTERING CAPABILITIES OF WAFERS MADE THEREFROM - A wafer processing method for improving gettering capabilities of wafers made therefrom is presented. The method includes the steps of preparing, annealing and ion-implanting. The preparing step involves preparing the wafer from a silicon ingot. The annealing step involves forming first gettering sites in both sides of the wafer by annealing the wafer. The ion-implanting step involves forming second gettering sites in a back side of the wafer in which the first gettering sites are already formed. | 2010-01-14 |
20100009521 | METHOD OF PRODUCING SEMICONDUCTOR WAFER - There is provided a production method in which the beveling step conducted for preventing the cracking or chipping in a raw wafer during the grinding can be omitted when the raw wafer cut out from a crystalline ingot is processed into a double-side mirror-finished semiconductor wafer and a semiconductor wafer can be obtained cheaply by shortening the whole of the production steps for the semiconductor wafer and decreasing the machining allowance of silicon material in the semiconductor wafer to reduce the kerf loss of the semiconductor material as compared with the conventional method. | 2010-01-14 |
20100009522 | Method for Forming Chalcogenide Switch with Crystallized Thin Film Diode Isolation - A three-dimensional memory array formed of one or more two-dimensional memory arrays of one-time programmable memory elements arranged in horizontal layers and stacked vertically upon one another; and a two-dimensional memory array of reprogrammable phase change memory elements stacked on the one or more two-dimensional memory arrays as the top layer of the three-dimensional memory array. | 2010-01-14 |
20100009523 | MASK AND METHOD OF FABRICATING A POLYSILICON LAYER USING THE SAME - A mask includes a primary opaque pattern and a number of clusters of secondary opaque patterns. The primary opaque pattern defines a number of strip transparent slits whose extending directions are substantially the same. The clusters of the secondary opaque patterns are connected to the primary opaque pattern, and each of the clusters of the secondary opaque patterns is disposed in one of the transparent slits, respectively. Each of the clusters of the secondary opaque patterns includes a number of secondary opaque patterns, and extending directions of at least a portion of the secondary opaque patterns and the extending directions of the transparent slits together form included angles that are not equal to about 90°. | 2010-01-14 |
20100009524 | METHOD FOR IMPROVING SEMICONDUCTOR SURFACES - A semiconductor fabrication method. The method includes providing a semiconductor substrate, wherein the semiconductor substrate includes a semiconductor material. Next, a top portion of the semiconductor substrate is removed. Next, a first semiconductor layer is epitaxially grown on the semiconductor substrate, wherein a first atom percent of the semiconductor material in the first semiconductor layer is equal to a certain atom percent of the semiconductor material in the semiconductor substrate. | 2010-01-14 |
20100009525 | METHOD INCLUDING PRODUCING A MONOCRYSTALLINE LAYER - A method including producing a monocrystalline layer is disclosed. A first lattice constant on a monocrystalline substrate has a second lattice constant at least in a near-surface region. The second lattice constant is different from the first lattice constant. Lattice matching atoms are implanted into the near-surface region. The near-surface region is momentarily melted. A layer is epitaxially deposited on the near-surface region that has solidified in monocrystalline fashion. | 2010-01-14 |
20100009526 | FABRICATION METHOD AND FABRICATION APPARATUS OF GROUP III NITRIDE CRYSTAL SUBSTANCE - A fabrication method of a group III nitride crystal substance includes the steps of cleaning the interior of a reaction chamber by introducing HCl gas into the reaction chamber, and vapor deposition of a group III nitride crystal substance in the cleaned reaction chamber. A fabrication apparatus of a group III nitride crystal substance includes a configuration to introduce HCl gas into the reaction chamber, and a configuration to grow a group III nitride crystal substance by HVPE. Thus, a fabrication method of a group III nitride crystal substance including the method of effectively cleaning deposits adhering inside the reaction chamber during crystal growth, and a fabrication apparatus employed in the fabrication method are provided. | 2010-01-14 |
20100009527 | INTEGRATED CIRCUIT SYSTEM EMPLOYING SINGLE MASK LAYER TECHNIQUE FOR WELL FORMATION - A method for manufacturing an integrated circuit system that includes: providing a substrate; forming a mask layer over the substrate; implanting a first well through an opening in the mask layer into the substrate; and implanting a second well through the mask layer and the opening via a single implant into the substrate. | 2010-01-14 |
20100009528 | Method for Rapid Thermal Treatment Using High Energy Electromagnetic Radiation of a Semiconductor Substrate for Formation of Dielectric Films - A method for fabricating semiconductor devices, e.g., SONOS cell. The method includes providing a semiconductor substrate (e.g., silicon wafer, silicon on insulator) having a surface region, which has a native oxide layer. The method includes treating the surface region to a wet cleaning process to remove a native oxide layer from the surface region. In a specific embodiment, the method includes subjecting the surface region to an oxygen bearing environment and subjecting the surface region to a high energy electromagnetic radiation having wavelengths ranging from about 300 to about 800 nanometers for a time period of less than 10 milli-seconds to increase a temperature of the surface region to greater than 1000 Degrees Celsius. In a specific embodiment, the method causes formation of an oxide layer having a thickness of less than 10 Angstroms. In a preferred embodiment, the oxide layer is substantially free from pinholes and other imperfections. In a specific embodiment, the oxide layer is a gate oxide layer. | 2010-01-14 |
20100009529 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - Provided is a manufacturing method of a semiconductor device, which comprises forming a film stack of a gate insulating film, a charge storage film, insulating film, polysilicon film, silicon oxide film, silicon nitride film and cap insulating film over a semiconductor substrate; removing the film stack by photolithography and etching from a low breakdown voltage MISFET formation region and a high breakdown voltage MISFET formation region; forming gate insulating films, polysilicon film and cap insulating film over the semiconductor substrate, forming a gate electrode in the low breakdown voltage MISFET formation region and high breakdown voltage MISFET formation region, and then forming a gate electrode in a memory cell formation region. By the manufacturing technology of a semiconductor device for forming the gate electrodes of a first MISFET and a second MISFET in different steps, the present invention makes it possible to provide the first MISFET and the second MISFET each having improved reliability. | 2010-01-14 |
20100009530 | SEMICONDUCTOR DEVICE FABRICATION METHOD - A semiconductor device fabrication method including the steps of: forming an interlayer insulating film on a substrate; forming an opening in the interlayer insulating film; forming an alloy layer containing manganese and copper to cover the inner surface of the opening; forming a first copper layer of a material containing primarily copper on the alloy layer to fill the opening; forming, on the first copper layer, a second copper layer of a material containing primarily copper and a higher concentration of oxygen, carbon or nitrogen than the first copper layer; heating the substrate on which the second copper layer has been formed; and removing the second copper layer. | 2010-01-14 |
20100009531 | METHODS OF FORMING A CONTACT STRUCTURE - In a method of forming a contact structure, a first insulation layer including a first contact hole is formed on a substrate. A metal layer including tungsten is formed to fill the first contact hole. A planarization process is performed on the metal layer until the first insulation layer is exposed to form a first contact. A second contact is grown from the first contact. The second contact is formed without performing a photolithography process and an etching process to prevent misalignments. | 2010-01-14 |
20100009532 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MANUFACTURING APPARATUS THEREFOR - Provided is a manufacturing method for improving the reliability of a semiconductor device having a back electrode. After formation of semiconductor elements on the surface of a silicon substrate, the backside surface thereof, which is opposite to the element formation surface, is subjected to the following steps in a processing apparatus. After deposition of a first metal film over the backside surface of the silicon substrate in a first chamber, it is heat treated to form a metal silicide film. Then, a nickel film is deposited in a third chamber, followed by deposition of an antioxidant conductor film in a second chamber. Heat treatment for alloying the first metal film and the silicon substrate is performed at least prior to the deposition of the nickel film. The first chamber has therefore a mechanism for depositing the first metal film and a lamp heating mechanism. | 2010-01-14 |
20100009533 | Conformal Films on Semiconductor Substrates - A layer of diffusion barrier or seed material is deposited on a semiconductor substrate having a recessed feature. The method may include a series of new deposition cycles, for example, a first net deposition cycle and a second net deposition cycle. The first net deposition cycle includes depositing a first deposited amount of the diffusion barrier or seed material and etching a first etched amount of the diffusion barrier or seed material. The second net deposition cycle including depositing a second deposited amount of the diffusion barrier or seed material and etching a second etched amount of the diffusion barrier or seed material. At least one of the process parameters of the first cycle differs from that of the second allows providing a graded deposition effects to reduce a risk of damaging any under layers and dielectric. A deposited layer of diffusion barrier or seed material is generally more conformal. | 2010-01-14 |
20100009534 | METHOD FOR PATTERNING A SEMICONDUCTOR DEVICE - A method for patterning a semiconductor device can include forming a conductive layer over a semiconductor substrate; alternatively forming positive photoresists and negative photoresists over the conductive layer, forming a plurality of first conductive lines by selectively removing a portion of the conductive layer using the positive photoresist and the negative photoresist as masks; forming an oxide film over the semiconductor substrate including the first conductive lines and the conductive layer; performing a planarization process over the oxide film using the uppermost surface of the first conductive line as a target; removing the plurality of first conductive lines using the oxide film as a mask; forming a plurality if trenches in the semiconductor substrate and removing a portion of the oxide film to expose the uppermost surface of the conductive layer; and then forming a plurality of second conductive lines by removing the exposed conductive layer using the oxide film as a mask. | 2010-01-14 |
20100009535 | METHODS AND SYSTEMS FOR BARRIER LAYER SURFACE PASSIVATION - This invention pertains to methods and systems for fabricating semiconductor devices. One aspect of the present invention is a method of depositing a gapfill copper layer onto a barrier layer for semiconductor device metallization. In one embodiment, the method includes forming the barrier layer on a surface of a substrate and subjecting the barrier layer to a process condition so as to form a removable passivated surface on the barrier layer. The method further includes removing the passivated surface from the barrier layer and depositing the gapfill copper layer onto the barrier layer. Another aspect of the present invention is an integrated system for depositing a copper layer onto a barrier layer for semiconductor device metallization. In one embodiment, the integrated system comprises at least one process module configured for barrier layer deposition and passivated surface formation and at least one other process module configured for passivated surface removal and deposition of copper onto the barrier layer. The system further includes at least one transfer module coupled so that the substrate can be transferred between the modules substantially without exposure to an oxide-forming environment. | 2010-01-14 |
20100009536 | MULTILAYER LOW REFLECTIVITY HARD MASK AND PROCESS THEREFOR - A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN). | 2010-01-14 |
20100009537 | METHOD OF POLISHING NICKEL-PHOSPHOROUS - The invention is directed to a method of chemically-mechanically polishing a a surface of a substrate, comprising contacting a surface of a substrate comprising nickel-phosphorous with a chemical-mechanical polishing composition comprising wet-process silica, an agent that oxidizes nickel-phosphorous, and an aminopolycarboxylic acid, wherein the polishing composition has a pH of about 1 to about 5, and abrading at least a portion of the nickel-phosphorous to polish the substrate. | 2010-01-14 |
20100009538 | Silicon nitride polishing liquid and polishing method - A silicon nitride polishing liquid for chemical mechanical polishing of a body to be polished in a planarization process for manufacturing of a semiconductor integrated circuit, the body to be polished including at least a first layer containing silicon nitride and a second layer containing at least one silicon-including material selected from the group consisting of polysilicon, modified polysilicon, silicon oxide, silicon carbide, and silicon oxycarbide, the silicon nitride polishing liquid having a pH of 2.5 to 5.0, and including (a) colloidal silica, (b) an organic acid that has at least one sulfonic acid group or phosphonic acid group in the molecular structure thereof and functions as a polishing accelerator for silicon nitride, and (c) water. | 2010-01-14 |
20100009539 | CERIUM OXIDE POWDER, METHOD FOR PREPARING THE SAME, AND CMP SLURRY COMPRISING THE SAME - Disclosed is cerium oxide powder for a CMP abrasive, which can improve polishing selectivity of a silicon oxide layer to a silicon nitride layer and/or within-wafer non-uniformity (WIWNU) during chemical mechanical polishing in a semiconductor fabricating process. More particularly, the cerium oxide powder is obtained by using cerium carbonate having a hexagonal crystal structure as a precursor. Also, CMP slurry comprising the cerium oxide powder as an abrasive, and a shallow trench isolation method for a semiconductor device using the CMP slurry as polishing slurry are disclosed. | 2010-01-14 |
20100009540 | POLISHING COMPOUND, ITS PRODUCTION PROCESS AND POLISHING METHOD - A polishing compound for chemical mechanical polishing of a substrate, which comprises (A) abrasive grains, (B) an aqueous medium, (C) tartaric acid, (D) trishydroxymethylaminomethane and (E) at least one member selected from the group consisting of malonic acid and maleic acid, and more preferably, which further contains a compound having a function to form a protective film on the wiring metal surface to prevent dishing at the wiring metal portion, such as benzotriazole. By use of this polishing compound, the copper wirings on the surface of a semiconductor integrated circuit board can be polished at a high removal rate while suppressing formation of scars as defects in a polishing step. Particularly in a first polishing step of polishing copper wirings having a film made of tantalum or a tantalum compound as a barrier film, excellent selectivity will be obtained, dishing and erosion due to polishing are less likely to occur, and an extremely high precision flat surface of a semiconductor integrated circuit board can be obtained. | 2010-01-14 |
20100009541 | Process for Adjusting the Size and Shape of Nanostructures - In accordance with the invention, a lateral dimension of a microscale device on a substrate is reduced or adjusted by the steps of providing the device with a soft or softened exposed surface; placing a guiding plate adjacent the soft or softened exposed surface; and pressing the guiding plate onto the exposed surface. Under pressure, the soft material flows laterally between the guiding plate and the substrate. Such pressure induced flow can reduce the lateral dimension of line spacing or the size of holes and increase the size of mesas. The same process also can repair defects such as line edge roughness and sloped sidewalls. This process will be referred to herein as pressed self-perfection by liquefaction or P-SPEL. | 2010-01-14 |
20100009542 | SUBSTRATE PROCESSING METHOD - A substrate processing method that forms an opening, which has a size that fills the need for downsizing a semiconductor device and is to be transferred to an amorphous carbon film, in a photoresist film of a substrate to be processed. Deposit is accumulated on a side wall surface of the opening in the photoresist film using plasma produced from a deposition gas having a gas attachment coefficient S of 0.1 to 1.0 so as to reduce the opening width of the opening. | 2010-01-14 |
20100009543 | Method For Manufacturing Semiconductor Device - Disclosed is a method for manufacturing a semiconductor device. The method includes sequentially depositing a polishing stop film and a mask oxide film on a semiconductor substrate, forming a photosensitive film pattern on the mask oxide film to expose a device isolation region, sequentially etching the mask oxide film and the polishing stop film under first and second etching process conditions using the photosensitive film pattern as a mask to form a hard mask pattern, and etching the semiconductor substrate under third etching process conditions using the hard mask pattern to form a trench for a device-isolation film. Advantageously, the method simplifies an overall process without using a spacer and secures a desired margin in the subsequent processes, e.g., gap-filling an insulating material in the trench and chemical mechanical polishing of the insulating material. | 2010-01-14 |
20100009544 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A coating solution of SOG is applied on a silicon oxynitride film ( | 2010-01-14 |
20100009545 | Methods of Fabricating Oxide Layers on Silicon Carbide Layers Utilizing Atomic Oxygen - Methods of forming oxide layers on silicon carbide layers are disclosed, including placing a silicon carbide layer in a chamber such as an oxidation furnace tube that is substantially free of metallic impurities, heating an atmosphere of the chamber to a temperature of about 500° C. to about 1300° C., introducing atomic oxygen in the chamber, and flowing the atomic oxygen over a surface of the silicon carbide layer to thereby form an oxide layer on the silicon carbide layer. In some embodiments, introducing atomic includes oxygen providing a source oxide in the chamber and flowing a mixture of nitrogen and oxygen gas over the source oxide. The source oxide may comprise aluminum oxide or another oxide such as manganese oxide. Some methods include forming an oxide layer on a silicon carbide layer and annealing the oxide layer in an atmosphere including atomic oxygen. | 2010-01-14 |
20100009546 | Aminosilanes for Shallow Trench Isolation Films - The present invention is a process for spin-on deposition of a silicon dioxide-containing film under oxidative conditions for gap-filling in high aspect ratio features for shallow trench isolation used in memory and logic circuit-containing semiconductor substrates, such as silicon wafers having one or more integrated circuit structures contained thereon, comprising the steps of:
| 2010-01-14 |
20100009547 | LASER WORKING METHOD - An object to be processed is restrained from warping at the time of laser processing. A modified region M | 2010-01-14 |
20100009548 | METHOD FOR HEAT-TREATING SILICON WAFER - Provided is a heat treatment method wherein generation of slip dislocation in silicon wafer RTP is suppressed, in order to solve a problem of not sufficiently suppressing generation of slip dislocation of silicon wafers in conventional RTP. A step is provided for suspending temperature rising for 10 seconds or longer at a temperature in a range of over 700° C. to below 950° C., so as to prevent generation of slip dislocation during rapid heating, at least at a silicon wafer portion that contacts with a supporting section of a rapid heating apparatus or at a portion on the outermost circumference section of the silicon wafer. | 2010-01-14 |
20100009549 | WAFER TREATING METHOD - A wafer treating method includes the steps of irradiating a wafer, provided with devices on the face side, from the back side with a laser beam capable of being transmitted through the wafer, while converging the laser beam to a predetermined depth, so as to form a denatured layer between the face side and the back side of the wafer, and separating the wafer into a back-side wafer on the back side relative to the denatured layer and a face-side wafer on the face side relative to the denatured layer. The denatured layer remaining in the face-side wafer is removed, and the face-side wafer is finished to a predetermined thickness, whereby the devices constituting the face-side wafer are finished into products, and the back-side wafer is recycled. | 2010-01-14 |
20100009550 | METHOD AND APPARATUS FOR MODIFYING INTEGRATED CIRCUIT BY LASER - [PROBLEMS] To provide a method and an apparatus for cutting a conductive link of a redundant circuit in a semiconductor circuit. | 2010-01-14 |
20100009551 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A p-n junction is formed at the interface of a low-concentration n-type impurity layer and a p-type diffusion region in the vicinity of the upper major surface of an n-type semiconductor substrate of a semiconductor device. A mask composed of an absorber is placed on the upper major surface of the semiconductor device, and electron beams are radiated. Thereafter, heat treatment is conducted. As a result, the peak of the crystal lattice defect densities is present in the vicinity of the upper major surface of the n-type semiconductor substrate, and the crystal lattice defect densities are decreasingly distributed toward the lower major surface. Thereby, a semiconductor device that can minimize the variation of the breakdown voltage characteristics of the p-n junction of the diode, and can control the optimum carrier lifetime can be obtained. | 2010-01-14 |
20100009552 | Connector - A connector adequately detects a state of an electronic component such as a memory card which is fitted in the connector by way of insertion, even when scrapes of a housing of the electronic component are produced due to insertion and removal of the electronic component which is fitted. In this connector ( | 2010-01-14 |
20100009553 | CONNECTOR ASSEMBLY - A connector assembly includes a substrate and a connector mounted thereon. The substrate defines a cutout. The connector includes a housing and an array of terminals. The housing has a pair of guiding arms and a cross bar bridged between the guiding arms to collectively define a receiving space therebetween corresponding to the cutout. The array of terminals is assembled on the cross bar and electrically connected to the substrate. | 2010-01-14 |
20100009554 | Microelectronic interconnect element with decreased conductor spacing - A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines. | 2010-01-14 |
20100009555 | ELECTRICAL CONNECTOR TRANSMITTING HIGH FREQUENCY SIGNAL - An electrical connector includes an insulating housing ( | 2010-01-14 |
20100009556 | ELECTRICAL CONNECTOR ASSEMBLY - An electrical connector assembly ( | 2010-01-14 |
20100009557 | ELECTRICAL CONNECTOR - An electrical connector ( | 2010-01-14 |
20100009558 | ELECTRICAL CONNECTOR HAVING HEAT SINK WITH LARGE DISSIPATION AREA - An electrical connector ( | 2010-01-14 |
20100009559 | ELECTRCAL CONNECTOR FOR RECEIVING A CPU - An electrical connector for receiving a CPU ( | 2010-01-14 |