02nd week of 2021 patent applcation highlights part 59 |
Patent application number | Title | Published |
20210013086 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE - A semiconductor device includes: a substrate; an ion-implanted silicon layer disposed in the substrate; a first insulator layer disposed over the ion-implanted silicon layer; an active device disposed over the first insulator layer; and a conductive via configured to penetrate the first insulator layer for coupling the ion-implanted silicon layer and the active device. | 2021-01-14 |
20210013087 | PRODUCING A BURIED CAVITY IN A SEMICONDUCTOR SUBSTRATE - In a method for producing a buried cavity in a semiconductor substrate, trenches are produced in a surface of a semiconductor substrate down to a depth that is greater than cross-sectional dimensions of the respective trench in a cross section perpendicular to the depth, wherein a protective layer is formed on sidewalls of the trenches. Isotropic etching through bottom regions of the trenches is carried out. After carrying out the isotropic etching, the enlarged trenches are closed by applying a semiconductor epitaxial layer to the surface of the semiconductor substrate. | 2021-01-14 |
20210013088 | THREE-DIMENSIONAL MEMORY DEVICES WITH DEEP ISOLATION STRUCTURES - A method for forming a three-dimensional memory device includes forming, on a first side of a first substrate, a peripheral circuitry including first and second peripheral devices, a first interconnect layer, and a shallow trench isolation (STI) structure between the first and second peripheral devices, and forming, on a second substrate, a memory array including a plurality of memory cells and a second interconnect layer. The method includes bonding the first and second interconnect layers and forming an isolation trench through the first substrate and exposing a portion of the STI structure. The isolation trench is formed through a second side of the first substrate that is opposite to the first side. The method includes disposing an isolation material to form an isolation structure in the isolation trench and performing a planarization process to remove portions of the isolation material disposed on the second side of the first substrate. | 2021-01-14 |
20210013089 | METHOD FOR FORMING TRENCHES - A method is provided for forming at least one trench to be filled with an isolating material to form an isolating trench, in a substrate based on a semiconductor material, the method including at least the following successive steps: providing a stack including at least the substrate, a first hard mask layer, and a second hard mask layer; making at least a first opening and a second opening, by carrying out isotropic etchings; performing a third, anisotropic, etching of the substrate in line with the second opening, so as to obtain the at least one trench; performing a fourth, isotropic, etching of the first layer so as to enlarge the first opening and obtain a first enlarged opening; and performing a fifth, anisotropic, etching so as to simultaneously enlarge the second opening and increase a depth of the at least one trench. | 2021-01-14 |
20210013090 | METHOD OF MANUFACTURING A TEMPLATE WAFER - A method for manufacturing a semiconductor device includes implanting gas ions in a donor wafer and bonding the donor wafer to a carrier wafer to form a compound wafer. The method also includes subjecting the compound wafer to a thermal treatment to cause separation along a delamination layer and growing an epitaxial layer on a portion of separated compound wafer to form a semiconductor device layer. The method further includes cutting the carrier wafer. | 2021-01-14 |
20210013091 | METHOD OF PREPARING AN ISOLATION REGION IN A HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE - A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices. | 2021-01-14 |
20210013092 | SEMICONDUCTOR SUBSTRATE POLISHING METHODS - Polishing slurries for polishing semiconductor substrates are disclosed. The polishing slurry may include first and second sets of colloidal silica particles with the second set having a silica content greater than the first set. | 2021-01-14 |
20210013093 | HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE HAVING ENHANCED CHARGE TRAPPING EFFICIENCY - A multilayer semiconductor on insulator structure is provided in which the handle substrate and an epitaxial layer in interfacial contact with the handle substrate comprise electrically active dopants of opposite type. The epitaxial layer is depleted by the handle substrate free carriers, thereby resulting in a high apparent resistivity, which improves the function of the structure in RF devices. | 2021-01-14 |
20210013094 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes providing a wafer having a first surface, wherein the wafer includes a gate electrode having a top surface, and the top surface is leveled with the first surface; and forming an alignment structure on the top surface. The method further includes forming a photoresist on the alignment layer to cover a portion of the top surface; and removing portions of the alignment layer uncovered by the photoresist to form an alignment structure on the top surface. The method further includes forming a dielectric surrounding the alignment structure on the first surface and over the alignment structure, removing a portion of the dielectric to expose the alignment structure by CMP; removing the alignment structure to expose at least a portion of the top surface of the gate electrode, and forming a gate conductor over and in contact with the gate electrode. | 2021-01-14 |
20210013095 | METHODS OF FORMING A CONDUCTIVE CONTACT STRUCTURE TO A TOP ELECTRODE OF AN EMBEDDED MEMORY DEVICE ON AN IC PRODUCT AND A CORRESPONDING IC PRODUCT - One illustrative method disclosed herein includes, among other things, selectively forming a sacrificial material on an upper surface of a top electrode of a memory cell, forming at least one layer of insulating material around the sacrificial material and removing the sacrificial material so as to form an opening in the at least one layer of insulating material, wherein the opening exposes the upper surface of the top electrode. The method also includes forming an internal sidewall spacer within the opening in the at least one layer of insulating material and forming a conductive contact structure that is conductively coupled to the upper surface of the top electrode, wherein a portion of the conductive contact structure is surrounded by the internal sidewall spacer. | 2021-01-14 |
20210013096 | METHOD FOR MANUFACTURING INTERCONNECTION STRUCTURE - A method for manufacturing an interconnection structure includes forming a second dielectric layer on a wafer. The wafer includes a first dielectric layer and a conductive element embedded in the first dielectric layer. An opening is formed in the second dielectric layer to expose the conductive element. A dielectric spacer layer is selectively formed to be in contact with surfaces defining the opening of the second dielectric layer. The dielectric spacer layer exposes the conductive element. A bottom via is formed in the opening and in contact with the dielectric spacer layer and the conductive element. A portion of the dielectric spacer layer is removed to form a dielectric spacer in contact with the bottom via. A top via is formed in the opening and over the bottom via and the dielectric spacer. | 2021-01-14 |
20210013097 | INTERCONNECT ARCHITECTURE WITH ENHANCED RELIABILITY - Interconnect structures having enhanced reliability is provided in which an electrically conductive structure having a line portion and a via portion is formed utilizing a subtractive process. In some embodiments, a non-conductive barrier liner is formed on physically exposed sidewalls of the via portion and physically exposed sidewalls and a topmost surface of the line portion of the electrically conductive structure. An electrically conductive metal cap is formed on a topmost surface of the via portion of the electrically conductive structure. In other embodiments, a conductive barrier spacer is formed on physically exposed sidewalls of the via portion and physically exposed sidewalls of the line portion of the electrically conductive structure. An electrically conductive metal cap is formed on a topmost surface of the via portion of the electrically conductive structure. | 2021-01-14 |
20210013098 | 3D Integrated Circuit and Methods of Forming the Same - An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer. | 2021-01-14 |
20210013099 | REDUCING THE PLANARITY VARIATION IN A DISPLAY DEVICE - Disclosed herein are techniques for reducing a variation in the planarity of a display device. In some embodiments, a method includes applying a first pressure to a top surface of a display device at a first temperature. The display device includes a backplane, a plurality of dies, and a plurality of fusible interconnections between the backplane and the plurality of dies. The first pressure is applied in a direction that is perpendicular to a plane of the backplane on which the plurality of dies are arranged. The first pressure and the first temperature are selected to cause the plurality of fusible interconnections to absorb variations in a planarity of the top surface of the display device. | 2021-01-14 |
20210013100 | WAFER PROCESSING METHOD - A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side or a front side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form modified layers in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of applying an ultrasonic wave to the polyester sheet in each of the plurality of separate regions corresponding to each device chip, pushing up each device chip through the polyester sheet, then picking up each device chip from the polyester sheet. | 2021-01-14 |
20210013101 | WAFER PROCESSING METHOD - A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side or a front side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form modified layers in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of applying an ultrasonic wave to the polyolefin sheet in each of the plurality of separate regions corresponding to each device chip, pushing up each device chip through the polyolefin sheet, then picking up each device chip from the polyolefin sheet. | 2021-01-14 |
20210013102 | WORKPIECE PROCESSING METHOD - A workpiece processing method includes holding a workpiece unit on a holding table and forming a division start point. The workpiece unit has a workpiece having a front side and a back side, and an additional member formed on the back side of the workpiece. The additional member is different in material from the workpiece. The workpiece unit is held on the holding table with the additional member opposed to the holding table. The division start point is formed by applying a laser beam to the front side of the workpiece with the focal point of the laser beam set inside the workpiece. The laser beam forms a modified layer inside the workpiece and simultaneously forming a division start point inside the additional member due to the leakage of the laser beam from the focal point toward the back side of the workpiece. | 2021-01-14 |
20210013103 | SEMICONDUCTOR DEVICE WITH ELONGATED PATTERN - A semiconductor device includes a semiconductor substrate, a source/drain region, a source/drain contact, a conductive via and a first polymer layer. The source/drain region is in the semiconductor substrate. The source/drain contact is over the source/drain region. The source/drain via is over the source/drain contact. The first polymer layer extends along a first sidewall of the conductive via and is separated from a second sidewall of the conductive via substantially perpendicular to the first sidewall of the conductive via. | 2021-01-14 |
20210013104 | SEMICONDUCTOR STRUCTURES AND METHODS FOR FABRICATING THE SAME - A semiconductor structure includes a semiconductor substrate, a gate stack disposed over the semiconductor substrate, a first oxide spacer disposed along a sidewall of the gate stack, a protection portion disposed over the first oxide spacer, and an interlayer dielectric layer disposed over the semiconductor substrate. The first oxide spacer and the protection portion are disposed between the gate stack and the interlayer dielectric layer. | 2021-01-14 |
20210013105 | SEMICONDUCTOR ARRANGEMENTS AND METHODS FOR MANUFACTURING THE SAME - Semiconductor arrangements and methods of manufacturing the same. The semiconductor arrangement may include: a substrate including a base substrate, a first semiconductor layer on the substrate, and a second semiconductor layer on the first semiconductor layer; first and second fin structures formed on the substrate and extending in the same straight line, each of the first and second fin structures including at least portions of the second semiconductor layer; a first isolation part formed around the first and second fin structures on opposite sides of the straight line; first and second FinFETs formed on the substrate based on the first and second fin structures respectively; and a second isolation part between the first and second fin structures and intersecting the first and second fin structures to isolate the first and second fin structures from each other. | 2021-01-14 |
20210013106 | VERTICAL FIELD EFFECT TRANSISTOR REPLACEMENT METAL GATE FABRICATION - A method for fabricating a semiconductor device includes forming a semiconductor structure including a substrate, a first vertical fin and a second vertical fin longitudinally spaced from the first vertical fin with each of the first and second vertical fin having a hardmask cap, and a bottom spacer layer on the substrate. The method further includes forming first and second bottom source/drains within the substrate respectively beneath the first and second vertical fins, forming first and second top source/drains respectively on the first and second vertical fins, forming a vertical oxide pillar between the first and second vertical fins, removing a portion of the oxide pillar to reduce a cross-sectional dimension to define a lower recessed region, and depositing a metal gate material about the first and second vertical fins wherein portions of the metal gate material are disposed within the recessed region of the oxide pillar. | 2021-01-14 |
20210013107 | METHOD FOR FORMING FILM STACKS WITH MULTIPLE PLANES OF TRANSISTORS HAVING DIFFERENT TRANSISTOR ARCHITECTURES - Three-dimensional integration can overcome scaling limitations by increasing transistor density in volume rather than area. To provided gate-all-around field-effect-transistor devices with different threshold voltages and doping types on the same substrate, methods are provided for growing adjacent nanosheet stacks having channels with different doping profiles. In one example, a first nanosheet stack is formed having channels with first doping characteristics. Then the first nanosheet stack is etched, and a second nanosheet stack is formed in plane with the first nanosheet stack. The second nanosheet stack has channels with different doping characteristics. This process can be repeated for additional nanosheet stacks. In another example, the formation of the nanosheet stacks with channels having different doping characteristics is performed by restricting layer formation to predefined locations using a patterned layer (e.g., a conformal oxide layer) that limits epitaxial growth to exposed regions of the substrate where the patterned layer is etched away. | 2021-01-14 |
20210013108 | SILICIDE FORMATION FOR SOURCE/DRAIN CONTACT IN A VERTICAL TRANSPORT FIELD-EFFECT TRANSISTOR - A method for manufacturing a semiconductor device includes forming a first vertical transistor structure in a first device region on a substrate, and forming a second vertical transistor structure in a second device region on the substrate. The first vertical transistor structure includes a first plurality of fins, and the second vertical transistor structure includes a second plurality of fins. A plurality of first source/drain regions are grown from upper portions of the first plurality of fins, and a contact liner layer is formed on the first source/drain regions. The method further includes forming a plurality of first silicide portions from the contact liner layer on the first source/drain regions, and forming a plurality of second silicide portions on a plurality of second source/drain regions extending from upper portions of the second plurality of fins. The second silicide portions have a different composition than the first silicide portions. | 2021-01-14 |
20210013109 | MULTIPLE THRESHOLD VOLTAGE DEVICES - The present disclosure relates to semiconductor structures and, more particularly, to multiple threshold voltage devices and methods of manufacture. The structure includes: a gate dielectric material; a gate material on the gate dielectric material, the gate material comprising different thickness in different regions each of which are structured for devices having a different Vt; and a workfunction material on the gate material. | 2021-01-14 |
20210013110 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING A PLURALITY OF CHANNEL PATTERNS - A semiconductor device manufacturing method includes forming a gate dielectric layer surrounding first semiconductor patterns and second semiconductor patterns; forming a first organic pattern covering the second semiconductor patterns; forming a sacrificial pattern interposed between the first semiconductor patterns and exposing both side surfaces of the first semiconductor patterns, and a conductive pattern surrounding the second semiconductor patterns and disposed between the first organic pattern and the second semiconductor patterns; forming a second organic pattern covering the first semiconductor patterns, the gate dielectric layer, the sacrificial pattern, and the first organic pattern; and forming a cross-linking layer interposed between the first organic material pattern and the second organic material pattern. | 2021-01-14 |
20210013111 | METHOD FOR THRESHOLD VOLTAGE TUNING THROUGH SELECTIVE DEPOSITION OF HIGH-K METAL GATE (HKMG) FILM STACKS - A method for microfabrication of a three dimensional transistor stack having gate-all-around field-effect transistor devices. The channels hang between source/drain regions. Each channel is selectively deposited with layers of materials designed for adjusting the threshold voltage of the channel. The layers may be oxides, high-k materials, work function materials and metallization. The three dimensional transistor stack forms an array of high threshold voltage devices and low threshold voltage devices in a single package. | 2021-01-14 |
20210013112 | VERTICAL FIELD-EFFECT TRANSISTOR (VFET) DEVICES AND METHODS OF FORMING THE SAME - Vertical field-effect transistor (VFET) devices and methods of forming the devices are provided. The methods may include forming a channel region including a first channel region and a second channel region, forming a first cavity in the substrate, forming a first bottom source/drain in the first cavity, forming a second cavity in the substrate, and forming a second bottom source/drain in the second cavity. The first cavity may expose a lower surface of the first channel region, and the second cavity may expose a lower surface of the second channel region. The method may also include after forming the first bottom source/drain and the second bottom source/drain, removing a portion of the channel region between the first channel region and the second channel region to separate the first channel region from the second channel region. | 2021-01-14 |
20210013113 | METHOD AND DEVICE FOR TESTING ARRAY SUBSTRATE, AND COMPUTER READABLE STORAGE MEDIUM - Disclosed is a method for testing an array substrate, including: sequentially applying a curing drive signal to curing pad circuits according to an arrangement order of the curing pad circuits in a testing circuit board, the curing pad circuit is connected with at least two array substrates; and performing an array test on the array substrates in the curing pad circuit by the curing drive signal. The present application also discloses a device for testing an array substrate, and a computer readable storage medium. | 2021-01-14 |
20210013114 | SEMICONDUCTOR DEVICE AND METHOD OF TESTING A SEMICONDUCTOR DEVICE - Provided is a semiconductor device that allows reduction of a measurement time of a PCMTEG and improvement of productivity in an IC manufacturing process. A PCMTEG region | 2021-01-14 |
20210013115 | MICROELECTRONIC PACKAGE WITH UNDERFILLED SEALANT - Embodiments may relate to a microelectronic package comprising an integrated heat spreader (IHS) coupled with a package substrate. A sealant may be positioned between, and physically coupled to, the IHS and the package substrate. The sealant may at least partially extend from a footprint of the IHS. Other embodiments may be described or claimed. | 2021-01-14 |
20210013116 | PACKAGED DEVICE WITH DIE WRAPPED BY A SUBSTRATE - A die-wrapped packaged device includes at least one flexible substrate having a top side and a bottom side that has lead terminals, where the top side has outer positioned die bonding features coupled by traces to through-vias that couple through a thickness of the flexible substrate to the lead terminals. At least one die includes a substrate having a back side and a topside semiconductor surface including circuitry thereon having nodes coupled to bond pads. One of the sides of the die is mounted on the top side of the flexible circuit, and the flexible substrate has a sufficient length relative to the die so that the flexible substrate wraps to extend over at least two sidewalls of the die onto the top side of the flexible substrate so that the die bonding features contact the bond pads. | 2021-01-14 |
20210013117 | INTEGRATED HEAT SPREADER (IHS) WITH HEATING ELEMENT - Embodiments may relate to a microelectronic package that includes a lid coupled with a package substrate such that a die is positioned between the lid and the package substrate. The lid may include a heating element that is to heat an area between the lid and the die. Other embodiments may be described or claimed. | 2021-01-14 |
20210013118 | SUBSTRATE STRUCTURE AND SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure includes a package substrate, at least one semiconductor die, a heat dissipating device, at least one electronic device and a heat transmitting structure. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is electrically connected to the first surface of the package substrate. The heat dissipating device is thermally connected to the first surface of the package substrate. The electronic device is electrically connected to the second surface of the package substrate. The electronic device has a first surface and a second surface opposite to the first surface, and the first surface of the electronic device faces the second surface of the package substrate. The heat transmitting structure is disposed adjacent to the second surface of the package substrate, and thermally connected to the electronic device and the heat dissipating device. | 2021-01-14 |
20210013119 | SEMICONDUCTOR STRUCTURE WITH HEAT DISSIPATION STRUCTURE AND METHOD OF FABRICATING THE SAME - A semiconductor structure with a heat dissipation structure includes a first device wafer includes a front side and a back side. A first transistor is disposed on the front side. The first transistor includes a first gate structure disposed on the front side. Two first source/drain doping regions are embedded within the first device wafer at two side of the first gate structure. A channel region is disposed between the two first source/drain doping regions and embedded within the first device wafer. A first dummy metal structure contacts the back side of the first device wafer, and overlaps the channel region. | 2021-01-14 |
20210013120 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a base and a conductive layer to form a composite substrate. The conductive layer covers a surface of the base. The semiconductor device also includes a dielectric layer covering the conductive layer. The conductive layer is disposed between the dielectric layer and the base. The semiconductor device further includes a GaN-containing composite layer, a gate electrode disposed over the GaN-containing composite layer, a source electrode and a drain electrode disposed on the GaN-containing composite layer. The source electrode and the drain electrode are disposed at two opposite sides of the gate electrode. In addition, a method for manufacturing the semiconductor device with a composite substrate is provided. | 2021-01-14 |
20210013121 | ELECTRONIC DEVICE - An electronic device includes a metal member and a connected member. A metal connecting layer is provided between a lower-side surface of the metal member and an upper-side surface of the connected member, to connect the metal member and the connected member to each other. The metal connecting layer includes at least one of metal films, each of which is made of gold or gold alloy. A thickness of the metal connecting layer in an opposing area between the metal member and the connected member is smaller than a flatness of each of the lower-side surface and the upper-side surface. A rust-preventing film is formed on a side wall of the metal member in such a way that the rust-preventing film extends from an outer periphery of the metal connecting layer to a position away from the outer periphery by a predetermined distance. | 2021-01-14 |
20210013122 | PLATING FILM AND PLATED MEMBER - Provided is a plating film containing Au and Tl, including Tl oxides including Tl | 2021-01-14 |
20210013123 | ULTRAVIOLET (UV)-CURABLE SEALANT IN A MICROELECTRONIC PACKAGE - Embodiments may relate to a microelectronic package that includes an integrated heat spreader (IHS) coupled with a package substrate. The microelectronic package may further include a sealant material between the package substrate and the IHS. The sealant material may be formed of a material that cures when exposed to ultraviolet (UV) wavelengths. Other embodiments may be described or claimed. | 2021-01-14 |
20210013124 | HEAT DISSIPATING STRUCTURE FOR ELECTRONIC UNITS AND DISPLAY DEVICE COMPRISING SAME - Provided are a heat dissipating structure with which stress on an electronic unit that generates heat can be reduced, and a display device comprising the same. The heat dissipating structure comprises: at least two electronic units, e.g. electronic units, that are provided on a circuit hoard, differ from one another in height from the circuit board, and generate heat; a dissipating member for dissipating heat generated from the electronic units; and heat conducting members that are sandwiched between the electronic units and the heat dissipating member so as to conduct heat, wherein the heat conducting members provided between the electronic units and the heat dissipating member have the same thickness. | 2021-01-14 |
20210013125 | INFORMATION HANDLING SYSTEM LOW FORM FACTOR INTERFACE THERMAL MANAGEMENT - Information handling system thermal rejection of thermal energy generated by one or more components, such as a central processing unit and graphics processing unit, is enhanced by disposing boron arsenide between the one or more components and a heat transfer structure that directs thermal energy from the one or more components to a heat rejection region, such as cooling fan exhaust. For instance, the boron arsenide is a layer formed with chemical vapor deposition on a copper heat pipe or a layer of thermal grease infused with the boron arsenide. | 2021-01-14 |
20210013126 | METAL INVERSE OPAL SUBSTRATE WITH INTEGRATED JET COOLING IN ELECTRONIC MODULES - Embodiments of the disclosure relate to an MIO substrate with integrated jet cooling for electronic modules and a method of forming the same. In one embodiment, a substrate for an electronic module includes a thermal compensation base layer having an MIO structure and a cap layer overgrown on the MIO structure. A plurality of orifices extends through the thermal compensation base layer between an inlet face and an outlet face positioned opposite to the inlet face, defining a plurality of jet paths. A plurality of integrated posts extends outward from the cap layer, wherein each integrated post of the plurality of integrated posts is positioned on the outlet face between each orifice of the plurality of orifices. | 2021-01-14 |
20210013127 | THERMAL DISSIPATION STRUCTURE FOR INTEGRATED CIRCUITS - A thermal dissipation structure for integrated circuits includes a semiconductor substrate, a thermal dissipation trench, a metal seed layer and a metal layer. The semiconductor substrate has a first surface and a second surface which is opposite to the first surface. Integrated circuits are located on and thermally coupled with the first surface. The thermal dissipation trench is formed within the second surface. The metal seed layer seals the thermal dissipation trench to define a thermal dissipation channel. The thermal dissipation channel includes an inlet and an outlet. The metal layer is an electroplated layer formed from the metal seed layer. | 2021-01-14 |
20210013128 | SEMICONDUCTOR DEVICE - In an inactive region of an active region, a gate pad, a gate poly-silicon layer, and a gate finger are provided at a front surface of a semiconductor substrate, via an insulating film. The gate poly-silicon layer is provided beneath the gate pad, sandwiching the insulating film therebetween. The gate pad, the gate poly-silicon layer, a gate finger, gate electrodes of a trench gate structure, a gate finger, and a second measurement pad are electrically connected in the order stated. As a result, the gate electrodes where parasitic resistance occurs and the gate poly-silicon layer where built-in resistance occurs are connected in series between the second measurement pad and the gate pad. A resistance value of the overall gate resistance that is a combined resistance of the built-in resistance and the parasitic resistance may be measured by the second measurement pad. | 2021-01-14 |
20210013129 | ELECTRONIC APPARATUS - An electronic apparatus includes: a first metal layer; an electronic component that is provided on the first metal layer; a second metal layer that is provided on the first metal layer and on the electronic component; and an insulating resin that fills a space between the first metal layer and the second metal layer so as to cover the electronic component. The second metal layer includes: a sheet-like electrode pad portion; and a connection portion that is disposed along a peripheral edge of the electrode pad portion, and that protrudes from the electrode pad portion toward the first metal layer so as to electrically connect the second metal layer to the first metal layer. | 2021-01-14 |
20210013130 | SEMICONDUCTOR MODULE - A semiconductor module includes: a circuit board; a semiconductor chip having a first electrode pad on a first surface, bonded to the circuit board at a second surface that is opposite to the first surface, and having side surfaces intersecting the first surface and the second surface; an external terminal electrically connected to the first electrode pad; and an insulating member configured to fix the external terminal, wherein by the insulating member contacting the side surfaces of the semiconductor chip at a plurality of locations, parallel movement and rotational movement of the semiconductor chip relative to the insulating member in a plane parallel, to the first surface are restricted, and wherein the external terminal penetrates the insulating member. | 2021-01-14 |
20210013131 | ELECTRONIC DEVICE - An electronic device includes a substrate, a first conductive pad and a chip. The first conductive pad is disposed on the substrate. The chip includes a second conductive pad electrically connected to the first conductive pad, and the first conductive pad is disposed between the substrate and the second conductive pad. The first conductive pad has a first groove. | 2021-01-14 |
20210013132 | Die Attach Methods and Semiconductor Devices Manufactured based on Such Methods - A semiconductor device includes a carrier, a power semiconductor die that includes first and second opposite facing main surfaces, a side surface extending from the first main surface to the second main surface, and first and second electrodes disposed on the first and second main surfaces, respectively, a die attach material arranged between the carrier and the first electrode, wherein the die attach material forms a fillet at the side surface of the power semiconductor die, wherein a fillet height of the fillet is less than about 95% of a height of the power semiconductor die, wherein the height of the power semiconductor die is a length of the side surface, and wherein a maximum extension of the die attach material over edges of a main surface of the power semiconductor die facing the die attach material is less than about 200 micrometers. | 2021-01-14 |
20210013133 | LEADLESS PACKAGED DEVICE WITH METAL DIE ATTACH - A leadless packaged semiconductor device includes a metal substrate having at least a first through-hole aperture having a first outer ring and a plurality of cuts through the metal substrate to define spaced apart metal pads on at least two sides of the first through-hole aperture. A semiconductor die that has a back side metal (BSM) layer on its bottom side and a top side with circuitry coupled to bond pads is mounted top side up on the first outer ring. A metal die attach layer is directly between the BSM layer and walls of the metal substrate bounding the first through-hole aperture that provides a die attachment that fills a bottom portion of the first through-hole aperture. Bond wires are between metal pads and the bond pads. A mold compound is also provided including between adjacent ones of the metal pads. | 2021-01-14 |
20210013134 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES, CORRESPONDING DEVICE AND CIRCUIT - A method of manufacturing semiconductor devices such as integrated circuits comprises: providing one or more semiconductor chips having first and second opposed surfaces, coupling the semiconductor chip or chips with a support substrate with the second surface towards the support substrate, embedding the semiconductor chip or chips coupled with the support substrate in electrically-insulating packaging material by providing in the packaging material electrically-conductive passageways. The electrically-conductive passageways comprise: electrically-conductive chip passageways towards the first surface of the at least one semiconductor chip, and/or electrically-conductive substrate passageways towards the support substrate. | 2021-01-14 |
20210013135 | Package Lead Design with Grooves for Improved Dambar Separation - A lead frame includes a die pad, a first lead extending away from the die pad, a peripheral structure mechanically connected to the first lead and the die pad, and a first groove in an outer surface of the first lead. The first groove extends longitudinally along the first lead away from the die pad. | 2021-01-14 |
20210013136 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In one example, a semiconductor device comprises a substrate and an electronic device on a top side of the substrate, a lead frame on the top side of the substrate over the electronic device, wherein the lead frame comprises a connection bar and a lead, a component mounted to the connection bar and the lead on a top side of the lead frame, and an encapsulant on the top side of the substrate, wherein the encapsulant contacts a side of the electronic device and a side of the component. Other examples and related methods are also disclosed herein. | 2021-01-14 |
20210013137 | SEMICONDUCTOR DEVICE WITH LEAD FRAME THAT ACCOMMODATES VARIOUS DIE SIZES - A semiconductor device is assembled using a lead frame having leads that surround a central opening. The leads have proximal ends near to the central opening and distal ends spaced from the central opening. A heat sink is attached to a bottom surface of the leads and a semiconductor die is attached to a top surface of the leads, where the die is supported on the proximal ends of the leads and spans the central opening. Bond wires electrically connect electrodes on an active surface of the die and the leads. An encapsulant covers the bond wires and at least the top surface of the leads and the die. The distal ends of the leads are exposed to allow external electrical communication with the die. | 2021-01-14 |
20210013138 | STACKED DIE SEMICONDUCTOR PACKAGE - A stacked die semiconductor package includes a leadframe including a die pad and lead terminals on at least two sides of the die pad, a top die having circuitry coupled to bond pads, and bottom die having a back side that is attached by die attach material to the die pad and a top side having at least one redistribution layer (RDL) over and coupled to a top metal level including connections to input/output (IO) nodes on the top metal level. The RDL provides a metal pattern including wirebond pads that match locations of the bond pads of the top die. The bond pads on the top die are flip-chip attached to the wirebond pads of the bottom die, and the bond wires are positioned between the wirebond pads and the lead terminals. | 2021-01-14 |
20210013139 | SEMICONDUCTOR PACKAGE INCLUDING REDISTRIBUTED LAYER AND METHOD FOR FABRICATION THEREFOR - A semiconductor package is provided. The semiconductor package includes a redistribution layer, a semiconductor chip, solder balls, an interposer, an encapsulant layer, and an underfill layer. The semiconductor chip is electrically connected to the redistribution layer, and disposed on an upper surface of the redistribution layer. The solder balls are disposed on the upper surface of the redistribution layer spaced apart from the semiconductor chip and are electrically connected to the redistribution layer. The interposer is electrically connected to the solder balls, and is disposed on an upper surface of the solder balls. The encapsulant layer encapsulates the semiconductor chip and side surfaces of the redistribution layer under the interposer. The underfill layer fills a space between a lower surface of the interposer and an upper surface of the encapsulant layer. The encapsulant layer includes a side surface encapsulant region surrounding the side surfaces of the redistribution layer. | 2021-01-14 |
20210013140 | SEMICONDUCTOR STRUCTURE, PACKAGE STRUCTURE, AND MANUFACTURING METHOD THEREOF - A semiconductor structure including at least one integrated circuit component is provided. The at least one integrated circuit component includes a first semiconductor substrate and a second semiconductor substrate electrically coupled to the first semiconductor substrate, wherein the first semiconductor substrate and the second semiconductor substrate are bonded through a first hybrid bonding interface, and at least one of the first semiconductor substrate or the second semiconductor substrate includes at least one first embedded capacitor. | 2021-01-14 |
20210013141 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE, AND VEHICLE - Provided is a semiconductor device including: a circuit board; a wiring pattern; a first semiconductor chip and a second semiconductor chip; a first lead frame; and a second lead frame; wherein the first lead frame and the second lead frame each comprises: a chip joining portion provided above at least a part of the semiconductor chip; a wiring joining portion provided above at least a part of the wiring pattern; and a bridging portion for connecting the chip joining portion and the wiring joining portion; and in the first direction, a space between the bridging portion of the first lead frame and the bridging portion of the second lead frame is smaller than a space between the chip joining portion of the first lead frame and the chip joining portion of the second lead frame. | 2021-01-14 |
20210013142 | METHOD OF FORMING A PACKAGED SEMICONDUCTOR DEVICE USING GANGED CONDUCTIVE CONNECTIVE ASSEMBLY AND STRUCTURE - A packaged semiconductor device has a die attach pad and leads disposed proximate to the die attach pad. Each lead has a lead bottom surface and a lead end surface. A semiconductor device attached adjacent to a top surface of the die attach pad, and a conductive clip is attached to the semiconductor device and at least one of the leads. The conductive clip comprises a first tie bar extending from a first side surface of the conductive clip. A package body encapsulates the semiconductor device, the conductive clip, portions of the leads, at least a portion of the first tie bar, and at least a portion of the die attach pad. Each lead end surface is exposed in a side surface of the package body, and an end surface of the first tie bar is exposed in a first side surface of the package body. A conductive layer is disposed on each lead end surface but is not disposed on the end surface of the first tie bar. | 2021-01-14 |
20210013143 | CAPACITOR AND METHOD FOR PRODUCING THE SAME - A capacitor includes at least one multi-wing structure; a laminated structure, where the laminated structure clads the at least one multi-wing structure and includes at least one dielectric layer and a plurality of conductive layers, and the at least one dielectric layer and the plurality of conductive layers form a structure that a conductive layer and a dielectric layer are adjacent to each other; at least one first external electrode, where the first external electrode is electrically connected to some conductive layer(s) in the plurality of conductive layers; at least one second external electrode, wherein the second external electrode is electrically connected to the other conductive layer(s) in the plurality of conductive layers, and a conductive layer in the laminated structure adjacent to each conductive layer in the some conductive layer(s) includes at least one conductive layer in the other conductive layer(s). | 2021-01-14 |
20210013144 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - In one example, a semiconductor device comprises a substrate comprising a dielectric, a first conductor on a top side of the dielectric, and a second conductor on a bottom side of the dielectric, wherein the dielectric has an aperture, and the first conductor comprises a partial via contacting a pad of the second conductor through the aperture, an electronic device having an interconnect electrically coupled to the first conductor, and an encapsulant on a top side of the substrate contacting a side of the electronic device. Other examples and related methods are also disclosed herein. | 2021-01-14 |
20210013145 | ETCH STOP LAYER-BASED APPROACHES FOR CONDUCTIVE VIA FABRICATION AND STRUCTURES RESULTING THEREFROM - Etch stop layer-based approaches for via fabrication are described. In an example, an integrated circuit structure includes a plurality of conductive lines in an ILD layer, wherein each of the plurality of conductive lines has a bulk portion including a metal and has an uppermost surface including the metal and a non-metal. A hardmask layer is on the plurality of conductive lines and on an uppermost surface of the ILD layer, and includes a first hardmask component on and aligned with the uppermost surface of the plurality of conductive lines, and a second hardmask component on and aligned with regions of the uppermost surface of the ILD layer. A conductive via is in an opening in the hardmask layer and on a portion of one of the plurality of conductive lines, the portion having a composition different than the uppermost surface including the metal and the non-metal. | 2021-01-14 |
20210013146 | Interconnect Structures and Methods of Forming the Same - Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via. | 2021-01-14 |
20210013147 | ELECTRONIC DEVICE WITH SHORT CIRCUIT PROTECTION ELEMENT, FABRICATION METHOD AND DESIGN METHOD - An electronic device includes: a control terminal, which extends on a first face of a substrate; a first conduction terminal, which extends in the substrate at the first face of the substrate; a first insulating layer interposed between the control terminal and the first conduction terminal; a conductive path, which can be biased at a biasing voltage; and a protection element, coupled to the control terminal and to the conductive path, which forms an electrical connection between the control terminal and the conductive path and is designed to melt, and thus interrupt electrical connection, in the presence of a leakage current higher than a critical threshold between the control terminal and the first conduction terminal through the first insulating layer. | 2021-01-14 |
20210013148 | BUSBAR, METHOD FOR MANUFACTURING THE SAME AND POWER MODULE COMPRISING THE SAME - A conducting busbar ( | 2021-01-14 |
20210013149 | STANDARD CELL AND AN INTEGRATED CIRCUIT INCLUDING THE SAME - An integrated circuit including: a power rail including first and second conductive lines spaced apart from each other in a vertical direction, wherein the first and second conductive lines extend in parallel to each other in a first horizontal direction, and are electrically connected to each other, to supply power to a first standard cell, wherein the first and second conductive lines are disposed at a boundary of the first standard cell; and a third conductive line between the first and second conductive lines and extending in a second horizontal direction orthogonal to the first horizontal direction, to transfer an input signal or an output signal of the first standard cell. | 2021-01-14 |
20210013150 | SEMICONDUCTOR DEVICE WITH TRANSISTOR LOCAL INTERCONNECTS - A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate. The first transistor and a second transistor are formed on the semiconductor substrate. Each transistor comprises a source, a drain, and a gate. The gate of the first transistor extends longitudinally as part of a first linear strip and the gate of the second transistor extends longitudinally as part of the second linear strip parallel to and spaced apart from the first linear strip. A first CB layer forms a local interconnect layer electrically connected to the gate of the first transistor. A second CB layer forms a local interconnect layer electrically connected to the gate of the second transistor. A CA layer forms a local interconnect layer extending longitudinally between a first end and a second end of the CA layer. The CA layer is electrically connected to the first and second CB layers. The first CB layer is electrically connected adjacent the first end of the CA layer and the second layer is electrically connected adjacent the second end of the CA layer. The first CB layer, the second CB layer and the CA layer are disposed between a first metal layer and the semiconductor substrate. The first metal layer being disposed above each source, each drain, and each gate of the first and second transistors. The CA layer extends substantially parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers. At least one via selectively provides an electrical connection between the CA or CB layers and the at least one metal layer. | 2021-01-14 |
20210013151 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A package structure includes an insulating encapsulation, at least one semiconductor die, a redistribution circuit structure, and first reinforcement structures. The at least one semiconductor die is encapsulated in the insulating encapsulation. The redistribution circuit structure is located on the insulating encapsulation and electrically connected to the at least one semiconductor die. The first reinforcement structures are embedded in the redistribution circuit structure. A shape of the package structure includes a polygonal shape on a vertical projection along a stacking direction of the insulating encapsulation and the redistribution circuit structure, and the first reinforcement structures are located on and extended along diagonal lines of the package structure. | 2021-01-14 |
20210013152 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a first substrate, a second substrate provided on the first substrate, a semiconductor chip provided between the first substrate and the second substrate, solder structures extending between the first substrate and the second substrate and spaced apart from the semiconductor chip, and bumps provided between the semiconductor chip and the second substrate. The solder structures electrically connect the first substrate and the second substrate. | 2021-01-14 |
20210013153 | DISPLAY SUBSTRATE ASSEMBLY AND METHOD OF MANUFACTURING THE SAME, AND DISPLAY APPARATUS - In embodiments of the present disclosure, there is provided a display substrate assembly including: a base substrate; a light shielding layer on the base substrate; and an active layer of a thin film transistor, above the base substrate. An orthographic projection of the active layer on the base substrate in a thickness direction of the base substrate is within an orthographic projection of the light shielding layer on the base substrate in the thickness direction of the base substrate, and the light shielding layer includes an ion-doped amorphous silicon layer. In embodiments of the present disclosure, there is also provided a method of manufacturing a display substrate assembly and a display apparatus including the display substrate assembly. | 2021-01-14 |
20210013154 | Flip-Chip Die Package Structure and Electronic Device - A flip-chip die package includes a substrate, a die, a plurality of conductive bumps, and a first metal structure, where an upper surface of the die is electrically coupled, using the conductive bumps, to a surface that is of the substrate and that faces the die, and the first metal structure includes a plurality of first metal rods disposed between the substrate and the die, where each first metal rod is electrically coupled to the substrate and the die, and the first metal rods are arranged around a first active functional circuit, and the first active functional circuit includes an electromagnetic radiation capability or an electromagnetic receiving capability in the die. | 2021-01-14 |
20210013155 | MULTI-METAL PACKAGE STIFFENER - A semiconductor package system includes a semiconductor package including at least one semiconductor device having a first side and a second side and a substrate having a first side and a second side. The second side of the at least one semiconductor device is positioned on the first side of the substrate. At least one stiffener element is provided on the semiconductor package. The at least one stiffener element includes at least two metal elements having different coefficients of thermal expansion joined together. | 2021-01-14 |
20210013156 | PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - Disclosed are package substrates and semiconductor packages including the same. A package substrate may have a plurality of corner regions; a core layer having a first surface and a second surface; an upper layer, which includes a plurality of first wiring structures and a plurality of first dielectric layers; and a lower layer, which includes a plurality of second wiring structures and a plurality of second dielectric layers. Additionally, an area proportion of top surfaces of the first wiring structures in the upper layer relative to a top surface of the upper layer on each of the corner regions is less than an area proportion of top surfaces of the second wiring structures in the lower layer relative to a top surface of the lower layer on each of the corner regions. | 2021-01-14 |
20210013157 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer having a first surface and a second surface. A first metal film is disposed on the first surface. An outer portion of the first surface beyond an outer periphery of the first metal film is left uncovered by the first metal film. A semiconductor substrate has an inner region of a first thickness and a peripheral region of a second thickness, greater than the first thickness. A portion of the first semiconductor layer is between the inner region and the first metal layer. The peripheral region of the semiconductor substrate is below the outer portion of the first surface of the first semiconductor layer. A second metal film is below the inner region of the semiconductor substrate and adjacent to the peripheral region of the semiconductor substrate. | 2021-01-14 |
20210013158 | METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE - A method for manufacturing a semiconductor package includes following operations. A die having a first surface and a second surface opposite to the first surface is provided. A polymeric film is disposed over the second surface of the die. An adhesive film is provided. The die and the polymeric film are attached to a carrier substrate through the adhesive film. The die, the polymeric film and the adhesive film are molded with a molding compound. The polymeric film is sandwiched between the die and the adhesive film upon attaching to the carrier substrate. | 2021-01-14 |
20210013159 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a semiconductor device, a plurality of through semiconductor vias (TSV), a first seal ring, and a second seal ring. The TSVs penetrate through the semiconductor device. The TSVs are adjacent to an edge of the semiconductor device. The first seal ring is disposed on and physically connected to one end of each of the TSVs. The second seal ring is disposed on and physically connected to another end of each of the TSVs. | 2021-01-14 |
20210013160 | CHIP PACKAGE WITH LID - Structures and formation methods of a chip package are provided. The chip package includes a substrate and a semiconductor die over the substrate. The chip package also includes a lid covering a top surface of the semiconductor die. The lid has a first support structure and a second support structure, and the first support structure and the second support structure are positioned at respective corner portions of the substrate. An opening penetrates through the lid to expose a space containing the semiconductor die, and the lid has a side edge extending from an edge of the first support structure to an edge of the second support structure. | 2021-01-14 |
20210013161 | MOISTURE-RESISTANT ELECTRONIC COMPONENT AND PROCESS FOR PRODUCING SUCH A COMPONENT - An electronic component includes a first set comprising an interconnect layer and an electronic circuit having a front face and a back face, which is connected to the interconnect layer by the front face, wherein the first set comprises a metal plate having a front face and a back face joined to the back face of the electronic circuit; a coupling agent between the front face of the metal plate and the back face of the electronic circuit, configured to thermally and electrically connect the metal plate to the electronic circuit; and in that the electronic component comprises: one or more layers made of organic materials stacked around the first set and the metal plate using a printed circuit-type technique and encapsulating the electronic circuit; a thermally conductive metal surface arranged at least partially in contact with the back face of the metal plate. | 2021-01-14 |
20210013162 | Three-Dimensional Module with Integrated Passive Components - A three-dimensional (3-D) module with integrated passive components includes a plurality of vertically stacked sub-modules. Each sub-module comprises a device level comprising a high-k dielectric (e.g. ceramic) material and an interconnect level comprising a low-k dielectric (e.g. organic) material. The passive components in the device level are fired integrally, whereas the device level and the interconnect level are fired independently. | 2021-01-14 |
20210013163 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes an antenna zone and a routing zone. The routing zone is disposed on the antenna zone, where the antenna zone includes a first insulation layer and two or more second insulation layer and a thickness of the first insulation layer is different from that of the second insulation layer. | 2021-01-14 |
20210013164 | SEMICONDUCTOR DEVICE - A ground pad is disposed on a substrate. A plurality of transistors, each grounded at an emitter thereof, are in a first direction on a surface of the substrate. An input line connected to bases of the transistors is on the substrate. At least two shunt inductors are each connected at one end thereof to the input line and connected at the other end thereof to the ground pad. In the first direction, the two shunt inductors are on opposite sides of a center of a region where the transistors are arranged. | 2021-01-14 |
20210013165 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, a transistor, and a first harmonic termination circuit. The transistor is formed at the semiconductor substrate. The transistor amplifies an input signal supplied to an input end and outputs an amplified signal through an output end. The first harmonic termination circuit attenuates a harmonic component included in the amplified signal. The first harmonic termination circuit is formed at the semiconductor substrate such that one end of the first harmonic termination circuit is connected to the output end of the transistor and the other end of the first harmonic termination circuit is connected to a ground end of the transistor. | 2021-01-14 |
20210013166 | BOND PAD RELIABILITY OF SEMICONDUCTOR DEVICES - The disclosed subject matter relates to a structure and method to improve bond pad reliability of semiconductor devices. According to an aspect of the present disclosure, a bond pad structure is provided that includes a dielectric layer and at least one bond pad in the dielectric layer, wherein the bond pad has a top surface. A passivation layer has an opening over the bond pad, wherein the opening has sidewalls. A low-k barrier layer is covering the sidewalls of the opening and the top surface of the bond pad. Protective structures are formed over the sidewalls of the opening. | 2021-01-14 |
20210013167 | MICROELECTRONIC DEVICE WITH SOLDER-FREE PLATED LEADS - A microelectronic device has a solder-free package lead extending through an electrically non-conductive package structure to an exterior of the microelectronic device. The package lead includes a pillar contacting a terminal on a die and extending partway through the package structure, and an external lead electrically coupled to the pillar and extending to an exterior of the microelectronic device. The package lead is free of a solder joint. The microelectronic device may be formed by forming an access cavity package structure, to expose the pillar, and forming the external lead by a plating process. The microelectronic device may be formed by providing an external lead lamina containing the external lead, and forming a plated metal joint by a plating process that connects the external lead to the pillar. | 2021-01-14 |
20210013168 | SEMICONDUCTOR DEVICE WITH A SEMICONDUCTOR CHIP CONNECTED IN A FLIP CHIP MANNER - A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional surface of the semiconductor chip. The connecting member extends a distance between the wiring board surface and the functional surface. A sealing material seals a gap space between the wiring board and the semiconductor chip. An electrode is formed at the wiring board surface and arranged outside of an outer periphery of the sealing material. A lateral distance between an outer periphery of the semiconductor chip and the outer periphery of the sealing material is between 0.1 mm and a lateral distance from the outer periphery of the semiconductor chip to the electrode. | 2021-01-14 |
20210013169 | DISPLAY PANEL AND MANUFACTURING METHOD OF THE DISPLAY PANEL - A display panel is manufactured that includes a first panel substrate, a second panel substrate that is opposite the first panel substrate and has a protruding portion protruding from the first panel substrate, and a wiring board connected to the protruding portion of the second panel substrate. A manufacturing method of the display panel includes: overlapping protruding terminals and wiring terminals with the protruding terminals and the wiring terminals being opposite each other through an anisotropic conductive film; exposing the conductive layer on a surface of particles, located between the protruding terminals and the wiring terminals that are opposite each other, of the particles in the anisotropic conductive film; and curing the curable resin layer of particles, located in regions between the protruding terminals or regions between the wiring terminals when viewed in a normal direction of the second panel substrate, of the particles in the anisotropic conductive film. | 2021-01-14 |
20210013170 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a seal portion; an electronic element disposed within the seal portion; a first lead terminal; a second lead terminal having one end that is disposed to be close to the one end of the first lead terminal within the seal portion, and another end that is exposed from the seal portion; a first connecting element disposed within the seal portion, and having one end that is electrically connected to a control electrode of the electronic element, and another end that is electrically connected to the one end of the second lead terminal; a first conductive bonding agent for joining together the control electrode of the electronic element and the one end of the first connecting element in a conductive manner; and a second conductive bonding agent. | 2021-01-14 |
20210013171 | CLIPS FOR SEMICONDUCTOR PACKAGES - A clip for a semiconductor package and a semiconductor having a clip is disclosed. In one example, the clip includes a first planar portion, a plurality of first pillars, and a plurality of first solder balls. Each first pillar of the plurality of first pillars is coupled to the first planar portion. Each first solder ball of the plurality of first solder balls is coupled to a corresponding first pillar of the plurality of first pillars. | 2021-01-14 |
20210013172 | METHOD OF TRANSFERRING MICRO DEVICE - A method of transferring a micro device is provided. The method includes: aligning a transfer plate with the micro device thereon with a receiving substrate having a contact pad thereon such that the micro device is above or in contact with the contact pad; moving a combination of the transfer plate with the micro device thereon and the receiving substrate into a confined space with a relative humidity greater than or equal to about 85% so as to condense some water between the micro device and the contact pad; and attaching the micro device to the contact pad. | 2021-01-14 |
20210013173 | Bonding Through Multi-Shot Laser Reflow - A method includes performing a first laser shot on a first portion of a top surface of a first package component. The first package component is over a second package component, and a first solder region between the first package component and the second package component is reflowed by the first laser shot. After the first laser shot, a second laser shot is performed on a second portion of the top surface of the first package component. A second solder region between the first package component and the second package component is reflowed by the second laser shot. | 2021-01-14 |
20210013174 | METHOD OF LIQUID ASSISTED BONDING - A method of liquid assisted bonding includes: forming a structure with a liquid layer between an electrode of a device and a contact pad of a substrate, and two opposite surfaces of the liquid layer being respectively in contact with the electrode and the contact pad in which hydrogen bonds are formed between the liquid layer and at least one of the electrode and the contact pad; and evaporating the liquid layer to break said hydrogen bonds such that at least one of a surface of the electrode facing the contact pad and a surface of the contact pad facing the electrode is activated so as to assist a formation of a diffusion bonding between the electrode of the device and the contact pad in which a contact area between the electrode and the contact pad is smaller than or equal to about 1 square millimeter. | 2021-01-14 |
20210013175 | METHOD OF ASSEMBLING A SEMICONDUCTOR POWER MODULE COMPONENT AND A SEMICONDUCTOR POWER MODULE WITH SUCH A MODULE COMPONENT AND MANUFACTURING SYSTEM THEREFOR - A method of assembling a semiconductor power module component | 2021-01-14 |
20210013176 | PRE-STACKING MECHANICAL STRENGTH ENHANCEMENT OF POWER DEVICE STRUCTURES - A method includes placing a coupling mechanism material layer on a backside of a wafer having power devices fabricated on a frontside thereof, and placing conductive spacer blocks on the coupling mechanism material layer on a backside of the selected wafer. The method further includes activating the coupling mechanism material to bond the conductive spacer blocks to the backside of the selected wafer, and singulating the wafer to separate the vertical device stacks, each of the singulated vertical device stacks including a device die bonded to, or fused with, a conductive spacer block. | 2021-01-14 |
20210013177 | SEMICONDCUTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes a redistribution structure, at least one semiconductor device, a heat dissipation component, and an encapsulating material. The at least one semiconductor device is disposed on and electrically connected to the redistribution structure. The heat dissipation component is disposed on the redistribution structure and includes a concave portion for receiving the at least one semiconductor device and an extending portion connected to the concave portion and contacting the redistribution structure, wherein the concave portion contacts the at least one semiconductor device. The encapsulating material is disposed over the redistribution structure, wherein the encapsulating material fills the concave portion and encapsulates the at least one semiconductor device. | 2021-01-14 |
20210013178 | ELECTRONIC MODULE AND ELECTRONIC DEVICE - An electronic module includes: a plurality of heat generating members provided over a first surface of a board; a frame joined to the first surface of the board and provided between the plurality of heat generating members that are arranged; and a lid configured to cover the first surface of the board and thermally coupled to each of the plurality of heat generating members, the frame being a grid-shaped frame or a mesh-shaped frame. | 2021-01-14 |
20210013179 | MODULAR VOLTAGE REGULATORS - A device includes a semiconductor die. The semiconductor die has formed thereon a plurality of multi-phase voltage regulator modules of the same design formed on a common semiconductor substrate. | 2021-01-14 |
20210013180 | SEMICONDUCTOR PACKAGE INCLUDING STACKED SEMICONDUCTOR CHIPS - Disclosed is a semiconductor package. The semiconductor package includes a substrate including an opening, a first semiconductor chip, disposed on the substrate, including a plurality of first chip pads exposed through the opening, a second semiconductor chip, disposed on the first semiconductor chip to partially overlap with the first semiconductor chip, including a plurality of second chip pads, aligned with the opening, and a redistribution layer formed on a surface on which the second chip pads of the second semiconductor chip are disposed. One or more of the second chip pads overlaps with the first semiconductor chip and is covered by the first semiconductor chip and with the remaining pads of the second chip pads being exposed through the opening. The redistribution layer includes redistribution pads, exposed through the opening, and includes redistribution lines, configured to connect the one or more of the second chip pads to the redistribution pads. | 2021-01-14 |
20210013181 | SEMICONDUCTOR PACKAGE - A package-on-package type package includes a lower semiconductor package and an upper semiconductor package. The lower semiconductor package includes a first semiconductor device including a through electrode, a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode, a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device, a second molding member covering a sidewall of the first molding member, and an upper redistribution layer disposed on the second semiconductor device and electrically connected to the second through electrode. | 2021-01-14 |
20210013182 | Opposing Planar Electrically Conductive Surfaces Connected for Establishing a Two-Dimensional Electric Connection Area Between Component Carrier Stacks - A component carrier with a first stack and a second stack. The first stack includes at least one first electrically insulating layer structure and at least one first electrically conductive layer structure having a first connection body with a first exposed planar electrically conductive surface. The second stack includes at least one second electrically insulating layer structure and at least one second electrically conductive layer structure having a second connection body with a second exposed planar electrically conductive surface. The first stack and the second stack are connected with each other so that the first exposed planar electrically conductive surface and the second exposed planar electrically conductive surface are connected to establish a vertical two-dimensional electrically conductive connection. | 2021-01-14 |
20210013183 | SEMICONDUCTOR MODULE - A semiconductor module according to the present disclosure includes: an insulating substrate; a first conductor disposed on the insulating substrate; a second conductor disposed on the insulating substrate; a first semiconductor element disposed on the first conductor; a second semiconductor element disposed on the second conductor; a first busbar connected to the first conductor in a region between the first semiconductor element and the second semiconductor element; a second busbar connected to the second semiconductor element; and an output busbar connecting the first semiconductor element to the second conductor and connected to the second conductor in the region between the first semiconductor element and the second semiconductor element. The output busbar is disposed at least partially overlapping the first busbar, and in an overlap region between the output busbar and the first busbar, the output busbar is located above the first busbar. | 2021-01-14 |
20210013184 | LED TRANSFER METHOD AND DISPLAY MODULE MANUFACTURED THEREBY - A micro light emitting diode (LED) transfer method includes: preparing a transfer substrate including a plurality of micro LEDs, the plurality of micro LEDs having electrodes disposed in a first direction and a second direction different from the first direction on the transfer substrate; sequentially transferring a first set of micro LEDs among the plurality of micro LEDs in block units from the transfer substrate to first regions of a target substrate; and sequentially transferring a second set of micro LEDs among the plurality of micro LEDs in block units from the transfer substrate to second regions of the target substrate, and in the sequential transferring of the second set of micro LEDs, the second set of micro LEDs transferred to the second regions are disposed in the same electrode direction as an electrode direction of the first set of micro LEDs transferred to the first regions. | 2021-01-14 |
20210013185 | Full Spectrum White Light Emitting Devices - A full spectrum white light emitting device includes photoluminescence materials which generate light with a peak emission wavelength in a range from about 490 nm to about 680 nm; and a broadband solid-state excitation source operable to generate broadband excitation light with a dominant wavelength in a range from about 420 nm to about 480 nm. The device is operable to generate white light with a Correlated Color Temperature in a range from about 1800K to about 6800K, a CRI R9 less than 90, a spectrum whose intensity decreases from its maximum value in the orange to red region of the spectrum to about 50% of the maximum value at a wavelength in a range from about 645 nm to about 695 nm, and over a wavelength range from about 430 nm to about 520 nm, a maximum percentage intensity deviation of light emitted by the device is less than 60% from the intensity of light of at least one of a black-body curve and CIE Standard Illuminant D of the same Correlated Color Temperature. | 2021-01-14 |