02nd week of 2021 patent applcation highlights part 60 |
Patent application number | Title | Published |
20210013186 | LIGHTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A lighting device and a related manufacturing method are provided. The lighting device includes a substrate and at least one lighting unit formed on the substrate. The lighting unit includes an accommodating hole and a first light emitting diode spaced apart from the accommodating hole. The accommodating hole is for a second light emitting diode. | 2021-01-14 |
20210013187 | LIGHT EMITTING DEVICE - A light emitting device includes: a substrate including a base member including an upper surface, a lower surface and one or more lateral surfaces, and defining a recess that is opened at the upper surface and the lateral surfaces and surrounds an outer perimeter of the upper surface; a first light emitting element; a second light emitting element; a light guide member covering the first and the second light emitting elements and the upper surface of the base member; and a first reflective member having a closed-ring shape surrounding the upper surface of the base member and the light guide member, a portion of the first reflective member being located in the recess. At least one of the lateral surfaces of the base member and corresponding at least one of one or more outer lateral surfaces of the first reflective member are in the same plane. | 2021-01-14 |
20210013188 | PACKAGE ON ACTIVE SILICON SEMICONDUCTOR PACKAGES - Systems and methods for providing a low profile stacked die semiconductor package in which a first semiconductor package is stacked with a second semiconductor package and both semiconductor packages are conductively coupled to an active silicon substrate that communicably couples the first semiconductor package to the second semiconductor package. The first semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a first interconnect pattern having a first interconnect pitch. The second semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a second interconnect pattern having a second pitch that is greater than the first pitch. The second semiconductor package may be stacked on the first semiconductor package and conductively coupled to the active silicon substrate using a plurality of conductive members or a plurality of wirebonds. | 2021-01-14 |
20210013189 | SEMICONDUCTOR PACKAGE - Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a first semiconductor chip on a first substrate, a first molding layer covering a sidewall of the first semiconductor chip and including at least two guide holes that expose the first substrate and are spaced apart from each other in a periphery of the first substrate, a second substrate on the first molding layer, a connection terminal between the first substrate and the second substrates and connecting the first and second substrates to each other, and an alignment structure that extends from a bottom surface of the second substrate into each of the at least two guide holes of the first molding layer. A height of the alignment structure is greater than a height of the first molding layer and the first semiconductor chip. | 2021-01-14 |
20210013190 | PIXEL STRUCTURE, DISPLAY APPARATUS INCLUDING THE PIXEL STRUCTURE, AND METHOD OF MANUFACTURING THE PIXEL STRUCTURE - A pixel structure of a display apparatus includes an electrode line, at least one ultra small light-emitting diode, and a connection electrode. The electrode line includes a second electrode separated from a first electrode and at a same level as the first electrode on a base substrate. The at least one ultra small light-emitting diode is on the base substrate and has a length less than a distance between the first and second electrodes. A connection electrode includes a first contact electrode connecting the first electrode to the ultra small light-emitting diode and a second contact electrode connecting the second electrode to the ultra small light-emitting diode. | 2021-01-14 |
20210013191 | PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - Provided are a package structure and a method of manufacturing the same. The package structure includes a die, a first passive device, a plurality of through insulator vias (TIVs), an encapsulant, and a plurality of conductive connectors. The die has a front side and a backside opposite to each other. The first passive device is disposed aside the die. The TIVs are disposed between the die and the first passive device. The encapsulant laterally encapsulates the TIVs, the first passive device, and the die. The conductive connectors are disposed on the backside of the die, wherein the conductive connectors are electrically connected to the die and the first passive device by a plurality of solders. | 2021-01-14 |
20210013192 | TRANSIENT VOLTAGE SUPRESSOR WITH A PUNCH-THROUGH SILICON CONTROLLED RECTIFIER LOW-SIDE STEERING DIODE - A transient voltage suppressor (TVS) device uses a punch-through silicon controlled rectifier (SCR) structure for the low-side steering diode where the punch-through SCR structure realizes low capacitance at the protected node. In some embodiments, the punch-through silicon controlled rectifier of the low-side steering diode includes a first doped region formed in a first epitaxial layer, a first well formed spaced apart from the first doped region where the first well is not biased to any electrical potential, and a second doped region formed in the first well. The first doped region, the first epitaxial layer, the first well and the second doped region form the punch-through silicon controlled rectifier, with the first doped region forming the anode and the second doped region forming the cathode of the punch-through silicon controlled rectifier. | 2021-01-14 |
20210013193 | ESD PROTECTION DEVICE WITH DEEP TRENCH ISOLATION ISLANDS - An electronic device includes a substrate having a second conductivity type including a semiconductor surface layer with a buried layer (BL) having a first conductivity type. In the semiconductor surface layer is a first doped region (e.g., collector) and a second doped region (e.g., emitter) both having the first conductivity type, with a third doped region (e.g., a base) having the second conductivity type within the second doped region, wherein the first doped region extends below and lateral to the third doped region. At least one row of deep trench (DT) isolation islands are within the first doped region each including a dielectric liner extending along a trench sidewall from the semiconductor surface layer to the BL with an associated deep doped region extending from the semiconductor surface layer to the BL. The deep doped regions can merge forming a merged deep doped region that spans the DT islands. | 2021-01-14 |
20210013194 | ELECTROSTATIC PROTECTION CIRCUIT, ARRAY SUBSTRATE, AND DISPLAY DEVICE - The present disclosure provides an electrostatic protection circuit, an array substrate, and a display device. The electrostatic protection circuit includes: a first voltage line, to which a high level voltage is applied; a second voltage line, to which a low level voltage is applied; and a switch assembly, including a plurality of first switch units and a plurality of second switch units arranged along a straight line and sharing an active layer. The first switch units are respectively coupled between the signal lines and the first voltage line, and are turned on in response to negative static electricity on the signal lines. The second switch units are respectively coupled between the signal lines and the second voltage line, and are turned on in response to positive static electricity on the signal lines. The signal lines are arranged in a peripheral region of the array substrate. | 2021-01-14 |
20210013195 | SEMICONDUCTOR DEVICE FOR A LOW-LOSS ANTENNA SWITCH - A semiconductor device is disclosed. The semiconductor device includes a substrate, a metal-oxide-semiconductor device, and a feature. The metal-oxide-semiconductor device is disposed in the substrate. The feature is disposed adjacent to the metal-oxide-semiconductor device. The feature extends into the substrate with a first depth and the metal-oxide-semiconductor device extends into the substrate with a second depth smaller than the first depth. | 2021-01-14 |
20210013196 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device includes a MOS structure part and first to third temperature sensing portions. The MOS structure part has a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, trenches, and gate electrodes provided in the trenches via a gate insulating film. The first to the third temperature sensing portions are provided in plural and each includes the semiconductor substrate, the first semiconductor layer, a temperature sensing trench, a first polysilicon layer of the first conductivity type and a second polysilicon layer of the second conductivity type provided in the temperature sensing trench via an insulating film, a cathode electrode connected to the first polysilicon layer, and an anode electrode connected to the second polysilicon layer. | 2021-01-14 |
20210013197 | THIN FILM RESISTOR - A semiconductor device includes: a metal thin film disposed on a semiconductor substrate; and first and second contact structures disposed on the metal thin film, wherein the first and second contact structures are laterally spaced from each other by a dummy layer that comprises at least one polishing resistance material. | 2021-01-14 |
20210013198 | DEVICES AND METHODS FOR LAYOUT-DEPENDENT VOLTAGE HANDLING IMPROVEMENT IN SWITCH STACKS - Devices and methods for layout-dependent voltage handling improvement in switch stacks. In some embodiments, a switching device can include a first terminal and a second terminal, a radio-frequency signal path implemented between the first terminal and the second terminal, and a plurality of switching elements connected in series to form a stack between the second terminal and ground. The stack can have an orientation relative to the radio-frequency signal path, and the switching elements can have a non-uniform distribution of a first parameter based in part on the orientation of the stack. | 2021-01-14 |
20210013199 | INTEGRATED CIRCUIT DEVICES WITH NON-COLLAPSED FINS AND METHODS OF TREATING THE FINS TO PREVENT FIN COLLAPSE - An integrated circuit device with a substrate and a plurality of fins is provided where fin width is less than 11 nanometers, fin height is greater than 155 nanometers and spacing between any two neighboring fins is less than 30 nanometers and each fin is in non-collapsed state. An integrated circuit device with a substrate and a plurality of fins is provided where fin width is less than 15 nanometers, fin height is greater than 190 nanometers and spacing between any two neighboring fins is less than 30 nanometers and each fin is in non-collapsed state. A method for forming a fin-based transistor structure is provided where a plurality of fins on a substrate are pre-treated with at least one of a self-assembled monolayer, a non-polar solvent, and a surfactant. One or more of these treatments is to reduce adhesion and/or cohesive forces to prevent occurrence of fin collapse. | 2021-01-14 |
20210013200 | SEMICONDUCTOR DEVICE HAVING GATE ISOLATION LAYER - A semiconductor device includes a substrate having a first region and a second region, first active fins that extend in a first direction in the first region, second active fins that extend in the first direction in the second region, a first field insulating layer between the first active fins and that extend in a second direction, a second field insulating layer between the second active fins and extending in the second direction, a gate line that extends in the second direction on the second field insulating layer, the gate line linearly along with the first field insulating layer, a gate isolation layer between the first field insulating layer and the gate line, and gate spacers that extend in the second direction, the gate spacers in contact with both sidewalls of each of the first field insulating layer, the gate line, and the gate isolation layer. | 2021-01-14 |
20210013201 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING A STANDARD CELL WHICH INCLUDES A FIN - Disclosed herein is a semiconductor integrated circuit device including a standard cell with a fin extending in a first direction. The fin and a gate line extending in a second direction perpendicular to the first direction and provided on the fin constitute an active transistor. The fin and a dummy gate line provided in parallel with the gate line constitute a dummy transistor. The active transistor shares a node as its source or drain with the dummy transistor. | 2021-01-14 |
20210013202 | SILICON CARBIDE MOSFET WITH SOURCE BALLASTING - A method for making an integrated device that includes a plurality of planar MOSFETs, includes forming a plurality of doped body regions in an upper portion of a silicon carbide substrate composition and a plurality of doped source regions. A first contact region is formed in a first source region and a second contact region is formed in a second source region. The first and second contact regions are separated by a JFET region that is longer in one planar dimension than the other. The first and second contact regions are separated by the longer planar dimension. The JFET region is bounded on at least one side corresponding to the longer planar dimension by a source region and a body region in conductive contact with at least one contact region. | 2021-01-14 |
20210013203 | METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT - A method of manufacturing a semiconductor integrated circuit includes a first ion implantation process implanting impurity ions of a second conductivity type into a bottom surface of a semiconductor substrate by adjusting an acceleration voltage and a projection range for forming a first current suppression layer, and a second ion implantation process implanting impurity ions of a first conductivity type into the bottom surface of the semiconductor substrate by adjusting an acceleration voltage and a projection range for forming a second current suppression layer. The semiconductor integrated circuit includes a first well region of the first conductivity type and a second well region of the second conductivity type provided in an upper portion of the first well region. The first current suppression layer is separated from the first well region and the second current suppression layer is provided under the first current suppression layer. | 2021-01-14 |
20210013204 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes pattering an upper portion of a substrate to form a first active pattern, the substrate including a semiconductor element having a first lattice constant, performing a selective epitaxial growth process on an upper portion of the first active pattern to form a first source/drain region, doping the first source/drain region with gallium, performing an annealing process on the first source/drain region doped with gallium, and forming a first contact pattern coupled to the first source/drain region. The first source/drain region includes a semiconductor element having a second lattice constant larger than the first lattice constant. | 2021-01-14 |
20210013205 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin, third fin, and fourth fin. A dielectric layer is formed over fins and a work function adjustment layer is formed over dielectric layer. A hard mask is formed covering third and fourth fins. A first conductive material layer is formed over first fin and not over second fin. A second conductive material layer is formed over first and second fins. A first metal gate electrode fill material is formed over first and second fins. The hard mask covering third and fourth fins is removed. A third conductive material layer is formed over third fin and not over fourth fin. A fourth conductive material layer is formed over third and fourth fins, and a second metal gate electrode fill material is formed over third and fourth fins. | 2021-01-14 |
20210013206 | SEMICONDUCTOR DEVICE - A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode running across the active pattern and extending in a second direction intersecting the first direction, a source/drain pattern on the active pattern and adjacent to a side of the gate electrode, an active contact in a contact hole exposing the source/drain pattern, an insulating pattern filling a remaining space of the contact hole in which the active contact is provided, a first via on the active contact, and a second via on the gate electrode. The active contact may include a first segment that fills a lower portion of the contact hole and a second segment that vertically protrudes from the first segment. The first via is connected to the second segment. The insulating pattern is adjacent in the first direction to the second via. | 2021-01-14 |
20210013207 | SEMICONDUCTOR DEVICES WITH NANOWIRES AND METHODS FOR FABRICATING THE SAME - A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size. | 2021-01-14 |
20210013208 | GATED THYRISTORS - Disclosed herein are gated thyristors and related devices and techniques. In some embodiments, an integrated circuit (IC) device may include a metal portion and a gated thyristor on the metal portion. The gated thyristor may include a stack of alternating p-type and n-type material layers, and the stack may be on the metal portion. The IC device may further include a gate line spaced apart from one of the material layers by a gate dielectric. | 2021-01-14 |
20210013209 | DYNAMIC RANDOM-ACCESS MEMORY AND METHOD OF MANUFACTURING THE SAME - Provided is a DRAM including a substrate, first bit line structures, second bit line structures, and word line structures. The substrate has active regions each including pillar structures arranged along a first direction. Two first bit line structures extended along the first direction and buried in the substrate are disposed between the active regions arranged along a second direction. Each second bit line structure is located between the pillar structures and extended through the active regions along the second direction to be disposed on the first bit line structures and electrically connected to the first bit line structures. The word line structures are disposed on and spaced apart from the second bit line structures. Each word line structure extended along the second direction is located between the pillar structures and passes through the active regions arranged along the second direction. A manufacturing method of the DRAM is also provided. | 2021-01-14 |
20210013210 | VERTICAL MEMORY DEVICE - Disclosed is a vertically stacked 3D memory device, and the memory device may include a bit line extended vertically from a substrate, and including a first vertical portion and a second vertical portion, a vertical active layer configured to surround the first and second vertical portions of the bit line, a word line configured to surround the vertical active layer and the first vertical portion of the bit line, and a capacitor spaced apart vertically from the word line, and configured to surround the vertical active layer and the second vertical portion of the bit line. | 2021-01-14 |
20210013211 | DRAM SEMICONDUCTOR DEVICE HAVING REDUCED PARASITIC CAPACITANCE BETWEEN CAPACITOR CONTACTS AND BIT LINE STRUCTURES AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are provided. The method includes forming a plurality of bit line structures on a semiconductor substrate, wherein there is a plurality of trenches between the bit line structures. The method also includes forming a first oxide layer conformally covering the bit line structures and the trenches, and forming a photoresist material layer in the trenches and on the first oxide layer, wherein the photoresist material layer has an etch selectivity that is higher than that of the first oxide layer. The method further includes removing the photoresist material layer to form a plurality of capacitor contact holes between the bit line structures, and forming a capacitor contact in the capacitor contact holes. | 2021-01-14 |
20210013212 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING SPACER - A semiconductor device includes a substrate, a first impurity implantation region and a second impurity implantation region on the substrate and spaced apart from each other, a storage node contact in contact with the first impurity implantation region, the storage node contact including an upper contact having a first width, and a lower contact having a second width that is greater than the first width at a lower portion of the upper contact, a bit line electrically connected to the second impurity implantation region and configured to cross the substrate, a bit line node contact between the bit line and the second impurity implantation region, and a spacer between the storage node contact and the bit line and between the storage node contact and the bit line node contact. | 2021-01-14 |
20210013213 | APPARATUS INCLUDING BARRIER MATERIALS WITHIN ACCESS LINE STRUCTURES, AND RELATED METHODS AND ELECTRONIC SYSTEMS - An apparatus comprising a memory array comprising access lines. Each of the access lines comprises an insulating material adjacent a bottom surface and sidewalls of a base material, a first conductive material adjacent the insulating material, a second conductive material adjacent the first conductive material, and a barrier material between the first conductive material and the second conductive material. The barrier material is configured to suppress migration of reactive species from the second conductive material. Methods of forming the apparatus and electronic systems are also disclosed. | 2021-01-14 |
20210013214 | APPARATUS INCLUDING ACCESS LINE STRUCTURES AND RELATED METHODS AND ELECTRONIC SYSTEMS - An apparatus comprising a memory array comprising wordlines, bit lines, and memory cells. Each memory cell is coupled to an associated one of the wordlines and an associated one of the bit lines. Each of the wordlines is buried in a substrate and comprises a lower conductive material, an upper conductive material, and an oxidation material of the lower conductive material between the lower conductive material and the upper conductive material. In additional embodiments, the apparatus comprises access lines, digit lines, and memory cells. The access lines comprise an oxidized material between a first conductive material and a second conductive material, the oxidized material comprising an oxide of the first conductive material. Methods of forming the apparatus and electronic systems are also disclosed. | 2021-01-14 |
20210013215 | STATIC RANDOM ACCESS MEMORY - An SRAM (static random access memory) includes a semiconductor substrate; a plurality of PD transistors, each including a first fin structure formed on the semiconductor substrate, a PD gate structure formed across the first fin structure and covering a portion of a top and sidewall surfaces of the first fin structure, and a first source/drain doped layer formed in the first fin structure on both sides of the PD gate structure; a plurality of adjacent transistors, each including a second fin structure formed on the semiconductor substrate and a second source/drain doped layer formed in the second fin structure; an isolation layer, formed on the semiconductor substrate; a fin sidewall film, formed on the isolation layer and covering sidewall surfaces of each PD gate structure; and a first PD dielectric layer, formed on the isolation layer and covering sidewall surfaces of the first source/drain doped layer. | 2021-01-14 |
20210013216 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device may include a first cell structure, a second cell structure, a pad structure, a circuit, and an opening. The pad structure may include a first stepped structure and a second stepped structure located between the first cell structure and the second cell structure. The first stepped structure may include first pads electrically connected to the first and second cell structures and stacked on top of each other, and the second stepped structure may include second pads electrically connected to the first and second cell structures and stacked on top of each other. The circuit may be located under the pad structure. The opening may pass through the pad structure to expose the circuit, and may be located between the first stepped structure and the second stepped structure to insulate the first pads and the second pads from each other. | 2021-01-14 |
20210013217 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate having a first region and a second region, a first semiconductor element positioned in the first region of the substrate, a second semiconductor element positioned in the first region of the substrate, a bridge conductive unit electrically connected the first semiconductor element and the second semiconductor element, and a programmable unit positioned in the second region and electrically connected to the bridge conductive unit. | 2021-01-14 |
20210013218 | SEMICONDUCTOR STORAGE DEVICE, MANUFACTURING METHOD OF SEMICONDUCTOR STORAGE DEVICE, AND ELECTRONIC DEVICE - A semiconductor storage device and an electronic device that include a ferroelectric capacitor having a more optimized structure, as a memory cell are provided. A semiconductor storage device includes a field-effect transistor provided in an active region of a semiconductor substrate, a ferroelectric capacitor including a first capacitor electrode and a second capacitor electrode sandwiching a ferroelectric film, the first capacitor electrode being electrically connected to one of a source or a drain of the field-effect transistor, a source line electrically connected to the second capacitor electrode of the ferroelectric capacitor, and a bit line electrically connected to another one of the source or the drain of the field-effect transistor, in which a gate electrode of the field-effect transistor extends in a first direction across the active region, and the source line and the bit line extend in a second direction orthogonal to the first direction. | 2021-01-14 |
20210013219 | SEMICONDUCTOR STORAGE DEVICE AND MULTIPLIER-ACCUMULATOR - A semiconductor storage device and a multiplier-accumulator are provided that are capable of applying a sufficient voltage to a ferroelectric capacitor and are suitable for high integration. A semiconductor storage device includes: a transistor; and a ferroelectric capacitor that is formed by sandwiching a ferroelectric material between a pair of conductive materials, one of the pair of conductive materials being electrically connected to a gate electrode of the transistor, in which a channel of the transistor is three-dimensionally formed over a plurality of surfaces. | 2021-01-14 |
20210013220 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device is provided. The semiconductor device includes a semiconductor substrate and a first gate stack. An isolation feature is formed in the semiconductor substrate, and a cell region and a peripheral region adjacent to the cell region are defined in the semiconductor substrate. The first gate stack is disposed on the peripheral region of the semiconductor substrate. The first gate stack includes a first dielectric layer and a gate electrode layer disposed on the first dielectric layer and covering a top surface of the first dielectric layer. The first dielectric layer is disposed on the semiconductor substrate and has a concave profile. | 2021-01-14 |
20210013221 | Memory Arrays And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells And Operative Through-Array-Vias - A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region. At least a majority of channel material of the dummy channel-material strings is replaced in the TAV region with insulator material and operative TAVs are formed in the TAV region. Other methods and structures independent of method are disclosed. | 2021-01-14 |
20210013222 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device according to an embodiment of the present disclosure may include forming a first sacrificial layer including a first portion and a second portion having a thickness thicker than a thickness of the first portion, forming a stack including first material layers and second material layers alternating with each other on the first sacrificial layer, forming a channel structure passing through the stack and extending to the first portion, forming a slit passing through the stack and extending to the second portion, removing the first sacrificial layer through the slit to form a first opening, and forming a second source layer connected to the channel structure in the first opening. | 2021-01-14 |
20210013223 | MEMORY DEVICE - A memory device with large storage capacity is provided. A NAND memory device includes a plurality of connected memory elements each provided with a writing transistor and a reading transistor. An oxide semiconductor is used in a semiconductor layer of the writing transistor, whereby a storage capacitor is not necessary or the size of the storage capacitor can be reduced. The reading transistor includes a back gate. When a reading voltage is applied to the back gate, data stored in the memory element is read out. | 2021-01-14 |
20210013224 | PROCESS FOR A 3-DIMENSIONAL ARRAY OF HORIZONTAL NOR-TYPE MEMORY STRINGS - In the highly efficient fabrication processes for HNOR arrays provided herein, the channel regions of the storage transistors in the HNOR arrays are protected by a protective layer after deposition until the subsequent deposition of a charge-trapping material before forming local word lines. Both the silicon for the channel regions and the protective material may be deposited in amorphous form and are subsequently crystallized in an anneal step. The protective material may be silicon boron, silicon carbon or silicon germanium. The protective material induces greater grain boundaries in the crystallized silicon in the channel regions, thereby providing greater charge carrier mobility, greater conductivity and greater current densities. | 2021-01-14 |
20210013225 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor storage device includes a stacked body in which a plurality of conducting layers are stacked through a plurality of insulating layers in a first direction, a semiconductor layer penetrating the stacked body, extending in the first direction and including metal atoms, and a memory film including a first insulator, a charge storage layer and a second insulator that are provided between the stacked body and the semiconductor layer. The semiconductor layer surrounds a third insulator penetrating the stacked body and extending in the first direction, and at least one crystal grain in the semiconductor layer has a shape surrounding the third insulator. | 2021-01-14 |
20210013226 | Memory Arrays - A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. The individual memory cells comprise a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode electrically couples to the first source/drain region. Wordline structures extend elevationally through the insulative material and the memory cells of the vertically-alternating tiers. Individual of the gates that are in different of the memory cell tiers directly electrically couple to individual of the wordline structures. Sense-lines electrically couple to multiple of the second source/drain regions of individual of the transistors. Other embodiments are disclosed. | 2021-01-14 |
20210013227 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes wirings arranged in parallel along a first direction, the wirings including first and second wirings that are adjacent and a third wiring adjacent to the second wiring, a first pillar between the first and second wirings and a second pillar between the second and third wirings, the first and second pillars each extending in a second direction crossing the first direction toward the semiconductor substrate, and first and second bit lines connected to the first and second pillars, respectively. A first voltage is applied to the second wiring during a program operation on a first memory cell at an intersection of the second wiring and the first pillar, and a second voltage higher than the first voltage is applied to the second wiring during a program operation on a second memory cell at an intersection of the second wiring and the second pillar. | 2021-01-14 |
20210013228 | ELECTRONIC DEVICES AND SYSTEMS WITH CHANNEL OPENINGS OR PILLARS EXTENDING THROUGH A TIER STACK, AND METHODS OF FORMATION - Device, systems, and structures include a stack of vertically-alternating tiers of materials arranged in one or more decks of tiers. A channel opening, in which a channel pillar may be formed, extends through the stack. The pillar includes a “shoulder portion” extending laterally into an “undercut portion” of the channel opening, which undercut portion is defined along at least a lower tier of at least one of the decks of the stack. | 2021-01-14 |
20210013229 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises: a substrate; a first semiconductor portion provided separated from the substrate in a first direction intersecting a surface of the substrate, the first semiconductor portion extending in a second direction intersecting the first direction; a first gate electrode extending in the first direction; a first insulating portion which is provided between the first semiconductor portion and the first gate electrode, includes hafnium (Hf) and oxygen (O), and includes an orthorhombic crystal as a crystal structure; a first conductive portion provided between the first semiconductor portion and the first insulating portion; and a second insulating portion provided between the first semiconductor portion and the first conductive portion. An area of a facing surface of the first conductive portion facing the first semiconductor portion is larger than an area of a facing surface of the first conductive portion facing the first gate electrode. | 2021-01-14 |
20210013230 | INTEGRATED CIRCUIT INCLUDING CLUBFOOT STRUCTURE CONDUCTIVE PATTERNS - An integrated circuit includes a standard cell. The standard cell may include a plurality of gate lines and a plurality of first wirings. The plurality of first wirings may include a clubfoot structure conductive pattern that includes a first conductive pattern and a second conductive pattern spaced apart from each other. Each of the first conductive pattern and the second conductive pattern may include a first line pattern extending in a first direction and a second line pattern protruding from one end of the first line pattern in a direction perpendicular to the first direction. The plurality of gate lines may be spaced apart from each other by a first pitch in the first direction, and the plurality of second wirings may be spaced apart from each other by a second pitch in the first direction. The first pitch may be greater than the second pitch. | 2021-01-14 |
20210013231 | ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, DISPLAY PANEL AND DISPLAY DEVICE - The present disclosure relates to an array substrate, a method for manufacturing the same, a display panel, and a display device. The array substrate includes: a gate metal layer, disposed on the substrate and the gate metal layer including a grounding wire located in the peripheral region; a gate insulating layer, at least covering the gate metal layer; and a conductive layer structure, disposed over the gate insulating layer and including an auxiliary grounding wire located in the peripheral region, wherein the auxiliary grounding wire is connected to the grounding wire. The present disclosure can prevent ESD more effectively. | 2021-01-14 |
20210013232 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY PANEL - The present disclosure provides an array substrate, a method of manufacturing the same, and a display panel. The array substrate includes a base substrate, a thin film transistor disposed at a side of the base substrate. The thin film transistor includes a first electrode, a second electrode, and a gate electrode. The array substrate includes a data line disposed at the side of the base substrate The array substrate includes a connection electrode electrically connecting the first electrode of the thin film transistor to the data line. An orthographic projection of an active layer of the thin film transistor on the base substrate is located within an orthographic projection of the gate electrode of the thin film transistor on the base substrate. | 2021-01-14 |
20210013233 | ARRAY SUBSTRATE, MANUFACTURING METHOD, DISPLAY PANEL AND DISPLAY DEVICE THEREOF - Arrangements disclosed in the present disclosure provide an array substrate, a manufacturing, a display panel and a display device. The array substrate comprises: a first signal line comprising a first extension portion along a first direction and a first connection portion along a second direction, which is provided with via holes; a second signal line comprising a second extension portion and a second connection portion along the second direction, which is provided with via holes; and a conductive connection layer, configured to connect the first signal line and the second signal line through the via holes of the first connection portion and second connection portion. The first connection portion and the second connection portion are lined up in a direction perpendicular to the second direction. | 2021-01-14 |
20210013234 | ELECTRONIC DEVICES - An electronic device is provided. The electronic device includes a substrate, a first gate circuit, a second gate circuit, a signal line, and a shielding layer. The substrate includes a display area and a peripheral area. The first gate circuit is disposed in the peripheral area. The second gate circuit is disposed in the peripheral area. The signal line is coupled between the first gate circuit and the second gate circuit. The signal line includes a specific line segment, and the specific line segment overlaps the display area. The shielding layer is disposed in the display area. The shielding layer overlaps the specific line segment. | 2021-01-14 |
20210013235 | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE - A semiconductor device including: a first gate electrode; a first gate insulating layer on the first gate electrode; a first oxide semiconductor layer on the first insulating layer; source and drain electrodes connected to the first oxide semiconductor layer; a second gate insulating layer on the first oxide semiconductor layer; a second oxide semiconductor layer on the second gate insulating layer; a second gate electrode on the second oxide semiconductor layer, the second gate electrode being in contact with the second oxide semiconductor layer; a first insulating layer on the second gate electrode, the first insulating layer having a part of a first aperture overlapping with the second oxide semiconductor layer in a planar view; and a first connecting electrode electrically connecting the first gate electrode and the second gate electrode via the first aperture. | 2021-01-14 |
20210013236 | LED LIGHTING DEVICE PACKAGE AND DISPLAY PANEL USING THE SAME - A light emitting device package includes: a plurality of light emitting structures, each having a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer; a common first electrode extended in parallel with first and second surfaces of the plurality of light emitting structures at a level different from levels of the first and second surfaces while connecting respective first conductivity-type semiconductor layers of the plurality of light emitting structures; a plurality of second electrodes connected to respective second conductivity-type semiconductor layers of the plurality of light emitting structures; a plurality of wavelength converters; and a molded portion having a partition wall structure separating the plurality of wavelength converters from each other, and including a material having a modulus lower than a modulus of the plurality of light emitting structures. | 2021-01-14 |
20210013237 | DISPLAY PANEL AND METHOD FOR MANUFACTURING SAME - A display panel and a method for manufacturing the display panel are provided. The display panel includes a planar region and a bending region. The display panel includes a flexible substrate and a driving circuit layer. The flexible substrate at least includes a first flexible layer, a barrier layer and a second flexible layer. The driving circuit layer is disposed at a side of the second flexible layer away from the barrier layer. In the bending region, a groove is disposed at a side of the first flexible layer away from the barrier layer. The technical problem of stress concentration in the bending region is alleviated by disposing the groove. | 2021-01-14 |
20210013238 | ACTIVE MATRIX SUBSTRATE AND METHOD FOR MANUFACTURING SAME - An active matrix substrate includes a substrate; a plurality of gate bus lines and a plurality of source bus lines; an oxide semiconductor TFT that includes an oxide semiconductor layer, a gate insulating layer, and a gate electrode; a pixel electrode; and an upper insulating layer. The oxide semiconductor layer includes a high resistance region, and a first region and a second region. The high resistance region includes a channel region, a first channel offset region, and a second channel offset region. The upper insulating layer is disposed so as to overlap the channel region, the first channel offset region, and the second channel offset region, and so as not to overlap any of the first region and the second region, when viewed from the normal direction of the main surface of the substrate. | 2021-01-14 |
20210013239 | SEMICONDUCTOR DEVICE, DISPLAY DEVICE INCLUDING THE SEMICONDUCTOR DEVICE, DISPLAY MODULE INCLUDING THE DISPLAY DEVICE, AND ELECTRONIC DEVICE INCLUDING THE SEMICONDUTOR DEVICE, THE DISPLAY DEVICE, AND THE DISPLAY MODULE - To provide a semiconductor device including a planar transistor having an oxide semiconductor and a capacitor. In a semiconductor device, a transistor includes an oxide semiconductor film, a gate insulating film over the oxide semiconductor film, a gate electrode over the gate insulating film, a second insulating film over the gate electrode, a third insulating film over the second insulating film, and a source and a drain electrodes over the third insulating film; the source and the drain electrodes are electrically connected to the oxide semiconductor film; a capacitor includes a first and a second conductive films and the second insulating film; the first conductive film and the gate electrode are provided over the same surface; the second conductive film and the source and the drain electrodes are provided over the same surface; and the second insulating film is provided between the first and the second conductive films. | 2021-01-14 |
20210013240 | DISPLAY PANEL AND ORGANIC LIGHT RMITTING DISPLAY PANEL - An array substrate and a display panel; the array substrate includes a substrate ( | 2021-01-14 |
20210013241 | TOUCH DISPLAY DEVICE - A touch display device includes a substrate, first light emitting units, second light emitting units, an insulation layer, and mesh units. The first and the second light emitting units are disposed on the substrate. The second light emitting units are greater than the first light emitting units in area. The insulation layer is disposed on the first and the second light emitting units. The mesh units are disposed on the insulation layer. Each of the mesh units has a mesh frame and a mesh opening. At least one of the first light emitting units and at least one of the second light emitting units are disposed in the mesh opening respectively. A gap is disposed between a first end portion of at least one of the mesh frames and a second end portion of the mesh frame, and the first end portion is electrically connected to the second end portion. | 2021-01-14 |
20210013242 | FLEXIBLE ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, FLEXIBLE DISPLAY DEVICE - Embodiments of the present disclosure provide a flexible array substrate, a manufacturing method thereof, and a flexible display device, which relate to the field of display technology, and can reduce the difficulty of wiring, decrease the IR drop, and improve the problem that the wiring is prone to breakage when bent. The flexible array substrate includes a substrate, the substrate including a first sub-substrate and a second sub-substrate which are stacked, the second sub-substrate including a via hole, a wiring layer disposed between the first sub-substrate and the second sub-substrate, and a pixel array layer disposed on a side of the second sub-substrate facing away from the first sub-substrate, the wiring layer including a wiring, wherein the pixel array layer is electrically connected to the wiring through the via hole. | 2021-01-14 |
20210013243 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE - An array substrate, manufacturing method thereof, and a display device according to some arrangements of the present disclosure include: a first transistor and a second transistor; an active layer of the second transistor is disposed on a side of the interlayer dielectric layer of the first transistor away from the substrate; an insulating layer is disposed between the interlayer dielectric layer of the first transistor and the active layer of the second transistor, and the insulating layer has an ability to block hydrogen. | 2021-01-14 |
20210013244 | ACTIVE-MATRIX SUBSTRATE AND DISPLAY DEVICE - An active matrix substrate includes a plurality of first contact holes extending through an inorganic insulating film, a first protection layer that is a silicon nitride film, and a second protection layer, a plurality of second contact holes extending through the inorganic insulating film and the second protection layer, a first transistor, and a second transistor. A channel region of the second transistor does not overlap the first protection layer. | 2021-01-14 |
20210013245 | THIN-FILM TRANSISTOR SUBSTRATE - A thin-film transistor substrate includes an insulating substrate, a first insulating layer, a first thin-film transistor including a first oxide semiconductor film, a second insulating layer located upper than the first insulating layer, and a second thin-film transistor including a second oxide semiconductor film different in composition from the first oxide semiconductor film. At least a part of the first oxide semiconductor film is provided above and in contact with the first insulating layer. The first insulating layer is the uppermost insulating layer among insulating layers located lower than and in contact with the first oxide semiconductor film. At least a part of the second oxide semiconductor film is provided above and in contact with the second insulating layer. The second insulating layer is the uppermost insulating layer among insulating layers located lower than and in contact with the second oxide semiconductor film. | 2021-01-14 |
20210013246 | DISPLAY SUBSTRATE, MANUFACTURING METHOD THEREOF, DISPLAY PANEL, AND DISPLAY DEVICE - A display substrate, a manufacturing method thereof, a display panel, and a display device are provided. The method for manufacturing a display substrate includes: forming a thin film transistor on a base substrate; forming a planarization layer covering the thin film transistor; forming a metal mask layer on the planarization layer; patterning the metal mask layer to form an etching hole in the metal mask layer, the etching hole exposing a portion of the planarization layer; etching the portion of the planarization layer exposed by the etching hole to form a first via hole penetrating the planarization layer, and removing a remaining metal mask layer on the planarization layer. | 2021-01-14 |
20210013247 | MANUFACTURING METHOD OF DISPLAY PANEL - A manufacturing method of a display panel includes providing a substrate having a first surface and a second surface opposite to the first surface; forming a high-shielding position layer on the first surface, wherein the light-shielding positioning layer has at least one first alignment pattern; forming a transparent material layer on the second surface; forming a photoresist layer on the transparent material layer; performing an exposure process, such that a light beam passes through the at least one first alignment pattern to penetrate through the substrate and the transparent material layer to the photoresist layer; performing a developing process to pattern the photoresist layer and form a patterned photoresist layer; and performing an etching process to pattern the transparent positioning layer having at least one second alignment pattern. In a direction perpendicular to the substrate, at least one first alignment pattern overlaps with at least one second alignment pattern. | 2021-01-14 |
20210013248 | PIXEL UNIT AND MANUFACTURING METHOD THEREFOR, AND SENSOR AND SENSING ARRAY - A pixel unit and a manufacturing method thereof, a sensor, and a sensor array are provided. The pixel unit comprises: a photosensitive unit, configured to generate a photo-generated carrier according to received radiation; at least two transmission units, connected between the photosensitive unit and at least two floating diffusion nodes, and configured to transfer the photo-generated carrier from the photosensitive unit to the at least two floating diffusion nodes; and the at least two floating diffusion nodes, configured to store and output the photo-generated carrier generated by the photosensitive unit. Among the at least two floating diffusion nodes, the floating diffusion node spaced by more transmission units from the photosensitive unit has a lower electric potential. Forming an electric potential difference between at least two stages of floating diffusion nodes facilitates high-speed transfer of the photo-generated carrier, increases charge transfer speed, and thereby improves charge transfer efficiency. | 2021-01-14 |
20210013249 | IMAGE SENSOR - An image sensor includes a substrate configured to include a plurality of pixels, each pixel including a photodiode formed in the substrate, a plurality of deep trench isolation (DTI) structures formed in the substrate to optically isolate each of the plurality of pixels from neighboring pixels, and a transparent electrode layer arranged over the photodiode and electrically connected to the plurality of DTI structures. | 2021-01-14 |
20210013250 | IMAGE SENSOR INCLUDING A FIRST AND A SECOND ISOLATION LAYER - An image sensor is provided comprising a substrate comprising first and second surfaces opposite to each other. A first isolation layer is disposed on the substrate and forms a boundary of a sensing region. A second isolation layer is disposed at least partially in the substrate within the sensing region and has a closed line shape. A photoelectric conversion device is disposed within the closed line shape of the second isolation layer, and a color filter is disposed on the first surface of the substrate. | 2021-01-14 |
20210013251 | ACTIVE MATRIX SUBSTRATE AND METHOD FOR INSPECTING THE SAME - An active matrix substrate includes a pixel region including a plurality of pixels over a substrate and a frame region outside the pixel region. In the plurality of pixels, a plurality of photoelectric conversion elements are provided. In the frame region, an antistatic hole is provided. The pixel region and a portion of the frame region are covered with an insulating film, and the antistatic hole is bored through the insulating film. An antistatic wire is provided in the frame region so as to surround the pixel region, and has a surface exposed in the antistatic hole. | 2021-01-14 |
20210013252 | IMAGING DEVICE - An imaging device including a semiconductor substrate; a first pixel including a first photoelectric converter configured to convert incident light into charge, and a first diffusion region in the semiconductor substrate, configured to electrically connected to the first photoelectric converter and a second pixel including a second photoelectric converter, configured to convert incident light into charge, and a second diffusion region in the semiconductor substrate, configured to electrically connected to the second photoelectric converter, wherein an area of the first photoelectric converter is greater than an area of the second photoelectric converter in a plan view, both the first diffusion region and the second diffusion region overlap with the first photoelectric converter in the plan view, and neither the first diffusion region nor the second diffusion region overlaps with the second photoelectric converter in the plan view. | 2021-01-14 |
20210013253 | ELECTRONIC DEVICE - An electronic device includes: a capacitor; an insulating layer; at feast one trench provided in the insulating layer; and a first conductive plug, at least part of which is surrounded by the insulating layer. The capacitor includes: a first lower electrode provided along an inner wall of the at least one trench, a dielectric layer provided on the first lower electrode, and an upper electrode provided on the dielectric layer. At least part of the first conductive plug is positioned between an upper surface of the insulating layer and a lowermost portion of the at least one trench. | 2021-01-14 |
20210013254 | SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - The present technology relates to a solid-state imaging device capable of protecting a photoelectric conversion film with a sealing film that has excellent sealing properties and coverage, a method of manufacturing the solid-state imaging device, and an electronic apparatus. A solid-state imaging device includes: a photoelectric conversion film formed on the upper side of a semiconductor substrate; and a sealing film that is formed on the upper layer of the photoelectric conversion film and has a lower etching rate than that of silicon oxide. The present technology can be applied to solid-state imaging devices having a photoelectric conversion film on the upper side of a semiconductor substrate, and the like, for example. | 2021-01-14 |
20210013255 | MECHANISMS FOR FORMING IMAGE SENSOR DEVICE - An image sensor device is provided. The image sensor device includes a semiconductor substrate and a light sensing region in the semiconductor substrate. The image sensor device also includes a dielectric layer over the semiconductor substrate and a filter partially surrounded by the dielectric layer. The filter has a protruding portion protruding from a bottom surface of the dielectric layer. The image sensor device further includes a shielding layer between the dielectric layer and the semiconductor substrate and surrounding the protruding portion of the filter. In addition, the image sensor device includes a reflective element between the shielding layer and an edge of the light sensing region. | 2021-01-14 |
20210013256 | CHIP SCALE PACKAGE STRUCTURES - A chip scale package structure is provided. The chip scale package structure includes an image sensor chip and a chip. The image sensor chip includes a first redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the first redistribution layer. The chip includes a plurality of through silicon via (TSV) and a second redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the second redistribution layer. The area of the chip is smaller than that of the image sensor chip. The second redistribution layer of the chip bonds to the first redistribution layer of the image sensor chip. | 2021-01-14 |
20210013257 | PIXEL CIRCUIT AND METHOD OF OPERATING THE SAME IN AN ALWAYS-ON MODE - An embodiment method of operating an imaging device including a sensor array including a plurality of pixels, includes: capturing a first low-spatial resolution frame using a subset of the plurality of pixels of the sensor array; generating, using a processor coupled to the sensor array, a first depth map using raw pixel values of the first low-spatial resolution frame; capturing a second low-spatial resolution frame using the subset of the plurality of pixels of the sensor array; generating, using the processor, a second depth map using raw pixel values of the second low-spatial resolution frame; and determining whether an object has moved in a field of view of the imaging device based on a comparison of the first depth map to the second depth map. | 2021-01-14 |
20210013258 | SYSTEMS AND METHODS FOR TRANSFER OF MICRO-DEVICES - An apparatus for positioning micro-devices on a substrate includes one or more supports to hold a donor substrate and a destination substrate, an adhesive dispenser to deliver adhesive on micro-devices on the donor substrate, a transfer device including a transfer surface to transfer the micro-devices from the donor substrate to the destination substrate, and a controller. The controller is configured to operate the adhesive dispenser to selectively dispense the adhesive onto selected micro-devices on the donor substrate based on a desired spacing of the selected micro-devices on the destination substrate. The controller is configured to operate the transfer device such that the transfer surface engages the adhesive on the donor substrate to cause the selected micro-devices to adhere to the transfer surface and the transfer surface then transfers the selected micro-devices from the donor substrate to the destination substrate | 2021-01-14 |
20210013259 | MICRO LED GROUP SUBSTRATE, METHOD OF MANUFACTURING SAME, MICRO LED DISPLAY PANEL, AND METHOD OF MANUFACTURING SAME - Disclosed are a micro LED group substrate provided with a plurality of micro LEDs, a method of manufacturing the same, a micro LED display panel, and a method of manufacturing the same. More particularly, disclosed are a micro LED group substrate provided with a plurality of micro LEDs, a method of manufacturing the same, a micro LED display panel, and a method of manufacturing the same, wherein the need for a micro LED replacement process is eliminated. | 2021-01-14 |
20210013260 | Cooling for PMA (Perpendicular Magnetic Anisotropy) Enhancement of STT-MRAM (Spin-Torque Transfer-Magnetic Random Access Memory) Devices - A fabrication process for an STT MTJ MRAM device includes steps of cooling the device at individual or at multiple stages in its fabrication. The cooling process, which may be equally well applied during the fabrication of other multi-layered devices, is demonstrated to produce an operational device that is more resistant to adverse thermal effects during operation that would normally cause a similar device not so fabricated to lose stored data and otherwise fail to operate properly. | 2021-01-14 |
20210013261 | DATA STORAGE DEVICES INCLUDING A FIRST TOP ELECTRODE AND A DIFFERENT SECOND TOP ELECTRODE THEREON - Data storage devices are provided. A data storage device includes a memory transistor on a substrate and a data storage structure electrically connected to the memory transistor. The data storage structure includes a magnetic tunnel junction pattern and a top electrode on the magnetic tunnel junction pattern. The top electrode includes a first top electrode and a second top electrode on the first top electrode, and the first and second top electrodes include the same metal nitride. The first top electrode includes first crystal grains of the metal nitride, and the second top electrode includes second crystal grains of the metal nitride. In a section of the top electrode, the number of the first crystal grains per a unit length is greater than the number of the second crystal grains per the unit length. | 2021-01-14 |
20210013262 | MEMORY ELEMENT WITH A REACTIVE METAL LAYER - A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals. | 2021-01-14 |
20210013263 | MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion. | 2021-01-14 |
20210013264 | EFFICIENT INTERCONNECTING LAYER FOR TANDEM SOLAR CELLS - A tandem solar cell comprises a front subcell; a back subcell; and an interconnecting layer of Cr/MoO | 2021-01-14 |
20210013265 | LIGHT EMITTING DEVICE - The disclosure provides a light emitting device including a display element and an infrared light emitting element that are disposed on an insulating layer; and a reducer configured to reduce a quantity of light that is emitted in a direction of the display element from the infrared light emitting element in plan view from a direction perpendicular to the insulating layer. | 2021-01-14 |
20210013266 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE - An organic light emitting diode display device includes an overcoating layer on a substrate having an emitting area and a non-emitting area and including a plurality of convex portions and a plurality of concave portions; a first electrode on the overcoating layer; a light emitting layer on the first electrode; and a second electrode on the light emitting layer, wherein the light emitting layer includes first, second and third emitting material layers sequentially under the second electrode, and wherein the first emitting material layer emits a first light of a first wavelength, the second emitting material layer emits the first light of the first wavelength, and the third emitting material layer emits a second light of a second wavelength different from the first wavelength. | 2021-01-14 |
20210013267 | DISPLAY DEVICE - A display device includes a display panel and an anti-reflection unit directly disposed on the display panel. The display panel includes first to third light emitting elements, each of which includes first and second electrodes, and a light emitting layer, which is disposed between the first electrode and the second electrode. The pixel definition layer includes a first portion, in which a light-emitting opening exposing the first electrode is defined, and a second portion, which is disposed on and overlapped with the first portion. The anti-reflection unit includes first to third color filters overlapped with the first to third light emitting elements, respectively, and a color spacer, which is overlapped with the second portion and is thicker than each of the first to third color filters. | 2021-01-14 |
20210013268 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - A light emitting display device comprises a substrate, a first pixel electrode disposed on the substrate, a pixel defining film disposed on the first pixel electrode and having a first opening at least partially exposing the first pixel electrode, a first organic light emitting layer disposed on the pixel defining film and overlapping with the first opening of the pixel defining film, and a black matrix disposed on the first organic light emitting layer and having a first opening overlapping with the first organic light emitting layer. Light having passed through the first opening of the black matrix is one of red light, green light, and blue light. The first opening of the black matrix may have a shape with a curved portion. | 2021-01-14 |
20210013269 | CONDUCTIVE MEMBER, CONDUCTIVE FILM, DISPLAY DEVICE HAVING THE SAME, TOUCH PANEL, METHOD OF PRODUCING WIRING PATTERN OF CONDUCTIVE MEMBER, AND METHOD OF PRODUCING WIRING PATTERN OF CONDUCTIVE FILM - A conductive member has a wiring portion, and the wiring portion has a mesh-shaped wiring pattern in which line wirings each being composed of a plurality of thin metal wires arranged in parallel in one direction are overlapped in two or more directions. The line wiring in at least one direction is a straight line wiring in which a plurality of thin metal wires are straight lines. The straight line wiring in at least one direction has a non-equal pitch wiring pattern in which repetitive pitches of a predetermined number of the thin metal wires are equal and at least two pitches of the respective pitches of the predetermined number of the thin metal wires are different. The conductive member has a wiring pattern capable of reducing moiré compared to an equal pitch wiring pattern, particularly a wiring pattern capable of reducing both regular moiré and irregular moiré (noise). A conductive film, a display device, and a touch panel each include the conductive member. | 2021-01-14 |
20210013270 | ORGANIC LIGHT EMITTING DISPLAY PANEL AND ORGANIC LIGHT EMITTING DISPLAY DEVICE - An OLED panel includes a display area and a non-display area around the display area; a substrate, a driving device layer and a light emitting device layer arranged in the display area, an encapsulation layer covering the light emitting device layer; and a touch layer located on a side of the encapsulation layer facing away from the substrate, the touch layer comprising a touch electrode and a touch wire. The non-display area includes an electrostatic discharge portion, the electrostatic discharge portion is made of a conductive material and is located on a side of the encapsulation layer facing away from the substrate. The non-display area includes a blocking portion, the blocking portion is arranged around the display area, and is located between the substrate and the encapsulation layer. The electrostatic discharge portion is located on a side of the touch wire facing away from the display area. | 2021-01-14 |
20210013271 | DISPLAY APPARATUS - A display apparatus includes a substrate having a first transmissive area, a second transmissive area, a pixel area between the first transmissive area and the second transmissive area, a first pixel electrode in the pixel area, a first intermediate layer disposed on the first pixel electrode to emit light of a first color and an insulating layer covering edges of the first pixel electrode and defining a first emission area through a first opening exposing a portion of the first pixel electrode. A first partition wall is disposed on the insulating layer between the first emission area and the first transmissive area. A second partition wall is disposed on the insulating layer between the first emission area and the second transmissive area. An opposite electrode is disposed on the first intermediate layer in the pixel area and partially contacts the first partition wall and the second partition wall. | 2021-01-14 |
20210013272 | DISPLAY DEVICE, DISPLAY PANEL AND OLED ARRAY SUBSTRATE THEREOF - A display device, a display panel and an OLED array substrate thereof are provided. As an example, the OLED array substrate includes a display driving chip and a display area, and the display area includes a non-transparent display area and a transparent display area. The non-transparent display area includes a plurality of first OLED pixels arranged in an array. The transparent display area includes a set of at least one column of second OLED pixels; A driving mode of the set of the at least one column of second OLED pixels is an active drive, and the set of the at least one column of second OLED pixels and the plurality of first OLED pixels are controlled by the display driving chip. | 2021-01-14 |
20210013273 | ORGANIC LIGHT EMITTING DIODE DISPLAY INCLUDING CAPPING LAYER HAVING OPTICAL THICKNESS FOR IMPROVING OPTICS - An OLED display including first, second, and third color pixels on a substrate, each including a first electrode, an organic emission layer, a second electrode, and a capping layer, in which the first color pixel emits green light, and each of the second and third color pixels emits a color of light other than green, the organic emission layer of the first color pixel includes first and second emission layers that emit light, the organic emission layer of the second or third color pixel includes a third emission layer that emit light, the second and third emission layers include both a host and a dopant, the first emission layer includes the host, but not any dopants therein, and the second emission layer is disposed on the first electrode, and the first emission layer is disposed on the second emission layer. | 2021-01-14 |
20210013274 | LIGHT EMITTING PANEL AND DISPLAY APPARATUS - A light emitting substrate includes a base and pixel unit sets arranged on the base, wherein the pixel unit sets include a first sub-pixel, a second sub-pixel, and a third sub-pixel having colors different from each other, wherein adjacent sub-pixels have space therebetween, the pixel unit sets arranged in a same row include a first pixel unit set and a second pixel unit set adjacent to each other, the second sub-pixel of the first pixel unit set and the first sub-pixel of the second pixel unit set have a same color, the second sub-pixel of a third pixel unit set located in an adjacent row and on a side of the first sub-pixel and the third sub-pixel of the first pixel unit set have a same color, and the first sub-pixel of a fourth pixel unit set and the third sub-pixel of the first pixel unit set have a same color. | 2021-01-14 |
20210013275 | DISPLAY DEVICE - A display device includes: a substrate including a display area and a non-display area; and a plurality of sub-pixels arranged in the display area and including portions of an electrode disposed over the display area. The plurality of sub-pixels includes a first sub-pixel and a second sub-pixel to emit light of the same color, a first portion of the electrode of the first sub-pixel has a thickness different from a thickness of a second portion of the electrode of the second sub-pixel, and the first sub-pixel has a size different from a size of the second sub-pixel. | 2021-01-14 |
20210013276 | ELLIPTICALLY POLARIZING PLATE AND ORGANIC LIGHT-EMITTING DEVICE - An elliptically polarizing plate and an organic light-emitting device. The elliptically polarizing plate has superior visibility and excellent reflection characteristics and color characteristics on the side as well as the front, and an organic light-emitting device comprising the same. | 2021-01-14 |
20210013277 | ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY APPARATUS - An array substrate, a display panel, and a display apparatus. The array substrate includes a base substrate; a first electrode layer formed on the base substrate; a light emitting layer formed on the first electrode layer and including a non-transparent first light emitting region, a second light emitting region, and a transparent third light emitting region; and a second electrode layer formed on the light emitting layer. The first light emitting region includes first light emitting structures. The second light emitting region includes second light emitting structures. The third light emitting region includes third light emitting structures. The second light emitting region is located between the first light emitting region and the third light emitting region. A distribution density of first light emitting structures, a distribution density of second light emitting structures, and a distribution density of third light emitting structures are gradually changed in sequence. | 2021-01-14 |
20210013278 | DISPLAY DEVICE - A display device includes a substrate defining a concave portion recessed from a top surface of the substrate, a lower conductive layer in the concave portion, an upper conductive layer connected to the lower conductive layer, an insulating layer between the lower conductive layer and the upper conductive layer and in which a contact hole is defined, the upper conductive layer connected to the lower conductive layer at the contact hole, a thin-film transistor including a semiconductor layer and a gate electrode on the semiconductor layer, and a display element connected to the thin-film transistor. | 2021-01-14 |
20210013279 | ORGANIC LIGHT-EMITTING DIODE (OLED) DISPLAY PANEL AND METHOD THEREOF - Disclosed is an organic light-emitting diode (OLED) display panel which comprises a thin-film transistor (TFT) device layer and a light-emitting layer disposed on the thin-film transistor device layer. A reflection-enhancing layer provided between the thin-film transistor device layer and the light-emitting layer includes an insulating layer disposed on the thin-film transistor device layer, a plurality of reflecting electrodes disposed on the insulating layer in a matrix manner and corresponding one-to-one to each emitting area of the organic light-emitting diode display panel, and a planarization layer disposed on the insulating layer and covering the plurality of reflecting electrodes. A plurality of anodes of the light-emitting layer are disposed on the planarization layer, and the plurality of anodes of the light-emitting layer are positioned opposite to the plurality of reflecting electrodes. | 2021-01-14 |
20210013280 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A display device includes: a base substrate having a display region including a first region and a second region, and a non-display region; a first semiconductor layer including polysilicon at the second region; a first conductive layer on a first insulating layer, and including a bottom gate electrode at the first region and a second-first gate electrode at the second region; a second semiconductor layer including an oxide on a second insulating layer at the first region; a second conductive layer on a third insulating layer, and including a top gate electrode at the first region and a second-second gate electrode at the second region; and a third conductive layer on a fourth insulating layer, and including a first source electrode and a first drain electrode connected to the second semiconductor layer, and a second source electrode and a second drain electrode connected to the first semiconductor layer. | 2021-01-14 |
20210013281 | THIN FILM TRANSISTOR, DISPLAY APPARATUS INCLUDING THE SAME, AND MANUFACTURING METHODS THEREOF - A method of manufacturing a thin film transistor includes: removing an oxide film on a surface of an amorphous silicon layer by performing a surface cleaning; and forming an active layer by performing a heat treatment on the amorphous silicon layer, where the amorphous silicon layer is changed into crystalline silicon by the heat treatment. | 2021-01-14 |
20210013282 | DISPLAY DEVICE AND PRODUCTION METHOD FOR DISPLAY DEVICE - A display device according to the disclosure includes a substrate, a first transistor provided on the substrate, and a second transistor provided on the substrate, not overlapping the first transistor. The first transistor includes a polycrystalline silicon layer provided on the substrate, a first insulating film provided on the polycrystalline silicon layer, a first gate electrode provided on the first insulating film, and a second insulating film provided on the first gate electrode. The second transistor includes an oxide semiconductor layer provided on the first insulating film, a third insulating film provided on the oxide semiconductor layer, and a second gate electrode provided on the third insulating film. The first and third insulating films are SiOx films. The second insulating film is an SiNx film including hydrogen, and is provided overlapping the polycrystalline silicon layer, and is provided not overlapping the oxide semiconductor layer. | 2021-01-14 |
20210013283 | DISPLAY DEVICE AND BRIGHTNESS DETECTION METHOD THEREFOR - A display device includes a display layer, at least one brightness detecting unit group disposed on a light emitting side of the display layer, and a control module coupled to each of the brightness detecting units. The display layer includes a plurality of display units. Each display unit includes at least one sub-pixel. Each brightness detecting unit group includes a plurality of brightness detecting units, an orthographic projection of one brightness detecting unit on the display layer has an overlapping area with an arranging area of one display unit on the display layer. Respective portions, lying in overlapping areas, of the display units corresponding to different brightness detecting units in the same brightness detecting unit group are the same. | 2021-01-14 |
20210013284 | DISPLAY PANEL - A display panel includes a substrate including a display area and a transmission area arranged in the display area which is surrounded by a first side extending in a first direction, a second side extending in a second direction crossing the first direction, a third side facing the first side, and a fourth side facing the second side, pixels arranged in the display area, a first black line extending from the transmission area to the first side in a third direction different from the second direction and arranged with dummy pixels which do not emit light, and a second black line extending from the transmission area to the second side in a fourth direction different from the first direction and arranged with the dummy pixels which do not emit light, wherein the transmission area is arranged closer to the first and second sides than the third and fourth sides. | 2021-01-14 |
20210013285 | DISPLAY SUBSTRATE, METHOD FOR MANUFACTURING SAME, AND DISPLAY DEVICE - Disclosed are a display substrate, a method for manufacturing the same, and a display device. The display substrate includes: a base substrate, and a multilayered functional film layer on the base substrate. The multilayered functional film layer is provided with an opening penetrating through the multilayered functional film layer. A light-shielding film is on a side wall of the opening. | 2021-01-14 |