02nd week of 2021 patent applcation highlights part 61 |
Patent application number | Title | Published |
20210013286 | DISPLAY DEVICE - A display device includes: a substrate; a plurality of light-emitting diodes above the substrate; a plurality of pixel circuits above the substrate and electrically connected to the plurality of light-emitting diodes; a scan line extending in a first direction above the substrate, where the scan line delivers a scan signal to the plurality of pixel circuits; and a scan driver between the substrate and the plurality of pixel circuits and providing the scan signal to the scan line. A distance between the scan driver and the substrate is less than a distance between the plurality of pixel circuits and the substrate. | 2021-01-14 |
20210013287 | DISPLAY DEVICE - A display device includes a display panel which includes a display area and a non-display area, a plurality of signal wirings arranged in the display area, a plurality of fanout wirings arranged in the non-display area and electrically connected to the signal wirings, and a plurality of connecting wirings connecting the signal wirings to the fanout wirings, where some of the plurality of fanout wirings intersect and are overlapped with each other in a plan view. | 2021-01-14 |
20210013288 | DISPLAY DEVICE - A display device includes a base substrate; an organic layer disposed on the base substrate; and a first conductive layer disposed on the organic layer, wherein the first conductive layer includes a plurality of stacked films, the plurality of stacked films include a first conductive film disposed directly on the organic layer and a second conductive film disposed on the first conductive film, and the first conductive film has an oxygen concentration higher than an oxygen concentration of the second conductive film. | 2021-01-14 |
20210013289 | DISPLAY SUBSTRATE AND DISPLAY DEVICE - The present disclosure provides a display substrate, including a substrate, a first power line on the substrate, a second power line, and a plurality of pixel groups, each of which includes a plurality of pixels arranged in a first direction, the plurality of pixel groups are arranged in a second direction parallel to an extending direction of the first power line, the second direction is different from and intersects with the first direction, each of the plurality of pixels includes a light emitting unit having a first electrode and a second electrode, the first electrode of the light emitting unit is coupled to the first power line through an additional resistor with an additional resistance, and the second electrode of the light emitting unit is coupled to the second power line through an equivalent resistor with an equivalent resistance. | 2021-01-14 |
20210013290 | ELECTRONIC DEVICE - Provided is an electronic device. The electronic device includes at least one first transistor to which a data voltage is applied. The first transistor includes a first conductive layer disposed on a substrate and a first active layer, which is disposed on the first conductive layer, has one end and the other end which are made conductive, and includes a first channel region disposed between the one end and the other end. A second conductive layer overlapping the first conductive layer with a first insulating layer interposed between the second conductive layer and the first conductive layer is included in a storage capacitor in a panel, and the storage capacitor is disposed under the first channel region of the first active layer. In this way, an ultra-high definition panel is fabricated. | 2021-01-14 |
20210013291 | DISPLAY DEVICE - A display device includes a flexible substrate which includes a first surface and a second surface opposite to the first surface and includes, sequentially, a first portion in the display region, a second portion in the non-display region, a third portion bent in a direction opposite to a display surface, a fourth portion, a fifth portion bent in a direction toward the display surface, and a sixth portion; a plurality of signal wirings on the first surface at the second to sixth portions; and a plurality of first connection wirings on the second surface at the second portion, and the second portion overlaps with the fourth portion, the fifth portion, and the sixth portion, and the signal wirings and the first connection wirings are coupled to each other on the second surface at the second portion. | 2021-01-14 |
20210013292 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND MANUFACTURING METHOD THEREOF - A display device includes: a substrate; a semiconductor layer; a gate electrode overlapping the semiconductor layer; a common voltage line disposed on a same layer as the gate electrode; a common voltage line anti-oxidation layer disposed on the common voltage line; an interlayer insulating layer; source and drain electrodes disposed on the interlayer insulating layer; and a common voltage applying electrode disposed on a same layer as the source electrode and the drain electrode. The common voltage applying electrode is connected to the common voltage line through a first contact hole formed in the interlayer insulating layer, the common voltage line anti-oxidation layer includes an opening overlapping the common voltage line, the interlayer insulating layer is disposed in the opening, a width of the opening is smaller than a width of the common voltage line, and the first contact hole is disposed in the opening in a plan view. | 2021-01-14 |
20210013293 | DISPLAY PANEL AND DISPLAY APPARATUS - The disclosure relates to a display panel and a display apparatus. The display panel comprises: a substrate comprising a substrate display region corresponding to a display panel display region and a substrate non-display region corresponding to a display panel non-display region; a non-display region circuit located at the substrate non-display region; and a packaging layer located on the non-display region circuit and having at least a partial overlap area with the non-display region circuit, wherein the non-display region circuit comprises: a first conductive pattern; at least one buffer layer located at a side of the first conductive pattern close to the substrate; at least one gate insulating layer configured to electrically insulate the first conductive pattern and other conductive patterns; and at least one interlayer insulating layer located at a side of the first conductive pattern away from the substrate. | 2021-01-14 |
20210013294 | DISPLAY APPARATUS - A display apparatus includes: a substrate having a bending area between a first area and a second area; internal conductive lines on the substrate in the first area; external conductive lines on the substrate in the second area; an organic material layer covering the bending area and covering at least a portion of the internal conductive lines and the external conductive lines; and connection lines on the organic material layer and connecting the internal conductive lines to the external conductive lines, respectively. Organic through-holes are defined through the organic material layer, the connection lines are respectively connected to the internal conductive lines through the organic through-holes, and an upper surface of the organic material layer between the organic through-holes has a convex curved shape. | 2021-01-14 |
20210013295 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a display device includes preparing a carrier substrate, forming a first substrate layer on the carrier substrate, forming a first, second, and third through holes in the first substrate layer, forming a first intermediate conductive layer having a first exposed portion and a second exposed portion, forming a second intermediate conductive layer having a third exposed portion, forming a second substrate layer on the first substrate layer to cover the first intermediate conductive layer and the second intermediate conductive layer, forming a fourth through hole in the second substrate layer, forming a wiring on the second substrate layer, separating the first substrate layer from the carrier substrate, arranging a first electronic device on a surface of the first substrate layer, and arranging a second electronic device on the surface of the first substrate layer. | 2021-01-14 |
20210013296 | DISPLAY DEVICE - A display device includes: a first conductive layer on a resin substrate layer; a planarization film on the first conductive layer; and OLEDs on the planarization film. There is provided a second conductive layer in a frame area surrounding a display area. The second conductive layer is in contact with second electrodes of the OLEDs on the planarization film and also in contact with the first conductive layer in an external side of the planarization film. The second electrode is electrically connected to the first conductive layer via the second conductive layer. The planarization film includes, in the frame area, a portion where there is provided a trench. The first conductive layer is exposed from the planarization film in the trench. The second electrode is electrically connected to the first conductive layer via the second conductive layer in the trench. | 2021-01-14 |
20210013297 | DISPLAY DEVICE - The display device includes a non-display area. The non-display area includes: a slit formed in an edge cover; a first conductive layer formed in the same layer as an anode, and being in contact with a cathode; and a second conductive layer formed in the same layer as a capacitance electrode and provided to overlap the slit. | 2021-01-14 |
20210013298 | DISPLAY INCLUDING PLURALITY OF WIRINGS BYPASSING HOLE AREA ENCOMPASSED BY DISPLAY AREA, AND ELECTRONIC DEVICE INCLUDING SAME - Disclosed in various embodiments of the present invention are a display having at least one hole formed in a display area on which an image is displayed, and an electronic device including same. According to various embodiments, the electronic device comprises a display including the display area having a plurality of pixels and a plurality of wirings, wherein the display includes: a hole area encompassed by the display area; a plurality of first wirings, from among the plurality of wirings, extending from a first side of the display area so as to be formed at first intervals, and connected to the side opposite to the first side; second wirings, from among the plurality of wirings, extending from a second side of the display area so as to be arranged at the first intervals on the side opposite to the second side; and a plurality of third wirings, from among the plurality of wirings, extending from the first side of the display area so as to be formed at second intervals that are wider than the first intervals, and bypassing the hole area so as to be connected to the side opposite to the first side. Various embodiments are possible. | 2021-01-14 |
20210013299 | METHOD FOR MANUFACTURING DISPLAY DEVICE AND DISPLAY DEVICE - In a step of forming a plurality of control lines composed of a first metal layer a first metal layer branch line is formed. In a step of forming a plurality of power source lines composed of a second metal layer a second metal layer connecting portion is formed that connects each power source line with the first metal layer branch line via an opening of a first insulating film. In a step of forming a plurality of data signal lines composed of a third metal layer that is formed on a second insulating film the first metal layer branch line formed in the opening of the first insulating and the second metal layer connecting portion formed in an opening of the second insulating film are etched. | 2021-01-14 |
20210013300 | High Density Capacitor Implemented Using FinFET - A first and a second gate structure each extend in a first direction. A first and a second conductive contact extend in the first direction and are separated from the first and second gate structures in a second direction. A first isolation structure extends in the second direction and separates the first gate structure from the second gate structure. A second isolation structure extends in the second direction and separates the first conductive contact from the second conductive contact. The first gate structure is electrically coupled to a first electrical node. The second gate structure is electrically coupled to a second electrical node different from the first electrical node. The first conductive contact is electrically coupled to the second electrical node. The second conductive contact is electrically coupled to the first electrical node. | 2021-01-14 |
20210013301 | METAL-INSULATOR-METAL (MIM) CAPACITOR STRUCTURE AND METHOD FOR FORMING THE SAME - A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a substrate, and the substrate includes a capacitor region and a non-capacitor region. The MIM capacitor structure includes a first electrode layer formed over the substrate, and a first spacer formed on a sidewall of the first electrode layer. The MIM capacitor structure includes a second electrode layer formed over the first electrode layer, and a second spacer formed on a sidewall of the second electrode layer. The second spacer is in direct contact with an interface between the second electrode layer and a first dielectric layer. | 2021-01-14 |
20210013302 | CAPACITOR AND MANUFACTURING METHOD THEREFOR - A capacitor includes: at least one multi-wing structure including N axes and M wings, where the N axes extend along a first direction, and the M wings are a convex structure formed by extending from side walls of the N axes toward a direction perpendicular to the first direction, a first wing of the M wings and the N axes are formed of a first conductive material, and other wings are formed of a second conductive material; a conductive structure cladding the multi-wing structure; a dielectric layer disposed between the multi-wing structure and the conductive structure to isolate the multi-wing structure from the conductive structure; a first external electrode electrically connected to some or all multi-wing structures; and a second external electrode electrically connected to the conductive structure. | 2021-01-14 |
20210013303 | STRUCTURE AND METHOD FOR FORMING CAPACITORS FOR A THREE-DIMENSIONAL NAND - Embodiments of a three-dimensional capacitor for a memory device and fabrication methods are disclosed. The method includes forming, on a first side of a first substrate, a peripheral circuitry having a plurality of peripheral devices, a first interconnect layer, a deep well and a first capacitor electrode. The method also includes forming, on a second substrate, a memory array having a plurality of memory cells and a second interconnect layer, and bonding the first interconnect layer of the peripheral circuitry with the second interconnect layer of the memory array. The method further includes forming, on a second side of the first substrate, one or more trenches inside the deep well, disposing a capacitor dielectric layer on sidewalls of the one or more trenches, and forming capacitor contacts on sidewalls of the capacitor dielectric layer inside the one or more trenches. | 2021-01-14 |
20210013304 | SEMICONDUCTOR DEVICES INCLUDING DUMMY PATTERNS - A semiconductor device including a substrate having a cell, peripheral, and boundary area; a stack structure on the cell area and including insulating and interconnection layers that are alternately stacked; a molding layer on the peripheral area boundary areas; a selection line isolation pattern extending into the stack structure; a cell channel structure passing through the stack structure; and first dummy patterns extending into the molding layer on the peripheral area, wherein upper surfaces of the first dummy patterns, an upper surface of the selection line isolation pattern, and an upper surface of the cell channel structure are coplanar, and at least one of the first dummy patterns extends in parallel with the selection line isolation pattern or cell channel structure from upper surfaces of the first dummy patterns, the upper surface of the selection line isolation pattern, and the upper surface of the cell channel structure toward the substrate. | 2021-01-14 |
20210013305 | CHANNEL CONDUCTION IN SEMICONDUCTOR DEVICES - An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area. | 2021-01-14 |
20210013306 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate including a first active pattern and a second active pattern, a device isolation layer filling a first trench between the first and second active patterns, the device isolation layer including a silicon oxide layer doped with helium, a helium concentration of the device isolation layer being higher than a helium concentration of the first and second active patterns, and a gate electrode crossing the first and second active patterns. | 2021-01-14 |
20210013307 | Binary III-Nitride 3DEG heterostructure HEMT with graded channel for high linearity and high power applications - A HEMT comprising: a substrate; a channel layer coupled to the substrate; a source electrode coupled to the channel layer; a drain electrode coupled to the channel layer; and a gate electrode coupled to the channel layer between the source electrode and the drain electrode; wherein the channel layer comprises: at least a first GaN layer; and a first graded AlGaN layer on the first GaN layer, the Al proportion of the first graded AlGaN layer increasing with the distance from the first GaN layer. | 2021-01-14 |
20210013308 | SILICON CARBIDE SEMICONDUCTOR DEVICE - In a SiC-MOSFET, to increase the threshold voltage while reducing the channel resistance is difficult. And, when the channel resistance is lowered, the reliability may be reduced in such a manner that a current may flow when the device is turned off and malfunction may occur when the device is used as a normally-off device. According to the present invention, the threshold voltage is increased while the channel resistance is reduced, and reliability when used as a normally-off device is improved by adding at least any of sulfur, selenium, and tellurium to the channel region of the SiC MOSFET. | 2021-01-14 |
20210013309 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device includes a drift layer having a first conductivity type and a surface in which an active region is defined; a plurality of first doped regions having a second conductivity and arranged within the active region; a plurality of second doped regions having a second conductivity and arranged within the active region; and a metal layer disposed on the surface of the drift layer and forming a Schottky contact with the drift layer. Each of the first doped regions has a first minimum width and a first area and are spaced from each other by a first minimum spacing Each of the second doped regions has a second minimum width greater than the first minimum width and a second area greater than the first area and are spaced from the first doped region by a second minimum spacing less than the first minimum spacing. | 2021-01-14 |
20210013310 | Silicon Carbide Device with Compensation Layer and Method of Manufacturing - First dopants are implanted through a larger opening of a first process mask into a silicon carbide body, wherein the larger opening exposes a first surface section of the silicon carbide body. A trench is formed in the silicon carbide body in a second surface section exposed by a smaller opening in a second process mask. The second surface section is a sub-section of the first surface section. The larger opening and the smaller opening are formed self-aligned to each other. At least part of the implanted first dopants form at least one compensation layer portion extending parallel to a trench sidewall. | 2021-01-14 |
20210013311 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING SEMICONDUCTOR DEVICE - A semiconductor device including at least an inversion channel region includes an oxide semiconductor film containing a crystal that contains at least gallium oxide at the inversion channel region. | 2021-01-14 |
20210013312 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device includes a substrate, an active layer, a source electrode, a drain electrode, a p-type doped layer, a gate electrode, a passivation layer, and a field plate. The active layer is disposed on the substrate. The source electrode, the drain electrode and the p-type doped layer are disposed on the active layer. The p-type doped layer is disposed between the source electrode and the drain electrode, and has a first thickness. The gate electrode is disposed on the p-type doped layer. The passivation layer covers the gate electrode and the active layer. The field plate is disposed on the passivation layer and is electrically connected to the source electrode. The field plate includes a field dispersion portion disposed between the gate electrode and the drain electrode. The passivation layer between the field dispersion portion and the active layer has a second thickness smaller than the first thickness. | 2021-01-14 |
20210013313 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device and fabrication method thereof are provided. The method includes: providing a gate structure, a first dielectric layer, and source/drain doped layers on a base substrate and in the base substrate on sides of the gate structure; forming a mask layer on the gate structure between the source/drain doped layers; forming a second dielectric layer on the first dielectric layer and exposing the mask layer; etching the second dielectric layer and the first dielectric layer using the mask layer as an etch mask, to form first grooves on the sides of the gate structure and exposing the source/drain doped layers; forming a first conductive structure in each first groove; patterning the mask layer to form a second groove in the mask layer to expose the gate structure at the bottom of the second groove; and forming a spacer on sidewalls of the second groove. | 2021-01-14 |
20210013314 | VERTICAL GALLIUM OXIDE (GA2O3) POWER FETS - A vertical gallium oxide (Ga2O3) device having a substrate, an n-type Ga | 2021-01-14 |
20210013315 | Semiconductor Device and Method - A semiconductor device and method of manufacture are provided. A source/drain region is formed next to a spacer, which is adjacent to a gate electrode. An implantation is performed through an implantation mask into the source/drain region as well as the first spacer, forming an implantation region within the spacer. | 2021-01-14 |
20210013316 | TUNNEL FIELD-EFFECT TRANSISTOR AND METHOD FOR DESIGNING SAME - [Problem] To improve the drain current ON/OFF ratio characteristics. | 2021-01-14 |
20210013317 | EPITAXIAL STRUCTURE OF N-FACE GROUP III NITRIDE, ACTIVE DEVICE, AND METHOD FOR FABRICATING THE SAME WITH INTEGRATION AND POLARITY INVERSION - The present invention provides an epitaxial structure of N-face group III nitride, its active device, and the method for fabricating the same. By using a fluorine-ion structure in device design, a 2DEG in the epitaxial structure of N-face group III nitride below the fluorine-ion structure will be depleted. Then the 2DEG is located at a junction between a i-GaN channel layer and a i-Al | 2021-01-14 |
20210013318 | ELECTRODE FORMATION - Apparatuses, methods, and systems related to electrode formation are described. A first portion of a top electrode is formed over a dielectric material of a storage node. A metal oxide is formed over the first portion of the electrode. A second portion of the electrode is formed over the metal oxide. | 2021-01-14 |
20210013319 | SEMICONDUCTOR DEVICE INCLUDING CAPACITOR - Disclosed is a semiconductor device including a bottom electrode, a dielectric layer, and a top electrode that are sequentially disposed on a substrate. The dielectric layer includes a hafnium oxide layer including hafnium oxide having a tetragonal crystal structure, and an oxidation seed layer including an oxidation seed material. The oxidation seed material has a lattice constant having a lattice mismatch of 6% or less with one of a horizontal lattice constant and a vertical lattice constant of the hafnium oxide having the tetragonal crystal structure. | 2021-01-14 |
20210013320 | Method of Manufacturing a Semiconductor Device and Semiconductor Device - A method of manufacturing a semiconductor device is proposed. A silicon carbide, SiC, semiconductor body is provided. Ions are introduced into the SiC semiconductor body through a first surface of the SiC semiconductor body by at least one ion implantation process. Thereafter, a SiC device layer is formed on the first surface of the SiC semiconductor body. Semiconductor device elements are formed in or over the SiC device layer. | 2021-01-14 |
20210013321 | SPACER-CONFINED EPITAXIAL GROWTH - Semiconductor devices and methods of forming the same include forming a dummy gate on a stack of alternating channel layers and sacrificial layers. A spacer layer is formed over the dummy gate and the stack. Portions of the spacer layer on horizontal surfaces of the stack are etched away to form vertical spacers. Exposed portions of the stack are etched away. Semiconductor material is grown from exposed sidewalls of remaining channel layers to form source and drain structures that are constrained in lateral dimensions by the vertical spacers. | 2021-01-14 |
20210013322 | FLOATING GATE PREVENTION AND CAPACITANCE REDUCTION IN SEMICONDUCTOR DEVICES - A method for fabricating a semiconductor structure includes forming a plurality of vertical fins on a semiconductor substrate. The method further includes depositing a first dielectric layer in a shallow trench isolation region on the semiconductor substrate. The method further includes forming a plurality of dummy gate structures over each of the vertical fins. The method further includes depositing a hardmask on the dummy gate. The method further includes depositing a spacer layer on the exterior surfaces of the first dielectric layer, the dummy gate structures, the hardmask and the fins. The method further includes depositing a second dielectric layer on a portion of the spacer layer. The method further includes recessing spacer layer to expose a portion of the hardmask and the plurality of fins. The method further includes forming a source/drain region on the exposed portion of the plurality of fins. | 2021-01-14 |
20210013323 | PLUGS FOR INTERCONNECT LINES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION - Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer. | 2021-01-14 |
20210013324 | SEMICONDUCTOR DEVICE INCLUDING NON-SACRIFICIAL GATE SPACERS AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a substrate, a gate electrode on the substrate, a gate spacer on a sidewall of the gate electrode, an active pattern penetrating the gate electrode and the gate spacer, and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode extends in a first direction. The gate spacer includes a semiconductor material layer. The active pattern extends in a second direction crossing the first direction. | 2021-01-14 |
20210013325 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a semiconductor device includes the following steps. First patterned structures are formed on a substrate. Each of the first patterned structures includes a first semiconductor pattern and a first bottom protection pattern disposed between the first semiconductor pattern and the substrate. A first protection layer is formed on the first patterned structures and the substrate. A part of the first protection layer is located between the first patterned structures. A first opening is formed in the first protection layer between the first patterned structures. The first opening penetrates the first protection layer and exposes a part of the substrate. A first etching process is performed after forming the first opening. A part of the substrate under the first patterned structures is removed by the first etching process for suspending at least a part of each of the first patterned structures above the substrate. | 2021-01-14 |
20210013326 | MULTIPLE PLANES OF TRANSISTORS WITH DIFFERENT TRANSISTOR ARCHITECTURES TO ENHANCE 3D LOGIC AND MEMORY CIRCUITS - Microfabrication of a collection of transistor types on multiple transistor planes in which both HV (high voltage transistors) and LV (low-voltage transistors) stacks are designed on a single substrate. As high voltage transistors require higher drain-source voltages (Vds), higher gate voltages (Vg), and thus higher V | 2021-01-14 |
20210013327 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a method for manufacturing a semiconductor device by using a gate replacement technology, a gate space constituted by dielectric material portions, in which a semiconductor fin channel layer is exposed, is formed. The surfaces of the dielectric material portions are made hydrophobic. A first dielectric layer is formed on the semiconductor fin channel layer, while maintaining the surfaces of the dielectric material portions hydrophobic. A surface of the formed first dielectric layer is hydrophilic. A first conductive layer is formed over the first dielectric layer, while maintaining the surfaces of the dielectric material portions hydrophobic. A second conductive layer is formed over the first conductive layer and on the hydrophobic surfaces of the dielectric material portions, thereby filling the gate space. | 2021-01-14 |
20210013328 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - An insulating film configuring an uppermost layer of a gate insulating film of a memory cell comprises a silicon oxide film and is a layer to which a metal or metal oxide is added. A formation step of the insulating film comprises the steps of: forming the silicon oxide film; and adding the metal or the metal oxide in an atomic or molecular state by a sputtering process onto the silicon oxide film. Oxide of the metal has a higher dielectric constant than silicon oxide, and the metal oxide has a higher dielectric constant than silicon oxide. A High-K added layer is thus used as the insulating film configuring the gate insulating film of the memory cell, thereby a high saturation level of a threshold voltage can be maintained while a drive voltage (applied voltage for erase or write) is reduced, leading to improvement in reliability of the memory cell. | 2021-01-14 |
20210013329 | ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - An array substrate and a method for manufacturing the same are provided. In the method for manufacturing an array substrate, the conductivization of the active layer is advanced to be performed before the step of lifting off the photoresist. The method further replaces oxygen used in the prior art method with helium to enhance the manufacturing efficiency, reduce the production cost, and improve the production yield. | 2021-01-14 |
20210013330 | IGBT CHIP HAVING FOLDED COMPOSITE GATE STRUCTURE - An IGBT chip having a Γ-shape mixed gate structure includes a plurality of mixed gate units. Each of the mixed gate units includes a gate region and two active regions located at two sides of the gate region. The gate region includes a trench gate and a planar gate that is located on a surface of the gate region, and the planar gate is connected with the trench gate and formed a Γ-shape mixed structure. In this way, the IGBT chip can have a significantly improved chip density, while retaining features of low power consumption and high current density of the trench gate and a feature of a wide safe operating area of the planar gate. | 2021-01-14 |
20210013331 | HIGH ELECTRON MOBILITY TRANSISTOR DEVICES AND METHODS FOR FORMING THE SAME - A HEMT device includes a gate electrode disposed on a semiconductor layer; a first dielectric layer disposed on the gate electrode and having a first recess on a first side of the gate electrode, wherein a bottom surface of the first recess is lower than a top surface of the gate electrode; a source field plate disposed on the first dielectric layer and extending from a second side of the gate electrode into the first recess; a second dielectric layer disposed on the source field plate; a source electrode disposed on the second dielectric layer and electrically connected to the source field plate; a third dielectric layer disposed on the source electrode; and a drain structure disposed on the first side of the gate electrode and passing through the third dielectric layer. | 2021-01-14 |
20210013332 | INSULATING STRUCTURE OF HIGH ELECTRON MOBILITY TRANSISTOR AND MANUFACTURING METHOD THEREOF - An insulating structure of a high electron mobility transistor (HEMT) is provided, which comprises a gallium nitride layer, an aluminum gallium nitride layer disposed on the gallium nitride layer, a groove disposed in the gallium nitride layer and the aluminum gallium nitride layer, an insulating layer disposed in the groove, wherein a top surface of the insulating layer is aligned with a top surface of the aluminum gallium nitride layer, and a passivation layer, disposed on the aluminum gallium nitride layer and the insulating layer. | 2021-01-14 |
20210013333 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A high electron mobility transistor, including an active area, a buffer layer on the active area, a channel layer on the buffer layer, a barrier layer on the channel layer, and gate, source and drain on the barrier layer, and a trench isolation structure adjacent and surrounding the channel layer and the barrier layer to apply stress and modify two-dimension electron gas (2DEG) or two-dimension hole gas (2DHG) of the high electron mobility transistor. | 2021-01-14 |
20210013334 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode. | 2021-01-14 |
20210013335 | INSULATING STRUCTURE OF HIGH ELECTRON MOBILITY TRANSISTOR AND MANUFACTURING METHOD THEREOF - An insulating structure of a high electron mobility transistor (HEMT) is provided, which comprises a gallium nitride layer, an aluminum gallium nitride layer disposed on the gallium nitride layer, an insulating doped region disposed in the gallium nitride layer and the aluminum gallium nitride layer, and two sidewall insulating structures disposed at two sides of the insulating doped region respectively. | 2021-01-14 |
20210013336 | HIGH-ELECTRON-MOBILITY TRANSISTOR (HEMT) SEMICONDUCTOR DEVICES WITH REDUCED DYNAMIC RESISTANCE - High-electron-mobility transistor (HEMT) devices are described in this patent application. In some implementations, the HEMT devices can include a back barrier hole injection structure. In some implementations, the HEMT devices include a conductive striped portion electrically coupled to a drain contact. | 2021-01-14 |
20210013337 | FinFET Device and Method of Forming Same - A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, forming a first spacer over the dummy gate structure, implanting a first dopant in the fin to form a doped region of the fin adjacent the first spacer, removing the doped region of the fin to form a first recess, wherein the first recess is self-aligned to the doped region, and epitaxially growing a source/drain region in the first recess. | 2021-01-14 |
20210013338 | Semiconductor Device Structure and Method for Forming the Same - A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess. | 2021-01-14 |
20210013339 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device includes a current spreading region of the first conductivity type provided on a drift layer and having a higher impurity density than the drift layer; a base region of a second conductivity type provided on the current spreading region; a base contact region of the second conductivity type provided in a top part of the base region and having a higher impurity density than the base region; and an electrode contact region of the first conductivity type provided in a top part of the base region that is laterally in contact with the base contact region, the electrode contact region having a higher impurity density than the drift layer, wherein a density of a second conductivity type impurity element in the base contact region is at least two times as much as a density of a first conductivity type impurity element in the electrode contact region. | 2021-01-14 |
20210013340 | METHOD OF FABRICATING A FIELD-EFFECT TRANSISTOR - A method of fabricating a laterally diffused metal oxide semiconductor transistor including providing a substrate, forming a first well of a first doping polarity type in the substrate, forming a gate on a portion of the first well, the gate including an oxide layer and an at least partially conductive layer on the oxide layer, and forming a mask on at least a portion of the gate and at least a portion of the first well, wherein the mask has a sloping edge. The method further includes forming a second well of a second doping polarity type at least partially in the first well by implanting ions in the first well, the second well extending under a portion of the gate, the second doping polarity type being of opposite type to the first doping polarity type. The method includes forming a first one of a source and drain of the first doping polarity type in or on the second well, thereby defining a channel of the transistor under the gate. The method further includes forming a second one of the source and drain of the first doping polarity type in or on the first well, wherein the implanting includes directing at least a first beam of ions towards the first well at an angle substantially perpendicular to a surface plane of the substrate, and directing at least a second beam of ions towards the first well at an angle substantially offset from a surface normal of the substrate. | 2021-01-14 |
20210013341 | SEMICONDUCTOR STRUCTURE AND ASSOCIATED FABRICATING METHOD - A semiconductor structure is disclosed. The semiconductor structure includes: a substrate of a first conductivity; a first region of the first conductivity formed in the substrate; a second region of the first conductivity formed in the first region, wherein the second region has a higher doping density than the first region; a source region of a second conductivity formed in the second region; a drain region of the second conductivity formed in the substrate; a pickup region of the first conductivity formed in the second region and adjacent to the source region; and a resist protective oxide (RPO) layer formed on a top surface of the second region. An associated fabricating method is also disclosed. | 2021-01-14 |
20210013342 | SWITCH WITH INTEGRATED SCHOTTKY BARRIER CONTACT - Circuits, systems, devices, and methods related to a switch with an integrated Schottky barrier contact are discussed herein. For example, a radio-frequency switch can include an input node, an output node, and a transistor connected between the input node and the output node. The transistor can be configured to control passage of a radio-frequency signal from the input node to the output node. The transistor can include a first Schottky diode integrated into a drain of the transistor and/or a second Schottky diode integrated into a source of the transistor. The first Schottky diode and/or the second Schottky diode can be configured to compensate a non-linearity effect of the radio-frequency switch. | 2021-01-14 |
20210013343 | Source/Drain Epitaxial Layer Profile - The present disclosure describes a method that mitigates the formation of facets in source/drain silicon germanium (SiGe) epitaxial layers. The method includes forming an isolation region around a semiconductor layer and a gate structure partially over the semiconductor layer and the isolation region. Disposing first photoresist structures over the gate structure, a portion of the isolation region, and a portion of the semiconductor layer and doping, with germanium (Ge), exposed portions of the semiconductor layer and exposed portions of the isolation region to form Ge-doped regions that extend from the semiconductor layer to the isolation region. The method further includes disposing second photoresist structures over the isolation region and etching exposed Ge-doped regions in the semiconductor layer to form openings, where the openings include at least one common sidewall with the Ge-doped regions in the isolation region. Finally the method includes growing a SiGe epitaxial stack in the openings. | 2021-01-14 |
20210013344 | ACTIVE DEVICE SUBSTRATE AND MANUFACTURING METHOD THEREOF - An active device substrate includes a substrate, a first active device, and a second active device. The first active device includes a first gate, a crystallized metal oxide layer, a first insulation layer, a first source, and a first drain. The crystallized metal oxide layer is located on the first gate. The first insulation layer is sandwiched between the crystallized metal oxide layer and the first gate. An area from the top surface of the crystallized metal oxide layer to the bottom surface of the crystallized metal oxide layer is observed via a selected area diffraction mode of a transmission electron microscope, and a diffraction pattern of a crystallized phase can be observed. The second active device includes a second gate, a silicon semiconductor layer, a second source, and a second drain. A manufacturing method of an active device substrate is further provided. | 2021-01-14 |
20210013345 | FERROELECTRIC MEMORY DEVICE - A ferroelectric memory device according to one embodiment includes a semiconductor substrate, a fin structure disposed on the semiconductor substrate and having a trench, the trench having a bottom surface and a sidewall surface; a ferroelectric layer disposed on the bottom surface and the sidewall surface of the trench; a plurality of resistor layers stacked vertically in the trench, each resistor layer of the plurality of resistor layers having a different electrical resistance; and a gate electrode layer electrically connected to the each resistor layer in the plurality of resistor layers. The plurality of resistor layers are disposed between the gate electrode layer and the ferroelectric layer. | 2021-01-14 |
20210013346 | MODULAR PHOTOVOLTAIC SYSTEM - A modular photovoltaic system adapted for collecting light rays from a solar light source to generate electrical current, the system having a light-tracking solar collector adapted to collect the light rays, an edge-lit photovoltaic array, and a transport conduit adapted to transport the light rays to the edge-lit photovoltaic array. The edge-lit photovoltaic array has a plurality of edge-lit photovoltaic panels, each having a transparent diffusing pane positioned between two backing panels with inwardly directed photovoltaic surfaces. Each edge-lit photovoltaic panel perpendicularly contacts a lateral light distributor attached to the transport conduit, causing the transparent diffusing pane to illuminate the photovoltaic surfaces to generate electrical current. The light-tracking solar collector is adapted to rotate to remain oriented toward the solar light source. | 2021-01-14 |
20210013347 | FLAT PANEL DETECTION SUBSTRATE, FABRICATING METHOD THEREOF AND FLAT PANEL DETECTOR - The present disclosure provides a flat panel detection substrate, a fabricating method thereof and a flat panel detector. The flat panel detection substrate according to the present disclosure includes a base substrate; a bias electrode and a sense electrode on the base substrate; and a semiconductor layer over the bias electrode and the sense electrode, the semiconductor layer having a thickness greater than 100 nm. | 2021-01-14 |
20210013348 | SOLAR CELL, SOLAR CELL MODULE, AND METHOD FOR MANUFACTURING SOLAR CELL - A solar cell includes a photoelectric conversion substrate having a first surface that includes a texture structure, a coating layer provided on the first surface and having an opening exposing the first surface, and an electrode in the opening. The unevenness of the surface of the coating layer has a larger height difference than a height difference of the texture structure of the first surface. | 2021-01-14 |
20210013349 | HIGH OPTICAL POWER LIGHT CONVERSION DEVICE USING A PHOSPHOR ELEMENT WITH SOLDER ATTACHMENT - A light generator comprises a light conversion device and a light source arranged to apply a light beam to the light conversion element. The light conversion device includes an optoceramic or other solid phosphor element comprising one or more phosphors embedded in a ceramic, glass, or other host, a metal heat sink, and a solder bond attaching the optoceramic phosphor element to the metal heat sink. The optoceramic phosphor element does not undergo cracking in response to the light source applying a light beam of beam energy effective to heat the optoceramic phosphor element to the phosphor quenching point. | 2021-01-14 |
20210013350 | Semi-Transparent Solar Panel Apparatus - A semi-transparent solar panel apparatus for allowing light to pass through solar panels onto crops to maximize solar collection areas includes a plurality of cell columns comprising a plurality of solar cells. Each cell column has a space between the adjacent cell columns to allow light to pass therethrough. A pair of encapsulant sheets is coupled together on either side of the plurality of cell columns to maintain the arrangement of the cell columns. A bottom frame is coupled to the pair of encapsulant sheets. The pair of encapsulant sheets is coupled to a bottom horizontal portion within a bottom vertical portion. A top frame is coupled to the bottom frame with a top vertical portion coupled to the bottom vertical portion of the bottom frame to seal the pair of encapsulant sheets between a top horizontal portion and the bottom horizontal portion. | 2021-01-14 |
20210013351 | BACK-SHEET COMPRISING POLYBUTYLENE TEREPHTALATE - The present invention relates to a back-sheet comprising a weatherable layer, a structural layer and a functional layer whereby one of the layers comprises polybutylene terephthalate and one or both of the other layers comprises a polyolefin. The layer comprising polybutylene terephthalate preferably further comprises an impact modifier. The impact modifier comprises an elastomer that contains functional groups that bond chemically and/or interact physically with the polybutylene terephthalate and wherein the elastomer constitutes the dispersed phase at a concentration of 1-49 Vol %. Preferably the elastomer contains epoxy functional groups. The polyolefin is selected from the group consisting of polyethylene homo or copolymers, polypropylene homo or (block-)copolymers, cyclic olefin copolymers, polymethylpentene, a thermoplastic polyolefine (TPO), or blends thereof. | 2021-01-14 |
20210013352 | Thin film device with additional conductive lines and method for producing it - Object of the invention is to provide a new thin film device comprising at least one thin film cell, wherein the thin film cell comprises a first electrode, a photoactive layer and a second electrode, wherein the photoactive layer is arranged between the first and the second electrode, wherein at least one additional conductive line is arranged within an active area of the thin film cell and included in the photoactive layer and electrically interconnected with the first electrode and electrically insulated from the second electrode. Furthermore, the invention provides a method of forming a thin film device comprising at least one thin film cell, wherein the thin film cell comprises a first electrode, a photoactive layer and a second electrode and the photoactive layer is arranged between the first and the second electrode. | 2021-01-14 |
20210013353 | SINGLE CELL PHOTOVOLTAIC MODULE - A photovoltaic module includes a first transparent electrode layer characterized by a first sheet resistance, a second transparent electrode layer, and a photovoltaic material layer. The photovoltaic material layer is located between the first transparent electrode layer and the second transparent electrode layer. The photovoltaic module also includes a first busbar having a second sheet resistance lower than the first sheet resistance. The first transparent electrode layer, the second transparent electrode layer, and the photovoltaic material layer have an aligned region that forms a central transparent area of the photovoltaic module. The central transparent area including a plurality of sides. The first busbar is in contact with the first transparent electrode layer adjacent to at least a portion of each of the plurality of sides of the central transparent area. | 2021-01-14 |
20210013354 | SOLAR CELL - A solar cell includes a cell chip unit, and an optical unit. The optical unit includes a first optical layer, a second optical layer and a third optical layer that are sequentially disposed on the cell chip unit in such order. Each of the first optical layer and the third optical layer has a refractive index greater than that of the second optical layer. | 2021-01-14 |
20210013355 | PHOTOVOLTAIC MODULE WITH ENHANCED LIGHT COLLECTION - The present invention is applied to photo voltaic module enhanced light. In particular, the present invention relates to glass-glass and back contact photo photovoltaic modules with enhanced conversion efficiency in areas that are not usually active. | 2021-01-14 |
20210013356 | PHOTODETECTORS WITH CONTROLLABLE RESONANT ENHANCEMENT - Resonant cavity photodetector structures which integrate photodetection and filtering capabilities is described. A resonant cavity photodetector structure generally can comprise a region including a resonator, and an absorption region that can be integrated into a cavity of the resonator. The resonator can perform filtering that is suitable for high-bandwidth optical communications, such as Dense Wavelength Multiplexing (DWDM). In some cases, the resonator is a microring resonator. An absorption region can include a photodiode which performs optical energy detection acting as a photodetector, such as an avalanche photodiode (APD) wherein the photodiode. A coupling distance between the resonator region and the absorption region can be controlled, which allows control of a coupling strength between an optical mode of the resonator and the absorption region such that a quality factor (Q-factor) can be tuned. Thus, by adjusting the Q-factor, the resonant cavity photodetector structure can be tuned to achieve a desirable performance. | 2021-01-14 |
20210013357 | Photodiode - In an example, an avalanche photodiode comprises a substrate and a structure comprising a first layer and a second layer, the first and second layers over and parallel to the substrate, wherein the first layer is between the substrate and the second layer. The first layer is an Aluminium Arsenide Antimonide multiplication layer, and wherein the cross-sectional area parallel to the substrate of the first layer is smaller than that of the second layer, thereby forming a recess in a sidewall of the structure. | 2021-01-14 |
20210013358 | DUAL WAVELENGTH LIGHT EMITTING DEVICE, DUAL WAVELENGTH LIGHT TRANSCEIVING DEVICE AND DISPLAY - The present invention discloses a dual wavelength light emitting device comprising: a first light emitting device, configured to emit first kind of light; and a second light emitting device, configured to emit second kind of light. The first light emitting device is stacked above the second light emitting device, or stacked below the second light emitting device. The present invention also discloses a dual wavelength light transceiving device which can transmit light and receive light by the same layer. Comparing with a conventional micro LED, the area occupied by the dual wavelength light emitting device or the dual wavelength light transceiving device can be reduced. | 2021-01-14 |
20210013359 | SYSTEMS AND METHODS FOR LIGHT DIRECTION DETECTION MICROCHIPS - Embodiments of an improved light-direction detection (LDD) device are described herein. The LDD device includes a substrate and at least one predefined structure formed along the substrate by stacking metal layers, contacts, and vias available in the manufacturing process of the device. The predefined structure is formed along a photodiode pair to collectively define an optical sensor configured to detect direction of incident light without need for off-chip components. The device accommodates light direction detection in two or more orthogonal planes. | 2021-01-14 |
20210013360 | METHOD FOR MANUFACTURING STACKED THIN FILM, METHOD FOR MANUFACTURING SOLAR CELL, AND METHOD FOR MANUFACTURING SOLAR CELL MODULE - A method for manufacturing a stacked thin film, includes forming a photoelectric conversion layer on a first transparent electrode by sputtering using a target mainly composed of copper in an oxygen containing atmosphere. An oxygen partial pressure of the sputtering is in a range of 0.01 [Pa] or more and 4.8 [Pa] or less, and 0.24×d [Pa] or more and 2.4×d [Pa] or less when a deposition rate is d [μm/min], in formation of the photoelectric conversion layer. A sputtering temperature is 300° C. or more and 600° C. or less, in formation of the photoelectric conversion layer. | 2021-01-14 |
20210013361 | MANUFACTURING OF A SEMICONDUCTOR PHOTOSENSITIVE DEVICE - The present disclosure relates to a method of manufacturing a semiconductor device, including the successive steps of: a) forming doped germanium on a germanium layer covering a first support; b) covering said doped germanium with a second support; and c) removing the first support. | 2021-01-14 |
20210013362 | METHODS OF MAKING SEMICONDUCTOR RADIATION DETECTOR - Disclosed herein is an apparatus and a method of making the apparatus. The method comprises obtaining a plurality of semiconductor single crystal chunks. Each of the plurality of semiconductor single crystal chunks may have a first surface and a second surface. The second surface may be opposite to the first surface. The method may further comprise bonding the plurality of semiconductor single crystal chunks by respective first surfaces to a first semiconductor wafer. The plurality of semiconductor single crystal chunks forming a radiation absorption layer. The method may further comprise forming a plurality of electrodes on respective second surfaces of each of the plurality of semiconductor single crystal chunks, depositing pillars on each of the plurality of semiconductor single crystal chunks and bonding the plurality of semiconductor single crystal chunks to a second semiconductor wafer by the pillars. | 2021-01-14 |
20210013363 | STACK-LIKE III-V SEMICONDUCTOR PRODUCT AND PRODUCTION METHOD - A stack-like III-V semiconductor product comprising a substrate and a sacrificial layer region arranged on an upper side of the substrate and a semiconductor layer arranged on an upper side of the sacrificial layer region. The substrate, the sacrificial layer region and the semiconductor layer region each comprise at least one chemical element from the main groups HI and a chemical element from the main group V. The sacrificial layer region differs from the substrate and from the semiconductor layer in at least one element. An etching rate of the sacrificial layer region differs from an etching rate of the substrate and from an etching rate of the semiconductor layer region at least by a factor of ten. The sacrificial layer region is adapted in respect of its lattice to the substrate and to the semiconductor layer region. | 2021-01-14 |
20210013364 | METHOD FOR MANUFACTURING CONCENTRATOR PHOTOVOLTAIC MODULE, AND TRANSPORT JIG - A method for manufacturing a concentrator photovoltaic module including: power generating elements whereon sunlight is concentrated by condenser lenses; and a housing accomodating the power generating elements. The housing includes a resin frame body, a metal bottom plate closing a bottom-side opening of the frame body and an inner surface wherein power generating elements are disposed. The method includes: a peripheral edge of the inner surface of the bottom plate connected to a bottom end surface of the frame body, fixing the bottom plate to the frame body creating the housing; and fixing the housing to a transport jig for transporting the housing horizontally. The transport jig includes a support portion corresponding to the bottom end surface of the frame body, and supports the housing. The housing is fixed to the transport jig, with the support portion attached to a peripheral edge of an outer surface of the bottom plate. | 2021-01-14 |
20210013365 | METHOD OF FABRICATING NON-POLAR AND SEMI-POLAR DEVICES USING EPITAXIAL LATERAL OVERGROWTH - A method of fabricating a semiconductor device, comprising: forming a growth restrict mask on or above a III-nitride substrate, and growing one or more island-like III-nitride semiconductor layers on the III-nitride substrate using the growth restrict mask The III-nitride substrate has an in-plane distribution of off-angle orientations with more than 0.1 degree; and the off-angle orientations of an m-plane oriented crystalline surface plane range from about +28 degrees to about −47 degrees towards a c-plane. The island-like III-nitride semiconductor layers have at least one long side and short side, wherein the long side is perpendicular to an a-axis of the island-like III-nitride semiconductor layers. The island-like III-nitride semiconductor layers do not coalesce with neighboring island-like III-nitride semiconductor layers. | 2021-01-14 |
20210013366 | GROUP 13 ELEMENT NITRIDE LAYER, FREE-STANDING SUBSTRATE, FUNCTIONAL ELEMENT, AND METHOD OF PRODUCING GROUP 13 ELEMENT NITRIDE LAYER - A group 13 nitride layer is composed of a polycrystalline group 13 nitride and is constituted by a plurality of monocrystalline particles having a particular crystal orientation approximately in a normal direction. The group 13 nitride comprises gallium nitride, aluminum nitride, indium nitride or the mixed crystal thereof. The group 13 nitride layer includes an upper surface and a bottom surface, and a full width at half maximum of a (1000) plane reflection of X-ray rocking curve on the upper surface is 20000 seconds or less and 1500 seconds or more. | 2021-01-14 |
20210013367 | System and Method for Making Micro LED Display - By using chip-by-chip, mainly separation technology, micro LED display can be made very accurately and efficiently. Firstly, after epitaxial process, the LED epi-wafer is processed into micro LEDs. Secondly, bonding substrates with driving circuits are provided for the LED epi-wafer. Then, each LED chip can be fastened to the substrate chip-by-chip simultaneously or sequentially, and each LED chip may be transferred by using separation technology simultaneously or sequentially. The LED epi-wafer per se can also be provided as LED display substrate. A light conversion layer and color defining layer can be patterned and sequentially formed on each LED chip individually to provide a LED display. | 2021-01-14 |
20210013368 | MICRO-LED TRANSFER METHOD, MANUFACTURING METHOD, DEVICE AND ELECTRONIC APPARATUS - The present disclosure discloses a micro-LED transfer method, a manufacturing method, device and an electronic apparatus. The transfer method comprises: in accordance with a sequence of micro-LEDs of blue, green and red, epitaxially growing micro-LEDs of two or all of the three colors on a single GaAs original substrate; epitaxially growing bumping electrodes corresponding to the micro-LEDs on a receiving substrate; bonding the micro-LEDs of the two or all of the three colors with the bumping electrodes on the receiving substrate; and removing the GaAs original substrate. The method can be used to transfer micro-LEDs of a variety of colors, in order to improve the production efficiency. | 2021-01-14 |
20210013369 | MANUFACTURING METHOD OF SEMICONDUCTOR LIGHT EMITTING DEVICE - Provided a manufacturing method of a semiconductor light emitting device including forming a plurality of light emitting cells that are separated on a first substrate, forming a first planarization layer by providing an insulating material on the plurality of light emitting cells, forming a second planarization layer by providing a photoresist on the first planarization layer to have a flat upper surface, and soft baking the photoresist, and dry etching the second planarization layer to a predetermined depth to expose a portion of the first planarization layer provided on the plurality of light emitting cells, and a portion of the second planarization layer remaining between the plurality of light emitting cells on the first planarization layer, wherein forming the second planarization layer and dry etching are repeated at least once to remove the portion of the second planarization layer provided between the plurality of light emitting cells. | 2021-01-14 |
20210013370 | LIGHT-EMITTING DEVICE AND DISPLAY APPARATUS - Provided are a light-emitting device and a display apparatus. The light-emitting device includes: sub-pixels located on an array substrate, the sub-pixels each includes a first electrode and a second electrode that are disposed opposite to each other, and a quantum migrating layer between the first electrode and the second electrode. The quantum migrating layer includes a non-light-exiting region and a light-exiting region corresponding to a backlight source. Transparent charged particles and quantum dots, which can be driven by an electric field to migrate in the light-exiting region and the non-light-exiting region, are encapsulated in an accommodating cavity of the quantum migrating layer. When there are quantum dots gathered in the light-exiting region, the quantum dots are excited to emit light; when there is no quantum dot in the light-exiting region, the light emitted by the backlight source directly passes and exits through the light-exiting region. | 2021-01-14 |
20210013371 | QUANTUM DOT LED WITH SPACER PARTICLES - Embodiments of the present application relate to the use of quantum dots mixed with spacer particles. An illumination device includes a first conductive layer, a second conductive layer, and an active layer disposed between the first conductive layer and the second conductive layer. The active layer includes a plurality of quantum dots that emit light when an electric field is generated between the first and second conductive layers. The quantum dots are interspersed with spacer particles that do not emit light when the electric field is generated between the first and second conductive layers. | 2021-01-14 |
20210013372 | Combining light-emitting elements of differing divergence on the same substrate - An optoelectronic device includes a semiconductor substrate and a monolithic array of light-emitting elements formed on the substrate. The light-emitting elements include a first plurality of first emitters, configured to emit respective first beams of light with a first angular divergence, at respective first positions in the array, and a second plurality of second emitters, configured to emit respective second beams of light with a second angular divergence that is at least 50% greater than the first angular divergence, at respective second positions in the array. | 2021-01-14 |
20210013373 | Strain-relaxed InGaN-alloy template - The invention is directed to a method for fabricating strain-relaxed InGaN-alloy templates with higher indium compositions, reduced threading-dislocation densities, improved surface morphologies, and lowered point-defect densities. The method employs nanopatterns fabricated onto the surface of GaN-based templates or bulk-GaN substrates using conventional semiconductor processing. The nanopatterns are specifically designed to enable maskless nanoepitaxial growth of InGaN alloys while simultaneously promoting combined elastic and plastic strain relaxation during nanoepitaxy of InGaN alloys in a manner that raises alloy compositions and reduces defect formation. These templates enable subsequent growth of III-Nitride optoelectronics operating at wavelengths spanning most of the visible-light spectrum while simultaneously enabling higher efficiencies than attained using strain-relaxed InGaN alloys grown by conventional planar heteroepitaxy. | 2021-01-14 |
20210013374 | III-NITRIDE OPTOELECTRONIC DEVICES AND METHOD OF PRODUCTION - An optoelectronic device includes an oxide substrate, an oxide epitaxial layer arranged on the oxide substrate, and a III-nitride active layer arranged on the oxide epitaxial substrate. | 2021-01-14 |
20210013375 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device package includes a carrier, a conductive pillar, an adhesive layer and a package body. The conductive pillar is disposed on the carrier. The conductive pillar has a top surface facing away from the carrier. The adhesive layer is disposed on the top surface of the conductive pillar. The package body is disposed on the carrier. The package body has a top surface facing away from the carrier. The top surface has a first portion and a second portion. The first portion and the second portion of the top surface of the package body are discontinuous. | 2021-01-14 |
20210013376 | LIGHT EMITTING DEVICE PACKAGE - Embodiments relate to a light emitting device package and a light source device. A light emitting device package according to the embodiment may include a first package body; a second package body disposed on the first package body, and comprising an opening passing through an upper surface and a lower surface of the second package body; and a light emitting device disposed in the opening, and comprising a first bonding part and a second bonding part. The first package body may include a first opening and a second opening that pass through an upper surface and a lower surface of the first package body. The upper surface of the first package body may be coupled with the lower surface of the second package body, the first bonding part may be disposed on the first opening, and the second bonding part may be disposed on the second opening. | 2021-01-14 |
20210013377 | METHOD TO IMPROVE PERFORMANCE OF DEVICES COMPRISING NANOSTRUCTURES - The invention is in the field of nanostructure synthesis. Provided are highly luminescent core/shell nanostructures with zinc fluoride and zinc acetate bound to their surface. Also provided are methods of preparing the nanostructures, films comprising the nanostructures, and devices comprising the nanostructures. | 2021-01-14 |
20210013378 | SEMICONDUCTOR DEVICE PACKAGE - An embodiment discloses a semiconductor device package comprising: a body including a cavity; a semiconductor device disposed in the cavity; a light transmitting member disposed in the cavity; and an adhesive layer for fixing the light transmitting member to the body, wherein the semiconductor device generates light in an ultraviolet wavelength band, and the adhesive layer comprises polymer resin and wavelength conversion particles which absorb the light in the ultraviolet wavelength band and generate light in a visible wavelength band. | 2021-01-14 |
20210013379 | LIGHT-EMITTING DIES INCORPORATING WAVELENGTH-CONVERSION MATERIALS AND RELATED METHODS - In accordance with certain embodiments, electronic devices feature a polymeric binder, a frame defining an aperture therethrough, and a semiconductor die (e.g., light-emitting or a light-detecting element) suspended in the binder and within the aperture of the frame. | 2021-01-14 |
20210013380 | CONTROLLING OFF-STATE APPEARANCE OF A LIGHT EMITTING DEVICE - Systems for apparatuses formed of light emitting devices. Solutions for controlling the off-state appearance of lighting system designs is disclosed. Thermochromic materials are selected in accordance with a desired off-state of an LED device. The thermochromic materials are applied to a structure that is in a light path of light emitted by the LED device. In the off-state the LED device produces a desired off-state colored appearance. When the LED device is in the on-state, the thermochromic materials heat up and become more and more transparent. The light emitted from the device in its on-state does not suffer from color shifting due to the presence of the thermochromic materials. Furthermore, light emitted from the LED device in its on-state does not suffer from attenuation due to the presence of the thermochromic materials. Techniques to select and position thermochromic materials in or around LED apparatuses are presented. | 2021-01-14 |
20210013381 | Light-Emitting Device - A light emitting device is disclosed. In an embodiment a light-emitting device includes a pixel comprising at least three sub-pixels, wherein a first sub-pixel includes a first conversion element having a green phosphor, wherein a second sub-pixel includes a second conversion element having a red phosphor and wherein a third sub-pixel is free of a conversion element, the third sub-pixel configured to emit blue primary radiation, wherein each sub-pixel has an edge length of at most 100 μm, and wherein the light-emitting device is configured to enhance a gamut coverage of an emitted radiation. | 2021-01-14 |
20210013382 | LIGHT CONVERSION FILM COMPRISING A QUANTUM DOT LAYER, BACKLIGHT UNITS FOR DISPLAY DEVICES INCLUDING THE LIGHT CONVERSION FILM, AND METHOD OF MANUFACTURING A QUANTUM DOT DISPERSION - A light conversion film is disclosed. The light conversion film includes a first transparent support layer and a second transparent support layer are formed on upper and lower surfaces of a quantum dot layer, respectively. The quantum dot layer contains 0.4 to 2.0% by weight of quantum dot particles containing 5% by weight or more and less than 35% by weight of cadmium; 0.05 to 0.75% by weight of cadmium-free quantum dot particles; 0.1 to 10% by weight of scattering agent; and 75 to 98% by weight of matrix material, based on the total weight of the quantum dot layer. A backlight unit for a display device including the light conversion film is disclosed. | 2021-01-14 |
20210013383 | LIGHT-EMITTING DEVICE - A light-emitting device is provided. The light-emitting device includes a light-emitting element having a peak light-emitting wavelength in the range of 440 nm to 470 nm, and a fluorescent member. The fluorescent member includes a first fluorescent material having a peak light-emitting wavelength in the range of 480 nm to less than 520 nm, a second fluorescent material having a peak light-emitting wavelength in the range of 520 nm to less than 600 nm, and a third fluorescent material having a peak light-emitting wavelength in the range of 600 nm to 670 nm. The light-emitting device has a ratio of an effective radiant intensity for melatonin secretion suppression to an effective radiant intensity for blue-light retinal damage of 1.53 to 1.70 when the light-emitting device emits light with a correlated color temperature of 2700 K to less than 3500 K; 1.40 to 1.70 when the light-emitting device emits light with a correlated color temperature of 3500 K to less than 4500 K; 1.40 to 1.70 when the light-emitting device emits light with a correlated color temperature of 4500 K to less than 5700 K; and 1.35 to 1.65 when the light-emitting device emits light with a correlated color temperature of 5700 K to 7200 K. | 2021-01-14 |
20210013384 | WAVELENGTH CONVERSION APPARATUS - Provided is a wavelength conversion apparatus that includes a metal substrate; and a light-emitting ceramic layer. The light-emitting ceramic layer is used for absorbing excitation light and emitting excited light having a wavelength different from that of the excitation light. A metal reflective layer and a silica gel layer are stacked between the metal substrate and the light-emitting ceramic layer, and the reflective layer is used for reflecting the excited light and an unconverted part of the excitation light. The wavelength conversion device can reduce heat generated in the wavelength conversion apparatus, while realizing an aim of emitting excited light having a high illumination intensity in the wavelength conversion apparatus. | 2021-01-14 |
20210013385 | LIGHT EMITTING DEVICE, METHOD OF MANUFACTURING COVERING MEMBER, AND METHOD OF MANUFACTURING LIGHT EMITTING DEVICE - A method of manufacturing a covering member includes: providing a first light-reflective member comprising a through-hole, the through-hole having first and second openings; arranging a light-transmissive resin containing a wavelength-conversion material within the through-hole; distributing the wavelength-conversion material predominantly on a side of the first opening of the through-hole within the light-transmissive resin; and after the step of distributing the wavelength-conversion material, removing a portion of the light-transmissive resin from a side of the second opening of the through-hole. | 2021-01-14 |