03rd week of 2015 patent applcation highlights part 48 |
Patent application number | Title | Published |
20150017741 | PLASMA ETCHING METHOD - In a plasma etching method of plasma-etching a sample which has a first magnetic film, a second magnetic film disposed above the first magnetic film, a metal oxide film disposed between the first magnetic film and the second magnetic film, a second metal film disposed over the second magnetic film and forming an upper electrode, and a first metal film disposed below the first magnetic film and forming a lower electrode, the plasma etching method includes the steps of: a first process for etching the first magnetic film, the metal oxide film, and the second magnetic film by using carbon monoxide gas; and a second process for etching the sample by using mixed gas of hydrogen gas and inactive gas after the first process. In this case, the first metal film is a film containing therein tantalum. | 2015-01-15 |
20150017742 | METHODS FOR MANUFACTURING A DATA STORAGE DEVICE - Methods for manufacturing a data storage device are provided. A method may include forming an interlayer dielectric layer on a substrate, patterning the interlayer dielectric layer in a peripheral region of the substrate to form first trenches, forming first bit lines in the first trenches, patterning the interlayer dielectric layer between the first bit lines in the peripheral region to form second trenches extending along the first trenches after the formation of the first bit lines, and forming second bit lines in the second trenches. | 2015-01-15 |
20150017743 | MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - Memory devices and methods of fabricating the same include a substrate including a cell region and a peripheral circuit region, data storages on the cell region, first bit lines on and coupled to the data storages, first contacts coupled to peripheral transistors on the peripheral circuit region, and second bit lines on and coupled to the first contacts. The second bit lines may each have a lowermost surface lower than a lowermost surface of the data storages. | 2015-01-15 |
20150017744 | METHOD OF REMOVING PARTICLES FROM A DISPLAY PANEL AND APPARATUS FOR PERFORMING THE SAME - A method of removing particles from a display panel is disclosed. In one aspect, the method includes charging the particles and applying an electric field to the charged particles to capture the charged particles. Organic particles and inorganic particles may be forcibly charged to capture the organic and inorganic particles using a metal bar so that the organic and inorganic particles may be substantially removed. | 2015-01-15 |
20150017745 | POLISHING METHOD AND POLISHING APPARATUS - A polishing method capable of preventing damage to a substrate is disclosed. The polishing method includes inspecting a periphery of a substrate for an abnormal portion, polishing the substrate if the abnormal portion is not detected, and not polishing the substrate if the abnormal portion is detected. The abnormal portion of the substrate may be an foreign matter, such as an adhesive, attached to the periphery of the substrate. After polishing of the substrate, the periphery of the substrate may be inspected again for an abnormal portion. | 2015-01-15 |
20150017746 | METHODS OF FORMING A SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes forming a first transistor and a second transistor on a substrate, monitoring processes of forming the first and second transistors to find an error and performing an additional ion implantation process to form a low-concentration dopant region or a halo region on the first transistor or the second transistor corresponding to a found error. | 2015-01-15 |
20150017747 | METHOD FOR FORMING A SOLAR CELL WITH A SELECTIVE EMITTER - A method for producing a solar cell with a selective emitter is disclosed. A semiconductor substrate ( | 2015-01-15 |
20150017748 | APPARATUS AND METHOD FOR MANUFACTURING LED PACKAGE - An apparatus for manufacturing an light emitting diode (LED) package, includes: a heating unit heating an LED package array in a lead frame state in which a plurality of LED packages are installed to be set in an array on a lead frame; a testing unit testing an operational state of each of the LED packages in the LED package array by applying a voltage or a current to the LED package array heated by the heating unit; and a cutting unit cutting only an LED package determined to be a functional product or an LED package determined to be a defective product from the lead frame to remove the same according to the testing results of the testing unit. | 2015-01-15 |
20150017749 | FLEXIBLE PACKAGING SUBSTRATE AND FABRICATING METHOD THEREOF AND PACKAGING METHOD FOR OLED USING THE SAME - Provided herein is a flexible packaging substrate, comprising a first polymer layer; a metal foil layer disposed on the first polymer layer; a second polymer layer disposed on the metal foil layer; and wherein the surface area of the metal foil layer is larger than those of both the first and the second polymer layer. Also provided are a fabricating method for the same and a method for packaging an organic electroluminescent device using the same. The flexible packaging substrate according to the present invention is able to prevent oxygen and moisture from permeating effectively, allowing the service life of the packaged device prolonged. Additionally, the fabrication according to the examples of the present invention was performed through simple processes, and thereby the packaging process was simplified and the packaging performance was improved. | 2015-01-15 |
20150017750 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor light emitting device includes a light emitting chip and a fluorescent material layer. The light emitting chip includes a semiconductor layer, a first electrode, a second electrode, an insulating layer, a first interconnect layer, a second interconnect layer, a first metal pillar, a second metal pillar, and a resin layer. The semiconductor layer includes a light emitting layer, a first major surface, and a second major surface formed on a side opposite to the first major surface. The fluorescent material layer is provided on the first major surface and has a larger planer size than the light emitting chip. | 2015-01-15 |
20150017751 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object is to suppress discharge due to static electricity generated by peeling, when an element formation layer including a semiconductor element is peeled from a substrate. Over the substrate, the release layer and the element formation layer are formed. The support base material which can be peeled later is fixed to the upper surface of the element formation layer. The element formation layer is transformed through the support base material, and peeling is generated at an interface between the element formation layer and the release layer. Peeling is performed while the liquid is being supplied so that the element formation layer and the release layer which appear sequentially by peeling are wetted with the liquid such as pure water. Electric charge generated on the surfaces of the element formation layer and the release layer can be diffused by the liquid, and discharge by peeling electrification can be eliminated. | 2015-01-15 |
20150017752 | METHOD OF MANUFACTURING ORGANIC LIGHT-EMITTING DIODE (OLED) DISPLAY - A method of manufacturing an organic light-emitting diode (OLED) display is disclosed. In one aspect, the method includes forming a color filter on a thin film transistor substrate, forming an organic planarization layer on the color filter, and performing a vacuum heat-treatment on the color filter and organic planarization layer. The method also includes forming a first electrode on the organic planarization layer, forming an organic light-emitting layer on the first electrode, and forming a second electrode on the organic light-emitting layer. The vacuum heat-treatment is performed at a temperature in the range of about 150° C. to about 300° C. under a pressure substantially equal to or lower than about 10 | 2015-01-15 |
20150017753 | THIN FILM DEPOSITION APPARATUS AND MANUFACTURING METHOD OF ORGANIC LIGHT EMITTING DIODE DISPLAY USING THE SAME - The example embodiments provide a thin film deposition apparatus for deposition of an organic material having a low volatility characteristic, and a method for manufacturing an OLED display using the same. A thin film deposition apparatus includes a crucible assembly evaporating an organic material toward a substrate, and a pattern mask provided in one side of the substrate facing the crucible assembly. The crucible assembly includes a crucible coupled with the heater and containing an organic material therein, and a guide pipe coupled to an entrance of the crucible and forming an inner space extended in one direction toward the substrate from the entrance of the crucible. | 2015-01-15 |
20150017754 | COMPOSITION FOR FORMING N-TYPE DIFFUSION LAYER, METHOD FOR PRODUCING SEMICONDUCTOR SUBSTRATE HAVING N-TYPE DIFFUSION LAYER, AND METHOD FOR PRODUCING SOLAR CELL ELEMENT - The invention provides composition for forming an n-type diffusion layer, the composition comprising a compound containing a donor element, a dispersing medium, and an organic filler; a method for producing a semiconductor substrate having an n-type diffusion layer; and a method for producing a photovoltaic cell element. | 2015-01-15 |
20150017755 | Method for fabricating Cu-In-Ga-Se Film Solar Cell - A method for fabricating a Cu—In—Ga—Se film solar cell is provided. The method comprises: a) fabricating a molybdenum back electrode on a substrate; b) fabricating a Cu—In—Ga—Se absorbing layer on the molybdenum back electrode; c) performing an annealing; d) fabricating an In2Se3 or ZnS buffer layer on the Cu—In—Ga—Se absorbing layer; e) fabricating an intrinsic zinc oxide high impedance layer; f) fabricating an indium tin oxide film low impedance layer on the intrinsic zinc oxide high impedance layer; g) fabricating an aluminum electrode on the indium tin oxide film low impedance layer. | 2015-01-15 |
20150017756 | APPARATUS AND METHOD FOR PRODUCING CIGS ABSORBER LAYER IN SOLAR CELLS - A method of forming an absorber layer of a solar cell includes forming a plurality of precursor layers over a surface of a bottom electrode of a solar cell substrate. The step of forming includes depositing a first layer comprising selenium and copper and at least one of gallium or indium over at least a portion of the surface using a sputtering source or an evaporation source, the first layer having a first concentration of copper, depositing a second layer comprising selenium and at least one of the group consisting of copper, gallium or indium over at least the portion of the surface, the second layer having a second concentration of copper less than the first concentration of copper, and annealing the precursor layers to form an absorber layer. | 2015-01-15 |
20150017757 | APPARATUS AND METHODS FOR FORMING THIN FILM SOLAR CELL MATERIALS - A method for forming thin film solar cell materials introducing a first inert gas mixture that includes hydrogen selenide into a chamber at a first pressure value until the chamber reaches a second pressure value and at a first temperature value, wherein the second pressure value is a predefined percentage of the first pressure value. The temperature in the chamber is increased to a second temperature value for a selenization process so that the pressure in the chamber increases to a third pressure value. Residual gas that is generated during the selenization process can be removed from the chamber. A second inert gas mixture that includes hydrogen sulfide is added into the chamber until the chamber reaches a fourth pressure value. The temperature in the chamber is increased to a third temperature value for a sulfurization process. The chamber is cooled after the sulfurization process. | 2015-01-15 |
20150017758 | SYSTEMS, METHODS, AND MEDIA FOR LASER DEPOSITION - In accordance with some embodiments of the disclosed subject matter, mechanisms for pulsed laser deposition are provided. In some embodiments, a system for pulsed laser deposition is provided, the system comprising: a pulsed laser configured to project a pulsed laser beam at a rotating target material and cause metal clusters to be ablated from the rotating target material; and a confinement mechanism configured to control deposition of the metal clusters on a substrate. | 2015-01-15 |
20150017759 | METHOD FOR PRODUCING MULTIPLE-SURFACE IMPOSITION VAPOR DEPOSITION MASK, MULTIPLE-SURFACE IMPOSITION VAPOR DEPOSITION MASK OBTAINED THEREFROM, AND METHOD FOR PRODUCING ORGANIC SEMICONDUCTOR ELEMENT - A method for producing a multiple-surface imposition vapor deposition mask enhances definition and reduces weight even when a size is increased. Each of multiple masks in an open space in a frame is configured by a metal mask having a slit, and a resin mask that is positioned on a front surface of the metal mask and has openings corresponding to a pattern to be produced by vapor deposition arranged by lengthwise and crosswise in a plurality of rows. In formation of the plurality of masks, after each of the metal masks and a resin film material for producing the resin mask are attached to the frame, the resin film material is processed, and the openings corresponding to the pattern to be produced by vapor deposition are formed in a plurality of rows lengthwise and crosswise, whereby the multiple-surface imposition vapor deposition mask of the above described configuration is produced. | 2015-01-15 |
20150017760 | METHOD FOR MANUFACTURING MOLECULAR MEMORY DEVICE - According to one embodiment, a method for manufacturing a molecular memory device includes: forming a first wiring layer including a plurality of first wirings extending in a first direction; forming a sacrificial film on the first wiring layer; forming a plurality of core members on the first wiring layer, the core member extending in a second direction crossing the first direction and being formed from an insulating material different from the sacrificial film; forming a second wiring on a side surface of the core member; removing a portion of the sacrificial film located immediately below the second wiring; embedding a polymer; and embedding an insulating. The embedding a polymer includes embedding a polymer serving as a memory material between the first wiring and the second wiring. The embedding an insulating member includes embedding an insulating member in a space between the second wirings between the core members. | 2015-01-15 |
20150017761 | METHOD FOR FABRICATING THIN-FILM TRANSISTOR - A method for fabricating a thin-film transistor is described. A structure is provided, including a substrate transmitting an excimer laser light, a diffusion prevention film on the substrate, a gate electrode and a gate insulating film on the diffusion prevention film, and an oxide semiconductor layer on the gate insulating film. The structure is irradiated with an excimer laser light from the side of the substrate, so that two outer regions of the oxide semiconductor layer beside the region corresponding to the gate electrode are irradiated by the excimer laser light, with the gate electrode as a mask, to be reduced in resistance and thereby one of the two outer regions forms a source region and the other one forms a drain region. The diffusion prevention film includes a SiN:F film containing fluorine in a SiN film. | 2015-01-15 |
20150017762 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object is to provide a display device with excellent display characteristics, where a pixel circuit and a driver circuit provided over one substrate are formed using transistors which have different structures corresponding to characteristics of the respective circuits. The driver circuit portion includes a driver circuit transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using a metal film, and a channel layer is formed using an oxide semiconductor. The pixel portion includes a pixel transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using an oxide conductor, and a semiconductor layer is formed using an oxide semiconductor. The pixel transistor is formed using a light-transmitting material, and thus, a display device with higher aperture ratio can be manufactured. | 2015-01-15 |
20150017763 | Microelectronic Assembly With Thermally and Electrically Conductive Underfill - A microelectronic assembly may include a microelectronic element having a surface and a plurality of contacts at the surface; a first element consisting essentially of at least one of semiconductor or dielectric material, the first element having a surface facing the surface of the microelectronic element and a plurality of first element contacts at the surface of the first element; electrically conductive masses each joining a contact of the plurality of contacts of the microelectronic element with a respective first element contact of the plurality of first element contacts; a thermally and electrically conductive material layer between the surface of the microelectronic element and the surface of the first element and adjacent conductive masses of the conductive masses; and an electrically insulating coating electrically insulating the conductive masses and the surfaces of the microelectronic element and the first element from the thermally and electrically conductive material layer | 2015-01-15 |
20150017764 | METHOD OF FORMING A SEMICONDUCTOR PACKAGE - A method of forming a semiconductor package includes forming an interconnecting structure on an adhesive layer, wherein the adhesive layer is on a carrier. The method further includes placing a semiconductor die on a surface of the interconnecting structure. The method further includes placing a package structure on the surface of the interconnecting structure, wherein the semiconductor die fits in a space between the interconnecting structure and the package structure. The method further includes performing a reflow to bond the package structure to the interconnecting structure. | 2015-01-15 |
20150017765 | METHOD FOR PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BONDS TO ENCAPSULATION SURFACE - A microelectronic assembly ( | 2015-01-15 |
20150017766 | ELECTRONIC DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - There is provided an electronic device including at least a first electrode, a second electrode disposed to be spaced apart from the first electrode, and an active layer disposed over the second electrode from above the first electrode and formed of an organic semiconductor material. A charge injection layer is formed between the first electrode and the active layer and between the second electrode and the active layer, and the charge injection layer is formed of an organic material having an increased electric conductivity when the charge injection layer is oxidized. | 2015-01-15 |
20150017767 | METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE HAVING SGTS - In a method for producing a semiconductor device, Si pillars that include i-layers, N | 2015-01-15 |
20150017768 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including an active region including a plurality of device regions. The semiconductor device further includes a first device disposed in a first device region of the plurality of device regions, the first device including a first gate structure, first gate spacers disposed on sidewalls of the first gate structure, and first source and drain features. The semiconductor device further includes a second device disposed in a second device region of the plurality of device regions, the second device including a second gate structure, second gate spacers disposed on sidewalls of the second gate structure, and second source and drain features. The second and first source and drain features having a source and drain feature and a contact feature in common. The common contact feature being a self-aligned contact. | 2015-01-15 |
20150017769 | VERTICAL SEMICONDUCTOR DEVICE, MODULE AND SYSTEM EACH INCLUDING THE SAME, AND METHOD FOR MANUFACTURING THE VERTICAL SEMICONDUCTOR DEVICE - A vertical semiconductor device having a vertical channel region is disclosed. The vertical semiconductor device includes a pillar having a vertical channel region, a bit line buried in a semiconductor substrate located at a lower part of the pillar, and a body connection unit configured to couple at least one sidewall of the pillar to the semiconductor substrate. As a result, the floating body effect of the vertical semiconductor device can be more effectively removed. | 2015-01-15 |
20150017770 | 3-D NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A three dimensional (3-D) non-volatile memory device includes a pipe gate including a first pipe gate, a second pipe gate formed on the first pipe gate, and a first interlayer insulating layer interposed between the first pipe gate and the second pipe gate, word lines alternately stacked with second interlayer insulating layers on the pipe gate, a pipe channel buried within the pipe gate, and memory cell channels coupled to the pipe channel and arranged to pass through the word lines and the second interlayer insulating layers. | 2015-01-15 |
20150017771 | 3D NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A 3D non-volatile memory device includes a pipe gate, at least one first channel layer including a first pipe channel layer formed in the pipe gate and a pair of first source side channel layer and first drain side channel layer connected to the first pipe channel layer, and at least one second channel layer including a second pipe channel layer formed in the pipe gate and positioned over the first pipe channel layer and a pair of second source side channel layer and second drain side channel layer connected to the second pipe channel layer. | 2015-01-15 |
20150017772 | Method Of Doping A Polycrystalline Transistor Channel For Vertical NAND Devices - A method of doping the polycrystalline channel in a vertical FLASH device is disclosed. This method uses a plurality of high energy ion implants to dope the channel at various depths of the channel. In some embodiments, these ion implants are performed at an angle offset from the normal direction, such that the implanted ions pass through at least a portion of the surrounding ONO stack. By passing through the ONO stack, the distribution of ranges reached by each ion may differ from that created by a vertical implant. | 2015-01-15 |
20150017773 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In the semiconductor device, a line-type buried gate is formed by burying a non-operating gate (isolation gate) with a polysilicon material to reduce a work function and a Gate Induced Drain Leakage (GIDL) caused by the non-operating gate, resulting in improvement of refresh characteristics of the semiconductor device. Operating gates including a metal conductive material may be formed in a separate step. | 2015-01-15 |
20150017774 | METHOD OF FORMING FINS WITH RECESS SHAPES - Thermal oxidation treatment methods and processes used during fabrication of semiconductor devices are provided. One method includes, for instance: obtaining a device with at least one cavity etched into the device; performing a thermal oxidation treatment to the at least one cavity; and cleaning the at least one cavity. One process includes, for instance: providing a semiconductor device with a substrate, at least one layer over the substrate and at least one fin; forming at least one gate over the fin; doping at least one region below the fin; applying a spacer layer over the device; etching the spacer layer to expose at least a portion of the gate material; etching a cavity into the at least one fin; etching a shaped opening into the cavity; performing thermal oxidation processing on the at least one cavity; and growing at least one epitaxial layer on an interior surface of the cavity. | 2015-01-15 |
20150017775 | Device with a Vertical Gate Structure - A device includes a wafer substrate, a conical frustum structure formed in the wafer substrate, and a gate all-around (GAA) structure circumscribing the middle portion of the conical frustum structure. The conical frustum structure includes a drain formed at a bottom portion of the conical frustum, a source formed at a top portion of the vertical conical frustum, and a channel formed at a middle portion of the conical frustum connecting the source and the drain. The GAA structure overlaps with the source at one side of the GAA structure, crosses over the channel, and overlaps with the drain at another side of the GAA structure. | 2015-01-15 |
20150017776 | EPITAXIAL GROWTH OF DOPED FILM FOR SOURCE AND DRAIN REGIONS - Embodiments of mechanisms for epitaxially growing one or more doped silicon-containing materials to form source and drain regions of finFET devices are provided in this disclosure. The dopants in the one or more doped silicon-containing materials can be driven into the neighboring lightly-doped-drain (LDD) regions by thermal anneal to dope the regions. The epitaxially growing process uses a cyclical deposition/deposition/etch (CDDE) process. In each cycle of the CDDE process, a first and a second doped materials are formed and a following etch removes most of the second doped material. The first doped material has a higher dopant concentration than the second material and is protected from the etching process by the second doped material. The CDDE process enables forming a highly doped silicon-containing material. | 2015-01-15 |
20150017777 | METHOD OF FABRICATING MOS DEVICE - Provided is a method of fabricating a MOS device including the following steps. A gate structure is formed on a substrate and a first spacer is formed at a sidewall of the gate structure. A first implant process is performed to form source and drain extension regions in the substrate. A spacer material layer is formed on the gate structure, the first spacer and the substrate. A treatment process is performed so that stress form the spacer material layer is applied onto and memorized in a channel between two source and drain extension regions. An anisotropic process is performed to remove a portion of the spacer material so that a second spacer is formed. A second implant process is performed to form source and drain regions in the substrate. | 2015-01-15 |
20150017778 | Capacitor in Post-Passivation Structures and Methods of Forming the Same - A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer. | 2015-01-15 |
20150017779 | SEMICONDUCTOR DEVICE HAVING STACKED STORAGE NODES OF CAPACITORS IN CELL REGION SEPARATED FROM PERIPHERAL REGION - Methods of fabricating a semiconductor device are provided. The method includes forming a first mold layer on a in a cell region and a peripheral region, forming first storage nodes penetrating the first mold layer in the cell region and a first contact penetrating the first mold layer in the peripheral region, forming a second mold layer on the first mold layer, forming second storage nodes that penetrate the second mold layer to be connected to respective ones of the first storage nodes, removing the second mold layer in the cell and peripheral regions and the first mold layer in the cell region to leave the first mold layer in the peripheral region, and forming a second contact that penetrates a first interlayer insulation layer to be connected to the first contact. Related devices are also provided. | 2015-01-15 |
20150017780 | Nonvolatile Resistive Memory Element With an Integrated Oxygen Isolation Structure - A nonvolatile resistive memory element includes one or more novel oxygen isolation structures that protect the resistive switching material of the memory element from oxygen migration. One such oxygen isolation structure comprises an oxygen barrier layer that isolates the resistive switching material from other portions of the resistive memory device during fabrication and/or operation of the memory device. Another such oxygen isolation structure comprises a sacrificial layer that reacts with unwanted oxygen migrating toward the resistive switching material during fabrication and/or operation of the memory device. | 2015-01-15 |
20150017781 | METHOD OF FORMING SHALLOW TRENCH ISOLATION STRUCTURE - A method of forming a shallow trench isolation structure is disclosed. Hard mask patterns are formed on a substrate. A portion of the substrate is removed, using the hard mask patterns as a mask, to form first trenches in the substrate, wherein a fin is disposed between the neighboring first trenches. A filling layer is formed in the first trenches. A patterned mask layer is formed on the filling layer. A portion of the filling layer and a portion of the fins are removed, using the patterned mask layer as a mask, to form second trenches in the substrate. A first insulating layer is formed on the substrate filling in the second trenches. | 2015-01-15 |
20150017782 | BONDING DEVICE AND BONDING METHOD - A bonding device for bonding substrates together, includes: a first holding unit configured to hold a first substrate on a lower surface thereof; a second holding unit located below the first holding unit and configured to hold a second substrate on an upper surface thereof; a moving mechanism configured to move the first holding unit or the second holding unit in a horizontal direction and a vertical direction; a first image pickup unit located in the first holding unit and configured to pick up an image of the second substrate held in the second holding unit; and a second image pickup unit located in the second holding unit and configured to pick up an image of the first substrate held in the first holding unit, at least one of the first image pickup unit and the second image pickup unit including an infrared camera. | 2015-01-15 |
20150017783 | METHOD FOR MANUFACTURING BONDED SOI WAFER - The present invention is directed to a method for manufacturing an SOI wafer in which the bonded SOI wafer after the delamination by the ion implantation delamination method is subjected to a rapid thermal oxidation process such that an oxide film is formed on a surface of the SOI layer, the oxide film is removed, the bonded SOI wafer is then subjected to a flattening heat treatment to flatten the surface of the SOI layer, the flattening heat treatment causing migration of silicon atoms of the surface of the SOI layer, and the bonded SOI wafer is then subjected to a sacrificial oxidation process to adjust a film thickness of the SOI layer. The method enables efficient manufacture of a high quality SOI wafer having an SOI layer with sufficiently reduced surface roughness of the SOI layer surface and fewer deep pits in the SOI layer surface. | 2015-01-15 |
20150017784 | SEMICONDUCTOR PROCESSING APPARATUS USING LASER - Provided is a semiconductor processing apparatus, including a first laser beam irradiation unit having a first variable beam expanding telescope and a first galvanometer scanner transferring a first laser beam having a first wavelength, a second laser beam irradiation unit having a second variable beam expanding telescope and a second galvanometer scanner transferring a second laser beam having a second wavelength, and a telecentric lens. | 2015-01-15 |
20150017785 | METHOD OF FORMING SALICIDE BLOCK WITH REDUCED DEFECTS - A method of forming a salicide block with reduced defects is disclosed, the method including performing an ultraviolet cure process on a silicon nitride layer deposited in a previous step. High-energy ultraviolet light used in the ultraviolet cure process breaks the hydrogen-containing chemical bonds such as silicon-hydrogen and nitrogen-hydrogen in the silicon nitride layer, and the dissociated hydrogen forms molecular hydrogen which is thereafter evacuated away by a vacuuming apparatus. In this way, the hydrogen content in the silicon nitride layer can be effectively decreased and the reaction between hydrogen in the silicon nitride layer and photoresist subsequently coated thereon can hence be reduced. As a result, a salicide block with reduced defects can be obtained, thus improving process reliability and product yield. | 2015-01-15 |
20150017786 | Method for Treating Group III Nitride Substrate and Method for Manufacturing Epitaxial Substrate - Provided is a method for treating a group III nitride substrate capable of obtaining, in the case where a group III nitride layer is laminated thereon, a group III nitride substrate that can form an electronic device having excellent characteristics. The method for treating a group III nitride substrate includes the steps of CMPing a surface of a substrate, elevating a temperature of the group III nitride substrate after the CMP process to a predetermined annealing temperature under a nitrogen gas atmosphere, and holding the group III nitride substrate whose temperature has been elevated to the annealing temperature for four minutes or more and eight minutes or less in a first mixed atmosphere of a hydrogen gas and a nitrogen gas or a second mixed atmosphere of a hydrogen gas and an ammonia gas. | 2015-01-15 |
20150017787 | METHOD AND APPARATUS TO REDUCE CONTAMINATION OF PARTICLES IN A FLUIDIZED BED REACTOR - A method and fluidized bed reactor for reducing or eliminating contamination of silicon-coated particles are disclosed. The metal surface of one or more fluidized bed reactor components is at least partially coated with a hard protective layer comprising a material having an ultimate tensile strength of at least 700 MPa at 650° C. | 2015-01-15 |
20150017788 | METHOD FOR MAKING SILICON-GERMANIUM ABSORBERS FOR THERMAL SENSORS - A system and method for growing polycrystalline silicon-germanium film that includes mixing a GeH | 2015-01-15 |
20150017789 | ELECTRONIC DEVICE USING GROUP III NITRIDE SEMICONDUCTOR AND ITS FABRICATION METHOD AND AN EPITAXIAL MULTI-LAYER WAFER FOR MAKING IT - The present invention discloses an electronic device using a group III nitride substrate fabricated via the ammonothermal method. By utilizing the high-electron concentration of ammonothermally grown substrates having the dislocation density less than 10 | 2015-01-15 |
20150017790 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes: preparing a Si substrate having a flat portion with flat front and back surfaces and a bevel portion located at a periphery of the flat portion; forming a III-V nitride semiconductor film on the front surface of the Si substrate by epitaxial growth; and after forming the III-V nitride semiconductor film, grinding the Si substrate from the back surface. Amounts of working at the bevel portion on the front surface and the back surface of an outermost end portion of the bevel portion are asymmetrical. A first thickness measured from the front surface of the flat portion to the outermost end portion is smaller than a second thickness measured from the back surface of the flat portion to the outermost end portion. | 2015-01-15 |
20150017791 | FILM-FORMING COMPOSITION AND ION IMPLANTATION METHOD - There is provided an ion implantation method, a composition for forming an ion implantation film and a resist underlayer film-forming composition. An ion implantation method including the steps of: forming a film by applying a film-forming composition containing a compound including an element in group 13, group 14, group 15, or group 16 and an organic solvent onto a substrate and baking the film-forming composition; and implanting impurity ions into the substrate from above through the film and introducing the element in group 13, group 14, group 15, or group 16 in the film into the substrate. The film-forming composition is a film-forming composition for ion implantation containing a compound including an element in group 13, group 14, group 15, or group 16, and an organic solvent. In addition, the underlayer film-forming composition contains a compound having at least two borate ester groups. | 2015-01-15 |
20150017792 | METHOD AND SYSTEM FOR DIFFUSION AND IMPLANTATION IN GALLIUM NITRIDE BASED DEVICES - A method of forming a doped region in a III-nitride substrate includes providing the III-nitride substrate and forming a masking layer having a predetermined pattern and coupled to a portion of the III-nitride substrate. The III-nitride substrate is characterized by a first conductivity type and the predetermined pattern defines exposed regions of the III-nitride substrate. The method also includes heating the III-nitride substrate to a predetermined temperature and placing a dual-precursor gas adjacent the exposed regions of the III-nitride substrate. The dual-precursor gas includes a nitrogen source and a dopant source. The method further includes maintaining the predetermined temperature for a predetermined time period, forming p-type III-nitride regions adjacent the exposed regions of the III-nitride substrate, and removing the masking layer. | 2015-01-15 |
20150017793 | FORMATION OF LOCALISED MOLTEN REGIONS IN SILICON CONTAINING MULTIPLE IMPURITY TYPES - A method for creating an inwardly extending impurity distribution profile in a substrate comprising crystalline silicon material having a background doping of a first impurity type, comprising: a) providing one or more additional impurity sources with at least two different types of impurity atoms within the substrate or in proximity to the surface of the substrate, with each of these impurity atoms having different diffusion coefficients or segregation coefficients; b) locally melting a point on the surface of the substrate with a laser, whereby the at least two different types of impurity atoms are incorporated into the melted silicon material; c) removing the laser to allow the silicon material to recrystallise; d) controlling a rate of application and/or removal of the laser to control the creation of the impurity distribution profile, with different distribution profiles for each of the at least two types of impurity atoms in the recrystallised material. | 2015-01-15 |
20150017794 | METHODS FOR FORMING DOPED SILICON OXIDE THIN FILMS - The present disclosure relates to the deposition of dopant films, such as doped silicon oxide films, by atomic layer deposition processes. In some embodiments, a substrate in a reaction space is contacted with pulses of a silicon precursor and a dopant precursor, such that the silicon precursor and dopant precursor adsorb on the substrate surface. Oxygen plasma is used to convert the adsorbed silicon precursor and dopant precursor to doped silicon oxide. | 2015-01-15 |
20150017795 | Non-Volatile Memory With Silicided Bit Line Contacts - An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes. | 2015-01-15 |
20150017796 | TECHNIQUES PROVIDING METAL GATE DEVICESWITH MULTIPLE BARRIER LAYERS - A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers. | 2015-01-15 |
20150017797 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING METAL-CONTAINING CONDUCTIVE LINE - A semiconductor device includes: a semiconductor substrate having a trench therein, a metal-containing barrier layer extending along an inner wall of the trench and defining a wiring space in the trench, the wiring space having a first width along a first direction, and a metal-containing conductive line on the metal-containing barrier layer in the wiring space, and including at least one metal grain having a particle diameter of about the first width along the first direction. | 2015-01-15 |
20150017798 | METHOD OF MANUFACTURING THROUGH-SILICON-VIA - A method of manufacturing through-silicon-via (TSV) including the steps of sequentially forming a liner layer and a metal layer in a TSV hole, performing a chemical mechanical polishing process to remove the metal layer on the substrate so that the remaining metal layer in the TSV hole becomes a TSV, and forming a cap layer on the substrate without performing a NH | 2015-01-15 |
20150017799 | METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A patterned dielectric layer with a plurality of openings is formed on the substrate. A barrier layer is deposited in the openings by a first tool and a sacrificing protection layer is deposited on the barrier layer by the first tool. The sacrificing layer is removed and a metal layer is deposited on the barrier layer by a second tool. | 2015-01-15 |
20150017800 | Interconnect Structure for Semiconductor Devices - A method of manufacturing a semiconductor device with a cap layer for a copper interconnect structure formed in a dielectric layer is provided. In an embodiment, a conductive material is embedded within a dielectric layer, the conductive material comprising a first material and having either a recess, a convex surface, or is planar. The conductive material is silicided to form an alloy layer. The alloy layer comprises the first material and a second material of germanium, arsenic, tungsten, or gallium. | 2015-01-15 |
20150017801 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME - One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a substrate; forming a dielectric layer over the substrate; forming a first opening and a second opening at least partially simultaneously through the dielectric layer over the substrate; and forming a third opening through the bottom surface of the first opening and into at least a portion of the substrate. | 2015-01-15 |
20150017802 | Double-etch nanowire process - In an aspect of this disclosure, a method is provided comprising the steps of: (a) providing a silicon-containing substrate, (b) depositing a first metal on the substrate, (c) etching the substrate produced by step (b) using a first etch, and (d) etching the substrate produced by step (c) using a second etch, wherein the second etch is more aggressive towards the deposited metal than the first etch, wherein the result of step (d) comprises silicon nanowires. The method may further comprise, for example, steps (b1) subjecting the first metal to a treatment which causes it to agglomerate and (b2) depositing a second metal. | 2015-01-15 |
20150017803 | CUSTOMIZED ALLEVIATION OF STRESSES GENERATED BY THROUGH-SUBSTRATE VIA(S) - Fabrication of through-substrate via (TSV) structures is facilitated by: forming at least one stress buffer within a substrate; forming a through-substrate via contact within the substrate, wherein the through-substrate via structure and the stress buffer(s) are disposed adjacent to or in contact with each other; and where the stress buffer(s) includes a configuration or is disposed at a location relative to the through-substrate via conductor, at least in part, according to whether the TSV structure is an isolated TSV structure, a chained TSV structure, or an arrayed TSV structure, to customize stress alleviation by the stress buffer(s) about the through-substrate via conductor based, at least in part, on the type of TSV structure. | 2015-01-15 |
20150017804 | METHOD OF FORMING A PATTERN IN A SEMICONDUCTOR DEVICE AND METHOD OF FORMING A GATE USING THE SAME - A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized. | 2015-01-15 |
20150017805 | WAFER PROCESSING APPARATUS HAVING INDEPENDENTLY ROTATABLE WAFER SUPPORT AND PROCESSING DISH - An apparatus for processing a wafer is disclosed that includes a wafer support and a processing base. The wafer support is configured to support a wafer in a processing position, and to rotate the wafer about a first substantially vertical axis while in the processing position. The processing base includes a shallow dish configured to receive processing chemistry. The wafer support places the wafer in contact with the processing chemistry while in the processing position. The shallow dish is rotatable about a second substantially vertical axis when the wafer support is in the processing position. The rotation of the wafer is independent of the rotation of the shallow dish. Further, the processing base may include a heating element, such as an infrared heating element, that is disposed to locally elevate the temperature of of the shallow dish and chemistry contained in it. | 2015-01-15 |
20150017806 | POLISHING AGENT, POLISHING AGENT SET, AND SUBSTRATE POLISHING METHOD - The polishing agent of the invention comprises water, an abrasive grain containing a hydroxide of a tetravalent metal element, polyalkylene glycol, and at least one cationic polymer selected from the group consisting of allylamine polymers, diallylamine polymers, vinylamine polymers and ethyleneimine polymers. | 2015-01-15 |
20150017807 | METHODS OF FORMING PATTERNS - Methods of forming patterns are provided. The methods may include sequentially forming an etch-target layer and a photoresist layer on a substrate, exposing two first portions of the photoresist layer to light to transform the two first portions into two first photoresist patterns and exposing a second portion of the photoresist layer to light to transform the second portion into a second photoresist pattern disposed between the two first photoresist patterns. The method may also removing portions of the photoresist layer to leave the two first photoresist patterns and the second photo resist pattern on the etch-target layer such that the etch-target layer is exposed. | 2015-01-15 |
20150017808 | METHOD OF FORMING FINE PATTERNS OF SEMICONDUCTOR DEVICE - A method of forming a micro pattern of a semiconductor device may include forming an acid-extinguisher containing film on a substrate, forming a photoresist film containing a potential acid on the acid-extinguisher containing film, forming an exposed area containing acids by exposing a portion of the photoresist film to light, forming an insoluble polymer thin film between the acid-extinguisher containing film and the exposed area by extinguishing the acids of the exposed area at an interface between the acid-extinguisher containing film and the exposed area, developing the photoresist film to form a space exposing the insoluble polymer thin film in the exposed area and a photoresist pattern integrally connected to the insoluble polymer thin film, exposing the acid-extinguisher containing film through the space by removing the insoluble polymer thin film, and removing the acid-extinguisher containing film exposed through the space. | 2015-01-15 |
20150017809 | FLUOROCARBON BASED ASPECT-RATIO INDEPENDENT ETCHING - A method for etching features into an etch layer disposed below a patterned mask is provided. At least three cycles are provided, where each cycle comprises providing an ion bombardment, by creating a plasma, of the etch layer to create activated sites of surface radicals in parts of the etch layer exposed by the patterned mask, extinguishing the plasma, exposing the etch layer to a plurality of fluorocarbon containing molecules, which causes the fluorocarbon containing molecules to selectively bind to the activated sites, wherein the selective binding is self limiting, and providing an ion bombardment of the etch layer to initiate an etch reaction between the fluorocarbon containing molecule and the etch layer, wherein the ion bombardment of the etch layer to initiate an etch reaction causes the formation of volatile etch products formed from the etch layer and the fluorocarbon containing molecule. | 2015-01-15 |
20150017810 | DUAL CHAMBER PLASMA ETCHER WITH ION ACCELERATOR - The embodiments herein generally deal with semiconductor processing methods and apparatus. More specifically, the embodiments relate to methods and apparatus for etching a semiconductor substrate. A partially fabricated semiconductor substrate is provided in a reaction chamber. The reaction chamber is divided into an upper sub-chamber and a lower sub-chamber by a grid assembly. Plasma is generated in the upper sub-chamber, and the substrate is positioned in the lower sub-chamber. The grid assembly includes at least two grids, each of which is negatively biased, and each of which includes perforations which allow certain species to pass through. The uppermost grid is negatively biased in order to repel electrons. The lowermost grid is biased further negative (compared to the uppermost grid) in order to accelerate positive ions from the upper to the lower sub-chamber. Etching gas is supplied directly to the lower sub-chamber. The etching gas and ions react with the surface of the substrate to etch the substrate as desired. | 2015-01-15 |
20150017811 | METHOD FOR PROCESSING BASE BODY TO BE PROCESSED - An exemplary embodiment provides a method which etches a second layer in a base body to be processed having a first layer containing Ni and Si and a second layer containing Si and N which are exposed to a surface thereof. The method according to the exemplary embodiment includes (a) preparing a base body to be processed in a processing chamber, and (b) supplying a first processing gas which contains carbon and fluorine but does not contain oxygen into the processing chamber and generating plasma in the processing chamber. | 2015-01-15 |
20150017812 | SEQUENTIAL PRECURSOR DOSING IN AN ALD MULTI-STATION/BATCH REACTOR - Disclosed herein are methods of depositing layers of material on multiple semiconductor substrates at multiple processing stations within one or more reaction chambers. The methods may include dosing a first substrate with film precursor at a first processing station and dosing a second substrate with film precursor at a second processing station with precursor flowing from a common source, wherein the timing of said dosing is staggered such that the first substrate is dosed during a first dosing phase during which the second substrate is not substantially dosed, and the second substrate is dosed during a second dosing phase during which the first substrate is not substantially dosed. Also disclosed herein are apparatuses having a plurality of processing stations contained within one or more reaction chambers and a controller with machine-readable instructions for staggering the dosing of first and second substrates at first and second processing stations. | 2015-01-15 |
20150017813 | Semiconductor Device Manufacturing Method and Substrate Treatment System - A semiconductor device manufacturing method that includes: forming a gate insulating film containing a hafnium oxide and a zirconium oxide on a workpiece having a source, a drain and a channel; and subjecting the gate insulating film to a crystallization heat treatment at a temperature of 600 degrees C. or less is provided. The gate insulating film subjected to the crystallization heat treatment has a relative permittivity of 27 or more. | 2015-01-15 |
20150017814 | METHOD OF FORMING GATE OXIDE LAYER - A method of forming a gate oxide layer is disclosed, which introduces a rapid laser annealing process, performed on the surface of the gate SiON layer, prior to a high-temperature annealing process performed on the gate SiON layer. This enables the method of the invention to remove the intrinsic oxide layer, protect the doped nitrogen atoms from the adverse influence of organic absorption, and lead to the formation of an amorphized surface layer which is able to prevent nitrogen atoms located around the surface from escaping by volatilization and nitrogen atoms beneath the surface from diffusing towards the SiO | 2015-01-15 |
20150017815 | Combinatorial Non-Contact Wet Processing - An apparatus and method for combinatorial non-contact wet processing of a liquid material may include a source of a liquid material, a first reaction cell, a second reaction cell, a first plurality of gas jets disposed within an interior of the first reaction cell, the first plurality of gas jets configured to atomize the liquid material transferred to the interior of the first reaction cell, a second plurality of gas jets disposed within an interior of the second reaction cell, the second plurality of gas jets configured to atomize the liquid material transferred to the interior of the second reaction cell, a first vacuum element disposed along a periphery of the first reaction cell, and a second vacuum element disposed along a periphery of the at least a second reaction cell. | 2015-01-15 |
20150017816 | METHOD FOR PERFORMING LASER CRYSTALLIZATION - A method for performing a laser crystallization is provided. The method includes generating a laser beam, refracting the laser beam to uniformize an intensity of the laser beam at a focal plane of the laser beam. The laser beam whose intensity is uniformized is applied into an object substrate mounted with a stage. | 2015-01-15 |
20150017817 | LASER PROCESSING APPARATUS AND LASER PROCESSING METHOD - A laser processing apparatus includes a laser beam generating device that generates a first pulse laser beam for temporarily increasing a light absorptance in a predetermined region of a processing object, and a second pulse laser beam to be absorbed in the predetermined region in which the light absorptance has temporarily increased, and a support portion that is provided on a downstream of the first pulse laser beam and the second laser beam generated by the laser beam generating device and has a placement surface for placing the processing object. The laser beam generating device emits the second pulse laser beam with a delay with respect to the first pulse laser beam by a delay time within a predetermined period of time before the light absorptance that has temporarily increased in the predetermined region returns to an original value. | 2015-01-15 |
20150017818 | METHOD AND STRUCTURE OF PENETRATION AND COMBINATION FOR FLEXIBLE CIRCUIT BOARD WITH HINGE ASSEMBLY - Disclosed are a method and a structure of penetration and combination for a flexible circuit board with a hinge assembly. A pre-formed flexible circuit board is processed by taking a pre-folding line as a center line to fold a connection section of the flexible circuit board toward the terminal distribution section. Then, the connection section is rolled in a direction toward the terminal distribution section so as to make the connection section forming a rolled body. The rolled body is then put through the bore of the hinge assembly to have the rolled body completely extend through the bore of the hinge assembly so that the extension section of the flexible circuit board is positioned in the bore of the hinge assembly and the first end and the second end are respectively located at opposite sides of the bore of the hinge assembly. | 2015-01-15 |
20150017819 | FOLDABLE ELECTRICAL CONNECTOR-HOUSING SYSTEM AND METHOD OF MANUFACTURE THEREOF - A system and method of manufacture of a foldable electrical connector-housing system includes: a first end panel with an outer first end panel side having first end panel contacts; a second end panel having an outer second end panel side; a clip mechanism in at least one of the two end panels for attaching the foldable electrical connector-housing system to a flat surface; a fold mechanism is connected between the first end panel and the second end panel for folding into a folded configuration; and an electronic unit on the first end panel, the electronic unit coupled to the first end panel contacts. | 2015-01-15 |
20150017820 | ELECTRONIC SYSTEM AND CONNECTING MECHANISM THEREOF - A connecting mechanism for connecting an electronic device to a docking station includes a first socket, a first magnet, a fixing member, a first magnetic induction member, a first engaging member and a first driving member. The first socket is movably disposed in the electronic device and a first engaging recess is formed on a side of the first socket. The first magnet is disposed in the first socket. The fixing member is disposed on the docking station. The first magnetic induction member is disposed on the fixing member and corresponding to the first magnet. The first engaging member is movably disposed on the fixing member and has a first engaging portion. The first driving member is disposed between the fixing member and the first engaging member. | 2015-01-15 |
20150017821 | ELECTRICAL CONNECTOR ASSEMBLY WITH A SUPPORTING PLATE AND ASSEMBLY METHOD OF THE SAME - An electrical connector assembly includes an electrical connector and a complementary connector mated with the electrical connector. The electrical connector includes a shell and a terminal module received in the shell. The shell defining a mating portion extending forwardly and a receiving room recessed from the rear face thereof. The mating portion defines a mating face at a side surface thereof. The terminal module includes an insulator and a plurality of first terminals retained in the insulator. The insulator defines a first face and a second face opposite to the first face. The first terminals includes contacting portions protruding from the first face of the insulator. A supporting plate is inserted between the second face of the insulator and an inner surface of the receiving room and pushing the contacting portions of the first terminals exposed to the mating face. | 2015-01-15 |
20150017822 | TERMINAL SET OF ELECTRICAL CONNECTOR - A terminal set of an electrical connector includes signal terminal duos and ground terminal duos. The signal terminal duos have two signal terminals. The signal terminals are spaced apart by a first distance and each have a first recess. The direction of the depth of the first recess equals the longitudinal direction of the signal terminals. The ground terminal duos have two ground terminals. The signal terminal duos are disposed between the ground terminals. The ground terminals each have a second recess. The direction of the depth of the second recess equals the longitudinal direction of the ground terminals. The ground terminal and the adjacent signal terminal are spaced apart by a second distance. The first distance is shorter than the second distance. The ground terminals each partially bulges out transversely to form at least a bulging portion. The terminal set features terminal electrical impedance and alleviated inter-terminal resonance. | 2015-01-15 |
20150017823 | CONNECTOR - In the connector disclosed herein, a shunting member is arranged between the case and the cover member. The shunting member has a first contact piece elastically deformed by contact with a terminal inserted into a first terminal hole in the case, and a second contact piece elastically deformed by contact with a terminal inserted into a second terminal hole. | 2015-01-15 |
20150017824 | LOCK DEVICE FOR ELECTRONIC APPARATUS - A lock device for electronic apparatus includes a lock body and a key member. The lock body includes a front end, a rear end, and a bottom side defined between the front and the rear end and having at least one retaining section provided thereon. The lock body is configured for inserting into a slot on an electronic apparatus. When the lock body is inserted into the slot, the bottom side of the lock body is located corresponding to a plurality of terminals in the slot with the retaining section abutted against inner sides of the terminals, so that the lock body is held in the slot to lock the same. The key member is configured for detachably engaging with a lock core structure of the lock body, so that the lock body can be inserted into and extracted from the slot only with the key member. | 2015-01-15 |
20150017825 | Lever-Type Connector - A fitting operation lever includes rotation fulcrum holes rotationally engaged with boss portions on a first connector housing, boss guiding grooves enabling the boss portions and the rotation fulcrum holes to be engaged with or disengaged, flexible arms extending from lever main bodies so as to be superposed on outer surfaces of an outer cylindrical wall portion of a second connector housing a fitting starting time of the connector housings, and action point projecting portions provided at distal end sides of the flexible arms so as to be engaged with lever locking holes in the outer cylindrical portion at the fitting starting time. The engagement of the action point projecting portions with the lever locking holes can be released by deflecting and displacing the distal end sides in a direction in which the distal end sides move away from the outer surfaces. | 2015-01-15 |
20150017826 | ELECTRICAL CONNECTOR HOUSING - The invention relates to a front housing of an electrical connector, particularly for sealed applications, said front housing being designed to be connected to a base and being configured to be at least partially received in a main housing of said electrical connector, said front housing comprising: at least one locking means configured to engage a corresponding locking zone of said main housing so as to lock said front housing to said main housing, and said front housing further comprising a plurality of contact sockets designed to each receive an electrical conductor to connect to said base. The invention further relates to a main electrical connector housing, to an electrical connector, to a base and to an electrical connector assembly. | 2015-01-15 |
20150017827 | INTERCONNECTION SEAL - A seal for a cable and connector interconnection includes a unitary elastic body with a bore therethrough. The bore is provided with a cable outer diameter seal portion at a cable end, the cable outer diameter seal portion adjacent a connector cavity portion, the connector cavity portion adjacent a coupling nut cavity portion, and the coupling nut cavity portion adjacent a connector neck seal portion with a bulkhead seal at a connector end. The coupling nut cavity portion is longitudinally aligned with a coupling nut of the connector and is provided with a greater inner diameter than the cable outer diameter seal portion and the connector neck seal portion. The bulk head seal is provided with an outer diameter greater than an outer diameter of the connector neck seal portion. | 2015-01-15 |
20150017828 | Linkage Apparatus for Plugging PCB Board - A linkage apparatus is provided. The linkage apparatus is disposed between a bottom plate and a carrier plate, and the linkage apparatus includes a drag link and an “L” shape swing link. The drag link is rotatably connected to an end of the “L” shape swing link, and the drag link and the bottom plate are connected to a fixing pin by using a horizontal guide groove; a corner in the middle of the swing link is rotatably connected to the bottom plate, and another end is fastened to the carrier plate; another fixing pin connects the bottom plate and the carrier plate. The swing link is driven by the drag link, so that the carrier plate can be driven to vertically move. Therefore, hot plugging of a peripheral component interconnect (PCI) express card fastened on the carrier plate and plugging of another printed circuit board (PCB) that requires two-dimensional plugging can be implemented without interrupting a power supply. | 2015-01-15 |
20150017829 | CONNECTION STRUCTURE OF BRAIDED-SHIELD-TYPE ELECTRIC WIRE AND METHOD FOR MANUFACTURING SHIELD ELECTRIC WIRE HARNESS - A connection structure of a braided-shield-type electric wire for connecting the braided-shield-type electric wire including a plurality of sheathed electric wires and a braided shield member surrounding the sheathed electric wires to a connector and for electrically connecting the braided shield member to a shield shell in a connector housing, the connection structure comprising: a retainer that is arranged inside the braided shield member to hold the sheathed electric wires in a slidable state; a first annular conductive member that is fitted to an outer peripheral side of the retainer in a state where the braided shield member is sandwiched therebetween; and a second annular conductive member that is fitted to an outer peripheral side of the first annular conductive member in a state where the braided shield member is sandwiched therebetween. | 2015-01-15 |
20150017830 | CONNECTOR ASSEMBLY WITH PLATE FOR CONTACT NESTING AND EFFECTIVE HEAT DISSIPATION PATH - A connector assembly includes a plug connector and a receptacle connector mateable with each other. The plug connector includes a plug insulative housing and a pair of plug power contacts. The plug insulative housing includes a first plug cavity, a first plate cantileveredly extending into the first plug cavity, and upper and lower plug contact slots in communication with the first plug cavity. The pair of plug power contacts are respectively received in the upper and lower plug contact slots. Each plug power contact includes a flat contacting section exposed to the first plug cavity and a first soldering section. The flat contacting sections are positioned on upper and lower surfaces of the first plate, respectively. The plug connector and the receptacle connector define heat dissipation channels in communication with each other in order that generating heat can be effectively dissipated to the air. | 2015-01-15 |
20150017831 | CONNECTOR ASSEMBLY - A connector assembly includes a first connector and a second connector. The first connector is coupled to a first electronic device, and the second connector is coupled to a second electronic device and detachably mated with the first connector. The first connector includes a first housing and a magnetic member. The magnetic member is installed inside the first housing and for generating magnetic field. The second connector includes a second housing and a magnetic sensor disposed in the second housing. The magnetic sensor senses the magnetic field generated by the magnetic member when the second connector is mated with the first connector, so as to drive the second electronic device to power the first electronic device. | 2015-01-15 |
20150017832 | ELECTRICAL CONNECTOR - The invention relates to an electrical connector for connecting an electrical device to an electrical conductor ( | 2015-01-15 |
20150017833 | TERMINAL CRIMPED WIRE - A terminal crimped wire includes a wire including a conductor and an insulation sheath covering a circumference of the conductor, a crimping terminal crimped to the wire, an anticorrosion material which covers an exposed part of the wire drawn out of the crimping terminal, and an elastic member provided along a circumference of the wire. The wire is crimped to the crimping terminal via the elastic member interposed therebetween. | 2015-01-15 |
20150017834 | OUTLET FACEPLATE EXTENSION - An outlet faceplate extension device includes female receiving components at a first side, male electronic components at a second side, and a rim that is connectable to furniture. | 2015-01-15 |
20150017835 | UNIVERSAL SERIAL BUS APPARATUS AND ELECTRONIC DEVICE INCLUDING UNIVERSAL SERIAL BUS APPARATUS - An electronic device includes a power receiver that manages power transmitted from an outside; and a receptacle including a plurality of first basic connection terminals based on a first Universal Serial Bus (USB) interface and a plurality of first expansion connection terminals based on a second USB interface, wherein the first expansion connection terminals includes one or more first power supply terminals that transmit power received through a cable device connected with the receptacle to the power receiver. | 2015-01-15 |
20150017836 | ACTIVE PLUG CONNECTOR AND METHOD FOR ASSEMBLING THE SAME - An active plug connector ( | 2015-01-15 |
20150017837 | HIGH SPEED COMMUNICATION JACK - A high speed communication jack including a housing including a port for accepting a plug, the port including a plurality of pins each connected to a corresponding signal line in the plug and a shielding case surrounding the housing. A flexible circuit board between the shielding case and the housing having a substrate, a plurality of vias extending through the substrate with each via being configured to accommodate a pin on the housing, a plurality of traces on a first side of the substrate, with each trace extending from a corresponding one of the plurality of vias, and a shielding plane on a second side of the substrate opposite the first side of the substrate. | 2015-01-15 |
20150017838 | ELECTRICAL CONNECTOR WITH ENHANCED STRUCTURE - An electrical connector includes an housing and a plurality of first terminals The housing includes a first side wall, a second side wall opposite to the first side wall and two end walls connecting with the first side wall with the second side wall. The first side wall defining a plurality of first terminal passageways arranged in an inner surface thereof. Every adjacent first terminal passageways being partitioned with spaced walls and the spaced walls and the inner surface of the first side wall being on a same plane, The first terminals accommodated in the first terminal passageways. Some of the spaced walls further integrally extend enhanced walls respectively to unitarily connect with the second side wall, thereby defining a base portion located at a rear portion of the housing and a mating cavity in front of the base portion. | 2015-01-15 |
20150017839 | ELECTRICAL CONNECTOR - An electrical connector ( | 2015-01-15 |
20150017840 | SHIELDED CIRCULAR PLUG CONNECTOR UNIT WITH SYMMETRICALLY ARRANGED PLUG CONTACTS - A circular plug connector unit for shielded electrical cables, comprising an insulating body that is enveloped by a shielding sleeve, wherein plural electrical socket shaped plug contacts and/or pin shaped plug contacts are arranged in receiving cavities in the insulating body, wherein the shielding sleeve is interlocked with the insulating body. The plug side end of the shielding sleeve includes an even number of axially extending sleeve segments which are separated by longitudinal slots which are advantageously configured as sleeve segments that are short in axial direction and sleeve segments that are long in axial direction. Sleeve segments which are arranged in sequence advantageously have a uniform radial offset relative to each other in an alternating direction, wherein the sleeve segments of two identically configured shielding sleeves are insertable into one another with a rotational offset in circumferential direction of 360° divided by a number of the sleeve segments. | 2015-01-15 |