03rd week of 2014 patent applcation highlights part 30 |
Patent application number | Title | Published |
20140016379 | Voltage Source Converter and Method for Controlling the Converter - A control apparatus for use with a voltage source converter includes legs each of which is configured by a plurality of converter modules each having capacitors. Each of the legs has a first terminal on a positive side and a second terminal on a negative side. The control apparatus is operative to create command pulses for operating the converter modules to operate the converter modules. The command pulses have a frequency that is a non-integral multiple of a frequency of a system voltage. The non-integral multiple is 3.5, for example. | 2014-01-16 |
20140016380 | MULTI-LEVEL VOLTAGE CONVERTER - A multi-level voltage converter includes a multi-point converter circuit and at least one full bridge inverter circuit. The multi-point converter circuit is configured for converting a DC voltage into an intermediate multi-level voltage. The full bridge inverter circuit is electrically connected in series with the multi-point converter circuit and configured for receiving the intermediate multi-level voltage to generate a multi-level output voltage corresponding to a single phase output. | 2014-01-16 |
20140016381 | CURRENT DETECTING CIRCUIT, CONTROLLING CIRCUIT AND POWER CONVERSION CIRCUIT - The present invention provides a current detection circuit, a controlling circuit using the current detection circuit and a power conversion circuit using the controlling circuit, the current detection circuit comprises a sample keeping circuit, a rising edge detection circuit, a falling edge detection circuit, a sequential controlling circuit, a synchronous detection circuit and a lowpass filter. The inventive current detection circuit for the power conversion circuit obtains signals of the output current by detecting loop current of the master switch and processing the loop current. | 2014-01-16 |
20140016382 | Space Vector Modulation for Multilevel Inverters - Inverter is modulated based on first, second, and third switching states determined according to a reference vector represented as a sum of a remainder vector connecting the reference vector with a first vertex of a modulation triangle and a set of vertex vectors connecting a center vertex of space vector diagram with the first vertex. A first switching state of the inverter at the first vertex is determined based on angles of vertex vectors in the set. A second switching state of the inverter at a second vertex of the modulation triangle and a third switching state of the inverter at a third vertex of the modulation triangle are determined based on the first switching state and the remainder vector. | 2014-01-16 |
20140016383 | Electronic Device and Video System - This electronic device includes a control portion receiving DC power through an AC-DC conversion portion from an AC power supply and a connection portion connected to an external device in a state where the connection portion can receive DC power from the external device, while the control portion is configured to perform control of stopping receiving of the DC power received by the control portion through the AC-DC conversion portion from the AC power supply when the control portion receives DC power from the external device through the connection portion in a standby state. | 2014-01-16 |
20140016384 | CURRENT SENSING CIRCUIT AND CONTROL CIRCUIT THEREOF AND POWER CONVERTER CIRCUIT - A current sensing circuit and the control circuit thereof and a power converter circuit. The current sensing circuit includes a sample and hold circuit ( | 2014-01-16 |
20140016385 | ENERGY RECYCLING DEVICE - The present invention is related to an energy recycling device. The energy recycling device includes a substrate, multiple miniature receivers, for receiving infrared radiation, on the substrate and multiple current rectifiers electrically connected to the miniature receivers respectively. The miniature receivers transform the infrared radiation into alternating currents (AC). The current rectifiers rectify the alternating currents (AC) so as to transform the alternating currents (AC) into direct currents (DC). Thereby, the infrared radiation received by the miniature receivers can be first transformed into the alternating currents (AC) with extremely high frequencies, and then the alternating currents (AC) with extremely high frequencies can be transformed into direct currents (DC) usable by an electronic device. Accordingly, infrared can be used to supply power. | 2014-01-16 |
20140016386 | Circuit Arrangement with a Rectifier Circuit - A circuit arrangement includes a rectifier circuit having a first and a second load terminal, a first semiconductor device having a load path and a control terminal and a plurality of n, with n>1, second semiconductor devices, each having a load path between a first load terminal and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. The series circuit with the first semiconductor device and the second semiconductor devices are connected between the load terminals of the rectifier circuit. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. | 2014-01-16 |
20140016387 | Power Inverter - In a power inverter, a coolant passage is fixed to a chassis to cool the chassis; the chassis is divided into a first region and a second region by providing the coolant passage in the chassis; a power module is provided in the first region as fixed to the coolant passage; a capacitor module is provided in the second region; and the DC terminal of the capacitor module is directly connected to the DC terminal of the power module. | 2014-01-16 |
20140016388 | SEMICONDUCTOR DEVICE, ADJUSTMENT METHOD THEREOF AND DATA PROCESSING SYSTEM - A system includes a first device, a second device, and a bus interconnecting the first and second devices to each other, wherein the first device includes a first semiconductor chip that includes a first memory cell array including a plurality of first memory cells, a first control logic circuit accessing the first memory cell array and producing a first data signal in response to data stored in a selected one of the first memory cells, the first control logic circuit being configured to store first timing adjustment information and to produce a first output timing signal that is adjustable in timing of change from an inactive level to an active level by the first timing adjustment information, a first data electrode, and a first data control circuit coupled to the first control logic circuit and the first data electrode. | 2014-01-16 |
20140016389 | DRAM MEMORY CELLS RECONFIGURED TO PROVIDE BULK CAPACITANCE - A semiconductor device includes a Dynamic Random Access Memory (DRAM) memory array. The DRAM memory array includes a plurality of DRAM memory cells. Each of the DRAM memory cells includes a capacitor. Switching circuitry within the semiconductor device is configured to be switched to a state in which the switching circuitry connects capacitors of at least two of the DRAM memory cells together to provide a bulk capacitance between a first node and a second node. | 2014-01-16 |
20140016390 | LOGICAL MEMORY ARCHITECTURE, IN PARTICULAR FOR MRAM, PCRAM, OR RRAM - An architecture and method are provided for reading and writing, in parallel or in series, an electronic memory component based on a two-dimensional matrix of two-terminal binary memory unit cells built into a crossbar architecture. The component includes a logical column-selector located outside the matrix and activating at least one column, one or more cells of which are subjected to read or write processing. Also provided is a component and method with the reading of the status of the cells by differential detection on from two cells of two different rows, either between a storage column and a constant reference column, or between two rows or two storage columns. A component is also provided in which specific selection structure is exclusively dedicated to read operations, and/or in which complementary cells in two complementary columns connected together are encoded in a single atomic operation by means of a single write current. | 2014-01-16 |
20140016391 | SEMICONDUCTOR DEVICE - A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier. | 2014-01-16 |
20140016392 | Memory Having Isolation Units For Isolating Storage Arrays From A Shared I/O During Retention Mode Operation - A memory includes an I/O unit that is shared between multiple storage arrays. The shared I/O unit provides output data from the arrays. The memory includes an isolation unit connected between each storage array and the shared I/O unit. In addition, each of the storage arrays and the shared I/O unit may be connected to a separate switched voltage domain through for example, power gating circuits. If one or more of the storage arrays is placed in retention or low-voltage mode, the isolation units that are coupled to the affected storage arrays may be configured to isolate the bitlines of those storage arrays from the shared I/O data paths. | 2014-01-16 |
20140016393 | Memory Programming Methods And Memory Systems - Memory programming methods and memory systems are described. One example memory programming method includes programming a plurality of main cells of a main memory and erasing a plurality of second main cells of the main memory. The memory programming method further includes first re-writing one-time programmed data within a plurality of first one-time programmed cells of a one-time programmed memory during the programming and second re-writing one-time programmed data within a plurality of second one-time programmed cells of a one-time programmed memory during the erasing. Additional method and apparatus are described. | 2014-01-16 |
20140016394 | CCIRCUIT AND SYSTEM OF USING JUNCTION DIODE AS PROGRAM SELECTOR FOR METAL FUSES FOR ONE-TIME PROGRAMMABLE DEVICES - Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices. An OTP device can have at least one OTP element coupled to at least one diode in a memory cell. With a metal fuse is used by the OTP element, at least one contact and/or a plurality of vias can be built (possibly with use of one or more jumpers) in the program path to generate more Joule heat to assist with programming. The jumpers are conductive and can be formed of metal, metal gate, local interconnect, polymetal, etc. The metal fuse can also have an extended area that is longer than required by design rules for enhanced programmability. The OTP element can be polysilicon, silicided polysilicon, silicide, polymetal, metal, metal alloy, local interconnect, thermally isolated active region, CMOS gate, or combination thereof. | 2014-01-16 |
20140016395 | METHOD OF DRIVING NONVOLATILE SEMICONDUCTOR DEVICE - Pulse voltages V1 and V2 are applied to the first upper gate electrode and the second upper gate electrode, respectively, for a period T1 which is shorter than a period necessary to invert all the polarizations included in the ferroelectric film, while voltages Vs, Vd, and V3 are applied to the source electrode, the drain electrode, and the lower gate electrode film, respectively, so as to increase the values of the widths WRH1 and WRH2 and so as to decrease the value of the width WRL. The pulse voltages V1 and V2 have a smaller voltage than a voltage necessary to invert all the polarizations included in the ferroelectric film. The voltage Vs, the voltage Vd, the voltage V3, the pulse voltage V1, and the pulse voltage V2 satisfy the following relationship: Vs, Vd, V32014-01-16 | |
20140016396 | Adaptive Reading And Writing Of A Resistive Memory - An adaptive reading and programming method is presented for resistive memory. The core operating principle is to cause a change in the conductance of a resistive memory cell and measure the magnitude of the change. The magnitude of change can be used to determine the logic state of the resistive memory cell. The proposed methods are evaluated in simulation programs with integrated circuit emphasis and a hand analysis model is extracted to help explain the sources of power and energy consumption. | 2014-01-16 |
20140016397 | NONVOLATILE MEMORY DEVICE AND WRITE METHOD THEREOF - A nonvolatile memory device includes a memory cell array including a plurality of memory cells, and a data comparison write unit connected with the memory cell array and configured to support a comparison write operation. The nonvolatile memory device further includes control logic configured to selectively execute the comparison write operation based on a comparison between an access number of the memory cell array and a reference number. | 2014-01-16 |
20140016398 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device includes memory cells, each of which is arranged at an intersection between a first wiring and a second wiring intersecting each other. Each of the memory cells includes: a first electrode layer; a plurality of variable resistance layers laminated on the first electrode layer and functioning as variable resistance elements; a second electrode layer formed between the variable resistance layers; and a third electrode layer formed on the top one of the variable resistance layers. Each of the variable resistance layers is composed of a material containing carbon. | 2014-01-16 |
20140016399 | MEMORY ARCHITECTURES HAVING DENSE LAYOUTS - One embodiment relates to a memory device including a plurality of memory units tiled together to form a memory array. A memory unit includes a plurality of memory cells, which include respective capacitors and respective transistors, disposed on a semiconductor substrate. The capacitors include respective lower plates disposed in a conductive region in the semiconductor substrate. A wordline extends over the conductive region, and a contact couples the wordline to the conductive region so as to couple the wordline to the lower plates of the respective capacitors. The respective transistors are arranged so successive gates of the transistors are arranged on alternating sides of the wordline. | 2014-01-16 |
20140016400 | WORD LINE DRIVER CIRCUITS AND METHODS FOR SRAM BIT CELL WITH REDUCED BIT LINE PRE-CHARGE VOLTAGE - A memory device comprising a plurality of static random access memory (SRAM) bit cells, and a word line driver coupled to provide a word line signal to the bit cells. The word line driver receives a global word line signal that remains active while the word line signal is asserted and subsequently de-asserted, and the word line signal is coupled between a positive supply voltage (VDD) and a supply voltage below ground (VN). | 2014-01-16 |
20140016401 | MEMORY WITH TERMINATION CIRCUIT - Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a first termination circuit that includes a first resistor and a first switch, the first resistor being provided between a first power supply terminal and the signal line, the first switch controlling a current flowing through the first resistor to be turned on and off, and a control circuit that outputs a first control signal to the first termination circuit so that the first switch is turned on when the first transmitter-receiver receives data, the first switch is turned off when the first transmitter-receiver transmits the data, and the first switch is continuously on during a first predetermined period after receiving the data when the first transmitter-receiver further receives another data after receiving the data. | 2014-01-16 |
20140016402 | SRAM BIT CELL WITH REDUCED BIT LINE PRE-CHARGE VOLTAGE - An SRAM bit cell comprises a first inverter including a PMOS transistor and an NMOS transistor, and a second inverter including a PMOS transistor and an NMOS transistor. The first and second inverters are cross-coupled to each other. A plurality of pass transistors couple the inverters to bit lines. Approximately one-half of a supply voltage is provided to the bit lines during pre-charge operations. | 2014-01-16 |
20140016403 | SEMICONDUCTOR MEMORY DEVICE - In a loadless 4T-SRAM constituted using vertical-type transistor SGTs, a small SRAM cell area is realized. In a static memory cell constituted using four MOS transistors, the MOS transistors are SGTs formed on a bulk substrate in which the drains, gates, and sources are arranged in the vertical direction. The gates of access transistors are shared, as a word line, among a plurality of cells adjacent to one another in the horizontal direction. One contact for the word line is formed for each group of cells, thereby realizing a CMOS-type loadless 4T-SRAM with a very small memory cell area. | 2014-01-16 |
20140016404 | MAGNETIC RANDOM ACCESS MEMORY - A magnetic memory device such as a magnetic random access memory (MRAM), and a memory module and a memory system on which the magnetic memory device is mounted are disclosed. The MRAM includes magnetic memory cells each of which varies between at least two states according to a magnetization direction and an interface unit that provides various interface functions. The memory module includes a module board and at least one MRAM chip mounted on the module board, and further includes a buffer chip that manages an operation of the at least one MRAM chip. The memory system includes the MRAM and a memory controller that communicates with the MRAM, and may communicate an electric-to-optical conversion signal or an optical-to-electric conversion signal by using an optical link that is connected between the MRAM and the memory controller. | 2014-01-16 |
20140016405 | THERMALLY ASSISTED MAGNETIC WRITING DEVICE - A magnetic thermally-assisted switching device includes a reference layer, a storage layer magnetised along a variable direction, a spacer that separates the reference layer and the storage layer, and magnetically decouples them, a device for heating the pinning layer so that, during heating, the temperature of the pinning layer exceeds its blocking temperature such that the direction of magnetisation of the storage layer is no longer pinned, a device for applying a writing magnetic torque tending to align the magnetisation of the storage layer along one of two stable magnetisation directions once the blocking temperature is reached. The device also includes a device for applying a magnetic polarisation field at least during the heating phase before the blocking temperature is reached such that the direction of magnetisation of the storage layer is always along the direction of the magnetic polarisation field at the moment that the blocking temperature is reached. | 2014-01-16 |
20140016406 | ISOLATING, AT LEAST IN PART, LOCAL ROW OR COLUMN CIRCUITRY OF MEMORY CELL BEFORE ESTABLISHING VOLTAGE DIFFERENTIAL TO PERMIT READING OF CELL - An embodiment may include local row and column circuitry that are local to a memory cell of a memory device. Either the local row circuitry or the local column circuitry may be electrically isolated, at least in part, from at least one remaining portion of the memory device during the establishing of a voltage differential between the local row circuitry and the local column circuitry that is to permit the memory cell to be read during a read of the memory cell. The read may occur subsequent to the establishing of the voltage differential. Many variations, modifications, and alternatives are possible without departing from this embodiment. | 2014-01-16 |
20140016407 | Semiconductor Device And Method For Driving Semiconductor Device - A semiconductor device with a novel structure is provided, in which the operation voltage is reduced or the storage capacity is increased by reducing variation in the threshold voltages of memory cells after writing. The semiconductor device includes a plurality of memory cells each including a transistor including an oxide semiconductor and a transistor including a material other than an oxide semiconductor, a driver circuit that drives the plurality of memory cells, and a potential generating circuit that generates a plurality of potentials supplied to the driver circuit. The driver circuit includes a data buffer, a writing circuit that writes one potential of the plurality of potentials into each of the plurality of memory cells as data, a reading circuit that reads the data written into the memory cells, and a verifying circuit that verifies whether the read data agrees with data held in the data buffer or not. | 2014-01-16 |
20140016408 | NONVOLATILE MEMORY DEVICES HAVING VERTICALLY INTEGRATED NONVOLATILE MEMORY CELL SUB-STRINGS THEREIN - Nonvolatile memory devices according to embodiments of the invention include highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy memory cells to compensate for process artifacts that would otherwise yield relatively poor functioning memory cell strings when relatively large numbers of memory cells are stacked vertically on a semiconductor substrate using a plurality of vertical sub-strings electrically connected in series. | 2014-01-16 |
20140016409 | MULTIPLE STEP PROGRAMMING IN A MEMORY DEVICE - A method for multiple step programming programs data to an even page of memory cells. The even page of memory cells is read into a page buffer and the uncertain data is removed. An odd page of memory cells is programmed and the data from the even page data from the page buffer is reprogrammed to the even page of memory cells without the uncertain data. | 2014-01-16 |
20140016410 | MEMORY DEVICE AND METHOD ADJUSTING READ VOLTAGE ACCORDING TO VARYING THRESHOLD VOLTAGE DISTRIBUTIONS - A memory device comprises a memory cell that is in one of an erase state and first through N-th program states (N>2). The memory device can be read by determining a first read voltage between the erase state and the first program state based on variations of respective threshold voltage distributions of the erase state and the first program state, and determining one among second through N-th read voltages based on variations in respective threshold voltage distributions of two adjacent program states among the first through N-th program states, and determining remaining read voltages among the second through N-th read voltages based on the one read voltage. | 2014-01-16 |
20140016411 | DEVICES AND METHODS OF PROGRAMMING MEMORY CELLS - Devices and methods of programming memory cells, both SLC and MLC, such as to reduce charge-storage structure to charge-storage structure coupling, are shown and described. Programming of memory cells can include comparing a first page of data to a second page of data, and further programming cells corresponding to the first page of data that will not likely be affected by coupling from programming the second page of data. | 2014-01-16 |
20140016412 | SEMICONDUCTOR MEMORY APPARATUS, DATA TRANSMISSION DEVICE, AND RECORDING METHOD - According to one embodiment, a semiconductor memory apparatus includes a memory and a speed control unit. The speed control unit calculates a time-varying behavior of a permissible value of an accumulated amount of data written in the non-volatile semiconductor memory, where, after a start of a guaranteed period, data is written in the memory at a constant write speed so that the permissible value at an end time of the guaranteed period is equal to a sum of a first capacity and a second capacity. The first capacity is an accumulated amount of data written in the memory. The second capacity is an accumulated amount of data which is writable in the memory in a remaining time of the guaranteed period based on remaining rewritable times of existing blocks. The speed control unit controls a transmission speed of data from a host based on the permissible value. | 2014-01-16 |
20140016413 | NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF, AND MEMORY SYSTEM INCLUDING THE SAME - Provided is a method of operating a nonvolatile memory device that includes a substrate and memory blocks having a plurality of memory cells stacked along a direction perpendicular to the substrate. The method includes: reading data from a selected sub block among sub blocks of a selected memory block and selectively refreshing each sub block of the selected memory block in response to the reading of the selected sub block, wherein each sub block of the selected memory block is separately erased. | 2014-01-16 |
20140016414 | FLASH MEMORY - The present invention provides a flash memory including a memory cell, a current limiter and a program voltage generator. The memory cell is programmed in response to a program current and a program voltage. The current limiter reflects amount of the program current by a data-line signal, e.g., a data-line voltage. The program voltage generator generates and controls the program voltage in response to the data-line voltage, such that the program current can track to a constant reference current. | 2014-01-16 |
20140016415 | PROGRAMMING METHOD TO TIGHTEN THRESHOLD VOLTAGE WIDTH WITH AVOIDING PROGRAM DISTURB - A non-volatile storage system that performs a multi-stage programming process to program non-volatile storage to a set of data threshold voltage distributions. The multi-stage programming process includes performing a first stage of the multi-stage programming process to change threshold voltages of at least a subset of the non-volatile storage elements from an erased distribution to one or more intermediate distributions, performing an intermediate stage of the multi-stage programming process to change threshold voltages of at least some of the non-volatile storage elements to appropriate distributions of the data threshold voltage distributions, and performing a later stage of the multi-stage programming process, after performing the intermediate stage of the multi-stage programming process, to tighten only a subset of the data threshold voltage distributions. | 2014-01-16 |
20140016416 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF TESTING THE SAME - Provided is a semiconductor memory device in which a plurality of first and second data lines coupled to a memory cell array are alternately arranged. The semiconductor memory device includes a first write driving circuit configured to load a plurality of first write data transmitted through a plurality of third data lines into the plurality of first data lines in response to a first write enable signal; a second write driving circuit configured to load a plurality of second write data transmitted through a plurality of fourth data lines into the plurality of second data lines in response to a second write enable signal; and a column control circuit configured to activate at least one of the first and second write enable signals during a given period, in response to a plurality of data width option modes, during a parallel test mode. | 2014-01-16 |
20140016417 | ELASTIC BUFFER MODULE AND ELASTIC BUFFERING METHOD FOR TRANSMISSION INTERFACE - An elastic buffer module including a memory unit, a write control module, and a read control module is provided. The memory unit receives, stores, and outputs a data sequence from a transmitting side. The write control module removes at least part of auxiliary data from the data sequence and writes the data sequence that has the auxiliary data removed into the memory unit. The read control module reads the data sequence from the memory unit and adds auxiliary data to the data sequence to adjust a write state of the transmitting side and a read state of a receiving side. Additionally, an elastic buffering method of a transmission interface is also provided. | 2014-01-16 |
20140016418 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first core region and a second core region disposed along a first reference line parallel to a major axis, the first reference line connecting an input pad and an output pad; first and second cell blocks disposed in the first core region along the first reference line; third and fourth cell blocks disposed in the second core region along the first reference line; and a repeater positioned between the third and fourth cell blocks, and configured to receive data outputted from the first cell block or the second cell block, amplify the received data and transfer the amplified data to a second global input/output line. Reducing the number of needed global input/output lines leads to layout area reduction. Moreover, since repeaters are driven in read operations for a limited number of cell blocks, signal gain may be reduced, thus reducing overall power consumption. | 2014-01-16 |
20140016419 | MEMORY DEVICE AND A METHOD OF OPERATING SUCH A MEMORY DEVICE IN A SPECULATIVE READ MODE - A memory includes an array of memory cells with each memory cell coupled to an associated pair of bit lines. Read control circuitry is configured to activate a number of addressed memory cells in order to couple each addressed memory cell to its associated pair of bit lines. Sense amplifier circuitry is then coupled to the bit lines to determine the data value stored in each addressed memory. In a speculative read mode of operation, the sense amplifier circuitry evaluates the differential signals. Error detection circuitry is then used to capture the differential signals on the associated pair of bit lines for each addressed memory cell, and to apply an error detection operation to determine if the differential signals as evaluated by the sense amplifier circuitry had not developed to the necessary degree and, in that event, an error signal is asserted. | 2014-01-16 |
20140016420 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a sense amplifier circuit region including first wells disposed in a first direction, a driving circuit region including second wells disposed in a second direction, and a conjunction region disposed at an intersection region of the sense amplifier circuit region and the driving circuit region, a part of each of the first wells extending from the sense amplifier circuit region into the conjunction region, and the second wells being outside of the conjunction region. | 2014-01-16 |
20140016421 | SEMICONDUCTOR MEMORY DEVICE STORING REFRESH PERIOD INFORMATION AND OPERATING METHOD THEREOF - A semiconductor memory device which stores refresh period information thereby adjusting a refresh period and a method of operating the same. The semiconductor memory device includes a cell array and a refresh information storing unit. The cell array includes one or more cell regions each having a plurality of memory cells. The refresh information storing unit is configured to store first information including a first refresh period and second information including a second refresh period in correspondence to each of the cell regions. Memory cells included in each of the cell regions are refreshed at the first refresh period according to the first information in a first refresh time band and are refreshed at the second refresh period according to the second information in a second refresh time band. | 2014-01-16 |
20140016422 | SEMICONDUCTOR MEMORY DEVICE THAT CONTROLS REFRESH PERIOD, MEMORY SYSTEM AND OPERATING METHOD THEREOF - A semiconductor memory device includes a cell array and a refresh controller coupled to the cell array. The refresh controller is configured to insert at least one insertion refresh address in a first refresh address sequence based on address information about the cell array to generate a second refresh address sequence and to apply the second refresh address sequence to the cell array, such that selected cells may be refreshed more frequently without increasing an overall refresh rate. | 2014-01-16 |
20140016423 | Reducing Memory Refresh Exit Time - Components of a memory system, such as a memory controller and a memory device, that reduce delay in exiting self-refresh mode by controlling the refresh timing of the memory device. The memory device includes a memory core. An interface circuit of the memory device receives an external refresh signal indicating an intermittent refresh event. A refresh circuit of the memory device generates an internal refresh signal indicating an internal refresh event of the memory device. A refresh control circuit of the memory device performs a refresh operation on a portion of the memory core responsive to the internal refresh event, at a time relative to the intermittent refresh event indicated by the external refresh signal. | 2014-01-16 |
20140016424 | METHODS OF OPERATING DRAM DEVICES HAVING ADJUSTABLE INTERNAL REFRESH CYCLES THAT VARY IN RESPONSE TO ON-CHIP TEMPERATURE CHANGES - An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device. | 2014-01-16 |
20140016425 | VOLTAGE REGULATOR, VOLTAGE REGULATING SYSTEM, MEMORY CHIP, AND MEMORY DEVICE - A voltage regulator comprises a power source terminal configured to supply a power source voltage; an output terminal configured to output a load current; a first transistor which is connected between the power source terminal and the output terminal, is enabled by a signal applied from an amplifier in a first mode to generate a first current, and outputs the first current to the output terminal; and a second transistor which is connected between the power source terminal and the output terminal, is enabled by a signal applied from the amplifier in a second mode to generate a second current different from the first current, and outputs the second current to the output terminal, wherein the first transistor is enabled in the second mode, and the second transistor is disabled in the first mode. | 2014-01-16 |
20140016426 | SYSTEMS AND METHODS FOR PREVENTING DATA REMANENCE IN MEMORY - A system for preventing data remanence in memory is provided. The system includes a computing device, a memory chip coupled to the computing device and including memory, and a heater, the heater configured to prevent data remanence in a memory by providing heat to at least a portion of the memory. The memory includes a plurality of bits configured to electronically store data. | 2014-01-16 |
20140016427 | SEMICONDUCTOR MEMORY DEVICE HAVING SELECTIVE ACTIVATION CIRCUIT FOR SELECTIVELY ACTIVATING CIRCUIT AREAS - A semiconductor memory device includes a plurality of memory banks each including a plurality of circuit areas selected based on an address signal, any one of which is selected by a corresponding bank selective signal (source transistor control signals), and a selective activation circuit that, from among circuit areas included in a memory bank that is selected based on the bank selective signal, activates any one of the circuit areas based on the address signal, and deactivates at least one of rest of the circuit areas. According to the present invention, the power consumption can be reduced in an active state by a dynamic power control in response to an address signal, not by entire power control by an external command. | 2014-01-16 |
20140016428 | KNEADING APPARATUS - The present invention includes a kneading chamber ( | 2014-01-16 |
20140016429 | STEAMING PITCHER METHODS AND DEVICES - A steaming pitcher comprising a flow receiving surface adapted to receive an incoming flow of steam at a substantially oblique angle provides enhanced control of fluid flow inside the steaming pitcher to enhance mixing and heating of the fluid by the incoming steam. The steaming pitcher may also comprise flow directing and launching surfaces to assist in control of fluid flow patterns. A flow control kit with a flow receiving surface may be installed in an existing flat-bottom steaming pitcher to provide aspects of fluid flow control. The flow receiving, flow directing and launching surfaces of the steaming pitcher may be substantially smooth, faceted, or a combination thereof. | 2014-01-16 |
20140016430 | MIXING BUBBLE GENERATOR AND INSTALLATION CONFIGURATION - A new accumulator for generating mixing bubbles comprises pivoting, counterbalanced buckets, the buckets receiving air directed from blowers, either directly from injectors connected to the blowers, or from diffusers used for aeration of the liquid in the tank. A bucket, weighed down by a counterbalance, receives air from injectors or diffusers below, and, as the air displaces liquid in the bucket, the buoyancy of the bucket increases until it exceeds the downward force of the counterweight, at which time the bucket pivots upward to release a large mixing bubble into the tank. An assembly for installation of the accumulator affixes the accumulator on a rigid vertical piece depending from a horizontal bridge. | 2014-01-16 |
20140016431 | STIRRING METHOD AND STIRRING APPARATUS - A drug container is arranged in a horizontal state where a central axis extends along a horizontal direction, and the drug container is rotated about the central axis. In such a way, a drug solution in the drug container is moved along an inner surface of the drug container, and the drug container is reciprocally vibrated along the central axis in a state where the drug container is rotated, to stir the drug solution. | 2014-01-16 |
20140016432 | AUTOMATED SOLUTION DISPENSER - The present invention relates to an automated solution dispenser for dispensing a solution having a defined list of characteristics. In particular, the automated solution dispenser according to the present invention is provided with one or more of the following modules: Central Mixing Chamber (CMC), Flush and Verification System (FVS), Liquid Handling System (LHS), Control System (CS), Pivot Pipe System (PPS), Solid Handling System (SHS) (which includes a Delivery mechanism and a Measuring mechanism), a Bottle Handling System (BHS), a Water Purification System (WPS) and Bottle Marking/Label (BM). The combination of one or more of these modules enables the automation of the creation of solution having the required characteristics. | 2014-01-16 |
20140016433 | METHOD AND APPARATUS FOR GENERATING MICRO BUBBLES IN A FLUID FLOW - A method and apparatus for generating micro-bubbles and for mixing and/or blending fluids includes providing a pressurized elongate container, having at least one tube mounted in the container inlet. A pre-mixing chamber feeds into each tube. Each tube is cantilevered from the container inlet and has a fixed internal diameter. The tubes are replaceable so that the length of each tube in the container may be optimized to generate micro-bubbles. Tuning or optimizing of the micro-bubble generating system achieves a required pressure drop to form micro-bubbles of five microns or less, and may form nano-bubbles. An upstream pump pressurizes at least two fluids which feed into the pre-mixing chamber. Pressure from the container outlet may be controlled by a valve. The valve leads to a second container, which may be open to atmospheric pressure. | 2014-01-16 |
20140016434 | METHOD AND SYSTEM OF CONTROLLING TOWING SPEED OF A SENSOR STREAMER - Controlling towing speed of a sensor streamer. At least some of the of the embodiments are methods including: towing a sensor streamer through water at a towing speed; releasing interrogating energy within the water; recording energy received by the sensor streamer to create recorded energy; determining a value indicative of noise within the recorded energy; and changing the towing speed in real-time responsive to the value indicative of noise within the recorded energy. | 2014-01-16 |
20140016435 | ACQUISITION SCHEME FOR VIBROSEIS MARINE SOURCES - Control mechanisms, computer software and methods for driving vibrational source arrays underwater. An incoherent acquisition scheme drives individual source elements simultaneously and incoherently while a coherent acquisition scheme drives high-frequency individual source elements simultaneously and incoherently and low-frequency individual source elements simultaneously and coherently. Thus, denser coverage and an increased energy input is achieved for the source arrays. | 2014-01-16 |
20140016436 | METHODS AND SYSTEMS FOR RECONSTRUCTION OF LOW FREQUENCY PARTICLE VELOCITY WAVEFIELDS AND DEGHOSTING OF SEISMIC STREAMER DATA - Computational methods and systems for deghosting marine seismic streamer data are described. In particular, an exploration-seismology vessel tows a number of streamers that form a data acquisition surface located beneath a free surface. The methods computationally deghost or substantially remove receiver ghost signals from seismic data recorded by steamer receivers. The deghosting methods include low frequency compensation to recover vertical velocity wavefield information that is typically lost due to a low signal-to-noise ratio over a low frequency range independent of the free surface conditions or the shape of the data acquisition surface. | 2014-01-16 |
20140016437 | SYSTEMS FOR ACQUIRING AND PROCESSING SEISMIC DATA - Systems and methods may be provided for setting up a geophysical seismic information-gathering grid utilizing an alternating source pattern as well as an alternating receiver pattern using base patterns including but not limited to “I+H” or “H+I” and “box plus.” Use of such base patterns may allow seismic data to be collected and processed using a reduced number of sources and receivers to provide a seismic imaging plot having increased and noticeably improved resolution than is presently available. | 2014-01-16 |
20140016438 | SYSTEM AND METHOD FOR ULTRASOUND SCATTERER CHARACTERIZATION - A method for characterizing ultrasound scatterers in a medium comprises receiving ultrasound data representing a region of interest comprising a plurality of scatterers in a medium, the plurality of scatterers including aggregates of the scatterers. The ultrasound data is modeled data using an effective medium theory combined with the structure factor model, the structure factor model defining the spatial organization and concentration of the aggregates. The modeled ultrasound data is compared to theoretical data obtained with the effective medium theory combined with the structure factor model. From the comparison, dimensional data of the aggregates of the scatterers and the volume concentration of scatterers in the medium is determined. | 2014-01-16 |
20140016439 | BIRD REPELLENT APPARATUS - A bird repellent apparatus includes a speaker and a speaker control unit. The speaker control unit controls the speaker to emit an ultrasonic sound wave toward a predetermined area such that the ultrasonic sound wave is modulated to an audible frequency while traveling through air to generate a repellent sound with the audile frequency in the predetermined area for repelling birds. | 2014-01-16 |
20140016440 | RADIO-CONTROLLED WRISTWATCH - Provided is a radio-controlled wristwatch that receives a radio wave including day-related information from a satellite within a global positioning system, in which a cycle number of the day-related information is correctly updated even in a case where a power supply voltage drops. A radio-wave wristwatch ( | 2014-01-16 |
20140016441 | Electronic Timepiece - An electronic timepiece that receives RF signals and displays information suppresses loss of antenna sensitivity to a sufficiently low level without sacrificing display functions. Such an electronic timepiece has a dial on the face of which time is displayed, and an antenna in the shape of a polygon disposed on the back side of the dial. The antenna receives signals passing through the dial. A voltaic is disposed between the dial and the antenna. The distance in between the antenna and the voltaic device is at least 0.2 times the length of the antenna. | 2014-01-16 |
20140016442 | Timer Systems And Methods Of Monitoring A Period Of Time With Respect To An Article - Timer systems and methods of monitoring a period of time with respect to an article are described. In one aspect, a timer system includes a timing device comprising circuitry configured to monitor a period of time, an attachment system coupled with the timing device and configured to attach the timing device to as associated article for which the period of time is to be monitored, and wherein the circuitry of the timing device is further configured to generate a human perceptible signal to convey information regarding the period of time being monitored with respect to the associated article. | 2014-01-16 |
20140016443 | ELECTRONIC QUARTZ RESONATOR MODULE PROVIDED WITH SHOCK RESISTANT SECURING MEANS - The electronic module ( | 2014-01-16 |
20140016444 | JUMPER, TIMEPIECE MOVEMENT AND TIMEPIECE COMPRISING SUCH A JUMPER - A jumper for a timepiece movement is disclosed that includes a base and an elastically deformable arm extending from the base and provided with an abutment surface intended to cooperate with a notch of a mobile. The base may comprise a support element bearing the arm. The base may further comprise two link elements each linking an end of the support element to a fixed element of the base. The jumper may be associated with a control member arranged in such a way that an axial rotation of the control member provokes a displacement of the support element by deformation of a frame, of which the support element and the two link elements form sides. | 2014-01-16 |
20140016445 | TIMEPIECE - A timepiece is equipped with a novel type of entertainment, that is a mechanical card game. The timepiece includes: a dial ( | 2014-01-16 |
20140016446 | WATCH DIAL SECURED TO A BOTTOM PLATE - Assembly comprising a watch dial ( | 2014-01-16 |
20140016447 | TIMING SYSTEM AND DEVICE AND METHOD FOR MAKING THE SAME - A timing device for indicating the passage of a duration of time is disclosed. The timing device and system, in accordance with the embodiments of the invention, comprise an electrochemical component which generates a visual and/or audio indication of the passage of time. The timing device further comprises a compensating element, such as a varistor, a thermistor and/or combinations thereof. The compensating element regulates the response of the device with respect to changes in temperature. The timing device is configured to indicate the passage of a single duration of time or comprises zones that are activated in a range of prescribed times and individually or collectively indicate the passage of time or the passage of a range of times. | 2014-01-16 |
20140016448 | RECORDING HEAD WITH NEAR-FIELD ANTENNA AND COMPOSITE POLE - A near field transducer antenna has a first end proximate a media writing surface and a second end proximate a waveguide that delivers light to the antenna. The antenna includes an aperture disposed along a propagation axis that extends from the first end to the second end. A notch protrudes within the aperture. The notch is facing an opening of the aperture that extends along the propagation axis. A magnetic pole is proximate the antenna, and includes a first portion of magnetic material and a second portion of antenna material. The second portion is disposed over the opening of the aperture and facing the notch of the antenna. | 2014-01-16 |
20140016449 | LENS DRIVING DEVICE AND OPTICAL DISC APPARATUS - A lens driving device includes a lens holder for holding a lens, a supporter portion for supporting the lens holder in a movable manner, a drive portion for driving the lens holder, and an elastic portion for supplying the lens holder with a force in a predetermined direction. The supporter portion includes a shaft engaging with a bearing of the lens holder, and the force in a predetermined direction includes a force in a direction perpendicular to the shaft and a force in a direction to rotate the lens holder about the shaft. | 2014-01-16 |
20140016450 | POLYETHERIMIDE RESINS WITH VERY LOW LEVELS OF RESIDUAL CONTAMINATION - Compositions and methods for producing compositions comprising a monoamine-endcapped polyimide component. Based on a gas chromatography mass spectroscopy analysis of a surface rinse of the composition performed at room temperature, the composition can have at least one surface with less than or equal to 5 ppb releasable phosphorous residuals, and less than or equal to 5 ppb releasable volatile organic compound residuals. The composition can also comprise less than or equal to 10 ppb combined releasable residuals. Because of the very low levels of residual contamination, the compositions can be used to produce a variety of articles including a disk drive. | 2014-01-16 |
20140016451 | PHASE-ROTATED REFERENCE SIGNALS FOR MULTIPLE ANTENNAS - Systems, methods, and apparatuses for phase-rotated reference signals are provided. In accordance with one implementation, phase-rotated reference signals are transmitted from multiple transmit antennas on the same reference signal (RS) resource elements. The receiver may determine channel coefficients for links corresponding to the multiple antennas, based on the received signals at the RS resource elements. Time-domain filtering or frequency-domain orthogonal codes may be used to determine the channel coefficients for links corresponding to the multiple antennas. The phase-rotation information may be broadcasted in a system information block (SIB) message or signaled in a radio resource control (RRC) message. | 2014-01-16 |
20140016452 | TRANSMITTING APPARATUS, RECEIVING APPARATUS, COMMUNICATION SYSTEM, AND COMMUNICATION METHOD - A transmitting apparatus includes a group processing unit configured to divide plurally data of one block, control processing units configured to perform predetermined control processing for each of the divided data, a combination processing unit configured to combine the data subjected to the control processing into one signal, a transmission processing unit configured to apply predetermined transmission processing to the combined signal to convert the signal into a transmission signal, and a control-signal generating unit configured to retain a predetermined number of control value candidates, one set of which includes M control values used in the control processing carried out by the control processing units, and select, as a selected candidate, one of the control value candidates based on power information of the transmission signal, and generate M control signals corresponding to the selected candidate and input the control signals to the control processing units. | 2014-01-16 |
20140016453 | METHOD AND APPARATUS FOR OPTIMIZING AND SCALING CONTROL PLANE TRAFFIC IN CARRIER ETHERNET TRANSPORT NETWORKS - Methods and apparatuses for merging continuity check messages (CCMs) are described. Some embodiments determine multiplexer and de-multiplexer nodes in a network for multiplexing and de-multiplexing CCM traffic. One embodiment creates an optimization problem which when solved identifies nodes in the network that should be configured as multiplexer nodes to multiplex multiple CCMs into a group CCM and/or as de-multiplexer nodes to de-multiplex a group CCM into multiple CCMs. This embodiment uses the solution of the optimization problem to configure nodes in the network as multiplexer nodes and/or as de-multiplexer nodes. Another embodiment determines weights for different paths in the network that can be used for merging CCM traffic, and then merges the CCM traffic based on these weights. | 2014-01-16 |
20140016454 | HIGH AVAILABILITY TRANSPORT PROTOCOL METHOD AND APPARATUS - A system and method supporting efficient, scalable stateful switchover of transport layer connections in a telecommunications network element. One method involves receiving, at a network element comprising an active transport protocol process coupled to a standby protocol process, a request to configure a first transport layer connection maintained at the active transport protocol process for stateful switchover; receiving an event associated with the first transport layer connection; creating a message containing replicated event information based on the received event; sending the message to the standby transport protocol process; and processing the message at the standby transport protocol process, wherein the standby transport protocol process replicates state information for the first connection. | 2014-01-16 |
20140016455 | METHOD, DEVICE, AND SYSTEM FOR PROVIDING A SURVIVABILITY GATEWAY SERVICE - A method and apparatus dynamically pair a user's communication devices with a personal survivability gateway. The gateway can support the establishment of communication services in case of a network failure between a site where the user's communication devices are located and the site that provides the user's communication services. Preferably, the survivability gateway is configured so that if a network failure occurs, the user does not experience service degradation, or at least significant service degradation. For instance, the user's inbound and outbound communications during such an outage may be routed through his personal survivability gateway and a survivability proxy to limit, if not eliminate such service degradation. | 2014-01-16 |
20140016456 | MOBILE GATEWAYS IN POOL FOR SESSION RESILIENCE - Embodiments of the invention include a method for providing UE session resilience performed in a first PDN-GW that is coupled to a second PDN-GW, which are both in a PDN-GW pool. The method provides UE session resilience by allowing the first PDN-GW to provide connectivity for UE sessions previously serviced by the second PDN-GW after the second PDN-GW becomes non-operational. The first PDN-GW recognizes that the second PDN-GW failed and then activates a plurality of standby UE sessions. Each standby UE session is a backup UE session corresponding to a previously active UE session serviced on the second PDN-GW. Each standby UE session is associated with a UE device and a network resource identifier of an APN slice. The first PDN-GW transmits a message to a SGW that is servicing the UE sessions that indicates that the SGW should direct traffic previously bound for the second PDN-GW to the first PDN-GW. | 2014-01-16 |
20140016457 | Technique for Operating a Network Node - A technique of operating a network node of a multicast communication network comprising a plurality of network nodes which are interconnected with each other by communication links is provided, wherein the network node is associate with a common source network node. A method implementation of the technique comprises: determining a first path which connects the network node to the common source network node along a primary network tree, and determining a second path which connects the network node to the common source network node along a secondary network tree, wherein the first path and the second path show redundancy with respect to each other; receiving, at the network node, multicast data from the common source network node via the first path; triggering, by the network node, reception of multicast data from the common source network node via the second path if the network node detects a failure of the first path (e.g., determines that no multicast data is received via the first path). | 2014-01-16 |
20140016458 | ROUTER APPARATUS AND LINE SWITCHING METHOD IN ROUTER APPARATUS - A router apparatus for performing communication by switching a first and second line, the router apparatus includes: a setting unit which sets a first protection time until the first line is switched to the second line after a line failure in the first line is detected, and a second protection time until the second line is switched to the first line after recovery from the line failure in the first line is detected, to times corresponding to a quality state of the first line, respectively; and a line switching unit which switches the first line to the second line when the first protection time elapses and the line failure in the first line continues, or switches the second line to the first line when the second protection time elapses after the line failure in the first line is detected. | 2014-01-16 |
20140016459 | NETWORK SYSTEM, GATEWAY, AND PACKET DELIVERY METHOD - A gateway suppresses data volume considering processing load information of a destination to reduce communication traffic volume of a network without suppressing the information with high severity. In a network system comprising the data center, the management node and the gateway connected via a plurality of networks, a communication function section of the gateway includes a table control unit that receives the processing load information of the data center as a packet destination from the management node and retains the information in a transfer management table. A transfer stop control unit of the gateway judges whether or not transfer of the packet is suppressed using the processing load information retained in the transfer management table, and suppresses the transfer of the predetermined packet upon judgment to suppress the packet transfer. | 2014-01-16 |
20140016460 | Technique for Handling a Data Packet Stream - A method of handling a data packet stream at different communication protocol layer levels of a communication protocol layer stack of an UMTS communication device is provided. The method comprises: Receiving a data packet stream at the communication device; Determining whether, in case of a loss of a data packet of the data packet stream, it is possible to retransmit the lost data packet to the communication device; and immediately transmitting data packets of the data packet stream succeeding the lost data packet from a MAC protocol layer level to a RLC protocol layer level if it is determined that the lost data packet cannot be retransmitted to the communication device, and otherwise storing data packets of the data packet stream succeeding the lost data packet for a third period of time at the MAC protocol layer level, which third period of time is longer than the second time period. | 2014-01-16 |
20140016461 | PACKET RELAY DEVICE AND METHOD - When a delay between a packet relay device and a receiving terminal increases, congestion notifications are delayed, and communication quality declines. When a flow is assessed to be in a congestion state, a packet delay device overwrites, within a packet header of an acknowledgement packet for the flow which is received thereafter from a receiving terminal, a field which denotes a network congestion state with a value which denotes that a congestion state is in effect, and transmits same as an acknowledgement packet. It is thus possible to issue a congestion notification over a path from the packet relay device to the receiving terminal, eliminating a congestion notification path from the packet relay device to the receiving terminal and from the receiving terminal to the packet relay device, facilitating avoiding a decline in communication quality even if the delay between the packet relay device and the receiving terminal increases. | 2014-01-16 |
20140016462 | Communicating a Broadcast Message to Change Data Rates of Mobile Stations - A wireless communications network includes a base station to communicate with plural mobile stations over a wireless link. A broadcast message is sent to the plural mobile stations, with the broadcast message containing an indication for indicating to the plural mobile stations that the mobile stations are to change data rates for transmissions over a reverse wireless link. | 2014-01-16 |
20140016463 | PACKET PROCESSING APPARATUS AND PACKET PROCESSING METHOD - A packet processing apparatus includes a packet processing unit that performs a packet output process, an extraction unit that extracts information about each packet before the packet is inputted to the packet processing unit, and a contention handling unit that performs a process avoiding occurrence of contention between/among predetermined processes before the packet is inputted in the packet processing unit, the contention being predicted based on the information about the packet. As a process avoiding contention among series of processes including, for example, processes performed by the packet processing unit to read an amount of transmission rights from a storage unit, do subtraction, and write the amount of transmission rights back into the storage unit, the contention handling unit detects packets belonging to a same flow from information about predetermined number of successive packets and reports the information to the packet processing unit on a flow by flow basis. | 2014-01-16 |
20140016464 | QUALITY OF EXPERIENCE ENHANCEMENT THROUGH FEEDBACK FOR ADJUSTING THE QUALITY OF SERVICE IN COMMUNICATION NETWORKS - A method of enhancing Quality of Experience (QoE) associated with an application flow for an end-user in a communication network comprises: receiving a packet belonging to the application flow, the packet comprising QoE information determined based on previous packets exchanged within the application flow; decoding the QoE information from the received packet; and adjusting a QoS mechanism for the packet, based on the decoded QoE information for enhancing the QoE of the application flow. A network node for carrying out this method is disclosed. Also, a method for relaying QoE associated with an application flow for an end-user in a communication network comprises: receiving packets belonging to the application flow; calculating QoE information based on the received packets; and sending the calculated QoE information back to the communication network, the QoE information being included in a packet belonging to the application flow. A network node for carrying out this method is disclosed. | 2014-01-16 |
20140016465 | METHOD AND ARCHITECTURE FOR A SCALABLE APPLICATION AND SECURITY SWITCH USING MULTI-LEVEL LOAD BALANCING - A switch architecture and method provides scaling through multi-level load balancing of flows across data and application processing planes. An input/output module receives a communication session flow (forward) from a client device and selects one of a plurality of data processors to process the flow. The selected data processor determines the level of processing for the forward flow and selects an application processor from a plurality of such application processors. The application processor generates a session structure identifying actions to be performed on the forward flow and transfers the session structure to the selected data processor to perform the actions on the forward flow. The application processor also predictively generates and offloads a session structure for the associated reverse flow. If the reverse session structure is offloaded to a different data processor, either the forward or reverse flow redirects packets, or is redirected, to the data processor hosting the other flow. | 2014-01-16 |
20140016466 | TRAFFIC MANAGEMENT GATEWAY FOR MACHINE-TO-MACHINE NETWORK - A gateway for interfacing a capillary network of communicating devices with an access point of a cellular network. The gateway includes a plurality of input buffers designed to store elementary packets. A plurality of output buffers store composite packets formed by aggregation of elementary packets, each output buffer being associated with a type of flow of the cellular network. A flow regulator determines for each output buffer, parameters of size and/or transmission times of the composite packets such that the flow of these packets is consistent with the type of flow of the cellular network associated with the output buffer. A multiplexing device transfers and aggregates elementary packets, stored in the input buffers, in the form of composite packets having the parameters determined by the flow regulator. A scheduling device for transmitting the composite packets by the transmission resources of the cellular network. | 2014-01-16 |
20140016467 | Representing Bandwidth Constraints in Partially Controlled Environments - Disclosed is a network element (NE) comprising a receiver configured to receive a path computation request, a path computation element (PCE) coupled to the receiver and configured to compute a group of network paths through a network of NEs operating in a network stratum in response to the path computation request, wherein each network path comprises one or more physical links, and compute at least one constraint for each physical link, and an abstraction module coupled to the PCE and configured to receive the computed network path set and constraints, compute one or more abstract links that describe the network path group, and compute a constraint for each abstract link based on the physical link constraints. | 2014-01-16 |
20140016468 | ADAPTIVE HYBRID WIRELESS AND WIRED PROCESS CONTROL SYSTEM - A hybrid wired and wireless architecture for a process control system is disclosed that includes hierarchical adaptability and optimization capabilities. The system is arranged in three tiers, the first including a number of wireless end devices exchanging packets of data and/or instructions with the distributed control system, where each wireless end device is associated with one or more meters, remote terminal units, diagnostic devices, pumps, valves, sensors, or tank level measuring devices. The second tier includes a plurality of wireless routers, each including a memory that stores a routing table and a processor that routes packets. The third tier includes a master wireless gateway device operably connected to receive packets from and transmit packets to the distributed control system. The processor of each of the wireless routers routes packets across the tiers between the end devices and the wireless gateway devices based on the stored routing table. | 2014-01-16 |
20140016469 | DETERMINISTIC DISTRIBUTED NETWORK CODING - A network and a communication method are described. The network comprises: source nodes, receiver nodes, and coding nodes. The coding nodes are connected with input links for communication of input signals to the coding nodes and output links for communication of output signals from the coding nodes. The output signals are a linear combination of the input signals. The coefficients of the linear combination are deterministically chosen based on local information available locally at the coding node. | 2014-01-16 |
20140016470 | METHOD FOR TRAFFIC LOAD BALANCING - A method for balancing traffic load is disclosed. The method comprises: monitoring, by a stacking device in a distribution layer, traffic in an aggregation link between the stacking device and a core layer; when a traffic unbalance is monitored in the aggregation link, finding by said stacking device a data flow which causes said traffic unbalance from data flows transferred over the aggregation link; and determining by said stacking device an incoming interface through which the found data flow enters said stacking device, reallocating a new MAC address to the incoming interface, and sending the new MAC address allocated to the incoming interface to a terminal server, so as to enable said traffic unbalance to transit to traffic balance by way of said terminal server sending a data flow with the new MAC address as the destination MAC address. | 2014-01-16 |
20140016471 | LOAD BALANCING MECHANISM FOR SERVICE DISCOVERY MECHANISM IN STRUCTURED PEER-TO-PEER OVERLAY NETWORKS AND METHOD - An overlay network, node and application for load balanced service discovery. The application includes the steps of implementing the service discovery mechanism in the DHT P2P overlay network for finding a peer ( | 2014-01-16 |
20140016472 | METHOD AND A SYSTEM FOR CONTROLLING TRAFFIC CONGESTION IN A NETWORK - The present invention relates to a method for controlling traffic congestion in a network, the network comprising a plurality of nodes including a source node, intermediary nodes and a destination node. In one embodiment, this can be accomplished by collecting network topology information and various parameters from each nodes in the network, storing the collected information and parameters in a database, computing network statistics from at least one of the contemplated collected information thereby reflecting the probabilities of changing modulation at a specific state, computing optimal parameters of specific congestion mitigation mechanisms associated with the plurality of nodes and configuring each node's specific congestion mitigation mechanism, wherein for each mechanism the method calculates the optimal parameter configuration per node. | 2014-01-16 |
20140016473 | METHOD AND APPARATUS FOR ALLOCATING BANDWIDTH FOR A NETWORK - A method and apparatus for performing traffic engineering, e.g., allocating bandwidth, on a wireless access network are disclosed. For example, the method determines a number of subscriber stations (SSs) that a Base Station (BS) is capable of supporting in accordance with at least one performance objective for voice traffic, wherein the at least one performance objective for voice traffic comprises a type of codec. The method then allocates bandwidth by the base station in accordance with the number of subscriber stations that the base station is capable of supporting. | 2014-01-16 |
20140016474 | DELAYED BASED TRAFFIC RATE CONTROL IN NETWORKS WITH CENTRAL CONTROLLERS - A process is performed by a controller in a split-architecture network. The controller monitors congestion of traffic groups across the split-architecture network and executes the process to provide delay based data rate control to alleviate congestion of the traffic groups. The process includes configuring an ingress switch and egress switch for each traffic group to collect delay measurement data for data packets of each traffic group as they arrive at the ingress switch and egress switch. The delay measurement data is received from the ingress switch and egress switch of each traffic group. A check is made whether a minimum data packet delay for any traffic group exceeds a defined threshold value. A throttling rate is calculated for each traffic group in the split-architecture network, in response to the defined threshold value being exceeded. | 2014-01-16 |
20140016475 | METHOD AND DEVICE FOR RESOLVING COLLISION BETWEEN APERIODIC SRS AND UPLINK CONTROL SIGNALING - The present invention provides a method and device for resolving a collision between an aperiodic sounding reference signal (SRS) and an uplink control signaling. The method includes: acquiring priority criteria of the aperiodic SRS and the uplink control signaling of a UE; receiving, by the UE, a downlink control signaling transmitted by a base station, and acquiring a time when a transmission of the aperiodic SRS is needed; if a transmission of the uplink control signaling through a physical uplink control channel (PUCCH) is needed at the time when the transmission of the aperiodic SRS is needed, transmitting, by the UE, the aperiodic SRS or the uplink control signaling with a higher priority at the time according to the acquired priority criteria; if the transmission of the uplink control signaling through the PUCCH is not needed at the time, transmitting the aperiodic SRS at the time. | 2014-01-16 |
20140016476 | METHOD FOR OPERATING A FLOW-BASED SWITCHING SYSTEM AND SWITCHING SYSTEM - A method for operating a flow-based switching system in a network, including at least one network node designed to transport incoming network packets, in particular a switch ( | 2014-01-16 |
20140016477 | Implementing OSPF in Split-Architecture Networks - A method is implemented in a network element that functions as one of a plurality of controllers for one of a plurality of areas of a split architecture network. The controller provides a control plane for the area of the split architecture network where the controller is remote from a plurality of switches providing a data plane for the area of split architecture network. The controller facilitates optimized routing across the plurality of areas of the split architecture network by providing limited intra-area link cost data to other controllers of other areas of the split architecture network and to traditional routers of a network including the split architecture network. The limited intra-area link cost data provides costs of each possible shortest path traversal of the area of the controller without providing all internal link cost data. | 2014-01-16 |
20140016478 | METHOD AND APPARATUS FOR PROVIDING IMPROVED DETECTION OF OVERLAPPING NETWORKS - A method, apparatus and computer program product provide improved detection of overlapping wireless networks. In this regard, the method, apparatus and computer program product may utilize a processor, such as a processor on a wireless access point, to determine one or more parameters for a scan of a wireless network to identify overlapping networks. Wireless stations may utilize the parameters to determine the content of a scan report generated from a scan of the wireless network. The wireless stations may further utilize the parameters to determine which values should be monitored and/or recorded during the scan of the network. The wireless stations may respond to the access point with results corresponding to the parameters requested by the access point, and the access point may use the results to determine channel access parameters for other devices on the network, such as the wireless stations. | 2014-01-16 |