03rd week of 2013 patent applcation highlights part 13 |
Patent application number | Title | Published |
20130015507 | MULTIPLE ORIENTATION NANOWIRES WITH GATE STACK SENSORS - An electronic device includes a conductive channel defining a crystal structure and having a length and a thickness t | 2013-01-17 |
20130015508 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAMEAANM Jang; Wen-YuehAACI Hsinchu CityAACO TWAAGP Jang; Wen-Yueh Hsinchu City TW - A semiconductor device and a method for fabricating the same are described. The semiconductor device includes a well of a first conductive type, first doped regions of a second conductive type, gates of the second conductive type, second doped regions of the first conductive type, and isolation structures. The well is disposed in a substrate. The first doped regions are disposed in the well. The first doped regions are arranged in parallel and extend along a first direction. The gates are disposed on the substrate. The gates are arranged in parallel and extend along a second direction different from the first direction. One of the first doped regions is electrically connected to one of the gates. Each of the second doped regions is disposed in the first doped regions between two adjacent gates. Each of the isolation structures is disposed in the substrate between two adjacent first doped regions. | 2013-01-17 |
20130015509 | LOW RESISTANCE SOURCE AND DRAIN EXTENSIONS FOR ETSOIAANM Haran; Balasubramanian S.AACI WatervlietAAST NYAACO USAAGP Haran; Balasubramanian S. Watervliet NY USAANM Jagannathan; HemanthAACI GuilderlandAAST NYAACO USAAGP Jagannathan; Hemanth Guilderland NY USAANM Kanakasabapathy; Sivananda K.AACI NiskayunaAAST NYAACO USAAGP Kanakasabapathy; Sivananda K. Niskayuna NY USAANM Mehta; SanjayAACI NiskayunaAAST NYAACO USAAGP Mehta; Sanjay Niskayuna NY US - A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions. | 2013-01-17 |
20130015510 | Transistor, Semiconductor Device, and Method for Manufacturing the SameAANM Yan; JiangAACI NewburghAAST NYAACO USAAGP Yan; Jiang Newburgh NY USAANM Zhao; LichuanAACI BeijingAACO CNAAGP Zhao; Lichuan Beijing CN - The invention provides a transistor, a semiconductor device and a method for manufacturing the same. The method for manufacturing a transistor comprises: defining an active area on a semiconductor substrate, forming a dummy gate stack on the active area, primary spacers surrounding said dummy gate stack, and an insulating layer surrounding said primary spacers, and forming source/drain regions embedded in said active area; removing the dummy gate in said dummy gate stack to form a first recessed portion surrounded by the primary spacers; filling Cu simultaneously in said first recessed portion and in the source/drain contact holes penetrating said insulating layer to form a gate and source/drain contacts. By filling the gate and the source/drain contact holes with the metal Cu simultaneously in the Gate Last structure, the gate serial resistance and the source/drain contact holes resistance in the Gate Last process are decreased. Besides, the effect of metal filling is improved in small scale, and the process complexity and difficulty is efficiently decreased. | 2013-01-17 |
20130015511 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICEAANM MIYATA; ToshitakaAACI KanagawaAACO JPAAGP MIYATA; Toshitaka Kanagawa JPAANM AOKI; NobutoshiAACI KanagawaAACO JPAAGP AOKI; Nobutoshi Kanagawa JP - According to one embodiment, a semiconductor device includes a fin-type semiconductor layer formed on a semiconductor substrate, a source layer connected to one end of the fin-type semiconductor layer, a drain layer connected to the other end of the fin-type semiconductor layer, and a gate electrode that includes a first sub electrode that is arranged on the source layer side of the fin-type semiconductor layer to extend toward the drain layer side on the base side of the fin-type semiconductor layer and has a first work function and a second sub electrode that is arranged on the drain layer side of the fin-type semiconductor layer and has a second work function different from the first work function. | 2013-01-17 |
20130015512 | LOW RESISTANCE SOURCE AND DRAIN EXTENSIONS FOR ETSOI - A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions. | 2013-01-17 |
20130015513 | SOLID-STATE IMAGING DEVICE, SOLID-STATE IMAGING DEVICE MANUFACTURING METHOD, AND ELECTRONIC DEVICEAANM Kido; HideoAACI KanagawaAACO JPAAGP Kido; Hideo Kanagawa JPAANM Enomoto; TakayukiAACI KanagawaAACO JPAAGP Enomoto; Takayuki Kanagawa JPAANM Togashi; HideakiAACI KanagawaAACO JPAAGP Togashi; Hideaki Kanagawa JP - A solid-state imaging device includes: a first photodiode made up of a first first-electroconductive-type semiconductor region formed on a first principal face side of a semiconductor substrate, and a first second-electroconductive-type semiconductor region formed within the semiconductor substrate adjacent to the first first-electroconductive-type semiconductor region; a second photodiode made up of a second first-electroconductive-type semiconductor region formed on a second principal face side of the semiconductor substrate, and a second second-electroconductive-type semiconductor region formed within the semiconductor substrate adjacent to the second first-electroconductive-type semiconductor region; and a gate electrode formed on the first principal face side of the semiconductor substrate; with impurity concentration of a connection face between the second first-electroconductive-type semiconductor region and the second second-electroconductive-type semiconductor region being equal to or greater than impurity concentration of a connection face of an opposite layer of the second first-electroconductive-type semiconductor region of the second second-electroconductive-type semiconductor region. | 2013-01-17 |
20130015514 | SINGLE POLY NON-VOLATILE MEMORY CELLSAANM Herberholz; RainerAACI CambridgeAACO GBAAGP Herberholz; Rainer Cambridge GB - A non-volatile memory cell that includes a semiconductor substrate; a coupling capacitor located in a first active region of the semiconductor substrate; and at a shared second active region of the semiconductor substrate, a sense transistor and a tunnelling capacitor configured in parallel with the gate of the sense transistor. The coupling capacitor, sense transistor and tunnelling capacitor share a common floating gate electrode and the sense transistor includes source and drain regions arranged such that the tunnelling capacitor is defined by an overlap between the floating gate electrode and the drain region of the sense transistor. Word-line contacts may be to a separate active area from the coupling capacitor. This and/or other features can help to reduce Frenkel-Poole conduction. | 2013-01-17 |
20130015515 | FET eDRAM TRENCH SELF-ALIGNED TO BURIED STRAPAANM Anderson; Brent A.AACI JerichoAAST VTAACO USAAGP Anderson; Brent A. Jericho VT USAANM Barth, JR.; John E.AACI WillistonAAST VTAACO USAAGP Barth, JR.; John E. Williston VT USAANM Nowak; Edward J.AACI Essex JunctionAAST VTAACO USAAGP Nowak; Edward J. Essex Junction VT USAANM Rankin; Jed H.AACI RichmondAAST VTAACO USAAGP Rankin; Jed H. Richmond VT US - A structure and method of making a field effect transistor (FET) embedded dynamic random access memory (eDRAM) cell array, which includes: a buried silicon strap extending into a buried oxide (BOX) layer of a silicon-on-insulator (SOI) substrate; a recessed trench capacitor extending down into the substrate layer of the SOI substrate; a lateral surface of a conductive top plate formed on the recessed trench capacitor that contacts a first lateral surface of the buried silicon strap; a dielectric cap disposed above the conductive top plate; a first FET formed from the silicon layer of the SOI substrate, in which a source/drain region of the first FET contacts a second lateral surface of the buried silicon strap; and a passing wordline disposed on a portion of the dielectric cap opposite to and separate from the buried silicon strap and connected to a gate of a second FET in an adjacent row of the FET eDRAM cell array. | 2013-01-17 |
20130015516 | ASYMMETRICAL NON-VOLATILE MEMORY CELL AND METHOD FOR FABRICATING THE SAMEAANM Kim; Sang Y.AACI KulimAACO MYAAGP Kim; Sang Y. Kulim MYAANM Lee; Sang H.AACI KulimAACO MYAAGP Lee; Sang H. Kulim MYAANM May; Norhafizah CheAACI KulimAACO MYAAGP May; Norhafizah Che Kulim MY - The asymmetrical non-volatile memory cell is provided on a substrate of first conductivity type and comprises a control region and a floating region, wherein the control region is adjacent to the floating region and isolated from the floating region. The control region further comprises an implant region, having second conductivity type, disposed entirely across the control region and a polycrystalline silicon control gate disposed entirely over the implant region. The floating region further comprises a first voltage state of a drain implant region and a second voltage state of a source implant region, both having second conductivity type, the first voltage state is different from the second voltage state, a channel region that separates the drain implant region and the source implant region, and a polycrystalline silicon floating gate disposed entirely over the channel region and at least partially over the source implant region and drain implant region. | 2013-01-17 |
20130015517 | Semiconductor Memory Device Having Electrically Floating Body Transistor, Semiconductor Memory Device Having Both Volatile and Non-Volatile Functionality and Method of Operating - A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided. | 2013-01-17 |
20130015518 | SEMICONDUCTOR MEMORY DEVICEAANM SATO; HiroyasuAACI Kanagawa-kenAACO JPAAGP SATO; Hiroyasu Kanagawa-ken JPAANM NISHIHARA; KiyohitoAACI Kanagawa-kenAACO JPAAGP NISHIHARA; Kiyohito Kanagawa-ken JPAANM NAWATA; HidefumiAACI Kanagawa-kenAACO JPAAGP NAWATA; Hidefumi Kanagawa-ken JPAANM ICHIGE; MasayukiAACI Kanagawa-kenAACO JPAAGP ICHIGE; Masayuki Kanagawa-ken JPAANM OHBA; RyujiAACI Kanagawa-kenAACO JPAAGP OHBA; Ryuji Kanagawa-ken JP - In general, according to one embodiment, a semiconductor memory device includes active areas extending in a first direction, tunnel films provided on the active areas, floating gate electrodes provided on the tunnel films, an interelectrode insulating film provided on the floating gate electrodes and extending in a second direction, a control gate electrode provided on the interelectrode insulating film and extending in the second direction, a lower insulating portion provided between the active areas, between the tunnel films, and between the floating gate electrodes adjacent in the second direction, and an upper insulating portion provided between the lower insulating portion and the interelectrode insulating film. The lower insulating portion includes a void. Relative dielectric constant of the upper insulating portion is higher than that of the lower insulating portion. Relative dielectric constant of the interelectrode insulating film is higher than that of the upper insulating portion. | 2013-01-17 |
20130015519 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAMEAANM Fujii; ShosukeAACI Yokohama-shiAACO JPAAGP Fujii; Shosuke Yokohama-shi JPAANM Sakuma; KiwamuAACI Yokohama-shiAACO JPAAGP Sakuma; Kiwamu Yokohama-shi JPAANM Fujiki; JunAACI Yokohama-shiAACO JPAAGP Fujiki; Jun Yokohama-shi JPAANM Kinoshita; AtsuhiroAACI Kamakura-shiAACO JPAAGP Kinoshita; Atsuhiro Kamakura-shi JP - According to one embodiment, a nonvolatile semiconductor memory device includes first to n-th semiconductor layers which are stacked in a first direction perpendicular to a surface of a semiconductor substrate and which extend in a second direction parallel to the surface of the semiconductor substrate, an electrode which extends in the first direction along side surfaces of the first to n-th semiconductor layers, the side surfaces of the first to n-th semiconductor layers exposing in a third direction perpendicular to the first and second directions, and first to n-th charge storage layers located between the first to n-th semiconductor layers and the electrode respectively. The first to n-th charge storage layers are separated from each other in areas between the first to n-th semiconductor layers. | 2013-01-17 |
20130015520 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure in which a first insulating layer, a first semiconductor layer, . . . an n-th insulating layer, an n-th semiconductor layer, and an (n+1)-th insulating layer (n is a natural number equal to or more than 2) are stacked in order thereof in a first direction perpendicular to a surface of a semiconductor substrate and which extends in a second direction parallel to the surface of the semiconductor substrate, first to n-th memory strings which use the first to n-th semiconductor layers as channels respectively, a common semiconductor layer which combines the first to n-th semiconductor layers at first ends of the first to n-th memory strings in the second direction. | 2013-01-17 |
20130015521 | CROSS-HAIR CELL DEVICES AND METHODS FOR MANUFACTURING THE SAME - Systems and methods are disclosed for manufacturing grounded gate cross-hair cells and standard cross-hair cells of fin field-effect transistors (finFETs). In one embodiment, a process may include forming gate trenches and gates on and parallel to row trenches in a substrate, wherein the gate trenches and gates are pitch-doubled such that four gate trenches are formed for every two row trenches. In another embodiment, a process may include forming gate trenches, gates, and grounded gates in a substrate, wherein the gate trenches and gates are formed such that three gate trenches are formed for every two row trenches. | 2013-01-17 |
20130015522 | SEMICONDUCTOR DEVICE - A semiconductor device includes an active region formed in a semiconductor substrate made of silicon, and surrounded by an isolation region; and a gate electrode formed on the active region and the isolation region with a gate insulating film interposed between the gate electrode and the active region or the isolation region. P-type silicon alloy layers are formed in recess regions formed in regions of the active region located laterally outward of the gate electrode, and an upper end of a portion of each of the silicon alloy layers in contact with the isolation region is located below a portion of an upper surface of the active region under the gate insulating film. | 2013-01-17 |
20130015523 | FABRICATION OF LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR (LDMOS) DEVICES - Methods of making, structures, devices, and/or applications for lateral double-diffused metal oxide semiconductor (LDMOS) transistors are disclosed. In one embodiment, a method of fabricating an LDMOS transistor with source, drain, and gate regions on a substrate, can include: forming p-type and n-type buried layer (PBL, NBL) regions; growing an epitaxial (N-EPI) layer on the NBL/PBL regions; forming a p-doped deep p-well (DPW) region on the PBL region; forming a well region in the N-EPI layer; forming a doped body region; forming an active area and a field oxide (FOX) region, and forming a drain oxide between the source and drain regions of the LDMOS transistor; forming a gate oxide adjacent to the source and drain regions, and forming a gate on the gate oxide and a portion of the drain oxide; and forming a doped drain region, and first and second doped source regions. | 2013-01-17 |
20130015524 | SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOFAANM Hsu; Chun-WeiAACI Taipei CityAACO TWAAGP Hsu; Chun-Wei Taipei City TWAANM Huang; Po-ChengAACI Chiayi CityAACO TWAAGP Huang; Po-Cheng Chiayi City TWAANM Tsai; Teng-ChunAACI Tainan CityAACO TWAAGP Tsai; Teng-Chun Tainan City TWAANM Hsu; Chia-LinAACI Tainan CityAACO TWAAGP Hsu; Chia-Lin Tainan City TWAANM Lin; Chih-HsunAACI Ping-Tung CountyAACO TWAAGP Lin; Chih-Hsun Ping-Tung County TWAANM Chen; Yen-MingAACI New Taipei CityAACO TWAAGP Chen; Yen-Ming New Taipei City TWAANM Chen; Chia-HsiAACI Kao-Hsiung CityAACO TWAAGP Chen; Chia-Hsi Kao-Hsiung City TWAANM Kung; Chang-HungAACI Kaohsiung CityAACO TWAAGP Kung; Chang-Hung Kaohsiung City TW - A semiconductor device having a metal gate includes a substrate having a plurality of shallow trench isolations (STIs) formed therein, at least a metal gate positioned on the substrate, and at least a pair of auxiliary dummy structures respectively positioned at two sides of the metal gate and on the substrate. | 2013-01-17 |
20130015525 | CMOS WITH DUAL RAISED SOURCE AND DRAIN FOR NMOS AND PMOSAANM Cheng; KangguoAACI AlbanyAAST NYAACO USAAGP Cheng; Kangguo Albany NY USAANM Doris; Bruce B.AACI AlbanyAAST NYAACO USAAGP Doris; Bruce B. Albany NY USAANM Khakifirooz; AliAACI San JoseAAST CAAACO USAAGP Khakifirooz; Ali San Jose CA USAANM Haran; Balasubramanian S.AACI AlbanyAAST NYAACO USAAGP Haran; Balasubramanian S. Albany NY US - An apparatus and a method for creating a CMOS with a dual raised source and drain for NMOS and PMOS. The spacers on both stack gates are of equal thickness. In this method, a first insulating layer is formed on the surface. The first region is then masked while the other region has the first layer etched away and has an epitaxial source and drain grown on the region. A second layer is formed to all exposed surfaces. The second region is then masked while the first region is etched away. The epitaxial source and drain is formed on the first region. The second region can also be masked by adding a thin layer of undoped silicon and then oxidize it. Another way to mask the second region is to use a hard mask. Another way to form the second source and drain is to use amorphous material. | 2013-01-17 |
20130015526 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAMEAANM Liang; QingqingAACI LagrangevilleAAST NYAACO USAAGP Liang; Qingqing Lagrangeville NY USAANM Zhu; HuilongAACI PoughkeepsieAAST NYAACO USAAGP Zhu; Huilong Poughkeepsie NY USAANM Zhong; HuicaiAACI San JoseAAST CAAACO USAAGP Zhong; Huicai San Jose CA US - The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention comprises: a substrate which comprises a base layer, an insulating layer on the base layer, and a semiconductor layer on the insulating layer; and a first transistor and a second transistor formed on the substrate, the first and second transistors being isolated from each other by a trench isolation structure formed in the substrate. Wherein at least a part of the base layer under at least one of the first and second transistors is strained, and the strained part of the base layer is adjacent to the insulating layer. The semiconductor device according to the invention increases the speed of the device and thus improves the performance of the device. | 2013-01-17 |
20130015527 | Method of Forming Metal Silicide Regions on a Semiconductor DeviceAANM Thees; Hans-JuergenAACI DresdenAACO DEAAGP Thees; Hans-Juergen Dresden DEAANM Baars; PeterAACI DresdenAACO DEAAGP Baars; Peter Dresden DE - The present disclosure is directed to various methods of forming metal silicide regions on an integrated circuit device. In one example, the method includes forming a PMOS transistor and an NMOS transistor, each of the transistors having a gate electrode and at least one source/drain region formed in a semiconducting substrate, forming a first sidewall spacer adjacent the gate electrodes and forming a second sidewall spacer adjacent the first sidewall spacer. The method further includes forming a layer of material above and between the gate electrodes, wherein the layer of material has an upper surface that is positioned higher than an upper surface of each of the gate electrodes, performing a first etching process on the layer of material to reduce a thickness thereof such that the upper surface of the layer of material is positioned at a desired level that is at least below the upper surface of each of the gate electrodes, and after performing the first etching process, performing a second etching process to insure that a desired amount of the gate electrodes for the PMOS transistor and the NMOS transistor are exposed for a subsequent metal silicide formation process. The method concludes with the step of forming metal silicide regions on the gate electrode structures and on the source/drain regions. | 2013-01-17 |
20130015528 | METHOD AND SYSTEM FOR FORMING LOW CONTACT RESISTANCE DEVICEAANM Waite; AndrewAACI BeverlyAAST MAAACO USAAGP Waite; Andrew Beverly MA USAANM Erokhin; YuriAACI GeorgetownAAST MAAACO USAAGP Erokhin; Yuri Georgetown MA USAANM Todorov; StanislavAACI TopsfieldAAST MAAACO USAAGP Todorov; Stanislav Topsfield MA US - A method of treating a CMOS device. The method may include providing a first stress liner on a transistor of a first dopant type in the CMOS device. The method may further include exposing the CMOS device to first ions in a first exposure, the first ions configured to reduce contact resistance in a source/drain region of a transistor of a second dopant type. | 2013-01-17 |
20130015529 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR MANUFACTURING THE SAMEAANM Zhong; HuicaiAACI San JoseAAST CAAACO USAAGP Zhong; Huicai San Jose CA USAANM Liang; QingqingAACI LangrangevilleAAST NYAACO USAAGP Liang; Qingqing Langrangeville NY USAANM Ying; HaizhouAACI PoughkeepsieAAST NYAACO USAAGP Ying; Haizhou Poughkeepsie NY US - There are provided a semiconductor device structure and a method for manufacturing the same. The method comprises: forming at least one continuous gate line on a semiconductor substrate; forming a gate spacer surrounding the gate line; forming source/drain regions in the semiconductor substrate on both sides of the gate line; forming a conductive spacer surrounding the gate spacer; and performing inter-device electrical isolation at a predetermined region, wherein isolated portions of the gate line form gates of respective unit devices, and isolated portions of the conductive spacer form contacts of respective unit devices. Embodiments of the present disclosure are applicable to manufacture of contacts in integrated circuits. | 2013-01-17 |
20130015530 | METHOD OF FORMING POLYSILICON RESISTOR DURING REPLACEMENT METAL GATE PROCESS AND SEMICONDUCTOR DEVICE HAVING SAMEAANM KIM; JU YOUNAACI Suwon-siAACO KRAAGP KIM; JU YOUN Suwon-si KRAANM Kim; JedonAACI SeoulAACO KRAAGP Kim; Jedon Seoul KR - A method for manufacturing a semiconductor device, comprising forming a first gate stack portion on a substrate, the first gate stack portion including a first gate oxide layer and a first polysilicon layer on the first gate oxide layer, forming a second gate stack portion on the substrate, the second gate stack portion including a second gate oxide layer and a second polysilicon layer on the second gate oxide layer, forming a resistor portion on the substrate, the resistor portion including a third gate oxide layer and a third polysilicon layer on the third gate oxide layer, covering the resistor portion with a photoresist, removing respective first portions of the first and second polysilicon layers from the first and second gate stack portions, removing the photoresist from the resistor portion, and after removing the photoresist from the resistor portion, removing respective remaining portions of the first and second polysilicon layers from the first and second gate stack portions. | 2013-01-17 |
20130015531 | METHOD OF FORMING POLYSILICON RESISTOR DURING REPLACEMENT METAL GATE PROCESS AND SEMICONDUCTOR DEVICE HAVING SAMEAANM Kim; Ju YounAACI Suwon-siAACO KRAAGP Kim; Ju Youn Suwon-si KRAANM Kim; JedonAACI SeoulAACO KRAAGP Kim; Jedon Seoul KR - A method for manufacturing a semiconductor device, comprising forming a first gate stack portion on a surface of a substrate, the first gate stack portion including a first gate oxide layer and a first polysilicon layer on the first gate oxide layer, forming a second gate stack portion on the surface of the substrate, the second gate stack portion including a second gate oxide layer and a second polysilicon layer on the second gate oxide layer, forming a resistor portion in a recessed portion of the substrate below the surface of the substrate, the resistor portion including a third polysilicon layer, and removing the first and second polysilicon layers from the first and second gate stack portions to expose the first and second gate oxide layers, wherein at least one of a dielectric layer and a stress liner cover a top surface of the resistor portion during removal of the first and second polysilicon layers. | 2013-01-17 |
20130015532 | METHODS OF MANUFACTURING GATES FOR PREVENTING SHORTS BETWEEN THE GATES AND SELF-ALIGNED CONTACTS AND SEMICONDUCTOR DEVICES HAVING THE SAMEAANM Kim; Ju YounAACI Suwon-siAACO KRAAGP Kim; Ju Youn Suwon-si KRAANM Kim; JedonAACI SeoulAACO KRAAGP Kim; Jedon Seoul KR - A method for manufacturing a semiconductor device, comprising forming a metal gate of a transistor on a substrate by a replacement metal gate process, wherein an insulating layer is formed on the substrate adjacent the metal gate, forming a hard mask on the substrate including the insulating layer and the metal gate, the hard mask including an opening exposing the metal gate, performing a metal pull back process on the substrate to remove a predetermined depth of a top portion of the metal gate, depositing a protective layer on the substrate, including on the hard mask and on top of a remaining portion of the metal gate, and performing chemical mechanical polishing to remove the hard mask and the protective layer, wherein the protective layer formed on top of the remaining portion of the metal gate remains. | 2013-01-17 |
20130015533 | EPITAXIAL PROCESS FOR FORMING SEMICONDUCTOR DEVICESAANM WANG; Shiang-BauAACI Pingzchen CityAACO TWAAGP WANG; Shiang-Bau Pingzchen City TW - A method for forming a semiconductor device such as a MOSFET. The method includes forming gate electrode pillars on a silicon substrate via material deposition and etching. Following the etching step to define the pillars, an epitaxial silicon film is grown on the substrate between the pillars prior to forming recesses in the substrate for the source/drain regions of the transistor. The epitaxial silicon film compensates for substrate material that may be lost during formation of the gate electrode pillars, thereby producing source/drain recesses having a configuration amenable to be filled uniformly with silicon for later forming the source/drain regions in the substrate. | 2013-01-17 |
20130015534 | THREE DIMENSIONAL FET DEVICES HAVING DIFFERENT DEVICE WIDTHSAANM Cheng; KangguoAACI SchenectadyAAST NYAACO USAAGP Cheng; Kangguo Schenectady NY USAANM Doris; Bruce B.AACI BrewsterAAST NYAACO USAAGP Doris; Bruce B. Brewster NY USAANM Khakifirooz; AliAACI Mountain ViewAAST CAAACO USAAGP Khakifirooz; Ali Mountain View CA USAANM Kulkarni; PranitaAACI SlingerlandsAAST NYAACO USAAGP Kulkarni; Pranita Slingerlands NY US - A three dimensional FET device structure which includes a plurality of three dimensional FET devices. Each of the three dimensional FET devices include an insulating base, a three dimensional fin oriented perpendicular to the insulating base, a gate dielectric wrapped around the three dimensional fin and a gate wrapped around the gate dielectric and extending perpendicularly to the three dimensional fin, the three dimensional fin having a device width being defined as the circumference of the three dimensional fin in contact with the gate dielectric. At least a first of the three dimensional FET devices has a first device width while at least a second of the three dimensional FET devices has a second device width. The first device width is different than the second device width. Also included is a method of making the three dimensional FET device structure. | 2013-01-17 |
20130015535 | Configuration and Fabrication of Semiconductor Structure Having Asymmetric Field-effect Transistor with Tailored Pocket Portion Along Source/Drain Zone - An asymmetric insulated-gate field effect transistor ( | 2013-01-17 |
20130015536 | MEMS WITH SINGLE USE VALVE AND METHOD OF OPERATIONAANM Feyh; AndoAACI Palo AltoAAST CAAACO USAAGP Feyh; Ando Palo Alto CA USAANM Chen; Po-JuiAACI SunnyvaleAAST CAAACO USAAGP Chen; Po-Jui Sunnyvale CA US - In one embodiment, a method of opening a passageway to a cavity includes providing a donor portion, forming a heating element adjacent to the donor portion, forming a first sacrificial slab abutting the donor portion, wherein the donor portion and the sacrificial slab are a shrinkable pair, forming a first cavity, a portion of the first cavity bounded by the first sacrificial slab, generating heat with the heating element, forming a first reduced volume slab from the first sacrificial slab using the generated heat and the donor portion, and forming a passageway to the first cavity by forming the first reduced volume slab. | 2013-01-17 |
20130015537 | PIEZORESISTIVE PRESSURE SENSOR AND PROCESS FOR PRODUCING A PIEZORESISTIVE PRESSURE SENSORAANM Nowak; BirgitAACI TeltowAACO DEAAGP Nowak; Birgit Teltow DEAANM Ostrick; BernhardAACI TeltowAACO DEAAGP Ostrick; Bernhard Teltow DEAANM Peschka; AndreasAACI MichendorfAACO DEAAGP Peschka; Andreas Michendorf DE - A pressure sensor ( | 2013-01-17 |
20130015538 | MAGNETORESISTIVE RANDOM ACCESS MEMORY AND METHOD OF MAKING THE SAMEAANM LIU; Ming-TeAACI TaipeiAACO TWAAGP LIU; Ming-Te Taipei TWAANM CHIANG; Tien-WeiAACI HsinchuAACO TWAAGP CHIANG; Tien-Wei Hsinchu TWAANM KAO; Ya-ChenAACI Fuxing TownshipAACO TWAAGP KAO; Ya-Chen Fuxing Township TWAANM CHEN; Wen-ChengAACI HsinchuAACO TWAAGP CHEN; Wen-Cheng Hsinchu TW - A magnetoresistive random access memory (MRAM) cell includes a magnetic tunnel junction (MTJ), a top electrode disposed over the MTJ, a bottom electrode disposed below the MTJ, and an induction line disposed to one side of the MTJ. The induction line is configured to induce a perpendicular magnetic field at the MIJ. | 2013-01-17 |
20130015539 | MAGNETIC MEMORY DEVICE HAVING INCREASED MARGIN IN THICKNESS OF MAGNETIC LAYERSAANM CHOI; Won JoonAACI Ichon-siAACO KRAAGP CHOI; Won Joon Ichon-si KR - A magnetic memory device capable of ensuring a constant TMR difference even when the margin in a thickness of a magnetic layer constituting a KO is small is provided. The magnetic memory device includes a first magnetic layer having a fixed magnetization direction, a magnetization fixing layer formed on the first magnetic layer, a tunnel barrier layer formed on the magnetization fixing layer, and a second magnetic layer formed on the tunnel barrier layer and having a changeable magnetization direction. | 2013-01-17 |
20130015540 | MAGNETIC TUNNEL JUNCTION DEVICE AND METHOD FOR FABRICATING THE SAMEAANM CHOI; Won JoonAACI SeoulAACO KRAAGP CHOI; Won Joon Seoul KR - A magnetic tunnel junction device includes a first electrode having a curved top surface, a magnetic tunnel junction layer formed along the top surface of the first electrode, and a second electrode formed on the magnetic tunnel junction layer. | 2013-01-17 |
20130015541 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOFAANM KANAYA; HiroyukiAACI Yokohama-shiAACO JPAAGP KANAYA; Hiroyuki Yokohama-shi JP - A memory includes a semiconductor substrate. Cell transistors are on the substrate. Contact plugs each of which is buried between the adjacent cell transistors and electrically connected to a diffusion layer between the adjacent cell transistors. An interlayer dielectric film buries gaps between the contact plugs. A storage element is provided not above the contact plugs but above the interlayer dielectric film. A sidewall film covers a part of a side surface of the storage element, and is provided to overlap with one of the contact plugs as viewed from above a surface of the semiconductor substrate. A lower electrode is provided between a bottom of the storage element and the interlayer dielectric film and between the sidewall film and one of the contact plugs, and electrically connects the storage element to one of the contact plugs. | 2013-01-17 |
20130015542 | MAGNETO-ELECTRONIC DEVICES AND METHODS OF PRODUCTION - A magneto-electronic device includes a first electrode, a second electrode spaced apart from the first electrode, and an electric-field-controllable magnetic tunnel junction arranged between the first electrode and the second electrode. The electric-field-controllable magnetic tunnel junction includes a first ferromagnetic layer, an insulating layer formed on the first ferromagnetic layer, and a second ferromagnetic layer formed on the insulating layer. The first and second ferromagnetic layers have respective first and second magnetic anisotropies that are alignable substantially parallel to each other in a first state and substantially antiparallel in a second state of the electric-field-controllable magnetic tunnel junction. | 2013-01-17 |
20130015543 | MAGNETIC MEMORY CELL CONSTRUCTION - A magnetic tunnel junction cell having a free layer, a ferromagnetic pinned layer, and a barrier layer therebetween. The free layer has a central ferromagnetic portion and a stabilizing portion radially proximate the central ferromagnetic portion. The construction can be used for both in-plane magnetic memory cells where the magnetization orientation of the magnetic layer is in the stack film plane and out-of-plane magnetic memory cells where the magnetization orientation of the magnetic layer is out of the stack film plane, e.g., perpendicular to the stack plane. | 2013-01-17 |
20130015544 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAMEAANM HAN; Myeong WooAACI HwaseongAACO KRAAGP HAN; Myeong Woo Hwaseong KRAANM Yoo; Do JaeAACI SuwonAACO KRAAGP Yoo; Do Jae Suwon KRAANM Lee; Jung AunAACI SuwonAACO KRAAGP Lee; Jung Aun Suwon KRAANM Yoon; Jung HoAACI AnyangAACO KRAAGP Yoon; Jung Ho Anyang KRAANM Park; Chul GyunAACI YonginAACO KRAAGP Park; Chul Gyun Yongin KR - There is provided a semiconductor package including: a substrate including a semiconductor chip mounted thereon; a protective layer covering the semiconductor chip; a metal pattern mounted on the protective layer; and a first connective member connecting the semiconductor chip and the metal pattern. | 2013-01-17 |
20130015545 | SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD OF SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUSAANM Toumiya; YoshinoriAACI KumamotoAACO JPAAGP Toumiya; Yoshinori Kumamoto JPAANM Ootsuka; YoichiAACI KumamotoAACO JPAAGP Ootsuka; Yoichi Kumamoto JPAANM Maeda; KensakuAACI KanagawaAACO JPAAGP Maeda; Kensaku Kanagawa JP - A solid-state imaging device includes: a substrate on which plural pixels having photoelectric converters are formed; an inorganic microlens made of an inorganic material and formed above the substrate, and an organic microlens made of an organic material and formed adjacent to the inorganic microlens so that a hem portion touches or overlaps a hem portion of the inorganic microlens. | 2013-01-17 |
20130015546 | MULTI-LAYER PHOTOELECTRIC INTEGRATED CIRCUIT DEVICE WITH OVERLAPPING DEVICESAANM Joe; In-sungAACI SeoulAACO KRAAGP Joe; In-sung Seoul KRAANM Suh; Sung-dongAACI SeoulAACO KRAAGP Suh; Sung-dong Seoul KRAANM Na; Kyoung-wonAACI SeoulAACO KRAAGP Na; Kyoung-won Seoul KRAANM Ha; Kyoung-hoAACI SeoulAACO KRAAGP Ha; Kyoung-ho Seoul KRAANM Kim; Seong-guAACI Pyeongtaek-siAACO KRAAGP Kim; Seong-gu Pyeongtaek-si KRAANM Shin; Young-hwackAACI Yeonsu-guAACO KRAAGP Shin; Young-hwack Yeonsu-gu KR - An integrated circuit device includes a plurality of device layers disposed on a substrate. A first one of the device layers includes at least one photo device and/or at least one electronic device and a second one of the device layers includes at least one photo device overlying the at least one photo device and/or the at least one electronic device of the first one of the device layers. | 2013-01-17 |
20130015547 | PHOTOELECTRIC CONVERSION DEVICE, METHOD FOR MANUFACTURING THE SAME, PHOTO SENSOR AND IMAGING DEVICEAANM Hamano; MitsumasaAACI KanagawaAACO JPAAGP Hamano; Mitsumasa Kanagawa JP - Provided are a photoelectric conversion device capable of controlling an absorbance of the red region at a wavelength of 600 nm or more, and an imaging device having an improved color reproduction by using the photoelectric device. Provided are a photoelectric conversion device that includes a pair of electrodes, and a photoelectric conversion layer disposed between the pair of electrodes, in which the photoelectric conversion layer contains a p-type semiconductor compound and two or more different kinds of unsubstituted fullerenes, and an imaging device that includes the photoelectric conversion device. | 2013-01-17 |
20130015548 | INTEGRATED CIRCUIT WITH TEMPERATURE INCREASING ELEMENT AND ELECTRONIC SYSTEM HAVING THE SAMEAANM Chen; Hsieh-ChunAACI Taichung CityAACO TWAAGP Chen; Hsieh-Chun Taichung City TWAANM Chen; Tsang-YiAACI New Taipei CityAACO TWAAGP Chen; Tsang-Yi New Taipei City TW - To provide an integrated circuit with functionality under environment with temperature lower than a working condition, the integrated circuit is designed to include a heating element incorporated with signal pins on a carrier, such as a lead frame, that supports a chip die and controlled by a heating control unit to increase temperature of the chip die. The heating control unit provides voltage for the heating element when a detecting unit detects that the temperature of the chip die falls below a predetermined temperature and a power control unit provide operation power for the chip die when the temperature of the chip die detected by the detecting unit reaches or falls above the predetermined temperature. | 2013-01-17 |
20130015549 | Integrated Thermoelectric GeneratorAANM Fornara; PascalAACI PourrieresAACO FRAAGP Fornara; Pascal Pourrieres FRAANM Rivero; ChristianAACI RoussetAACO FRAAGP Rivero; Christian Rousset FR - An integrated thermoelectric generator includes a semiconductor. A set of thermocouples are electrically connected in series and thermally connected in parallel. The set of thermocouples include parallel semiconductor regions. Each semiconductor region has one type of conductivity from among two opposite types of conductivity. The semiconductor regions are electrically connected in series so as to form a chain of regions having, alternatingly, one and the other of the two types of conductivity. | 2013-01-17 |
20130015550 | JUNCTION BARRIER SCHOTTKY DIODE WITH ENFORCED UPPER CONTACT STRUCTURE AND METHOD FOR ROBUST PACKAGINGAANM Bhalla; AnupAACI Santa ClaraAAST CAAACO USAAGP Bhalla; Anup Santa Clara CA USAANM Pan; JiAACI San JoseAAST CAAACO USAAGP Pan; Ji San Jose CA USAANM Ng; DanielAACI CampbellAAST CAAACO USAAGP Ng; Daniel Campbell CA US - A semiconductor junction barrier Schottky (JBS-SKY) diode with enforced upper contact structure (EUCS) is disclosed. Referencing an X-Y-Z coordinate, the JBS-SKY diode has semiconductor substrate (SCST) parallel to X-Y plane. Active device zone (ACDZ) atop SCST and having a JBS-SKY diode with Z-direction current flow. Peripheral guarding zone (PRGZ) atop SCST and surrounding the ACDZ. The ACDZ has active lower semiconductor structure (ALSS) and enforced active upper contact structure (EUCS) atop ALSS. The EUC has top contact metal (TPCM) extending downwards and in electrical conduction with bottom of EUCS; and embedded bottom supporting structure (EBSS) inside TPCM and made of a hard material, the EBSS extending downwards till bottom of the EUCS. Upon encountering bonding force onto TPCM during packaging of the JBS-SKY diode, the EBSS enforces the EUCS against an otherwise potential micro cracking of the TPCM degrading the leakage current of the JBS-SKY diode. | 2013-01-17 |
20130015551 | METHOD FOR FABRICATING MEMORY DEVICE WITH BURIED DIGIT LINES AND BURIED WORD LINESAANM Wang; Kuo-ChenAACI Chiayi CityAACO TWAAGP Wang; Kuo-Chen Chiayi City TW - A method for fabricating a memory array includes providing a semiconductor substrate having thereon a plurality of line-shaped active areas and intermittent line-shaped trench isolation regions between the plurality of line-shaped active areas, which extend along a first direction; forming buried word lines extending along a second direction in the semiconductor substrate, the buried word lines intersecting with the line-shaped active areas and the intermittent line-shaped trench isolation regions, wherein the second direction is not perpendicular to the first direction; forming buried digit lines extending along a third direction in the semiconductor substrate, wherein the third direction is substantially perpendicular to the second direction; and forming storage nodes at storage node sites between the buried digit lines. | 2013-01-17 |
20130015552 | Electrical Isolation Of High Defect Density Regions In A Semiconductor DeviceAANM Kizilyalli; Isik C.AACI San FranciscoAAST CAAACO USAAGP Kizilyalli; Isik C. San Francisco CA USAANM Bour; David P.AACI CupertinoAAST CAAACO USAAGP Bour; David P. Cupertino CA USAANM Brown; Richard J.AACI Los GatosAAST CAAACO USAAGP Brown; Richard J. Los Gatos CA USAANM Edwards; Andrew P.AACI San JoseAAST CAAACO USAAGP Edwards; Andrew P. San Jose CA USAANM Nie; HuiAACI CupertinoAAST CAAACO USAAGP Nie; Hui Cupertino CA USAANM Romano; Linda T.AACI SunnyvaleAAST CAAACO USAAGP Romano; Linda T. Sunnyvale CA US - Embodiments of the invention include a III-nitride semiconductor layer including a first portion having a first defect density and a second portion having a second defect density. The first defect density is greater than the second defect density. An insulating material is disposed over the first portion. The insulating material is not formed on or is removed from the second portion. | 2013-01-17 |
20130015553 | High Voltage Isolation Trench, Its Fabrication Method and MOS DeviceAANM Jiang; YanfengAACI BeijingAACO CNAAGP Jiang; Yanfeng Beijing CN - A type of high voltage isolation trench, its fabrication method and an MOS device are disclosed. The isolation trench includes a trench extending to a buried oxide layer of a wafer, with high concentration N | 2013-01-17 |
20130015554 | Semiconductor Device and Method for Forming Passive Circuit Elements With Through Silicon Vias to Backside Interconnect Structures - A semiconductor wafer contains a substrate having a plurality of active devices formed thereon. An analog circuit is formed on the substrate. The analog circuit can be an inductor, metal-insulator-metal capacitor, or resistor. The inductor is made with copper. A through substrate via (TSV) is formed in the substrate. A conductive material is deposited in the TSV in electrical contact with the analog circuit. An under bump metallization layer is formed on a backside of the substrate in electrical contact with the TSV. A solder material is deposited on the UBM layer. The solder material is reflowed to form a solder bump. A wire bond is formed on a top surface of the substrate. A redistribution layer is formed between the TSV and UBM. The analog circuit electrically connects through the TSV to the solder bump on the back side of the substrate. | 2013-01-17 |
20130015555 | Method of Forming an Inductor on a Semiconductor Wafer - A semiconductor device has a substrate with an inductor formed on its surface. First and second contact pads are formed on the substrate. A passivation layer is formed over the substrate and first and second contact pads. A protective layer is formed over the passivation layer. The protective layer is removed over the first contact pad, but not from the second contact pad. A conductive layer is formed over the first contact pad. The conductive layer is coiled on the surface of the substrate to produce inductive properties. The formation of the conductive layer involves use of a wet etchant. The second contact pad is protected from the wet etchant by the protective layer. The protective layer is removed from the second contact pad after forming the conductive layer over the first contact pad. An external connection is formed on the second contact pad. | 2013-01-17 |
20130015556 | SUSPENDED BEAM FOR USE IN MEMS DEVICEAANM YANG; Chin-ShengAACI Hsinchu CityAACO TWAAGP YANG; Chin-Sheng Hsinchu City TW - A suspended beam includes a substrate, a main body and a first metal line structure. A first end of the main body is fixed onto the substrate. A second end of the main body is suspended. The first metal line structure is embedded in the main body. The width of the first metal line structure is smaller than the width of the main body. | 2013-01-17 |
20130015557 | SEMICONDUCTOR PACKAGE INCLUDING AN EXTERNAL CIRCUIT ELEMENTAANM Yang; ZhipingAACI CupertinoAAST CAAACO USAAGP Yang; Zhiping Cupertino CA USAANM Xue; JieAACI San RamonAAST CAAACO USAAGP Xue; Jie San Ramon CA USAANM Savic; JovicaAACI Downers GroveAAST ILAACO USAAGP Savic; Jovica Downers Grove IL USAANM Li; LiAACI San RamonAAST CAAACO USAAGP Li; Li San Ramon CA US - Circuit elements such as DC blocking capacitors used in communication such as a serial communication link between two or more electrical components are disposed in pre-existing openings in a support structure that supports at least one of the two electrical components. The openings may be plated and used for signal transmission from the one electrical component to a printed circuit board (PCB) supporting the substrate. The DC blocking capacitors may be oriented substantially vertically, and a non-conducting material may be disposed in each opening in the substrate such that the non-conducting material at least partially surrounds and fixes the orientation of the DC blocking capacitor disposed in the opening. | 2013-01-17 |
20130015558 | SEMICONDUCTOR DEVICEAANM NISHIZAKI; MamoruAACI TokyoAACO JPAAGP NISHIZAKI; Mamoru Tokyo JPAANM OTA; KenAACI TokyoAACO JPAAGP OTA; Ken Tokyo JP - A semiconductor device has at least a first capacitor and a second capacitor. First electrodes of the first and second capacitors are connected in common, a first voltage (½ VPERI) is applied to the first electrodes, a second voltage (for example, VPERI) that is different from the first voltage is applied to either one of the second electrodes, and the first voltage is applied to the other second electrode. A capacitor which constitutes a dummy capacitance is provided by applying one of the second electrodes of the first and second capacitors with the same voltage as the voltage applied to their first electrodes, whereby making it possible to increase the area of the compensation capacitance in the semiconductor device without changing a specified capacitance value. | 2013-01-17 |
20130015559 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAMEAANM LEE; Sung-HoAACI Hwaseong-siAACO KRAAGP LEE; Sung-Ho Hwaseong-si KRAANM Choi; JinAACI Yongin-siAACO KRAAGP Choi; Jin Yongin-si KRAANM Yoo; Yong-HoAACI Yongin-siAACO KRAAGP Yoo; Yong-Ho Yongin-si KRAANM Kang; Jong-HyukAACI SeoulAACO KRAAGP Kang; Jong-Hyuk Seoul KRAANM Cha; Hyun-JooAACI SeoulAACO KRAAGP Cha; Hyun-Joo Seoul KRAANM Park; Hee-DongAACI Yongin-siAACO KRAAGP Park; Hee-Dong Yongin-si KRAANM Park; Tae-JungAACI BusanAACO KRAAGP Park; Tae-Jung Busan KR - A semiconductor device includes a plurality of lower electrodes on a substrate, with each of the lower electrodes extending in a height direction from the substrate and including sidewalls, the lower electrodes being spaced apart from each other in a first direction and in a second direction, a plurality of first supporting layer patterns contacting the sidewalls of the lower electrodes, the first supporting layer patterns extending in the first direction between ones of the lower electrodes adjacent in the second direction, a plurality of second supporting layer patterns contacting the sidewalls of the lower electrodes, the second supporting layer pattern extending in the second direction between ones of the lower electrodes adjacent in the first direction, the plurality of second supporting layer patterns being spaced apart from the plurality of first supporting layer patterns in the height direction. | 2013-01-17 |
20130015560 | GROWTH OF BULK GROUP-III NITRIDE CRYSTALS AFTER COATING THEM WITH A GROUP-III METAL AND AN ALKALI METAL - A method of producing a Group-III nitride crystal by coating at least one surface of the seed with a thin wetting layer or film comprised of one or more Group-III and alkali metals. | 2013-01-17 |
20130015561 | MECHANISMS FOR MARKING THE ORIENTATION OF A SAWED DIEAANM Chen; Hsien-WeiAACI Sinying CityAACO TWAAGP Chen; Hsien-Wei Sinying City TW - Mechanisms for identifying orientation of a sawed die are provided. By making metal pattern in the corner stress relief region in one corner of the die different from the other corners, users can easily identify the orientation of the die. | 2013-01-17 |
20130015562 | ACTINIC-RAY- OR RADIATION-SENSITIVE RESIN COMPOSITION, ACTINIC-RAY- OR RADIATION-SENSITIVE FILM THEREFROM AND METHOD OF FORMING PATTERN USING THE COMPOSITIONAANM Yamamoto; KeiAACI Haibara-gunAACO JPAAGP Yamamoto; Kei Haibara-gun JPAANM Fujita; MitsuhiroAACI Haibara-gunAACO JPAAGP Fujita; Mitsuhiro Haibara-gun JPAANM Matsuda; TomokiAACI Haibara-gunAACO JPAAGP Matsuda; Tomoki Haibara-gun JP - Provided is an actinic-ray- or radiation-sensitive resin composition including (A) a resin that when acted on by an acid, is decomposed to thereby increase its solubility in an alkali developer, (B) an onium salt containing a nitrogen atom in its cation moiety, which onium salt when exposed to actinic rays or radiation, is decomposed to thereby generate an acid, and (C) a compound that when exposed to actinic rays or radiation, generates an acid, the compound being any of compounds of general formulae (1-1) and (1-2) below. | 2013-01-17 |
20130015563 | Semiconductor packageAANM Lee; Jung AunAACI SuwonAACO KRAAGP Lee; Jung Aun Suwon KRAANM Han; Myeong WooAACI HwaseongAACO KRAAGP Han; Myeong Woo Hwaseong KRAANM Yoo; Do JaeAACI SuwonAACO KRAAGP Yoo; Do Jae Suwon KRAANM Park; Chul GyunAACI YonginAACO KRAAGP Park; Chul Gyun Yongin KR - There is provided a semiconductor package, and more particularly, a semiconductor package including an antenna embedded in an inner portion thereof. The semiconductor package includes: a semiconductor chip; a main antenna disposed to be adjacent to the semiconductor chip and electrically connected thereto; a sealing part sealing both of the semiconductor chip and the main antenna; and an auxiliary antenna formed on an outer surface of the sealing part and coupled to the main antenna. | 2013-01-17 |
20130015564 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAMEAANM Matsuki; HirohisaAACI YokohamaAACO JPAAGP Matsuki; Hirohisa Yokohama JPAANM Sakuma; MasaoAACI YokohamaAACO JPAAGP Sakuma; Masao Yokohama JP - A semiconductor device (semiconductor module) includes a circuit board (module board) and a semiconductor element mounted on the circuit board. A shielding layer that blocks electromagnetic waves is disposed on the upper surface of the semiconductor element, and an antenna element is disposed over the shielding layer. The semiconductor element and the antenna element are electrically connected to each other by a connecting portion. This structure enables the semiconductor device to be reduced in size and to have both an electromagnetic-wave blocking function and an antenna function. | 2013-01-17 |
20130015565 | SUBSTRATE STRUCTURE, SEMICONDUCTOR DEVICE ARRAY AND SEMICONDUCTOR DEVICE HAVING THE SAME - A substrate structure has a first surface and a second surface. A plurality of carrying members are formed on the first surface and a plurality of conductive traces are formed on the second surface. In addition, the substrate structure has a first, a second and a third thermal stress relief structures. The first thermal stress relief structure is that lengths of the substrate structure in different axial directions are substantially equal to each other. The second thermal stress relief structure is that a plurality of separated alignment marks are formed on the substrate structure. The third thermal stress relief structure is that the substrate structure has at least one clearance area extending along one of the axial directions of the substrate structure and the clearance area has no carrying members and no conductive traces formed thereon. | 2013-01-17 |
20130015566 | APPARATUS AND METHODS FOR QUAD FLAT NO LEAD PACKAGINGAANM GONG; ZHIWEIAACI ChandlerAAST AZAACO USAAGP GONG; ZHIWEI Chandler AZ USAANM Xu; JianwenAACI San DiegoAAST CAAACO USAAGP Xu; Jianwen San Diego CA USAANM Gao; WeiAACO USAAGP Gao; Wei USAANM Hayes; Scott M.AACI ChandlerAAST AZAACO USAAGP Hayes; Scott M. Chandler AZ US - A method for fabricating a semiconductor package is disclosed that includes providing a supply of lead elements, mounting a plurality of the lead elements on a lead frame until a predetermined number of lead elements are placed on the lead frame, and connecting other components on the lead frame to the lead elements. | 2013-01-17 |
20130015567 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD FOR SAMEAANM Minamio; MasanoriAACI OsakaAACO JPAAGP Minamio; Masanori Osaka JPAANM Tanaka; ZyunyaAACI OsakaAACO JPAAGP Tanaka; Zyunya Osaka JPAANM Ijima; Shin-ichiAACI OsakaAACO JPAAGP Ijima; Shin-ichi Osaka JP - A semiconductor device of the present invention comprises: an outer package; a first lead frame including a first relay lead, a first die pad with a power element mounted thereon, and a first external connection lead which has an end protruding from the outer package; and a second lead frame including a second relay lead, a second die pad with a control element mounted thereon, and a second external connection lead which has an end protruding from the outer package, wherein the first die pad and the second die pad or the first external connection lead and the second relay lead are joined to each other at a joint portion, and an end of the second relay lead extending from a joint portion with the first relay lead is located inside the outer package. | 2013-01-17 |
20130015568 | GETTER STRUCTURE WITH OPTIMIZED PUMPING CAPACITYAANM FERRANDON; ChristineAACI SassenageAACO FRAAGP FERRANDON; Christine Sassenage FRAANM BAILLIN; XavierAACI CrollesAACO FRAAGP BAILLIN; Xavier Crolles FR - Getter structure comprising at least one getter portion arranged on a support and including at least two adjacent getter material parts arranged on the support one beside the other, with different thicknesses and of which the surface grain densities are different from one another. | 2013-01-17 |
20130015569 | Semiconductor Device and Method of Forming Substrate With Seated Plane for Mating With Bumped Semiconductor DieAANM Anderson; Samuel J.AACI TempeAAST AZAACO USAAGP Anderson; Samuel J. Tempe AZ USAANM Smiley; Thomas B.AACI CarlsbadAAST CAAACO USAAGP Smiley; Thomas B. Carlsbad CA US - A semiconductor device has a first insulating layer formed over a substrate. The substrate has a plurality of conductive layers and plurality of second insulating layers formed between the conductive layers. The substrate can be a PCB or interposer. A plurality of openings is formed in the first insulating layer by etching or laser direct ablation. A semiconductor die has a plurality of bumps formed over a surface of the semiconductor die. The pattern of openings coincides with a pattern of the bumps. The die is mounted to the substrate with the bumps disposed within the openings in the first insulating layer. Alternatively, a conductive paste can be disposed within the openings in the first insulating layer. The bumps are reflowed to electrically connect the die to the first substrate. The bumps are substantially contained within the openings of the first insulating layer to reduce bridging between adjacent bumps. | 2013-01-17 |
20130015570 | STACKED SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOFAANM Sato; TakaoAACI Edogawa-kuAACO JPAAGP Sato; Takao Edogawa-ku JP - In an embodiment, a stacked semiconductor package includes a wiring board having external connection terminals and internal connection terminals, and first and second modules stacked on the wiring board. Each of the first and second modules includes a plurality of semiconductor chips mounted on an interposer and a sealing resin layer. The interposers and the internal connection terminals of the wiring board are electrically connected by connecting members such as metal wires, printed wiring layers or metal bumps. The first and second modules are collectively sealed by a sealing resin layer formed on the wiring board. | 2013-01-17 |
20130015571 | Semiconductor Package And Method Of Manufacturing The SameAANM CHUN; Jung HwanAACI Chungcheongnam-DoAACO KRAAGP CHUN; Jung Hwan Chungcheongnam-Do KR - A semiconductor package and a method of manufacturing the same. The semiconductor package includes; a printed circuit board (PCB); a first semiconductor chip attached onto the PCB; an interposer that is attached onto the first semiconductor chip to cover a portion of the first semiconductor chip and comprises first connection pad units and second connection pad units that are electrically connected to each other, respectively, on an upper surface opposite to a surface of the interposer facing the first semiconductor chip; a second semiconductor chip attached onto the first semiconductor chip and the interposer as a flip chip type; a plurality of bonding wires that electrically connect the second connection pad units of the interposer to the PCB or the first semiconductor chip to the PCB; and a sealing member formed on the PCB to surround the first semiconductor chip, the second semiconductor chip, the interposer, and the bonding wires. | 2013-01-17 |
20130015572 | ELECTRONIC ASSEMBLY INCLUDING AN EMBEDDED ELECTRONIC COMPONENTAANM Ostmann; AndreasAACI BerlinAACO DEAAGP Ostmann; Andreas Berlin DEAANM Manessis; DionysiosAACI BerlinAACO DEAAGP Manessis; Dionysios Berlin DEAANM Bottcher; LarsAACI BerlinAACO DEAAGP Bottcher; Lars Berlin DEAANM Karaszkiewicz; StefanAACI BerlinAACO DEAAGP Karaszkiewicz; Stefan Berlin DE - An electronic unit is produced including at least one electronic component at least partially embedded in an insulating material. A film assembly is provided with at least one conductive layer and a carrier layer. The conductive layer includes openings in the form of holes for receiving bumps, which are connected to contact surfaces of the at least one electronic component. The at least one component is placed on the film assembly such that the bumps engage with the openings of the conductive layer. The at least one component is partially embedded from the side opposite of the bumps into a dielectric layer. The carrier layer of the film assembly is removed such that the surface of the bumps is exposed. A metallization layer is then deposited on the side of the remaining conductive layer having the exposed bumps and so as to produce conductor tracks that overlap with the bumps. | 2013-01-17 |
20130015573 | BALL GRID ARRAY WITH IMPROVED SINGLE-ENDED AND DIFFERENTIAL SIGNAL PERFORMANCE - An improved system and method for assigning power and ground pins and single ended or differential signal pairs for a ball grid array semiconductor package. In certain embodiments, the system uses a hexagonal pattern where the grid may be represented by a multiplicity of nested hexagonal patterns. | 2013-01-17 |
20130015574 | BUMP I/O CONTACT FOR SEMICONDUCTOR DEVICE - A bump contact electrically connects a conductor on a substrate and a contact pad on a semiconductor device mounted to the substrate. The first end of an electrically conductive pillar effects electrical contact and mechanical attachment of the pillar to the contact pad with the pillar projecting outwardly from the semiconductor device. A solder crown reflowable at a predetermined temperature into effecting electrical contact and mechanical attachment with the conductor is positioned in axial alignment with the second end of the pillar. A diffusion barrier electrically and mechanically joins the solder bump to the second end of the pillar and resists electro-migration into the first end of the solder crown of copper from the pillar. One diffusion barrier takes the form of a 2-20 micron thick control layer of nickel, palladium, titanium-tungsten, nickel-vanadium, or tantalum nitride positioned between the pillar and the solder crown. | 2013-01-17 |
20130015575 | Semiconductor Device with Solder Bump Formed on High Topography Plated Cu Pads - A semiconductor device has a first conductive layer formed over a substrate. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. The second insulating layer has a sidewall between a surface of the second insulating material and surface of the second conductive layer. A protective layer is formed over the second insulating layer and surface of the second conductive layer. The protective layer follows a contour of the surface and sidewall of the second insulating layer and second conductive layer. A bump is formed over the surface of the second conductive layer and a portion of the protective layer adjacent to the second insulating layer. The protective layer protects the second insulating layer. | 2013-01-17 |
20130015576 | Solder Bump with Inner Core Pillar in Semiconductor Package - A flip chip semiconductor package has a substrate with a plurality of active devices. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, second barrier layer, and adhesion layer are formed between the substrate and an intermediate conductive layer. The intermediate conductive layer is in electrical contact with the contact pad. A copper inner core pillar is formed by plating over the intermediate conductive layer. The inner core pillar has a rectangular, cylindrical, toroidal, or hollow cylinder form factor. A solder bump is formed around the inner core pillar by plating solder material and reflowing the solder material to form the solder bump. A first barrier layer and wetting layer are formed between the inner core pillar and solder bump. The solder bump is in electrical contact with the intermediate conductive layer. | 2013-01-17 |
20130015577 | Semiconductor Device and Method of Forming Base Substrate with Cavities Formed through Etch-Resistant Conductive Layer for Bump Locking - A semiconductor device has a base substrate with first and second etch-resistant conductive layers formed over opposing surfaces of the base substrate. First cavities are etched in the base substrate through an opening in the first conductive layer. The first cavities have a width greater than a width of the opening in the first conductive layer. Second cavities are etched in the base substrate between portions of the first or second conductive layer. A semiconductor die is mounted over the base substrate with bumps disposed over the first conductive layer. The bumps are reflowed to electrically connect to the first conductive layer and cause bump material to flow into the first cavities. An encapsulant is deposited over the die and base substrate. A portion of the base substrate is removed down to the second cavities to form electrically isolated base leads between the first and second conductive layers. | 2013-01-17 |
20130015578 | INTERCONNECTION AND ASSEMBLY OF THREE-DIMENSIONAL CHIP PACKAGESAANM Thacker; Hiren D.AACI San DiegoAAST CAAACO USAAGP Thacker; Hiren D. San Diego CA USAANM Cunningham; John E.AACI San DiegoAAST CAAACO USAAGP Cunningham; John E. San Diego CA USAANM Shubin; IvanAACI San DiegoAAST CAAACO USAAGP Shubin; Ivan San Diego CA USAANM Krishnamoorthy; Ashok V.AACI San DiegoAAST CAAACO USAAGP Krishnamoorthy; Ashok V. San Diego CA US - In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are aligned by positive features that are mechanically coupled to negative features recessed below the surfaces of adjacent semiconductor dies. Moreover, the chip package includes an interposer plate at approximately a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the interposer plate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as solder balls or spring connectors. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the interposer plate. | 2013-01-17 |
20130015579 | SOLDER BALL CONTACT SUSCEPTIBLE TO LOWER STRESS - A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball. | 2013-01-17 |
20130015580 | REPLACEMENT METAL GATE STRUCTURE AND METHODS OF MANUFACTUREAANM JAIN; SAMEER HAACI BeaconAAST NYAACO USAAGP JAIN; SAMEER H Beacon NY USAANM Johnson; Jeffrey B.AACI Essex JunctionAAST VTAACO USAAGP Johnson; Jeffrey B. Essex Junction VT USAANM Li; YingAACI NewburghAAST NYAACO USAAGP Li; Ying Newburgh NY USAANM Nayfeh; Hasan M.AACI PoughkeepsieAAST NYAACO USAAGP Nayfeh; Hasan M. Poughkeepsie NY USAANM Ramachandran; RavikumarAACI PleasantvilleAAST NYAACO USAAGP Ramachandran; Ravikumar Pleasantville NY US - A replacement metal gate structure and methods of manufacturing the same is provided. The method includes forming at least one trench structure and forming a liner of high-k dielectric material in the at least one trench structure. The method further includes adjusting a height of the liner of high-k dielectric material. The method further includes forming at least one workfunction metal over the liner, and forming a metal gate structure in the at least one trench structure, over the at least one workfunction metal and the liner of high-k dielectric material. | 2013-01-17 |
20130015581 | STRUCTURE AND METHOD FOR HIGH PERFORMANCE INTERCONNECTAANM Wann; HsingjenAACI CarmelAAST NYAACO USAAGP Wann; Hsingjen Carmel NY USAANM Ko; Ting-ChuAACI HsinchuAACO TWAAGP Ko; Ting-Chu Hsinchu TW - The present disclosure provides an integrated circuit structure. The integrated circuit structure includes a substrate having an IC device formed therein; a first dielectric material layer disposed on the substrate and having a first trench formed therein; and a first composite interconnect feature disposed in the first trench and electrically coupled with the IC device. The first composite interconnect feature includes a first barrier layer disposed on sidewalls of the first trench; a first metal layer disposed on the first barrier layer; and a first graphene layer disposed on the metal layer. | 2013-01-17 |
20130015582 | CIRCUIT BOARD, SEMICONDUCTOR DEVICE, PROCESS FOR MANUFACTURING CIRCUIT BOARD AND PROCESS FOR MANUFACTURING SEMICONDUCTOR DEVICEAANM Kondo; MasayoshiAACI TokyoAACO JPAAGP Kondo; Masayoshi Tokyo JPAANM Makino; NatsukiAACI TokyoAACO JPAAGP Makino; Natsuki Tokyo JPAANM Fujiwara; DaisukeAACI TokyoAACO JPAAGP Fujiwara; Daisuke Tokyo JPAANM Ito; YukaAACI TokyoAACO JPAAGP Ito; Yuka Tokyo JP - A circuit board ( | 2013-01-17 |
20130015583 | Chip Comprising an Integrated Circuit, Fabrication Method and Method for Locally Rendering a Carbonic Layer ConductiveAANM Hoeckele; UweAACI RegensburgAACO DEAAGP Hoeckele; Uwe Regensburg DE - A chip includes an integrated circuit and a carbonic layer. The carbonic layer includes a graphite-like carbon, wherein a lateral conducting path through the graphite-like carbon electrically connects two circuit elements of the integrated circuit. | 2013-01-17 |
20130015584 | OPTOELECTRONIC SEMICONDUCTOR DEVICE - An optoelectronic semiconductor device includes a substrate, a semiconductor system having an active layer formed on the substrate and an electrode structure formed on the semiconductor system, wherein the layout of the electrode structure having at least a first conductivity type contact zone or a first conductivity type bonding pad, a second conductivity type bonding pad, a first conductivity type extension electrode, and a second conductivity type extension electrode wherein the first conductivity type extension electrode and the second conductivity type extension electrode have three-dimensional crossover, and partial of the first conductivity type extension electrode and the first conductivity type contact zone or the first conductivity type bonding pad are on the opposite sides of the active layer. | 2013-01-17 |
20130015585 | STRUCTURES WITH THROUGH VIAS PASSING THROUGH A SUBSTRATE COMPRISING A PLANAR INSULATING LAYER BETWEEN SEMICONDUCTOR LAYERSAANM Kosenko; ValentinAACI Mountain ViewAAST CAAACO USAAGP Kosenko; Valentin Mountain View CA USAANM Savastiouk; SergeyAACI SaratogaAAST CAAACO USAAGP Savastiouk; Sergey Saratoga CA US - A through via contains a conductor ( | 2013-01-17 |
20130015586 | DE-SKEWED MULTI-DIE PACKAGES - A microelectronic package may have a plurality of terminals disposed at a face thereof which are configured for connection to at least one external component. e.g., a circuit panel. First and second microelectronic elements can be affixed with packaging structure therein. A first electrical connection can extend from a respective terminal of the package to a corresponding contact on the first microelectronic element, and a second electrical connection can extend from the respective terminal to a corresponding contact on the second microelectronic element, the first and second connections being configured such that a respective signal carried by the first and second connections in each group is subject to propagation delay of the same duration between the respective terminal and each of the corresponding contacts coupled thereto. | 2013-01-17 |
20130015587 | SEMICONDUCTOR DEVICE AND TEST METHODAANM Okutsu; AkihikoAACI YokohamaAACO JPAAGP Okutsu; Akihiko Yokohama JPAANM Saito; HitoshiAACI HachiojiAACO JPAAGP Saito; Hitoshi Hachioji JPAANM Okano; YoshiakiAACI ItabashiAACO JPAAGP Okano; Yoshiaki Itabashi JP - A semiconductor device includes a semiconductor substrate including an element region, an inner sealing and an outer sealing which are formed on the element region and have a first opening part and a second opening part, respectively, a multilayer interconnection structure which is formed on the substrate and stacks multiple inter-layer insulation films each including a wiring layer, a moisture resistant film formed between a first inter-layer insulation film and a second inter-layer insulation film which are included in the multilayer interconnection structure, a first portion which extended from a first side of the moisture resistant film and passes the first opening part, a second portion which extended from a second side of the moisture resistant film and passes through the second opening part, and a wiring pattern including a via plug which penetrates the moisture resistant film and connects the first portion and the second portion. | 2013-01-17 |
20130015588 | SEMICONDUCTOR DEVICE HAVING THROUGH ELECTRODE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a substrate, and a through electrode passing through the substrate. The semiconductor device has a pad region and a through electrode region. A pad covers the pad region, extends into the through electrode region, and delimits an opening in the through electrode region. A through electrode extends through the semiconductor substrate below the hole in the pad in the through region. | 2013-01-17 |
20130015589 | CHIP-ON-PACKAGE STRUCTURE FOR MULTIPLE DIE STACKSAANM Liao; Chih-ChinAACI Changhua CountyAACO TWAAGP Liao; Chih-Chin Changhua County TWAANM Chiu; Chin-TienAACI Taichung CityAACO TWAAGP Chiu; Chin-Tien Taichung City TWAANM Yu; CheemanAACI FremontAAST CAAACO USAAGP Yu; Cheeman Fremont CA USAANM Upadhyayula; Suresh KumarAACI San JoseAAST CAAACO USAAGP Upadhyayula; Suresh Kumar San Jose CA USAANM Li; Wen ChengAACI Taichung CityAACO TWAAGP Li; Wen Cheng Taichung City TWAANM Lu; ZhongAACI ShanghaiAACO CNAAGP Lu; Zhong Shanghai CN - A multi-die semiconductor device is disclosed. The device may include one or more first-sized die on a substrate and one or more second-sized die affixed over the one or more first-sized die. The second-sized die may have a larger footprint than the first-sized die. An internal molding compound may be provided on the substrate having a footprint the same size as the second-sized die. The second-sized die may be supported on the internal molding compound. Thereafter, the first and second-sized die and the internal molding compound may be encapsulated in an external molding compound. | 2013-01-17 |
20130015590 | MEMORY MODULE IN A PACKAGE - A microelectronic package can include a substrate having first and second opposed surfaces, at least two pairs of microelectronic elements, and a plurality of terminals exposed at the second surface. Each pair of microelectronic elements can include an upper microelectronic element and a lower microelectronic element. The pairs of microelectronic elements can be fully spaced apart from one another in a horizontal direction parallel to the first surface of the substrate. Each lower microelectronic element can have a front surface facing the first surface of the substrate and a plurality of contacts at the front surface. A surface of each of the upper microelectronic elements can at least partially overlie a rear surface of the lower microelectronic element in its pair. The microelectronic package can also include electrical connections extending from at least some of the contacts of each lower microelectronic element to at least some of the terminals. | 2013-01-17 |
20130015591 | MEMORY MODULE IN A PACKAGE - A microelectronic package can include a substrate having first and second opposed surfaces, first, second, third, and fourth microelectronic elements, and a plurality of terminals exposed at the second surface. Each microelectronic element can have a front surface facing the first surface of the substrate and a plurality of contacts at the front surface. The front surfaces of the microelectronic elements can be arranged in a single plane parallel to the first surface. Each microelectronic element can have a column of contacts exposed at the front surface and arranged along respective first, second, third, and fourth axes. The first and third axes can be parallel to one another. The second and fourth axes can be transverse to the first and third axes. The microelectronic package can also include electrical connections extending from at least some of the contacts of each microelectronic element to at least some of the terminals. | 2013-01-17 |
20130015592 | BOND PAD CONFIGURATIONS FOR SEMICONDUCTOR DIES - A semiconductor device is provided and includes a semiconductor die, and a plurality of bond pads having exposed surfaces arranged in an alternating interleaved pattern on the semiconductor die. Each of the surfaces of the bond pads have a first bond placement area that overlaps with a second bond placement area, with the first bond placement area having a major axis that is orthogonal to a major axis of the second bond placement area. A connecting bond is located at an intersection of the major axes of the first bond placement area and the second bond placement area on one or more of the bond pads. | 2013-01-17 |
20130015593 | Integrated Fan Drive System For Cooling Tower - A drive system for driving a fan in a wet cooling tower, wherein the fan has a fan hub and fan blades attached to the fan hub. The drive system has a high-torque, low speed permanent magnet motor having a motor casing, a stator and a rotatable shaft, wherein the rotatable shaft is configured for connection to the fan hub. The drive system includes a variable frequency drive device to generate electrical signals that effect rotation of the rotatable shaft of the motor in order to rotate the fan. | 2013-01-17 |
20130015594 | Splashguard For High Flow Vacuum Bubbler Vessel - The present invention is a container having a diptube inlet, at least one baffle disc positioned between the outlet of the diptube and the outlet of the container to provide a narrow annular space between the baffle disc and the sidewall of the container to prevent liquid droplets from entering the outlet to the container and the inner surface of the container sidewall and an annular, radially inward projecting deflector ledge on the sidewall, proximate the baffle disc. The present invention is also a process of delivering a chemical precursor from a container having the above structure. Liquid and vapor delivery are both contemplated. | 2013-01-17 |
20130015595 | CONTACT LENS - A contact lens formed of a composition comprising the reaction product of: A) at least 10 weight percent, based on the total composition weight excluding solvent, of at least one silicone-containing monomer of the formula I: where n is from 1 to 3, m is from 9 to 15, each a independently is C | 2013-01-17 |
20130015596 | ROBOTIC FABRICATOR - A fabrication system includes a tool-head for manufacturing, a first manipulator and a second manipulator. The first manipulator supports and manipulates an item, and is configured to provide six-axes of movement for positioning of the item relative the tool-head. The second manipulator carries a component and orients the component at a select orientation relative to the item supported on the first manipulator. The tool-head is configured to add material to at least one of the item and the component. The first and second manipulators provide at least six axes of fabrication for the tool-head. | 2013-01-17 |
20130015597 | IMPRINT APPARATUS AND ARTICLE MANUFACTURING METHODAANM Hattori; TadashiAACI Utsunomiya-shiAACO JPAAGP Hattori; Tadashi Utsunomiya-shi JP - An imprint apparatus includes: a first driving mechanism configured to move at least one of a mold holder and a substrate holder such that a mold and an imprint material are contact with each other; a second driving mechanism configured to move at least one of the holders such that the substrate is aligned with the mold; a measurement device configured to measure relative positions between a mold mark and a substrate mark in a state in which the mold and the imprint material are not in contact with each other; and a controller configured to control the second driving mechanism based on information of a relationship between a moving amount of at least one of the holders, and change in relative positions between the marks, information of the moving amount, and information of the measured relative positions. | 2013-01-17 |
20130015598 | IMPRINT APPARATUS AND ARTICLE MANUFACTURING METHODAANM KIMURA; AtsushiAACI Saitama-shiAACO JPAAGP KIMURA; Atsushi Saitama-shi JP - The imprint apparatus of the present invention includes a controller that has a first servo controller configured to servo-control a first drive unit; a second servo controller configured to servo-control a second drive unit; and a correction controller configured to execute calculation processing for calculating a correction value for correcting a force, which is applied to a mold or a substrate when the mold is brought into contact with the substrate via an imprint material, based on a relative position between a mold holding unit and a substrate holding unit in a contact direction and correct at least one of command values to be transmitted to the first or second drive unit by the first or second servo controller based on the correction value. | 2013-01-17 |
20130015599 | IMPRINT APPARATUS, AND METHOD OF MANUFACTURING ARTICLEAANM Kawahara; IzumiAACI Utsunomiya-shiAACO JPAAGP Kawahara; Izumi Utsunomiya-shi JP - The present invention provides an imprint apparatus which performs an imprint process of molding an imprint material on a substrate using a mold to form a pattern on the substrate, the apparatus including a measuring device including an off-axis detection system configured to detect a mark formed with respect to a shot region on the substrate, and configured to measure a position of the mark, and a controller configured to control the imprint process, wherein the controller is configured to control the imprint process so that measurement of the position of the mark by the measuring device, and adjustment of relative positions of the mold and the substrate based on the measurement are performed with respect to each of a plurality of shot regions on the substrate. | 2013-01-17 |
20130015600 | APPARATUS FOR PRODUCING POROUS BODY AND METHOD FOR PRODUCING POROUS BODY - An apparatus for producing a porous body that forms an expandable slurry containing at least inorganic powder, a foaming agent, and a binder into a sheet, causes the expandable slurry sheet to be foamed and baked, and thereby produces the porous body, the apparatus includes: a mixer preparing the expandable slurry by containing inorganic powder, a foaming agent, and a binder; a die-coater that has a discharge opening which discharges the expandable slurry provided from the mixer to an external thereof so as to shape the expandable slurry into a sheet; and a carrier sheet arranged so as to face the discharge opening of the die-coater with a gap interposed therebetween, and feeding the expandable slurry discharged from the discharge opening, wherein a flow path of the expandable slurry from inside the mixer to the discharge opening of the die-coater is hermetically sealed from an outside. | 2013-01-17 |
20130015601 | BLOCK FORMING APPARATUS AND METHODAANM Garrett; RobertAACI CalgaryAACO CAAAGP Garrett; Robert Calgary CAAANM Garrett; ArthurAACI CalgaryAACO CAAAGP Garrett; Arthur Calgary CA - A mold and method for making a hollow core concrete block. The mold has two opposing side walls; a bottom wall; a front wall; a top side with an opening through which the block can be removed from the mold; a cover, and a rear side through which liquid, such as concrete, can be poured into the mold. Extending from the two side walls are a pair of trunnions about which the mold is rotatable, such that when the mold is suspended by the trunnions and the mold is empty, gravity rotates the mold from a block-removal orientation in which the top side faces upwards to a mold-filling orientation in which the rear side faces upwards. The trunnions are also positioned such that when the mold is filled with the liquid, gravity rotates the mold from the mold-filling orientation to the block-removal orientation. | 2013-01-17 |
20130015602 | PROCESS FOR THE PRODUCTION OF A DOUBLE-CURVED PANELAANM BERNADET; PhilippeAACI ColomiersAACO FRAAGP BERNADET; Philippe Colomiers FRAANM GIUSEPPIN; LaurentAACI FinhanAACO FRAAGP GIUSEPPIN; Laurent Finhan FR - A process for the production of an aircraft panel made of double-curved composite material, with the panel being obtained from a three-dimensional preform that includes fibers that are distributed in a defined arrangement, includes manufacturing a flat fiber preform ( | 2013-01-17 |
20130015603 | PRODUCTION OF AND DRYING OF COPOLYMER FIBERS - The present invention concerns processes for reducing water in never-dried fiber comprising copolymer derived from the copolymerization of para-phenylenediamine, 5(6)-amino-2-(p-aminophenyl)benzimidazole; and terephthaloyl dichloride, the process comprising the steps of: (a) heating the never-dried fiber to a temperature of at least 20° C. but less than 100° C. until the moisture content of the fiber is 20 weight percent or less of the fiber; and (b) further heating the fiber to a temperature of at least 350° C. | 2013-01-17 |
20130015604 | Process of Producing PCR Pellets - A process for producing, from PCR polyolefin feedstock, pellets which are suitable for molding into useful articles suitable for food contact and other applications wherein feedstock fragrances are not desirable. | 2013-01-17 |
20130015605 | Method for the Production of Bodies in Plastic Material Comprising at Least Two Portions Hinged to Each Other by a Single Rotation PinAANM Sgaravatto; RobertoAACI ArzergrandeAACO ITAAGP Sgaravatto; Roberto Arzergrande ITAANM Chiarin; UlisseAACI ArzergrandeAACO ITAAGP Chiarin; Ulisse Arzergrande IT - The present invention relates to a method for the production of bodies in plastic comprising two portions hinged to each other by a single rotation pin. The method comprises the steps: a) predisposing a mould with two distinct forming chambers for the two portions; the mould comprises a third chamber for the single pin, made and positioned in such a way that the pin is formed already aligned along the hinge axis; the mould is provided with a pair of pegs axially distanced from each other to form the third chamber and sliding along the axis between a first and a second operating position; b) positioning the pegs in the first position; c) injecting plastic material inside the chambers; d) shifting the pegs from the first to the second position, bringing the pin to engage inside the seats; e) opening the mould and extracting the two assembled portions. | 2013-01-17 |
20130015606 | PLASTICS INJECTION MOULDING TOOL AND METHOD FOR PLASTICS INJECTION MOULDINGAANM Hackmann; BerndAACI LohneAACO DEAAGP Hackmann; Bernd Lohne DE - The invention relates, in first instance, to a plastics injection moulding tool having a hot runner nozzle ( | 2013-01-17 |