03rd week of 2012 patent applcation highlights part 14 |
Patent application number | Title | Published |
20120012931 | SOI MOS DEVICE HAVING BTS STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention discloses a SOI MOS device having BTS structure and manufacturing method thereof. The source region of the SOI MOS device comprises: two heavily doped N-type regions, a heavily doped P-type region formed between the two heavily doped N-type regions, a silicide formed above the heavily doped N-type regions and the heavily doped P-type region, and a shallow N-type region which is contact to the silicide; an ohmic contact is formed between the heavily doped P-type region and the silicide thereon to release the holes accumulated in body region of the SOI MOS device and eliminate floating body effects thereof without increasing the chip area and also overcome the disadvantages such as decreased effective channel width of the devices in the BTS structure of the prior art. The manufacturing method comprises steps of: forming a heavily doped P-type region via ion implantation, forming a metal layer above the source region and forming a silicide via the heat treatment between the metal layer and the Si underneath. The device in the present invention could be fabricated via simplified fabricating process with great compatibility with traditional CMOS technology. | 2012-01-19 |
20120012932 | FIN-LIKE FIELD EFFECT TRANSISTOR (FINFET) DEVICE AND METHOD OF MANUFACTURING SAME - A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a semiconductor substrate; a fin structure disposed over the semiconductor substrate; and a gate structure disposed on a portion of the fin structure. The gate structure traverses the fin structure and separates a source region and a drain region of the fin structure, the source and drain region defining a channel therebetween. The source and drain region of the fin structure include a strained source and drain feature. The strained source feature and the strained drain feature each include: a first portion having a first width and a first depth; and a second portion disposed below the first portion, the second portion having a second width and a second depth. The first width is greater than the second width, and the first depth is less than the second depth. | 2012-01-19 |
20120012933 | FORMATION METHOD AND STRUCTURE FOR A WELL-CONTROLLED METALLIC SOURCE/DRAIN SEMICONDUCTOR DEVICE - A device and method for forming a semiconductor device include growing a raised semiconductor region on a channel layer adjacent to a gate structure. A space is formed between the raised semiconductor region and the gate structure. A metal layer is deposited on at least the raised semiconductor region. The raised semiconductor region is silicided to form a silicide into the channel layer which extends deeper into the channel layer at a position corresponding to the space. | 2012-01-19 |
20120012934 | NONPLANAR DEVICE WITH THINNED LOWER BODY PORTION AND METHOD OF FABRICATION - A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode. | 2012-01-19 |
20120012935 | Semiconductor device and method of manufacturing semiconductor device - The disclosure concerns a method of manufacturing a semiconductor device including forming a plurality of fins made of a semiconductor material on an insulating layer; forming a gate insulating film on side surfaces of the plurality of fins; and forming a gate electrode on the gate insulating film in such a manner that a compressive stress is applied to a side surface of a first fin which is used in an NMOSFET among the plurality of fins in a direction perpendicular to the side surface and a tensile stress is applied to a side surface of a second fin which is used in a PMOSFET among the plurality of fins in a direction perpendicular to the side surface. | 2012-01-19 |
20120012936 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device including a semiconductor substrate having a logic formation region where a logic device is formed; a first impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a second impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a third impurity region formed in an upper surface of the first impurity region and having a conductivity type different from that of the second impurity region; a fourth region formed in an upper surface of the second impurity region and having a conductivity type different from that of the second impurity region; a first silicide film formed in an upper surface of the third impurity region; a second silicide film formed in an upper surface of the fourth impurity region and having a larger thickness than the first silicide film. | 2012-01-19 |
20120012937 | INTERCONNECTION STRUCTURE FOR N/P METAL GATES - The disclosure relates to integrated circuit fabrication, and more particularly to an interconnection structure for N/P metal gates. An exemplary structure for an interconnection structure comprises a first gate electrode having a first portion of a first work-function metal layer under a first portion of a signal metal layer; and a second gate electrode having a second portion of the first work-function metal layer interposed between a second work-function metal layer and a second portion of the signal metal layer, wherein the second portion of the signal metal layer is over the second portion of the first work-function metal layer, wherein the second portion of the signal metal layer and the first portion of the signal metal layer are continuous, and wherein a maximum thickness of the second portion of the signal metal layer is less than a maximum thickness of the first portion of the signal metal layer. | 2012-01-19 |
20120012938 | METHOD OF MANUFACTURING COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE - A method of manufacturing a CMOS device includes providing a substrate having a first region and a second region; forming a first gate structure and a second gate structure, each of the gate structures comprising a sacrificial layer and a hard mask layer; forming a patterned first protecting layer covering the first region and a first spacer on sidewalls of the second gate structure; performing an etching process to form first recesses in the substrate; performing a SEG process to form epitaxial silicon layers in each first recess; forming a patterned second protecting layer covering the second region; and performing a dry etching process with the patterned second protecting layer serving as an etching mask to etch back the patterned first protecting layer to form a second spacer on sidewalls of the first gate structure and to thin down the hard mask layer on the first gate structure. | 2012-01-19 |
20120012939 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention provides a semiconductor device, comprising: a semiconductor substrate having a first region and a second region; a first gate structure belong to a PMOS device on the first region; a second gate structure belong to an nMOS device on the second region; a multiple-layer first sidewall spacer on sidewalls of the first gate structure, wherein a layer of the multiple-layer first sidewall spacer adjacent to the first gat structure is an oxide layer; a multiple-layer second sidewall spacer on sidewalls of the second gate structure, wherein a layer of the multiple layers of second sidewall spacer adjacent to the first gat structure is a nitride layer. Application of the present invention may alleviate the oxygen vacancy in a high-k gate dielectric in a pMOS device, and further avoid the problem of EOT growth of an nMOS device during the high-temperature thermal treatment process, and therefore effectively improve the overall performance of the high-k gate dielectric CMOS device. | 2012-01-19 |
20120012940 | INTEGRATED CIRCUIT AND METHOD OF FABRICATION THEREOF - A method of forming an integrated circuit structure comprising the steps of forming a first and second device region on a surface of a wafer, forming a spacer of a first width on a sidewall of a first gate stack in the first device region, forming a spacer of a second width on a sidewall of a second gate stack in the second device region, with the first width being different from the second width. | 2012-01-19 |
20120012941 | FORMATION OF METAL GATE ELECTRODE USING RARE EARTH ALLOY INCORPORATED INTO MID GAP METAL - Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. A rare earth-rare earth alloy incorporated metal nitride layer is formed above a gate dielectric. This process provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting NMOS transistors. | 2012-01-19 |
20120012942 | SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - Provided are a semiconductor device and a method of forming the same. The method may include forming a gate dielectric layer including a plurality of elements on a substrate; supplying a specific element to the gate dielectric layer; forming a product though reacting the specific element with at least one of the plurality of elements; and removing the product. | 2012-01-19 |
20120012943 | ANTI-FUSE OF SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention provides an anti-fuse of a semiconductor device and a method of manufacturing the same, which has a stable current level and a stable operation. According to the present invention, in order for the anti-fuse to be stably operated, a region in which a gate and an active region partially overlap with each other is formed, and the overlapped region is destroyed when voltage is supplied. Accordingly, a current level can be stabilized, and stable operation is possible. | 2012-01-19 |
20120012944 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a memory block including a transistor region and a memory region. A variable resistance layer of the memory region acts as a gate insulating layer in the transistor region. | 2012-01-19 |
20120012945 | SEMICONDUCTOR DEVICE - A semiconductor device includes source electrodes having source fingers, drain electrodes having drain fingers, and gate electrodes having bent portions between steps formed in stepwise side portions of source fingers and steps formed in stepwise side portions of drain fingers and being bent in the bent portions along the source fingers and the drain fingers. A shape of the stepwise side portion of one source finger and that of the stepwise portion of the corresponding drain finger are symmetrical about a midpoint of an imaginary line that connects the other end of the source finger and the other end of the corresponding drain finger. | 2012-01-19 |
20120012946 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A device isolation region is made of a silicon oxide film embedded in a trench, an upper portion thereof is protruded from a semiconductor substrate, and a sidewall insulating film made of silicon nitride or silicon oxynitride is formed on a sidewall of a portion of the device isolation region which is protruded from the semiconductor substrate. A gate insulating film of a MISFET is made of an Hf-containing insulating film containing hafnium, oxygen and an element for threshold reduction as main components, and a gate electrode that is a metal gate electrode extends on an active region, the sidewall insulating film and the device isolation region. The element for threshold reduction is a rare earth or Mg when the MISFET is an n-channel MISFET, and the element for threshold reduction is Al, Ti or Ta when the MISFET is a p-channel MISFET. | 2012-01-19 |
20120012947 | SEMICONDUCTOR DEVICE - A semiconductor device includes a gate pad, a gate wiring conductor connected to the gate pad, and a gate electrode formed under the gate pad and the gate wiring conductor. Portions of the gate electrode closer to the gate pad have a higher resistance per unit area than portions of the gate electrode farther away from the gate pad. | 2012-01-19 |
20120012948 | METAL GATE SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, a source and a drain region formed on the semiconductor substrate, and a gate structure disposed on the substrate between the source and drain regions. The gate structure includes an interfacial layer formed over the substrate, a high-k dielectric formed over the interfacial layer, and a metal gate formed over the high-k dielectric that includes a first metal layer and a second metal layer, where the first metal layer is formed on a portion of the sidewalls of the gate structure and where the second metal layer is formed on another portion of the sidewalls of the gate structure. | 2012-01-19 |
20120012949 | PRESSURE SENSOR PACKAGE SYSTEMS AND METHODS - Embodiments relate to integrated circuit (IC) sensors and sensing systems and methods. In an embodiment, an IC sensor device includes at least one sensing element; a framing element disposed around the at least one sensing element at a wafer-level; and a package having at least one port predefined at the wafer-level by the framing element, the at least one port configured to expose at least a portion of the at least one sensing element to an ambient environment. | 2012-01-19 |
20120012950 | FUNCTIONAL DEVICE AND MANUFACTURING METHOD THEREOF - A functional device includes: a substrate; a functional structure formed on the substrate; a cavity in which the functional structure is disposed; and a cover which covers the cavity, wherein the cover includes a bumpy structure including rib shaped portions, or groove shaped portions, which cross a covering range covering at least the cavity. | 2012-01-19 |
20120012951 | PACKAGE FOR VACUUM ENCAPSULATION OF AN ASSOCIATED MICROELECTROMECHANICAL SYSTEM, AND A METHOD FOR DETECTING A PROBLEM WITH A SOLDER JOINT IN SUCH AN ASSEMBLY - Package (BT) for vacuum encapsulation of a microelectromechanical system (MEMS) provided with an electrically conductive element intended to be soldered to said package (BT), said package (BT) comprising a metallized base (FM), designed to be soldered to said microelectromechanical system (MEMS), and output electrical contacts (CES), electrically connected to electrical-contact elements of said microelectromechanical system. Said metallized base (FM) comprises a plurality of metallized surface portions (PSM), respectively bounded by an unmetallized solder stop region, and respectively connected to the rest of the metallized base (FM) by a metallized track (PTEM), having a small width relative to the corresponding width of said portion (PSM), said metallized surface portions (PSM) being designed to be soldered to said microelectromechanical system (MEMS). | 2012-01-19 |
20120012952 | Magnetic Storage Element Utilizing Improved Pinned Layer Stack - A magnetic tunnel junction (MTJ) storage element may comprise a pinned layer stack and a first functional layer. The pinned layer stack is formed of a plurality of layers comprising a bottom pinned layer, a coupling layer, and a top pinned layer. The first functional layer is disposed in the bottom pinned layer or the top pinned layer. | 2012-01-19 |
20120012953 | METHOD AND SYSTEM FOR PROVIDING MAGNETIC TUNNELING JUNCTION ELEMENTS HAVING LAMINATED FREE LAYERS AND MEMORIES USING SUCH MAGNETIC ELEMENTS - A method and system for providing a magnetic substructure usable in a magnetic device, as well as a magnetic element and memory using the substructure are described. The magnetic substructure includes a plurality of ferromagnetic layers and a plurality of nonmagnetic layers. The plurality of ferromagnetic layers are interleaved with the plurality of nonmagnetic layers. The plurality of ferromagnetic layers are immiscible with and chemically stable with respect to the plurality of nonmagnetic layers. The plurality of ferromagnetic layers are substantially free of a magnetically dead layer-producing interaction with the plurality of nonmagnetic layers. Further, the plurality of nonmagnetic layers induce a perpendicular anisotropy in the plurality of ferromagnetic layers. The magnetic substructure is configured to be switchable between a plurality of stable magnetic states when a write current is passed through the magnetic substructure. | 2012-01-19 |
20120012954 | MAGNETIC MEMORY ELEMENT AND STORAGE DEVICE USING THE SAME - An object of the invention is to ensure the thermal stability of magnetization even when a magnetic memory element is miniaturized. A magnetic memory element includes a first magnetic layer ( | 2012-01-19 |
20120012955 | MAGNETIC MEMORY - Provided is a magnetic random access memory to which spin torque magnetization reversal is applied, the magnetic random access memory being thermal stable in a reading operation and also being capable of reducing a current in a wiring operation. A magnetoresistive effect element formed by sequentially stacking a fixed layer, a nonmagnetic barrier layer, and a recording layer is used as a memory element. The recording layer adopts a laminated ferrimagnetic structure. The magnetic memory satisfies the expression M | 2012-01-19 |
20120012956 | MAGNETIC SENSOR AND MAGNETIC MEMORY - The invention relates to a magnetic sensor and a magnetic memory which sense magnetic information held by a ferromagnetic body without a current flowing through the ferromagnetic body. The magnetic sensor and magnetic memory use a magnetoresistive effect generated in a current that flows through a metal layer along an interface, on at least the interface side, with a ferromagnetic dielectric layer and said metal layer being joined through said interface. | 2012-01-19 |
20120012957 | NEUTRON DETECTOR WITH WAFER-TO-WAFER BONDING - A method of manufacturing a neutron detector comprises forming a first wafer by at least forming an oxide layer on a substrate, forming an active semiconductor layer on the oxide layer, and forming an interconnect layer on the active semiconductor layer, forming at least one electrically conductive pathway extending from the interconnect layer through the active semiconductor layer and the oxide layer, forming a circuit transfer bond between the interconnect layer and a second wafer, removing the substrate of the first wafer after forming the circuit transfer bond, depositing a bond pad on the oxide layer after removing the substrate of the first wafer, wherein the bond pad is electrically connected to the electrically conductive pathway, depositing a barrier layer on the oxide layer after removing the substrate of the first wafer, and depositing a neutron conversion layer on the barrier layer after depositing the barrier layer. | 2012-01-19 |
20120012958 | CHARGED PARTICLE COLLECTOR FOR A CMOS IMAGER - Charged particle sensing devices and methods of forming charged particle sensing devices are provided. The charged particle sensing device includes a source of charged particles, a plurality of collector electrodes for receiving a first portion of the charged particles and a grid formed around and spaced apart from the plurality of collector electrodes. The grid receives a second portion of the charged particles and directs backscattered charged particles, generated responsive to the second portion, to adjacent collector electrodes. | 2012-01-19 |
20120012959 | IMAGE SENSORS AND FABRICATION METHOD THEREOF - An image sensor is provided. The image sensor includes a pixel sensor, a color filter array comprising a plurality of color filters formed on the pixel sensor, wherein two adjacent color filters have a gap therebetween, and a gapless microlens array comprising a plurality of microlenses formed on the color filter array. The invention also provides a method for fabricating the image sensor. | 2012-01-19 |
20120012960 | METHOD AND SYSTEM OF EMBEDDED MICROLENS - A method of making an embedded microlens includes providing a substrate having a photo-sensing region, forming a dielectric film overlying the substrate, forming a mask having a circular opening over the dielectric film, the opening being center-aligned over the photo-sensing region, and etching the dielectric film to form a cavity under the mask by introducing an isotropic etchant through the opening, the cavity being characterized by a truncated plano-convex shape having a flat circular bottom and curved peripheral sides convex towards the dielectric film. The method further includes removing the mask, depositing a lens material with a higher refractive index than that of the dielectric film to fill the cavity, planarizing the lens material to form the embedded microlens in the cavity having a smooth top surface, and forming a color filter layer overlying the microlens. The dielectric film includes silicon dioxide having a refractive index of 1.5 or less. | 2012-01-19 |
20120012961 | SOLID-STATE IMAGING DEVICE AND METHOD OF MANUFACTURING OF SAME - A solid-state imaging device ( | 2012-01-19 |
20120012962 | ELECTRONIC DEVICE AND METHOD OF FABRICATING THE SAME - An electronic device and a method of fabricating the same are provided. The electronic device includes: a photodiode layer; a wiring layer formed on the first surface of the photodiode layer; a plurality of electrical contact pads formed on the wiring layer; a passivation layer formed on the wiring layer and the electrical contact pads; an antireflective layer formed on the second surface of the photodiode layer; a color filter layer formed on the antireflective layer; a dielectric layer formed on the antireflective layer and the color filter layer; and a microlens layer formed on the dielectric layer, allowing the color filter layer, the dielectric layer and the microlens layer to define an active region within which the electrical contact pads are positioned. As the electrical contact pads are positioned within the active region, an area of the substrate used for an inactive region can be eliminated. | 2012-01-19 |
20120012963 | MICRO DEVICE PACKAGING - In one embodiment, a method for making an optical micro device package includes: providing a substrate wafer having a plurality of solid state light sensors integrate therein; providing a transparent cover wafer coated with a material that alters the transparency characteristics of the cover wafer; forming a layer of light sensitive, photo definable adhesive material on the substrate wafer; selectively removing part of the layer of adhesive material in a pattern for a plurality of adhesive spacers between the substrate wafer and the cover wafer with each spacer surrounding a corresponding one of the light sensors; bonding the substrate wafer and the cover wafer together at the spacers to form a wafer assembly in which each spacer surrounds and seals a corresponding one of the light sensors within a cavity bounded by a spacer and the two wafers; and singulating individual device packages from the wafer assembly. | 2012-01-19 |
20120012964 | IMAGE SENSOR AND MANUFACTURING METHOD THEREOF - An image sensor includes: a photoelectric conversion pixel having a photoelectric conversion element that performs photoelectric conversion, and a light guide formed of a first material in an interlayer insulation film above the photoelectric conversion element; and a light-shielded pixel having a photoelectric conversion element that performs photoelectric conversion, a light guide formed of a second material that is different from the first material in an interlayer insulation film above the photoelectric conversion element, and a light-shielding layer formed above the light guide. | 2012-01-19 |
20120012965 | BACKSIDE ILLUMINATION SOLID-STATE IMAGING DEVICE - According to one embodiment, a backside illumination solid-state imaging device includes a semiconductor layer, a first light-receiving unit and a second light-receiving unit, a circuit unit, an impurity isolation layer, and a light-shielding film. A first light-receiving unit and a second light-receiving unit are formed adjacent to each other in the semiconductor layer, convert light applied from a lower surface side of the semiconductor layer into a signal, and store electric charges. A circuit unit is formed on an upper surface of the semiconductor layer. An impurity isolation layer is formed to reach to the upper surface from the lower surface in the semiconductor layer and isolates the first light-receiving unit from the second light-receiving unit. A light-shielding film is formed on part of the lower surface side in the impurity isolation layer so as to extend from the lower surface to the upper surface. | 2012-01-19 |
20120012966 | MULTI-CAVITY OPTICAL SENSING AND THERMOPILE INFRARED SENSING SYSTEM - The present invention discloses a multi-cavity optical sensing and thermopile infrared sensing system, which comprises an optical sensing part, a dielectric layer, a plurality of optical cavities, and a plurality of thermocouples. The dielectric layer covers on the top of the optical sensing part. The optical cavities are formed by a plurality of metal reflectors inside the dielectric layer. The thermocouples are laterally disposed near the bottom of the dielectric layer. In addition, a low temperature region is formed in an area which is the overlapping of vertical projections of such thermocouples and the optical sensing part; a high temperature region is formed by the overlapping of vertical projections of such thermocouples, but without the overlaying which belongs to the vertical projection of the optical sensing part. Therefore, the system can sense the ambient light brightness, color conditions and human blackbody infrared signals within the range of 8-12 micrometers wavelength. | 2012-01-19 |
20120012967 | Black silicon based metal-semiconductor-metal photodetector - A black silicon based metal-semiconductor-metal photodetector includes a silicon substrate and a black silicon layer formed on the silicon substrate. An interdigitated electrode pattern structure is formed on the black silicon layer, which can be a planar or U-shaped structure. A thin potential barrier layer is deposited at the interdigitated electrode pattern structure. An Al or transparent conductive ITO thin film is deposited on the thin potential barrier layer. A passivation layer is provided on the black silicon layer. In the black silicon based metal-semiconductor-metal photodetector, the black silicon layer, as a light-sensitive area, can respond to ultraviolet, visible and near infrared light. | 2012-01-19 |
20120012968 | SCHOTTKY DEVICE - A device according to the invention comprises a Schottky barrier formed by a metal-semiconductor junction between a semiconductor nanowire ( | 2012-01-19 |
20120012969 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a method of forming a wiring structure for a semiconductor device, an insulation layer is formed on a semiconductor substrate on which a plurality of conductive structures is positioned. An upper surface of the insulation layer is planarized and spaces between the conductive structures are filled with the insulation layer. The insulation layer is partially removed from the substrate to form at least one opening through which the substrate is partially exposed. A residual metal layer is formed on a bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer is formed on the residual metal layer and an upper sidewall of the opening with a metal material. Accordingly, an upper portion of the barrier layer can be prevented from being removed in a planarization process for forming the metal plug. | 2012-01-19 |
20120012970 | CAPACITOR DEVICE USING AN ISOLATED WELL AND METHOD THEREFOR - A semiconductor device includes an isolated p-type well, wherein the isolated p-type well is a first electrode of a capacitor device; a capacitor dielectric on the isolated p-type well; a p-type polysilicon electrode over the capacitor dielectric, wherein the p-type polysilicon electrode is a second electrode of the capacitor device; a first p-type contact region in the isolated p-type well, laterally extending from a first sidewall of the p-type polysilicon electrode; a second p-type contact region in the isolated p-type well, laterally extending from a second sidewall of the p-type polysilicon electrode, opposite the first sidewall of the p-type polysilicon electrode, wherein a portion of the isolated p-type well between the first and second p-type contact regions is under the p-type polysilicon electrode and the capacitor dielectric; and an n-type isolation region surrounding the isolated p-type well. This device may be conveniently coupled to a fringe capacitor. | 2012-01-19 |
20120012971 | Method of Fabricating Isolated Capacitors and Structure Thereof - A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors. | 2012-01-19 |
20120012972 | SINGLE-CRYSTAL SILICON SUBSTRATE, SOI SUBSTRATE, SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device of the present invention is arranged in such a manner that a MOS non-single-crystal silicon thin-film transistor including a non-single-crystal silicon thin film made of polycrystalline silicon, a MOS single-crystal silicon thin-film transistor including a single-crystal silicon thin film, and a metal wiring are provided on an insulating substrate. With this arrangement, (i) a semiconductor device in which a non-single-crystal silicon thin film and a single-crystal silicon thin-film device are formed and high-performance systems are integrated, (ii) a method of manufacturing the semiconductor device, and (iii) a single-crystal silicon substrate for forming the single-crystal silicon thin-film device of the semiconductor device are obtained. | 2012-01-19 |
20120012973 | LATERAL TRANSIENT VOLTAGE SUPPRESSOR WITH ULTRA LOW CAPACITANCE - A lateral transient voltage suppressor with ultra low capacitance is disclosed. The suppressor comprises a first type substrate and at least one diode cascade structure arranged in the first type substrate. The cascade structure further comprises at least one second type lightly doped well and at least one first type lightly doped well, wherein there are two heavily doped areas arranged in the second type lightly doped well and the first type lightly doped well. The cascade structure neighbors a second type well, wherein there are three heavily doped areas arranged in the second type well. The suppressor further comprises a plurality of deep isolation trenches arranged in the first type substrate and having a depth greater than depths of the second type lightly doped well, the second type well and the first type lightly doped well. Each doped well is isolated by trenches. | 2012-01-19 |
20120012974 | LATERAL TRANSIENT VOLTAGE SUPPRESSOR FOR LOW-VOLTAGE APPLICATIONS - A lateral transient voltage suppressor for low-voltage applications is disclosed. The suppressor comprises an N-type heavily doped substrate and at least two clamp diode structures horizontally arranged in the N-type heavily doped substrate. Each clamp diode structure further comprises a clamp well arranged in the N-type heavily doped substrate and having a first heavily doped area and a second heavily doped area. The first and second heavily doped areas respectively belong to opposite types. There is a plurality of deep isolation trenches arranged in the N-type heavily doped substrate and having a depth greater than depth of the clamp well. The deep isolation trenches can separate each clamp well. The present invention avoids the huge leakage current to be suitable for low-voltage application. | 2012-01-19 |
20120012975 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes a semiconductor substrate including a digital circuit area and an analog circuit area that is divided into an active element area disposed away from the digital circuit area and a passive element area disposed adjacent to the digital circuit area; a first well having a first conductivity type that is different from a second conductivity type of the semiconductor substrate and formed in a part of the semiconductor substrate corresponding to the passive element area; a second well having the second conductivity type and formed in the first well; a device isolation film formed on the second well; a digital circuit formed in the digital circuit area; an active element implemented by an analog circuit and formed in the active element area; and a passive element implemented by an analog circuit and formed on the device isolation film in the passive element area. | 2012-01-19 |
20120012976 | FUSE STRUCTURE HAVING CRACK STOP VOID, METHOD FOR FORMING AND PROGRAMMING SAME, AND DESIGN STRUCTURE - The disclosure relates generally to fuse structures, methods of forming and programming the same, and more particularly to fuse structures having crack stop voids. The fuse structure includes a semiconductor substrate having a dielectric layer thereon and a crack stop void. The dielectric layer includes at least one fuse therein and the crack stop void is adjacent to two opposite sides of the fuse, and extends lower than a bottom surface and above a top surface of the fuse. The disclosure also relates to a design structure of the aforementioned. | 2012-01-19 |
20120012977 | SECURE ANTI-FUSE WITH LOW VOLTAGE PROGRAMMING THROUGH LOCALIZED DIFFUSION HEATING - An antifuse is provided having a unitary monocrystalline semiconductor body including first and second semiconductor regions each having the same first conductivity type, and a third semiconductor region between the first and second semiconductor regions which has a second conductivity type opposite from the first conductivity type. An anode and a cathode can be electrically connected with the first semiconductor region. A conductive region including a metal, a conductive compound of a metal or an alloy of a metal can contact the first semiconductor region and extend between the cathode and the anode. The antifuse can further include a contact electrically connected with the second semiconductor region. In this way, the antifuse can be configured such that the application of a programming voltage between the anode and the cathode heats the first semiconductor region sufficiently to reach a temperature which drives a dopant outwardly therefrom, causing an edge of the first semiconductor region to move closer to an adjacent edge of the second semiconductor region, thus permanently reducing electrical resistance between the first and second semiconductor regions by one or more orders of magnitude. | 2012-01-19 |
20120012978 | SEMICONDUCTOR DEVICE - A semiconductor device formed by using semiconductor packages is provided. The semiconductor device includes two semiconductor packages adjacently arranged in opposite directions on an inductive conductor. Terminals of the two semiconductor packages are joined by a third lead. the third lead is arranged substantially in parallel to the inductive conductor. Leads at the joint portions have, for example, a bent structure, and the third lead is arranged to be close to the inductive conductor. | 2012-01-19 |
20120012979 | SEMICONDUCTOR CAPACITOR - An improved semiconductor capacitor and method of fabrication is disclosed. A nitride stack, comprising alternating sublayers of slow-etch and fast-etch nitride is deposited on a substrate. The nitride stack is etched via an anisotropic etch technique such as reactive ion etch. A wet etch then etches the nitride stack, forming a corrugated shape. The corrugated shape increases surface area, and hence increases the capacitance of the capacitor. | 2012-01-19 |
20120012980 | SEMICONDUCTOR CAPACITOR - A semiconductor capacitor and its method of fabrication are disclosed. A non-linear nitride layer is used to increase the surface area of a capacitor plate, resulting in increased capacitance without increase in chip area used for the capacitor. | 2012-01-19 |
20120012981 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention provides technology directed to a semiconductor device and a method of manufacturing the same. According to the present invention, metal contact plugs are formed to come into contact with both sidewalls of a capacitor, including lower electrodes, dielectric layers, and an upper electrode. Accordingly, contact resistance can be reduced because the contact area of the upper electrode and the metal contact plugs forming the capacitor, can be increased. Furthermore, the number of chips per wafer can be increased because the area in which the metal contact plugs and the capacitor are formed can be reduced. In addition, the generation of noise can be reduced because the contact area of the capacitor and the metal contact plugs is increased and thus voltage at the upper electrode is stabilized. | 2012-01-19 |
20120012982 | CAPACITORS AND METHODS OF FORMING - Capacitors and methods of forming semiconductor device capacitors are disclosed. Trenches are formed to define a capacitor bottom plate in a doped upper region of a semiconductor substrate, a dielectric layer is formed conformally over the substrate within the trenches, and a polysilicon layer is formed over the dielectric layer to define a capacitor top plate. A guard ring region of opposite conductivity and peripheral recessed areas may be added to avoid electric field crowding. A central substrate of lower doping concentration may be provided to provide a resistor in series below the capacitor bottom plate. A series resistor may also be provided in a resistivity region of the polysilicon layer laterally extending from the trenched area region. Contact for the capacitor bottom plate may be made through a contact layer formed on a bottom of the substrate. A top contact may be formed laterally spaced from the trenched area by patterning laterally extended portions of one or more of the dielectric, polysilicon and top metal contact layers. | 2012-01-19 |
20120012983 | SILICON WAFER AND METHOD OF MANUFACTURING SAME - This method of manufacturing a silicon wafer has a step of preparing a wafer, in which a surface of the silicon wafer is surface-treated, a step of setting stress, in which the stress S (MPa) subjected on the wafer is set, a step of inspecting, in which a defect on a surface of the wafer is inspected, and a step of determining, in which the wafer is evaluated if the wafer satisfies a criterion. In this method, it is possible to manufacture a wafer with cracking resistance even if it is subjected to a millisecond annealing by the FLA annealing treatment. | 2012-01-19 |
20120012984 | METHOD FOR GROWING GROUP 13 NITRIDE CRYSTAL AND GROUP 13 NITRIDE CRYSTAL - To grow a gallium nitride crystal, a seed-crystal substrate is first immersed in a melt mixture containing gallium and sodium. Then, a gallium nitride crystal is grown on the seed-crystal substrate under heating the melt mixture in a pressurized atmosphere containing nitrogen gas and not containing oxygen. At this time, the gallium nitride crystal is grown on the seed-crystal substrate under a first stirring condition of stirring the melt mixture, the first stirring condition being set for providing a rough growth surface, and the gallium nitride crystal is subsequently grown on the seed-crystal substrate under a second stirring condition of stirring the melt mixture, the second stirring condition being set for providing a smooth growth surface. | 2012-01-19 |
20120012985 | Substrate Stand-Offs for Semiconductor Devices - Substrate stand-offs for use with semiconductor devices are provided. Active pillars and dummy pillars are formed on a first substrate such that the dummy pillars may have a height greater than a height of the active pillars. The dummy pillars act as stand-offs when joining the first substrate to a second substrate, thereby creating greater uniformity. In an embodiment, the dummy pillars may be formed simultaneously as the active pillars by forming a patterned mask having openings with a smaller width for the dummy pillars than for the active pillars. When an electro-plating process of the like is used to form the dummy and active pillars, the smaller width of the dummy pillar openings in the patterned mask causes the dummy pillars to have a greater height than the active pillars. | 2012-01-19 |
20120012986 | METHOD FOR MANUFACTURING SOI SUBSTRATE AND SOI SUBSTRATE - A method is demonstrated to form an SOI substrate having a silicon layer with reduced surface roughness in a high yield. The method includes the step of bonding a base substrate such as a glass substrate and a bond substrate such as a single crystal semiconductor substrate to each other, where a region in which bonding of the base substrate with the bond substrate cannot be performed is provided at the interface therebetween. Specifically, the method is exemplified by the combination of: irradiating the bond substrate with accelerated ions; forming an insulating layer over the bond substrate; forming a region in which bonding cannot be performed in part of the surface of the bond substrate; bonding the bond substrate and the base substrate to each other with the insulating layer therebetween; and separating the bond substrate from the base substrate, leaving a semiconductor layer over the base substrate. | 2012-01-19 |
20120012987 | METHODS OF FORMING SEMICONDUCTOR CHIP UNDERFILL ANCHORS - Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in an insulating layer applied to a side of a semiconductor chip. The first opening does not extend through to the side. A second opening is formed in the insulating layer that exposes a portion of the side. | 2012-01-19 |
20120012988 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - According to an embodiment, a chip package is provided, which includes: a substrate having a first surface and a second surface; a device region formed in the substrate; a passivation layer formed overlying the first surface of the substrate; at least a polymer planarization layer formed overlying the passivation layer; a package substrate disposed overlying the first surface of the substrate; and a spacer layer disposed between the package substrate and the passivation layer, wherein the spacer layer and the package substrate surround a cavity overlying the substrate, wherein the polymer planar layer does not extends to an outer edge of the spacer layer. | 2012-01-19 |
20120012989 | METHOD OF MANUFACTURING SEMICONDUCTOR WAFER BONDING PRODUCT, SEMICONDUCTOR WAFER BONDING PRODUCT AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor wafer bonding product according to the present invention, including: a step of preparing a spacer formation film including a support base and a spacer formation layer; a step of attaching the spacer formation layer of the spacer formation film to a semiconductor wafer; a step of selectively exposing the spacer formation layer with an exposure light via a mask, which is placed at a side of the support base of the spacer formation film, so as to be passed through the support base; a step of removing the support base; a step of developing the spacer formation layer to form a spacer on the semiconductor wafer; and a step of bonding a transparent substrate to a surface of the spacer opposite to the semiconductor wafer. | 2012-01-19 |
20120012990 | Semiconductor Device and Method of Forming Protective Layer Over Exposed Surfaces of Semiconductor Die - A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. A shielding layer is formed between the first and second semiconductor die. An electrical interconnect, such as conductive pillar, bump, or bond wire, is formed between the first and second semiconductor die. A conductive TSV can be formed through the first and second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and electrical interconnect. A heat sink is formed over the second semiconductor die. An interconnect structure, such as a bump, can be formed over the second semiconductor die. A portion of a backside of the first semiconductor die is removed. A protective layer is formed over exposed surfaces of the first semiconductor die. The protective layer covers the exposed backside and sidewalls of the first semiconductor die. | 2012-01-19 |
20120012991 | Integrated shielding for a package-on-package system - An electronic package-on-package system with integrated shielding. The package-on-package system includes a first package having a first die and a second package having a second die and a substrate. The system also includes a conductive shield having a first portion and a second portion. The first portion is disposed between the first die and the second die and the second portion is disposed between the substrate and the first portion. The first portion is coupled to the second portion for shielding the first die from the second die. | 2012-01-19 |
20120012992 | SEMICONDUCTOR DEVICE - A semiconductor device having an improved whisker resistance in an exterior plating film is disclosed. The semiconductor device includes a tab with a semiconductor chip fixed thereto, plural inner leads, plural outer leads formed integrally with the inner leads, a plurality of wires for coupling electrode pads of the semiconductor chip and the inner leads with each other, and a sealing body for sealing the semiconductor chip. The outer leads project from the sealing body and an exterior plating film, which is a lead-free plating film, is formed on a surface of each of the outer leads. In the exterior plating film, the number of grains not larger than 1 μm in diameter and present on an interface side in the thickness direction of the exterior plating film is larger than the number of grains not larger than 1 μm and present on a surface side of the exterior plating film, whereby the difference in linear expansion coefficient between the exterior plating film and the outer lead is made small, thus making it possible to suppress the growth of whisker. | 2012-01-19 |
20120012993 | DIE PACKAGE INCLUDING SUBSTRATE WITH MOLDED DEVICE - A package is disclosed. The package includes a premolded substrate having a leadframe structure, a first device attached to the leadframe structure, and a molding material covering at least part of the leadframe structure and the first device. It also includes a second device attached to the premolded substrate. | 2012-01-19 |
20120012994 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES HAVING A GLASS SUBSTRATE - A method for manufacturing semiconductor devices is disclosed. A semiconductor wafer is provided having a first surface and a second surface opposite to the first surface. A first glass substrate is provided which has at least one of cavities and openings at the bonding surface. The first glass substrate is bonded to the first surface of the semiconductor wafer such that the metal pads are arranged within respective cavities or openings of the first glass substrate. The second surface of the semiconductor wafer is machined. At least one metallisation region is formed on the machined second surface of the semiconductor wafer. | 2012-01-19 |
20120012995 | Semiconductor device - A semiconductor device includes a semiconductor element having a rectangular two-dimensional geometry and serving as a heat source, a first heat sink section including the semiconductor element mounted thereon, and a second heat sink section joined to an opposite side of the first heat sink section that includes the semiconductor element. A relation among directional components of thermal conductivity is K | 2012-01-19 |
20120012996 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device that can properly relax a stress produced by a difference in coefficient of linear expansion between an insulating substrate and a cooler and can properly remove heat by cooling of a semiconductor element. A semiconductor device comprises an insulating substrate, a semiconductor element provided on the insulating substrate, a cooler, and a porous metal plate provided between the insulating substrate and the cooler. Through holes in the porous metal plate are open at least to that surface of the porous metal plate which faces the cooler. The sectional size of the pores decreases gradually from the cooler side toward the insulating substrate side. | 2012-01-19 |
20120012997 | Recessed Pillar Structure - A bump structure that may be used to interconnect one substrate to another substrate is provided. A recessed conductive pillar is formed on a first substrate such that the recessed conductive pillar has a recess formed therein. The recess may be filled with a solder material. A conductive pillar on a second substrate may be formed having a contact surface with a width less than or equal to a width of the recess. The first substrate may be attached to the second substrate such that the conductive pillar on the second substrate is positioned over or in the recess of the first substrate. The substrates may each be an integrated circuit die, an interposer, a printed circuit board, a high-density interconnect, or the like. | 2012-01-19 |
20120012998 | Conductive Sidewall for Microbumps - Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate. | 2012-01-19 |
20120012999 | SEMICONDUCTOR-ENCAPSULATING ADHESIVE, SEMICONDUCTOR-ENCAPSULATING FILM-FORM ADHESIVE, METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - The present invention relates to a semiconductor-encapsulating adhesive, a semiconductor-encapsulating film-form adhesive, a method for producing a semiconductor device, and a semiconductor device. The present invention provides a semiconductor-encapsulating adhesive comprising (a) an epoxy resin, and (b) a compound formed of an organic acid reactive with an epoxy resin and a curing accelerator. | 2012-01-19 |
20120013000 | STACKABLE MOLDED MICROELECTRONIC PACKAGES - A microelectronic package has a microelectronic element overlying or mounted to a first surface of a substrate and substantially rigid conductive posts projecting above the first surface or projecting above a second surface of the substrate remote therefrom. Conductive elements exposed at a surface of the substrate opposite the surface above which the conductive posts project are electrically interconnected with the microelectronic element. An encapsulant overlies at least a portion of the microelectronic element and the surface of the substrate above which the conductive posts project, the encapsulant having a recess or a plurality of openings each permitting at least one electrical connection to be made to at least one conductive post. At least some conductive posts are electrically insulated from one another and adapted to simultaneously carry different electric potentials. In particular embodiments, the openings in the encapsulant at least partially expose conductive masses joined to posts, fully expose top surfaces of posts and partially expose edge surfaces of posts, or may only partially expose top surfaces of posts. | 2012-01-19 |
20120013001 | STACKABLE MOLDED MICROELECTRONIC PACKAGES WITH AREA ARRAY UNIT CONNECTORS - A microelectronic package having a substrate, a microelectronic element, e.g., a chip, and terminals can have conductive elements electrically connected with element contacts of the chip and contacts of the substrate. Conductive elements can be electrically insulated from one another for simultaneously carrying different electric potentials. An encapsulant can overlie the first surface of the substrate and at least a portion of a face of the microelectronic element remote from the substrate, and may have a major surface above the microelectronic element. A plurality of package contacts can overlie a face of the microelectronic element remote from the substrate. The package contacts, e.g., conductive masses, substantially rigid posts, can be electrically interconnected with terminals of the substrate, such as through the conductive elements. The package contacts can have top surfaces at least partially exposed at the major surface of the encapsulant. | 2012-01-19 |
20120013002 | PACKAGE STRUCTURE - Disclosed is a package structure including a semiconductor chip disposed in a core board having a first surface and an opposite second surface. The package structure further includes a plurality of first and second electrode pads disposed on an active surface and an opposite inactive surface of the semiconductor chip respectively, the semiconductor chip having a plurality of through-silicon vias for electrically connecting the first and second electrode pads. As a result, the semiconductor chip is electrically connected to the two sides of the package structure via the through-silicon vias instead of conductive through holes, so as to enhance electrical quality and prevent the inactive surface of the semiconductor chip from occupying wiring layout space of the second surface of the core board to thereby increase wiring layout density and enhance electrical performance. | 2012-01-19 |
20120013003 | BGA PACKAGE WITH TRACES FOR PLATING PADS UNDER THE CHIP - A semiconductor flip-chip ball grid array package with one-metal-layered substrate. The sites of a two-dimensional array become usable for attaching solder balls of the signal (non-common net assignment) I/O type to the substrate under the chip area, when the sites can be routed for metal plating. The space to place a maximum number of signal routing traces is opened up by interrupting the periodicity of the site array from the edge of the substrate towards the center under the chip. The periodicity is preferably interrupted by depopulating entire aligned lines and rows of the two-dimensional array. | 2012-01-19 |
20120013004 | Semiconductor Device Having an Interconnect Structure with TSV Using Encapsulant for Structural Support - A semiconductor device includes a substrate and a via extending through the substrate. A first insulating layer is disposed on sidewalls of the via. An electrically conductive material is disposed in the via over the first insulating layer to form a TSV. A first interconnect structure is disposed over a first side of the substrate. A semiconductor die or a component is mounted to the first interconnect structure. An encapsulant is disposed over the first interconnect structure and semiconductor die or component. A second interconnect structure is disposed over the second side of the substrate. The second interconnect structure is electrically connected to the TSV. The second interconnect structure includes a second insulating layer disposed over the second surface of the substrate and TSV, and a first conductive layer disposed over the TSV and in contact with the TSV through the second insulating layer. | 2012-01-19 |
20120013005 | Packaging Structure and Method - A method of making a semiconductor device includes providing a substrate and forming a conductive layer on the substrate. The conductive layer includes a first metal. A semiconductor die is provided. A bump is formed on the semiconductor die. The bump includes a second metal. The semiconductor die is positioned proximate to the substrate to contact the bump to the conductive layer and form a bonding interface. The bump and the conductive layer are metallurgically reacted at a melting point of the first metal to dissolve a portion of the second metal from an end of the bump. The bonding interface is heated to the melting point of the first metal for a time sufficient to melt a portion of the first metal from the conductive layer. A width of the conductive layer is no greater than a width of the bump. | 2012-01-19 |
20120013006 | CHIP SCALE PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a chip scale package is provided, which includes forming a protection layer on the active surface of a chip and fixing the inactive surface of the chip to a transparent carrier; performing a molding process; removing the protection layer from the chip and performing a redistribution layer (RDL) process, thereby solving the conventional problems caused by directly attaching the chip on an adhesive film, such as film-softening caused by heat, encapsulant overflow, warpage, chip deviation and contamination that lead to poor electrical connection between the wiring layer formed in the RDL process and the chip electrode pads and even waste product as a result. Further, the transparent carrier employed in the invention can be separated by laser and repetitively used in the process to help reduce the fabrication cost. | 2012-01-19 |
20120013007 | PACKAGE-ON-PACKAGE SEMICONDUCTOR PACKAGE HAVING SPACERS DISPOSED BETWEEN TWO PACKAGE SUBSTRATES - A Package-on-Package (POP) semiconductor package has a structure in which a second semiconductor package is stacked on a first semiconductor package. A plurality of spacers are disposed between a first substrate of the first semiconductor package and a second substrate of the second semiconductor package so as to maintain a gap between the first substrate and the second substrate. The plurality of spacers may project from a bottom surface of the second substrate toward the first substrate, or may project from a top surface of the first substrate toward the second substrate. When an upper molding layer is formed on the second substrate so as to cover a second semiconductor chip, the plurality of spacers may be connected to the upper molding layer via through holes that vertically pass through the second substrate. When a first semiconductor chip is adhered to the top surface of the first substrate with an adhering layer, the plurality of spacers may be connected to the adhering layer on the top surface of the first substrate. | 2012-01-19 |
20120013008 | METALLIZATION PROCESSES, MIXTURES, AND ELECTRONIC DEVICES - One aspect of the present invention is a method of processing a substrate. In one embodiment, the method comprises forming an electrical conductor on or in the substrate by providing a mixture comprising metal particles and an electroless deposition solution and electrolessly depositing a metal matrix and co-depositing the metal particles. In another embodiment, the method comprises forming an electrical conductor on or in the substrate by providing a mixture comprising metal particles and an electrochemical plating solution and electrochemically plating a metal matrix and co-depositing the metal particles. Another aspect of the present invention is a mixture for the formation of an electrical conductor on or in a substrate. Another aspect of the present invention is an electronic device. | 2012-01-19 |
20120013009 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - The present invention discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a semiconductor substrate, a local interconnect structure connected to the semiconductor substrate, and at least one via stack structure electrically connected to the local interconnect structure, wherein the at least one via stack structure comprises a via having an upper via and a lower via, the width of the upper via being greater than that of the lower via; a via spacer formed closely adjacent to the inner walls of the lower via; an insulation layer covering the surfaces of the via and the via spacer; a conductive plug formed within the space surrounded by the insulation layer, and electrically connected to the local interconnect structure. The present invention is applicable to manufacture of a via stack in the filed of manufacturing semiconductor. | 2012-01-19 |
20120013010 | BONDING PAD FOR ANTI-PEELING PROPERTY AND METHOD FOR FABRICATING THE SAME - A bonding pad includes a conductive layer formed over an insulation layer, and a dummy pattern penetrating the insulation layer and stuck in the conductive layer, wherein a bonding process is performed. | 2012-01-19 |
20120013011 | Conductive Lines and Pads and Method of Manufacturing Thereof - A semiconductor device and method are disclosed. The semiconductor device includes a substrate having a first region and a second region and an insulating layer arranged on the substrate. A first conductive layer is arranged in or on insulating layer in the first region and a second conductive layer is arranged in or on the insulating layer in the second region. The first conductive layer comprises a first conductive material and the second conductive layer comprises a second conductive material wherein the first conductive material is different than the second conductive material. A metal layer is arranged on the first conductive layer. | 2012-01-19 |
20120013012 | METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES, AND SEMICONDUCTOR STRUCTURES FORMED BY SUCH METHODS - Methods of forming bonded semiconductor structures include temporarily, directly bonding together semiconductor structures, thinning at least one of the semiconductor structures, and subsequently permanently bonding the thinned semiconductor structure to another semiconductor structure. The temporary, direct bond may be established without the use of an adhesive. Bonded semiconductor structures are fabricated in accordance with such methods. | 2012-01-19 |
20120013013 | TEMPORARY SEMICONDUCTOR STRUCTURE BONDING METHODS AND RELATED BONDED SEMICONDUCTOR STRUCTURES - Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods. | 2012-01-19 |
20120013014 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - The semiconductor device comprises a metal line configured to be buried in an interlayer insulation layer formed over a semiconductor substrate, a first insulating pattern configured to be formed over the interlayer insulating layer and the first metal line so that the first metal line is exposed, a second insulating pattern configured to be buried between the first insulating patterns so that the first metal line is exposed, and a third insulating pattern configured to be formed over the first insulating pattern and the second insulating pattern so that the first metal line is exposed, thereby reducing the resistance of a contact plug, such that it operates at high speed and requires low power consumption. | 2012-01-19 |
20120013015 | Interconnection architecture for semiconductor device - An interconnection architecture, for a semiconductor device (having regions arranged to include at least an inner region, an intermediate region located at least aside the inner region, and an outer region located at least on a side of the intermediate region opposite to the inner region, includes: one or more pairs of first and second signal lines, each pair extending from the inner region into the intermediate region; first portions and second portions of the first and second signal lines being parallel, respectively, the first portions being located in the inner region; the first and second portion of at least the first signal line not being collinear; and an intra-pair line-spacing, d(i), for each pair including the following magnitudes, d | 2012-01-19 |
20120013016 | FLEXIBLE SEMICONDUCTOR PACKAGE APPARATUS HAVING A RESPONSIVE BENDABLE CONDUCTIVE WIRE MEMBER AND A MANUFACTURING THE SAME - A flexible semiconductor package apparatus having a responsive bendable conductive wire member is presented. The apparatus includes a flexible substrate, semiconductor chips, and conductive wires. The semiconductor chips are disposed on the flexible substrate and spaced apart from each other on the flexible substrate. Each semiconductor chip has bonding pads. The conductive wires are electrically connected to the bonding pads of the semiconductor chip. Each conductive wire has at least one elastic portion. One preferred configuration is that part of the conductive wire is wound to form a coil spring shape so that the coil spring shape of the conductive wire aid in preventing the conductive wire from being separated from the corresponding bonding pad of the semiconductor chip when the flexible substrate on which the semiconductor chips are mounted are bent, expanded or twisted. | 2012-01-19 |
20120013017 | INTEGRATED STRUCTURES OF HIGH PERFORMANCE ACTIVE DEVICES AND PASSIVE DEVICES - Integrated structures having high performance CMOS active devices mounted on passive devices are provided. The structure includes an integrated passive device chip having a plurality of through wafer vias, mounted to a ground plane. The structure further includes at least one CMOS device mounted on the integrated passive device chip using flip chip technology and being grounded to the ground plane through the through wafer vias of the integrated passive device chip. | 2012-01-19 |
20120013018 | DIE PACKAGE STRUCTURE AND RELATED DIE PACKAGE STRUCTURE MANUFACTURING METHOD - A die package structure, which comprises: a first die; a second die; a core material layer, provided between the first die and the second die; at least one via, penetrating through the first die, the second die and the core material layer; a metal material, stuffing into the via, such that the first die the second die, and the core material layer can be electrically contacted with each other; at least a signal contacting unit, contacting the metal material; and a dielectric layer, enclosing the first die, including at least one breach exposing the signal contacting unit. | 2012-01-19 |
20120013019 | SEMICONDUCTOR DEVICE - A signal line is formed in the a-th layer (a≧2) of a multi-layered interconnect layer and a redistribution layer. A plain line is formed in the b-th layer (b | 2012-01-19 |
20120013020 | MEMS Device Comprising a Hermetically Sealed Cavity and Devices Obtained Thereof - A MEMS device is disclosed comprising a cavity containing a MEMS component, the cavity being formed in a dielectric layer stack having a thickness t | 2012-01-19 |
20120013021 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDCUTOR DEVICE - An electronic component incorporation substrate and a method for manufacturing the same that provide a high degree of freedom for selecting materials. An electronic component incorporation substrate includes a first structure, which has a substrate and an electronic component. The substrate includes a substrate body having first and second surfaces. A first wiring pattern is formed on the first surface and electrically connected to a second wiring pattern formed on the second surface through a through via. The electronic component is electrically connected to the first wiring pattern. The electronic component incorporation substrate includes a sealing resin, which seals the first structure, and a third wiring pattern, which is connected to the second wiring pattern through a second via. | 2012-01-19 |
20120013022 | METHOD FOR FORMING 3D-INTERCONNECT STRUCTURES WITH AIRGAPS - Ultra-low capacitance interconnect structures, preferably Through Silicon Via (TSV) interconnects and methods for fabricating said interconnects are disclosed. The fabrication method comprises the steps of providing a substrate having a first main surface, producing at least one hollow trench-like structure therein from the first main surface, said trench-like structure surrounding an inner pillar structure of substrate material, depositing a dielectric liner which pinches off said hollow trench-like structure at the first main surface such that an airgap is created in the center of hollow trench-like structure and further creating a TSV hole and filling it at least partly with conductive material. | 2012-01-19 |
20120013023 | SEMICONDUCTOR DEVICE - The present invention provides a multilayer wiring technology by which high adhesiveness and high insulation reliability between wirings are obtained, while maintaining effective low capacitance between wirings. A semiconductor device is characterized in that a first insulating film is an insulating film formed of at least one layer which contains a siloxane structure containing silicon, oxygen and carbon; the siloxane structure in the inner part of the first insulating film contains a larger number of carbon atoms than the number of silicon atoms; and a modified layer which containing a smaller number of carbon atoms and a larger number of oxygen atoms per unit volume than the inner part of the first insulating film is formed on at least one of an interface between the first insulating film and the metal and an interface between the first insulating film and a second insulating film. | 2012-01-19 |
20120013024 | Layered Chip Package and Method of Manufacturing Same - A layered chip package includes a main body and wiring, the wiring including a plurality of wires disposed on a side surface of the main body. The main body includes a main part and a plurality of terminals. The main part includes a plurality of layer portions stacked. The terminals are disposed on at least either one of the top and bottom surfaces of the main part and electrically connected to the wires. Each of the layer portions includes a semiconductor chip, and a plurality of electrodes that are electrically connected to the wires. The electrodes include a plurality of first electrodes that are intended to establish electrical connection to the semiconductor chip, and a plurality of second electrodes that are not in contact with the semiconductor chip. In at least one of the layer portions, the first electrodes are in contact with and electrically connected to the semiconductor chip. | 2012-01-19 |
20120013025 | Layered Chip Package and Method of Manufacturing Same - A layered chip package includes a main body and wiring, the wiring including a plurality of wires disposed on a side surface of the main body. The main body includes a main part and a plurality of terminals. The main part includes a plurality of layer portions stacked. The terminals are disposed on at least either one of the top and bottom surfaces of the main part and electrically connected to the wires. Each of the layer portions includes a semiconductor chip. The plurality of wires include a plurality of common wires and a plurality of layer-dependent wires. In at least one of the layer portions, the semiconductor chip is electrically connected to the plurality of common wires and is selectively electrically connected to only the layer-dependent wire that the layer portion uses, among the plurality of layer-dependent wires. | 2012-01-19 |
20120013026 | STACKED SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A stacked semiconductor package and an electronic system, the stacked semiconductor package including a plurality of semiconductor chips, a set of the semiconductor chips being stacked such that an extension region of a top surface of each semiconductor chip of the set extends beyond an end of a semiconductor chip stacked thereon to form a plurality of extension regions; and a plurality of protection layers on the extension regions and on an uppermost semiconductor chip of the plurality of semiconductor chips. | 2012-01-19 |
20120013027 | SEMICONDUCTOR AND A METHOD OF MANUFACTURING THE SAME - A method including forming an intermediate product, the intermediate product being configured to include a wiring substrate including a plurality of first electrodes, a plurality of second electrodes and a plurality of test electrodes, a first semiconductor chip mounted over the wiring substrate and including a plurality of first pads electrically connected respectively to the first electrodes, and a second semiconductor chip stacked over the first semiconductor chip and including a plurality of second pads electrically connected respectively to the second electrodes; encapsulating the first and second semiconductor chips; and performing electrical tests on the first and second semiconductor chips by use of the test electrodes, after the encapsulating of the first and second semiconductor chips. | 2012-01-19 |
20120013028 | STACKED MICROELECTRONIC PACKAGES HAVING AT LEAST TWO STACKED MICROELECTRONIC ELEMENTS ADJACENT ONE ANOTHER - A microelectronic assembly includes first and second microelectronic elements. Each of the microelectronic elements has oppositely-facing first and second surfaces and edges bounding the surfaces. The first microelectronic element is disposed on the second microelectronic element with the second surface of the first microelectronic element facing toward the first surface of the second microelectronic element. The first microelectronic element preferably extends beyond at least one edge of the second microelectronic element and the second microelectronic element preferably extends beyond at least one edge of the first microelectronic element. A first edge of the first microelectronic element has a length that is smaller than a first edge of the second microelectronic element. A second edge of the first microelectronic element has a length that is greater than the second edge of the second microelectronic element. | 2012-01-19 |
20120013029 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES HAVING A METALLISATION LAYER - A method for manufacturing semiconductor devices is disclosed. In one embodiment a semiconductor substrate having a first surface, a second surface opposite to the first surface and a plurality of semiconductor components is provided. The semiconductor substrate has a device thickness. At least one metallisation layer is formed on the second surface of the semiconductor substrate. The metallisation layer has a thickness which is greater than the device thickness. | 2012-01-19 |
20120013030 | METHOD FOR PRODUCING PROGRESSIVE POWER EYEGLASS LENS - The present invention provides a method for producing a progressive-addition plastic lens having a prism thinning applied thereto without cutting and polishing. | 2012-01-19 |