03rd week of 2022 patent applcation highlights part 55 |
Patent application number | Title | Published |
20220020691 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device comprising a first logic cell and a second logic cell on a substrate. Each of the first and second logic cells includes a first active region and a second active region that are adjacent to each other in a first direction, a gate electrode that runs across the first and second active regions and extends lengthwise in the first direction, and a first metal layer on the gate electrode. The first metal layer includes a first power line and a second power line that extend lengthwise in a second direction perpendicular to the first direction, and are parallel to each other. The first and second logic cells are adjacent to each other in the second direction along the first and second power lines. The first and second active regions extend lengthwise in the second direction from the first logic cell to the second logic cell. | 2022-01-20 |
20220020692 | COMPOSITE COMPONENT AND METHOD FOR MANUFACTURING THE SAME - A composite component that includes an interposer structure and an electronic component. The interposer structure includes a Si base layer having a first main surface and a second main surface facing each other, a rewiring layer on the first main surface, a through Si via electrically connected to the rewiring layer and penetrating the Si base layer, an interposer electrode facing the second main surface, and an adhesive layer. The electronic component has a surface and a component electrode on the surface and connected to the through Si via, and is located between the interposer electrode and the Si base layer such that the component electrode and the surface are adhered to the second main surface of the Si base layer with the adhesive layer interposed therebetween. The through Si via extends from the second main surface, penetrates the adhesive layer, and is electrically connected to the component electrode. | 2022-01-20 |
20220020693 | Eccentric Via Structures for Stress Reduction - A method includes forming a first dielectric layer, forming a first redistribution line including a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes depositing a conductive material into the via opening to form a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, and the second via is offset from a center line of the conductive bump. | 2022-01-20 |
20220020694 | Graphene-Assisted Low-Resistance Interconnect Structures and Methods of Formation Thereof - A semiconductor structure is provided. The semiconductor structure comprises a first conductive feature embedded within a first dielectric layer, a via disposed over the first conductive feature, a second conductive feature disposed over the via, and a graphene layer disposed over at least a portion of the first conductive feature. The via electrically couples the first conductive feature to the second conductive feature. | 2022-01-20 |
20220020695 | Metrology Targets for High Topography Semiconductor Stacks - A metrology target for use in measuring misregistration between layers of a semiconductor device including a first target structure placed on a first layer of a semiconductor device, the first target structure including a first plurality of unitary elements respectively located in at least four regions of the first target structure, the first plurality of elements being rotationally symmetric with respect to a first center of symmetry and at least a second target structure placed on at least a second layer of the semiconductor device, the second target structure including a second plurality of elements respectively located in at least four regions of the second target structure, the second plurality of elements being rotationally symmetric with respect to a second center of symmetry, the second center of symmetry being designed to be axially aligned with the first center of symmetry and corresponding ones of the second plurality of elements being located adjacent corresponding ones of the first plurality of elements in the at least four regions in a non-surrounding arrangement, when the first and second layers are placed one on top of another. | 2022-01-20 |
20220020696 | WORKPIECE MANAGEMENT METHOD AND SHEET CUTTING MACHINE - A workpiece management method includes a frame unit forming step of forming a frame unit with a workpiece supported in an opening of an annular frame via a resin sheet, a printing step of, after performing the frame unit forming step, printing identification information of the workpiece on the resin sheet in an area between an outer periphery of the workpiece and an inner periphery of the annular frame, a processing step of processing the workpiece by a processing machine, a separation step of separating the processed workpiece from the resin sheet, and a storage step of storing the resin sheet from which the workpiece has been separated. A sheet cutting machine suitable for use in the workpiece management method is also disclosed. | 2022-01-20 |
20220020697 | MODULE AND METHOD OF MANUFACTURING THE SAME - A module is provided that includes a substrate having a first main surface, a component mounted on the first main surface, a first sealing resin disposed so as to cover the first main surface and the component, and a shield film covering at least an upper surface of the first sealing resin. The shield film includes a protective layer exposed to the outside and a conductive layer covered by the protective layer. The color of a surface of the conductive layer closer to the protective layer is different from the color of the protective layer. Moreover, the laser absorption coefficient of a material of the protective layer is higher than the laser absorption coefficient of a material forming the surface of the conductive layer closer to the protective layer. The module includes a marking section that is not covered by the protective layer and from which the conductive layer is exposed. | 2022-01-20 |
20220020698 | ELECTRONIC PACKAGE AND METHOD FOR MANUFACTURING THE SAME - The present disclosure provides an electronic package and method of manufacturing the same. The electronic package includes an electronic device including a first carrier and a first electronic component disposed on the first carrier, a second carrier adjacent to the first carrier of the electronic device, and a conductive layer at least partially covering the electronic device, and separating the electronic device from the second carrier. | 2022-01-20 |
20220020699 | PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - The invention provides a package structure, comprising: a substrate disposed with a solid grounded copper layer; at least two radio frequency chip modules disposed on the substrate; a plastic encapsulation disposed on the substrate, covered on a surface of the substrate, and coating the at least two radio frequency chip modules therein; a groove located between the adjacent two radio frequency chip modules, and penetrating an upper surface and a lower surface of the plastic encapsulation; a solder filling body filled in the groove, wherein an upper surface of the solder filling body is flushed with the upper surface of the plastic encapsulation; and a shielding layer covered on the upper surface and lateral surfaces of the plastic encapsulation, an upper surface of the solder filling body and lateral surfaces of the substrate; wherein a position of the solid grounded copper layer corresponds to a position of the groove, and makes contact with the solder filling body in the groove. | 2022-01-20 |
20220020700 | Stacking Via Structures for Stress Reduction - A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump. | 2022-01-20 |
20220020701 | SEMICONDUCTOR PACKAGE - A semiconductor package including a package substrate, a connection substrate on the package substrate and having on a lower corner of the connection substrate a recession that faces a top surface of the package substrate, a semiconductor chip on the connection substrate, a plurality of first connection terminals connecting the connection substrate to the semiconductor chip, and a plurality of second connection terminals connecting the package substrate to the connection substrate. The recession is laterally spaced apart from the second connection terminals. | 2022-01-20 |
20220020702 | Semiconductor Device and in-Vehicle Electronic Control Device Using the Same - In a semiconductor device equipped with a current mirror circuit, a highly reliable semiconductor device capable of suppressing a change in a mirror ratio of the current mirror circuit over time is provided. A current mirror circuit that includes a first MOS transistor and a plurality of MOS transistors paired with the first MOS transistor, and a plurality of wiring layers formed on an upper layer of the MOS transistor are provided. The plurality of wiring layers are arranged such that wiring patterns have the same shape within a predetermined range from an end of a channel region of each of the first MOS transistor and the plurality of MOS transistors. | 2022-01-20 |
20220020703 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a plurality of semiconductor chips each including a first main electrode on a top surfaces and including a second main electrode and a control electrode on a bottom surface; a first common main electrode connected to the first main electrodes; a printed board including a control wiring part and a main wiring part provided on a bottom surface of an insulating layer, and a common control electrode and a second common main electrode provided on a top surface of the insulating layer and electrically connected to the control wiring part and the main wiring part; projection electrodes bonding the control electrodes to the control wiring part; projection electrodes bonding the second main electrodes to the main wiring part; and a sealing member sealing the semiconductor chips and exposing the first common main electrode, the common control electrode, and the second common main electrode. | 2022-01-20 |
20220020704 | DIE STACK WITH REDUCED WARPAGE - A microelectronic device can include a polymer, a semiconductor, and a matching layer. The polymer can include a first coefficient of thermal expansion. The semiconductor can be coupled to the polymer layer. The matching layer can be adjacent the semiconductor, and the matching layer can include a second coefficient of thermal expansion that is about the same as the first coefficient of thermal expansion. | 2022-01-20 |
20220020705 | SEMICONDUCTOR WAFER THINNED BY STEALTH LASING - A semiconductor wafer thinned by a stealth lasing process, and semiconductor dies formed therefrom. After formation of an integrated circuit layer on a semiconductor wafer, the wafer may be thinned by focusing a laser at discrete points in the wafer substrate beneath the surface of the wafer. Upon completion of stealth lasing in one or more planar layers in the substrate, a portion of the substrate may be removed, leaving the wafer thinned to a desired final thickness. | 2022-01-20 |
20220020706 | TAMPER-RESISTANT CIRCUIT, BACK-END OF THE LINE MEMORY AND PHYSICAL UNCLONABLE FUNCTION FOR SUPPLY CHAIN PROTECTION - A tamper-resistant memory is formed by placing a solid-state memory array between metal wiring layers in the upper portion of an integrated circuit (back-end of the line). The metal layers form a mesh that surrounds the memory array to protect it from picosecond imaging circuit analysis, side channel attacks, and delayering with electrical measurement. Interconnections between a memory cell and its measurement circuit are designed to protect each layer below, i.e., an interconnecting metal portion in a particular metal layer is no smaller than the interconnecting metal portion in the next lower layer. The measurement circuits are shrouded by the metal mesh. The substrate, metal layers and memory array are part of a single monolithic structure. In an embodiment adapted for a chip identification protocol, the memory array contains a physical unclonable function identifier that uniquely identifies the tamper-resistant integrated circuit, a symmetric encryption key and a release key. | 2022-01-20 |
20220020707 | OPTOELECTRONIC SEMICONDUCTOR COMPONENT AND ARRANGEMENT - An optoelectronic semiconductor component includes a semiconductor body having a main emission surface and an active region arranged to emit electromagnetic radiation. The optoelectronic semiconductor component also includes a receiving element arranged on the side of the semiconductor body opposite to the main emission surface. The optoelectronic semiconductor component also includes a radiation-transmissive molding compound. The radiation-transmissive molding compound completely surrounds the semiconductor body and the receiving element. A receiver frequency is assigned to the receiving element. The receiving element is configured to extract energy for operating the active region from an alternating electromagnetic field. | 2022-01-20 |
20220020708 | CHANNELIZED FILTER USING SEMICONDUCTOR FABRICATION - An exemplary semiconductor technology implemented channelized filter includes a dielectric substrate with semiconductor fabricated metal traces on one surface, and input and output ports. A signal trace connected between the input and output port carries the signal to be filtered. Filter traces connect at intervals along the length of the signal trace to provide a reactance that varies with frequency. Ground traces provide a reference ground. A silicon enclosure with semiconductor fabricated cavities has a metal layer deposited over it. The periphery of the enclosure is dimensioned to engage corresponding ground traces about the periphery of the substrate. Walls of separate cavities enclose each of the filter traces to individually surround each thereby providing electromagnetic field isolation. Metal-to-metal conductive bonds are formed between cavity walls that engage the ground traces to establish a common reference ground. The filter traces preferably meander to minimize the footprint area of the substrate. | 2022-01-20 |
20220020709 | INTERLOCKED REDISTRIBUTION LAYER INTERFACE FOR FLIP-CHIP INTEGRATED CIRCUITS - This disclosure provides an integrated circuit device that includes a RDL that is interlocked with a bump (or “pillar”). The interlocked interface provides the contact RDL-bump interface with increased structural stability that can better withstand the thermal stresses associated with high performance devices IC devices. The interlock structure mitigates crack/delamination that occurs at the RDL-bump interface in large IC chips that are generally subjected to higher stresses during operation. | 2022-01-20 |
20220020710 | SINTERING PRESS FOR SINTERING ELECTRONIC COMPONENTS ON A SUBSTRATE - A sintering press for sintering electronic components on a substrate includes at least one reaction element extending along an element axis parallel to a pressing axis of the sintering press between a first element end and a second element end, the first element end forming a support plane for a respective substrate, at least one load cell operatively connected to the second element end, and an element plate slidably supporting the at least one reaction element and equipped with a heating circuit. The reaction element has a heating portion passing through the element plate and transmitting by conduction heat of the element plate to the substrate. The reaction element has a cooling portion ending with the second element end and shaped to dissipate the heat transmitted from the element plate to the heating portion. | 2022-01-20 |
20220020711 | SEMICONDUCTOR DEVICE INCLUDING UNEVEN CONTACT IN PASSIVATION LAYER AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device including a substrate, a passivation layer, and a connector. The passivation layer is disposed on the substrate. The connector is embedded in the passivation. An interface of the connector in contact with the passivation layer is uneven, thereby improving the structural stability of the connector. A method of manufacturing the semiconductor is also provided. | 2022-01-20 |
20220020712 | METHODS FOR BONDING SEMICONDUCTOR STRUCTURES AND SEMICONDUCTOR DEVICES THEREOF - Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is provided. The method includes the following operations. In a first semiconductor structure, a first bonding layer is formed having a first dielectric layer and a plurality of protruding contact structures. In a second semiconductor structure, a second bonding layer is formed having a second dielectric layer and a plurality of recess contact structures. The plurality of protruding contact structures are bonded with the plurality of recess contact structures such that each of the plurality of protruding contacts is in contact with a respective recess contact structure. | 2022-01-20 |
20220020713 | SEMICONDUCTOR PACKAGE - Provided is a semiconductor package including: a first substrate having a first electrode pad and a first protective layer in which a cavity is formed; a first bump pad arranged in the cavity and connected to the first electrode pad; a second substrate facing the first substrate and having a second bump pad; and a bump structure in contact with the first bump pad and the second bump pad, wherein the first electrode pad has a trapezoidal shape, and the first bump pad has a flat upper surface and an inclined side surface extending along a side surface of the first electrode pad. | 2022-01-20 |
20220020714 | SEMICONDUCTOR PACKAGE DEVICE - A semiconductor package device may include a redistribution substrate and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern, which includes including a body portion and a protruding portion extended from the body portion to form a single object, an insulating layer covering a side surface of the body portion, and an outer coupling terminal on the protruding portion. The body portion may have a first diameter in a first direction parallel to the top surface of the redistribution substrate, and the protruding portion may have a second diameter in the first direction, which is smaller than the first diameter. A top surface of the protruding portion may be parallel to the first direction, and a side surface of the protruding portion may be inclined at an angle to a top surface of the body portion. | 2022-01-20 |
20220020715 | UNIFORM CHIP GAPS VIA INJECTION-MOLDED SOLDER PILLARS - Systems and techniques that facilitate uniform qubit chip gaps via injection-molded solder pillars are provided. In various embodiments, a device can comprise one or more injection-molded solder interconnects. In various aspects, the one or more injection-molded solder interconnects can couple at least one qubit chip to an interposer chip. In various embodiments, the device can further comprise one or more injection-molded solder pillars. In various instances, the one or more injection-molded solder pillars can be between the at least one quit chip and the interposer chip. In various cases, the one or more injection-molded solder pillars can be in parallel with the one or more injection-molded solder interconnects. In various embodiments, the one or more injection-molded solder pillars can facilitate and/or maintain a uniform gap between the at least one qubit chip and the interposer chip. In various embodiments, a melting point of the one or more injection-molded solder pillars can be higher than a melting point of the one or more injection-molded solder interconnects. In various embodiments, the one or more injection-molded solder pillars can be superconductors. In various embodiments, a yield strength of the one or more injection-molded solder pillars can be between 3,000 pounds per square inch and 15,000 pounds per square inch, which can be higher than a yield strength of the one or more injection-molded solder interconnects. In various embodiments, the one or more injection-molded solder pillars can be binary tin alloys, tertiary tin alloys, and/or quaternary tin alloys. | 2022-01-20 |
20220020716 | MIXED HYBRID BONDING STRUCTURES AND METHODS OF FORMING THE SAME - Embodiments include a mixed hybrid bonding structure comprising a composite dielectric layer, where the composite dielectric layer comprises an organic dielectric material having a plurality of inorganic filler material. One or more conductive substrate interconnect structures are within the composite dielectric layer. A die is on the composite dielectric layer, the die having one or more conductive die interconnect structures within a die dielectric material. The one or more conductive die interconnect structures are directly bonded to the one or more conductive substrate interconnect structures, and the inorganic filler material of the composite dielectric layer is bonded to the die dielectric material. | 2022-01-20 |
20220020717 | STRENGTHENED WIRE-BOND - An electrical circuit in a semiconductor package may include a wire connected at each end by a bond point formed using a wire-bonding machine. When a connection point (e.g., a die pad) has a very small dimension, the wire used for the circuit may be required to have a similarly small diameter. This small diameter can lead to a weak bond point, especially in bonds that include a heel portion. The heel portion is a transition region of the bond point that may have less strength (e.g., as measure by a pull-test) than other portions of the bond point and/or may be exposed to more forces than other portions of the bond point. Accordingly, a capping-bond point may be applied to the bond point to strengthen the bond point by clamping the heel portion and shielding it from forces that could cause cracks. | 2022-01-20 |
20220020718 | LASER COMPRESSION BONDING DEVICE AND METHOD FOR SEMICONDUCTOR CHIP - A laser compression bonding device and method for a semiconductor chip are proposed. The device includes a conveyor unit that transports a semiconductor chip and a substrate, and a bonding head that includes a bonding tool for applying a pressure to the chip and substrate, a laser beam generator for emitting a laser beam, a thermal imaging camera for measuring temperatures of the surfaces of semiconductor chip and substrate, and a compression unit for controlling a pressure applied by the bonding tool and a position thereof, wherein the compression unit includes a mount on which the bonding tool is detachably mounted, and a servo motor and a load cell that apply a pressure to the mount or control a position thereof. The servo motor is controlled with two values for pressure application and positioning. | 2022-01-20 |
20220020719 | Depth-Adaptive Mechanism for Ball Grid Array Dipping - This document describes systems and techniques of a depth-adaptive mechanism for ball grid array dipping. In an aspect, a depth-adaptive mechanism having a tensioned mesh is positioned in a reservoir filled with flux. When solder balls of an integrated circuit component are dipped into the reservoir of flux, the solder balls are pressed up against the tensioned mesh. The tensioned mesh is configured to, first, elastically deform under the downward force applied by the solder balls and, second, provide an equal and opposite pushing force in order to facilitate solder ball extraction. In so doing, the solder balls of an integrated circuit component can be more easily extracted from flux when deep ball grid array dipping is performed. | 2022-01-20 |
20220020720 | MULTI-SEGMENT WIRE-BOND - A multifaceted capillary that can be used in a wire-bonding machine to create a multi-segment wire-bond is disclosed. The multifaceted capillary is shaped to apply added pressure and thickness to an outer segment of the multi-segment wire-bond that is closest to the wire loop. The added pressure eliminates a gap under a heel portion of the multi-segment wire-bond and the added thickness increases a mechanical strength of the heel portion. As a result, a pull test of the multi-segment wire-bond may be higher than a single-segment wire-bond and the multi-segment wire-bond may resist cracking, lifting, or breaking. | 2022-01-20 |
20220020721 | WAFER-BONDING STRUCTURE AND METHOD OF FORMING THEREOF - A method of forming a wafer-bonding structure includes a wafer-bonding step, a through silicon via (TSV) forming step, and a forming bonding pad step. In the wafer-bonding step, at least two wafers are corresponding to and bonded to each other by bonding surfaces thereof. In the TSV forming step, a TSV structure is formed on at least one side of a seal ring structure of one of the wafers, a conductive filler is disposed in the TSV structure, and the TSV structure is overlapped the side of one of the seal ring structure of one of the wafers and a portion of a seal ring structure of another one of the wafers. In the forming bonding pad step, a bonding pad is formed on an outer surface which is relative to the bonding surface of the wafer with the TSV structure, so as to form the wafer-bonding structure. | 2022-01-20 |
20220020722 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method of manufacturing a semiconductor device includes forming a metal bump on a first surface side of a semiconductor chip, positioning the semiconductor chip so the metal bump contacts a pad of an interconnection substrate, and applying a first light from a second surface side of the semiconductor chip and melting the metal bump with the first light. After the melting, the melted metal bump is allowed to resolidify by stopping or reducing the application of the first light. The semiconductor chip is then pressed toward the interconnection substrate. A second light is then applied from the second surface side of the semiconductor chip while the semiconductor chip is being pressed toward the interconnection substrate to melt the metal bump. After the melting, the melted metal bump is allowed to resolidify by the stopping or reducing of the application of the second light. | 2022-01-20 |
20220020723 | CHIP-CARRYING STRUCTURE AND CHIP-BONDING METHOD - A chip-carrying structure and a chip-bonding method are provided. The chip-carrying structure includes a circuit substrate for carrying a plurality of conductive materials, a plurality of micro heaters disposed on or inside the circuit substrate, and a micro heater control chip electrically connected to the micro heaters. Therefore, when a chip is disposed on two corresponding ones of the conductive materials, the micro heater control chip is configured to control a corresponding one of the micro heaters to start or stop heating the two corresponding conductive materials according to chip movement information of the chip. | 2022-01-20 |
20220020724 | ANISOTROPIC CONDUCTIVE FILM AND CONNECTED STRUCTURE - Anisotropic conductive films, each including an insulating adhesive layer and conductive particles insulating adhesive layer in a lattice-like manner. Among center distances between an arbitrary conductive particle and conductive particles adjacent to the conductive particle, the shortest distance to the conductive particle is a first center distance; the next shortest distance is a second center distance. These center distances are 1.5 to 5 times the conductive particles' diameter. The arbitrary conductive particle, conductive particle spaced apart from the conductive particle by the first center distance, conductive particle spaced apart from the conductive particle by first center distance or second center distance form an acute triangle. Regarding this acute triangle, an acute angle formed between a straight line orthogonal to a first array direction passing through the conductive particles and second array direction passing through conductive particles being 18 to 35°. These anisotropic conductive films have stable connection reliability in COG connection. | 2022-01-20 |
20220020725 | METHOD OF FORMING SEMICONDUCTOR STRUCTURE - The present invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a first substrate, and a bonding layer located on a surface of the first substrate. The material of the first bonding layer is a dielectric material containing element carbon (C). C atomic concentration of a surface layer of the first bonding layer away from the first substrate is higher than or equal to 35%. The first bonding layer of the semiconductor structure may be used to enhance bonding strength during bonding. | 2022-01-20 |
20220020726 | SEMICONDUCTOR PACKAGE STRUCTURE HAVING AN ANNULAR FRAME WITH TRUNCATED CORNERS - A semiconductor package structure includes a substrate having a substrate having a first surface and second surface opposite thereto, wherein the substrate comprises a wiring structure. The structure also has a first semiconductor die disposed on the first surface of the substrate and electrically coupled to the wiring structure, and a second semiconductor die disposed on the first surface and electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged in a side-by-side manner. A molding material surrounds the first semiconductor die and the second semiconductor die, wherein the first semiconductor die is separated from the second semiconductor die by the molding material. Finally, an annular frame mounted on the first surface of the substrate, wherein the annular frame surrounds the first semiconductor die and the second semiconductor die. | 2022-01-20 |
20220020727 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a base substrate, an insulating layer including a first region disposed on the base substrate and in which first and second openings are disposed and a second region, a remaining region of the base substrate other than the first region, a first semiconductor chip disposed on the base substrate and including bonding pads disposed closely to a first edge, at least one second semiconductor chip stacked on the first semiconductor chip in the form of a staircase toward a second edge, parallel to the first edge, and a molding portion covering the base substrate to encapsulate the first and second semiconductor chips, wherein the length of the first edge is disposed to overlap the second region, both ends of the second edge are disposed to overlap the first and second openings, and the molding portion fills the first and second openings. | 2022-01-20 |
20220020728 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a chip stack comprising semiconductor chips vertically stacked on a substrate in a first direction perpendicular to a top surface of the substrate, pillars between the substrate and the chip stack, an adhesive layer on a bottom surface of a lowermost semiconductor chip of the semiconductor chips, a first lower protective layer between the adhesive layer and the pillars, a second lower protective layer between the first lower protective layer and the adhesive layer, and a mold layer covering the chip stack and filling a space between the pillars. A thickness of the second lower protective layer in the first direction is greater than a thickness of the adhesive layer in the first direction. | 2022-01-20 |
20220020729 | MOLDED DIRECT BONDED AND INTERCONNECTED STACK - Dies and/or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth. | 2022-01-20 |
20220020730 | SEMICONDUCTOR DEVICE - A semiconductor device includes a heat dissipation member, multiple switching elements, and multiple signal terminals. The switching elements include a first switching element formed on a silicon substrate and a second switching element formed on a silicon carbide substrate, and include at least one of the first switching element or the second switching element in a plural number Each of the switching elements includes a temperature sense pad. The first switching element and the second switching element are alternately arranged in a predetermined direction in which a refrigerant flows. In the switching elements of same type as the switching element disposed on a most downstream side in the predetermined direction, the signal terminal corresponding to the temperature sense pad is provided for the switching element disposed on the most downstream side, and is not provided for the switching elements disposed on more upstream side. | 2022-01-20 |
20220020731 | Optoelectronic Lighting Device and Method for Manufacturing an Optoelectronic Lighting Device - In an embodiment an optoelectronic lighting device includes a support and at least one pixel having three illuminating elements, wherein the illuminating elements of the pixel are arranged on an upper side of the support, each illuminating element having a center point, wherein the illuminating elements are arranged around a central point lying on the upper side of the support such that the center points of the illuminating elements lie on a circular path with a defined radius revolving around the central point, wherein each illuminating element includes a base body with a quadrangular base surface, a corner of the base body of each illuminating element lying at least approximately on a line which extends between the center point of the respective illuminating element and the central point, and/or wherein each illuminating element includes a base body with a square base surface, the illuminating elements being arranged on the upper side of the support such that mutually opposite side surfaces of the base body of adjacent illuminating elements extend non-parallel to one another. | 2022-01-20 |
20220020732 | Full Spectrum White Light Emitting Devices - A full spectrum white light emitting device comprising: a broadband solid-state excitation source operable to generate broadband blue excitation light; and at least one photoluminescence material which generates green to red light, wherein the device generates white light whose intensity over the blue to cyan region of the spectrum has a maximum percentage deviation from the intensity of light of a black-body or CIE Standard Illuminant D of less than 50%. | 2022-01-20 |
20220020733 | LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE - A light emitting device includes: a mounting board; a plurality of light emitting elements disposed on the mounting board; a plurality of light transmissive members, each located on an upper surface of a respective one of the light emitting element; a first cover member located on or above the mounting board, the first cover member including: a first reflective material containing layer disposed between the light emitting elements and containing a first reflective material, and a light transmissive layer disposed between the light transmissive members; and a second cover member disposed around the light emitting elements. | 2022-01-20 |
20220020734 | DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A display device includes a first substrate; a first conductive pattern, a first voltage line and a second voltage line on the first substrate; an insulating layer on the first conductive pattern and the second voltage line; a plurality of first light-emitting elements on the insulating layer; a first electrode on the insulating layer and connected to the first conductive pattern, the first electrode overlapping the first voltage line; and a second electrode on the insulating layer and connected to the second voltage line, wherein the plurality of first light-emitting elements are in contact with the first electrode and the second electrode, and wherein a part of an upper surface of the first electrode that overlaps the first conductive pattern and a part of the upper surface of the first electrode that overlaps the first voltage line are located on the same plane. | 2022-01-20 |
20220020735 | THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT DEVICE HAVING A BACKSIDE POWER DELIVERY NETWORK - An integrated circuit (IC) package is described. The IC package includes a power delivery network. The IC package also includes a first die having a first surface and a second surface, opposite the first surface. The second surface is on a first surface of the power delivery network. The IC package further includes a second die having a first surface on the first surface of the first die. The IC package also includes package bumps on a second surface of the power delivery network, opposite the first surface of the power delivery network. The package bumps are coupled to contact pads of the power delivery network. | 2022-01-20 |
20220020736 | MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES - A microelectronic device comprises a first die comprising a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, and vertically extending strings of memory cells within the stack structure. The first die further comprises first control logic region comprising a first control logic devices including at least a word line driver. The microelectronic device further comprise a second die attached to the first die, the second die comprising a second control logic region comprising second control logic devices including at least one page buffer device configured to effectuate a portion of control operations of the vertically extending string of memory cells. Related microelectronic devices, electronic systems, and methods are also described. | 2022-01-20 |
20220020737 | ELECTRONIC MODULE - A electronic module includes a printed circuit board (PCB) substrate, a controller substrate, a controller, a memory device, and a heat spreader. The controller is disposed on the controller substrate. The memory device is disposed on the PCB substrate. The heat spreader is disposed on the controller and the memory device, in which the heat spreader has a first portion on the controller and a second portion on the memory device, and the heat spreader has a first opening between the first portion and the second portion. | 2022-01-20 |
20220020738 | LAYOUT DESIGNS OF INTEGRATED CIRCUITS HAVING BACKSIDE ROUTING TRACKS - An integrated circuit includes a semiconductor substrate, transistors on the semiconductor, horizontal routing tracks extending in a first direction in a first metal layer, and one or more backside routing tracks extending in the first direction in a backside metal layer. Each transistor has a gate terminal, a source terminal, and a drain terminal. A first transistor has a first terminal, a second terminal, and a third terminal. A first horizontal routing track of the horizontal routing tracks is conductively connected to the first terminal of the first transistor through a via connector. A first backside routing track is conductively connected to the second terminal of the first transistor through a backside via connector. The backside metal layer and the first metal layer are formed at opposite sides of the semiconductor substrate. | 2022-01-20 |
20220020739 | SEMICONDUCTOR DEVICE - A first ESD protection circuit is provided between a first high-potential side power supply and a first low-potential side power supply of a first power supply system and a second ESD protection circuit is provided between a second high-potential side power supply and a second low-potential side power supply of a second power supply system. A coupling circuit includes a bidirectional diode and couples the first and second low-potential side power supplies. A first transistor is composed of an n-channel MOS transistor, has a drain coupled to the first high-potential side power supply of the first power supply system, and has a back gate coupled to the second low-potential side power supply of the second power supply system. A resistor element is inserted in series between the drain of the first transistor and the first high-potential side power supply. | 2022-01-20 |
20220020740 | ISOLATED 3D SEMICONDUCTOR DEVICE PACKAGE - Described implementations provide wireless, surface mounting of at least two semiconductor devices on opposed surfaces of a leadframe, to provide an isolated, three-dimensional (3D) configuration. The described implementations minimize electrical failures, even for very high voltage applications, while enabling low inductance and high current. Resulting semiconductor device packages have mounting surfaces that provide desired levels of isolation and insulation, while still enabling straightforward mounting techniques, such as soldering, as well as high levels of thermal reliability. | 2022-01-20 |
20220020741 | Back Biasing of FD-SOI Circuit Block - A microelectronic circuit structure comprises a stack of bonded layers comprising a bottom layer and at least one upper layer. At least one of the upper layers comprises an oxide layer having a back surface and a front surface closer to the bottom layer than the back surface, and a plurality of FD-SOI transistors built on the from surface. At least a first back gate line and a second back gate line extend separate from each other above the back surface for independently providing a first back gate bias to a first group of transistors and a second back gate bias to a second different group of transistors. | 2022-01-20 |
20220020742 | SEMICONDUCTOR DEVICES - A semiconductor device includes a substrate including first and second active regions extending in a first direction and isolated from direct contact with each other in the first direction; a device isolation layer between the first and second active regions in the substrate; and first and second gate structures extending in a second direction on the substrate while respectively intersecting end portions of the first and second active regions. The first gate structure includes a first gate electrode. The second gate structure includes a second gate electrode. The first gate structure protrudes further toward the device isolation layer, as compared to the second gate structure, in a vertical direction that is perpendicular to the first and second directions, and a lower end of the first gate electrode is located on a lower height level than a lower end of the second gate electrode. | 2022-01-20 |
20220020743 | SELF-ALIGNED ISOLATION FOR SELF-ALIGNED CONTACTS FOR VERTICAL FETS - A method for manufacturing a vertical FET device includes providing a semiconductor substrate structure including a semiconductor substrate and a first semiconductor layer coupled to the semiconductor substrate. The first semiconductor layer is characterized by a first conductivity type. The method also includes forming a plurality of semiconductor fins coupled to the first semiconductor layer. Each of the plurality of semiconductor fins is separated by one of a plurality of recess regions. The method further includes epitaxially regrowing a semiconductor gate layer including a surface region in the plurality of recess regions. The method also includes forming an isolation region within the surface region of the semiconductor gate layer. The isolation region surrounds each of the plurality of semiconductor fins. The method includes forming a source contact structure coupled to each of the plurality of semiconductor fins and forming a gate contact structure coupled to the semiconductor gate layer. | 2022-01-20 |
20220020744 | HIGH PERFORMANCE NANOSHEET FABRICATION METHOD WITH ENHANCED HIGH MOBILITY CHANNEL ELEMENTS - In a method for forming a semiconductor device, an epitaxial layer stack is formed over a substrate. The epitaxial layer stack includes intermediate layers, one or more first nano layers with a first bandgap value and one or more second nano layers with a second bandgap value. Trenches are formed in the epitaxial layer stack to separate the epitaxial layer stack into sub-stacks such that the one or more first nano layers are separated into first nano-channels, and the one or more second nano layers are separated into second nano-channels. The intermediate layers are recessed so that the first nano-channels and the second nano-channels in each of the sub-stacks protrude from sidewalls of the intermediate layers. Top source/drain (S/D) regions are formed in the trenches and in direct contact with the first nano-channels. Bottom source/drain (S/D) regions are formed in the trenches and in direct contact with the second nano-channels. | 2022-01-20 |
20220020745 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a PMOS region and a NMOS region on a substrate, a first fin-shaped structure on the PMOS region, a first single diffusion break (SDB) structure in the first fin-shaped structure, a first gate structure on the first SDB structure, and a second gate structure on the first fin-shaped structure. Preferably, the first gate structure and the second gate structure are of different materials and the first gate structure disposed directly on top of the first SDB structure is a polysilicon gate while the second gate structure disposed on the first fin-shaped structure is a metal gate in the PMOS region. | 2022-01-20 |
20220020746 | HIGH VOLTAGE EXTENDED DRAIN MOSFET (EDMOS) DEVICES IN A HIGH-K METAL GATE (HKMG) - The present disclosure relates to semiconductor devices, and more particularly, to high voltage extended drain MOSFET (EDMOS) devices in a high-k metal gate (HKMG) and methods of manufacture. A structure of the present disclosure includes a plurality of extended drain MOSFET (EDMOS) devices on a high voltage well with a split-gate dielectric material including a first gate dielectric material and a second gate dielectric material, the second gate dielectric material including a thinner thickness than the first gate dielectric material, and a high-k dielectric material on the split-gate dielectric material. | 2022-01-20 |
20220020747 | HAFNIUM OXIDE-BASED FERROELECTRIC FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF - A hafnium oxide-based ferroelectric field effect transistor includes a substrate, an isolation region arranged around the substrate; a gate structure including a buffer layer, a floating gate electrode, a hafnium oxide-based ferroelectric film layer, a control gate electrode and a film electrode layer which are sequentially stacked from bottom to top at a middle part of an upper surface of the substrate, a side wall arranged outside the gate structure, a source region and a drain region arranged oppositely at two sides of the gate structure and are formed by extending from an inner side of the isolation region to the middle part of the substrate, a first metal silicide layer formed by extending from the inner side of the isolation region to the side wall, and a second metal silicide layer arranged on an upper surface of the gate structure. | 2022-01-20 |
20220020748 | METHODS OF FORMING AN APPARATUS INCLUDING LAMINATE SPACER STRUCTURES - An apparatus comprises a conductive structure, another conductive structure, and a laminate spacer structure interposed between the conductive structure and the another conductive structure in a first direction. The laminate spacer structure comprises a dielectric spacer structure, another dielectric spacer structure, and an additional dielectric spacer structure interposed between the dielectric spacer structure and the another dielectric spacer structure. The additional dielectric spacer structure comprises at least one dielectric material, and gas pockets dispersed within the at least one dielectric material. Additional apparatuses, memory devices, electronic systems, and a method of forming an apparatus are also described. | 2022-01-20 |
20220020749 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method of the semiconductor structure includes: providing a substrate; forming on an upper surface of the substrate first patterns each including a first main body and a first flank wall covering a sidewall of the first main body; forming a filling layer which covers the first flank wall and fills a gap between adjacent first patterns; and etching a top of each of the first patterns to obtain second main bodies, second flank walls and protrusions located on upper surfaces of the second flank walls, the second flank wall covering a sidewall of the second main body, and a top of the protrusion being at least higher than a top of the second main body. | 2022-01-20 |
20220020750 | APPARATUS COMPRISING COMPENSATION CAPACITORS - An apparatus comprising first and second interconnections spaced apart from one another, an interlayer insulating material over the first and second interconnections, first and second contacts in the interlayer insulating material and spaced apart from one another, third and fourth interconnections over the interlayer insulating material and spaced apart from one another, and compensation capacitors in a capacitor region. The third interconnections are coupled with the first interconnections through the first contacts and the fourth interconnections are coupled with the second interconnections through the second contacts. The compensation capacitors comprise lower electrodes over the interlayer insulating material, dielectric materials over the lower electrodes, and upper electrodes over the dielectric materials. The lower electrodes comprise edge portions in contact with the second contacts. The third interconnections are elongated over the dielectric materials and are configured to provide elongated portions as the upper electrodes of the compensation capacitors. Related methods, memory devices, and electronic systems are disclosed. | 2022-01-20 |
20220020751 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING SAME - The present application relates to a semiconductor structure and a method of manufacturing the same. The method includes: providing a substrate; forming a bitline contact hole located in the substrate, and a non-metal conductive layer with which a surface of the substrate is covered and the bitline contact hole is filled, the non-metal conductive layer provided with a first opening therein, the first opening aligned with the bitline contact hole; forming a metal conductive layer, with which a surface of the non-metal conductive layer is covered; forming an insulation layer, with which a surface of the metal conductive layer surface is covered; and etching the insulation layer, the metal conductive layer, and the non-metal conductive layer to form a bitline structure. | 2022-01-20 |
20220020752 | METHOD FOR MANUFACTURING A CAPACITOR - A method for manufacturing a capacitor includes: providing a substrate and a multilayer structure; forming a recess in the multilayer structure; forming a first electrode layer on a surface of the recess; performing a selective etching treatment to remove the first and second stack material layers; performing a selective vapor phase etching treatment to the first electrode layer to form a smaller thickness of the first electrode layer; and forming a dielectric layer and a second electrode layer in which the dielectric layer is between the first and second electrode layer. | 2022-01-20 |
20220020753 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device comprises a first gate structure extending in a first direction and including a first gate electrode and a first gate capping pattern, a second gate structure spaced apart from the first gate structure and extending in the first direction, and including a second gate electrode and a second gate capping pattern, an active pattern extending in a second direction, the active pattern below the second gate structure, an epitaxial pattern on one side of the second gate structure and on the active pattern, a gate contact connected to the first gate electrode, and a node contact connected to the second gate electrode and to the epitaxial pattern. An upper surface of the gate contact is at a same level as the first gate capping pattern, and an upper surface of the node contact is lower than the upper surface of the first gate capping pattern. | 2022-01-20 |
20220020754 | DUAL PORT MEMORY CELL WITH IMPROVED ACCESS RESISTANCE - The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell. | 2022-01-20 |
20220020755 | SONOS Memory and Method for Making the Same - The present application discloses a method for manufacturing a SONOS memory, including: providing a substrate, wherein a first transistor gate of the SONOS memory and a first layer used for forming a second transistor gate are formed on the substrate; forming a patterned second layer on the upper surface of the first layer, wherein the second layer exposes the first layer corresponding to the outer side of the second transistor gate; performing first etching on the first layer exposed by the second layer; removing the second layer; and performing second etching on the first layer to form the second transistor gate. The present application also discloses a SONOS memory. The present application can form a vertical structure outside a selective transistor and a storage transistor, thus forming a vertical side wall in the subsequent process, so as to improve the performance of the device. | 2022-01-20 |
20220020756 | Methods of Incorporating Leaker Devices into Capacitor Configurations to Reduce Cell Disturb, and Capacitor Configurations Incorporating Leaker Devices - Some embodiments include an integrated assembly having a row of conductive posts. The conductive posts are spaced from one another by gaps. Leaker device material extends is within at least some of the gaps. An insulative material is along sidewalls of the conductive posts. A conductive structure is over the conductive posts. The conductive structure has downward projections extending into at least some of the gaps. The leaker device material is configured as segments along sides of the downward projections and extends from the sides to one or more of the conductive posts. Some embodiments include methods of forming integrated assemblies. | 2022-01-20 |
20220020757 | SEMICONDUCTOR STORAGE DEVICE AND NEURAL NETWORK DEVICE - A semiconductor storage device according to one embodiment of the present disclosure includes: a substrate; a first storage element formed on the substrate and including a first insulating film; and a second storage element formed on the substrate and including a second insulating film having a film thickness of equal to or greater than 0.5 times and equal to or less than 2 times a film thickness of the first insulating film, the second storage element differing from the first storage element in power consumption at a time of writing. | 2022-01-20 |
20220020758 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a substrate with a cell array region, a first interface region, and a second interface region, the cell array region being provided with active regions, bit lines on the cell array region and the second interface region, dielectric patterns on top surfaces of the bit lines and extending along the top surfaces of the bit lines and further extending onto the first interface region, a device isolation pattern on the substrate, and including a first portion on the cell array region and a second portion on the first interface region, the first portion defining the active regions, the second portion being provided with first recesses, and each first recess being disposed between two adjacent dielectric patterns, and first sacrificial semiconductor patterns disposed on the first interface region and in the first recesses. The first sacrificial semiconductor patterns include polycrystalline silicon. | 2022-01-20 |
20220020759 | Integrated Circuitry, A Method Used In Forming Integrated Circuitry, And A Method Used In Forming A Memory Array Comprising Strings Of Memory Cells - A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The first tiers comprise doped silicon dioxide and the second tiers comprise undoped silicon dioxide. Horizontally-elongated trenches are formed into the stack. Through the trenches, the doped silicon dioxide that is in the first tiers is etched selectively relative to the undoped silicon dioxide that is in the second tiers. Conducting material is formed in the void space in the first tiers that is left by the etching. Structure independent of method is disclosed. | 2022-01-20 |
20220020760 | METHODS OF SEMICONDUCTOR DEVICE FABRICATION - Aspects of the disclosure provide a semiconductor device including a string of transistors stacked in a vertical direction over a substrate of the semiconductor device having a channel structure extending in the vertical direction. The string of transistors includes a first substring arranged along a first portion of the channel structure, a second substring arranged along a second portion of the channel structure, and a third substring arranged along a third portion of the channel structure. The second substring is between the first and the third substrings. Gate structures of transistors in the first substring are separated by first insulating layers. Gate structures of transistors in the second substring are separated by second insulating layers. Gate structures of transistors in the third substring are separated by third insulating layers. A volumetric mass density of the second insulating layers is lower than a volumetric mass density of the third insulating layers. | 2022-01-20 |
20220020761 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a stack of memory cells and a CMOS structure. The CMOS structure is located below the stack of memory cells. The CMOS structure includes a source line transistor and a bit line transistor. | 2022-01-20 |
20220020762 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - A three-dimensional semiconductor memory device includes a peripheral circuit structure having peripheral circuits on a semiconductor substrate, and landing pads connected to the peripheral circuits, an electrode structure on the peripheral circuit structure, the electrode structure including vertically stacked electrodes, a planarized dielectric layer that covers the electrode structure, peripheral through plugs spaced apart from the electrode structure, the peripheral through plugs penetrating the planarized dielectric layer to connect to the landing pads, conductive lines connected through contact plugs, respectively, to the peripheral through plugs, and at least one dummy through plug adjacent to a first peripheral through plug of the peripheral through plugs, the at least one dummy through plug penetrating the planarized dielectric layer and being insulated from the conductive lines. | 2022-01-20 |
20220020763 | Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells - A memory array comprising strings of memory cells comprises an upper stack above a lower stack. The lower stack comprises vertically-alternating lower conductive tiers and lower insulative tiers. The upper stack comprises vertically-alternating upper conductive tiers and upper insulative tiers. An intervening tier is vertically between the upper and lower stacks. The intervening tier is at least predominantly polysilicon and of different composition from compositions of the upper conductive tier and the upper insulative tier immediately-above the intervening tier and of different composition from compositions of the lower conductive tier and the lower insulative tier immediately-below the intervening tier. Channel-material strings of memory cells extend through the upper stack, the intervening tier, and the lower stack. Other structures and methods are disclosed. | 2022-01-20 |
20220020764 | THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A three-dimensional memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a substrate; a first stairway structure and a second stairway structure defined in the electrode structure, and positioned at different heights from each other; a sidewall of the electrode structure formed due to a difference in height between the first stairway structure and the second stairway structure; and a dielectric support passing through the electrode structure, and isolating a corner portion of the sidewall from the plurality of electrode layers. | 2022-01-20 |
20220020765 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD OF THE SAME - According to one embodiment, a semiconductor storage device is provided which includes a stacked body, a first pillar portion, a first separating portion, and a first supporting post. In the stacked body, a plurality of insulating layers and a plurality of electrically conductive layers are stacked alternately one on another. The stacked body is provided on a predetermined electrically conductive film. The first pillar portion includes a plurality of memory cells, and penetrates through the stacked body in a stacking direction of the stacked body. The first separating portion separates the stacked body into a plurality of blocks. The first supporting post extends locally within the stacked body from an upper surface of the predetermined electrically conductive film in the stacking direction. | 2022-01-20 |
20220020766 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor memory device includes a stacked structure on a substrate and a vertical structure penetrating the stacked structure. The stacked structured includes a plurality of conductive lines stacked on the substrate. The vertical structure may include a vertical insulating pattern and a channel film extending along sidewalls of the vertical insulating pattern. The vertical insulating pattern may include an inner region and an outer region. The outer region of the vertical insulating pattern may be placed between the channel film and the inner region of the vertical insulating pattern, and the outer region of the vertical insulating pattern may include a diffused metal. | 2022-01-20 |
20220020767 | Semiconductor memory device and a method of manufacturing the same - A semiconductor memory device including: a common source line; a substrate on the common source line; a plurality of gate electrodes arranged on the substrate and spaced apart from each other in a first direction perpendicular to a top surface of the common source line; a plurality of insulation films arranged among the plurality of gate electrodes; a plurality of channel structures penetrating through the plurality of gate electrodes and the plurality of insulation films in the first direction; and a plurality of residual sacrificial films arranged on the substrate and spaced apart from each other in the first direction, wherein the plurality of gate electrodes are disposed on opposite sides of the plurality of residual sacrificial films. | 2022-01-20 |
20220020768 | Memory Arrays And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells - A memory array comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells are in the stack. The channel-material strings project upwardly from material of an uppermost of the tiers. A first insulator material is above the material of the uppermost tier directly against sides of channel material of the upwardly-projecting channel-material strings. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Second insulator material is above the first insulator material. The first and second insulator materials comprise different compositions relative one another. Conductive vias in the second insulator material are individually directly electrically coupled to individual of the channel-material strings. Other embodiments, including methods, are disclosed. | 2022-01-20 |
20220020769 | SEMICONDUCTOR MEMORY DEVICE AND PRODUCTION METHOD THEREOF - A method of producing a semiconductor memory device includes, when three directions crossing each other are set to first, second, and third directions, respectively, laminating a plurality of first laminates and a plurality of second laminates on a semiconductor substrate in the third direction. The method further includes forming ends of the plurality of first laminates in shapes of steps extending in the first direction, and forming ends of the plurality of second laminates in shapes of steps extending in both directions of the first direction and the second direction. | 2022-01-20 |
20220020770 | Three-Dimensional Memory Device and Method - A semiconductor device and method of manufacture are provided. In embodiments a memory array is formed by manufacturing portions of a word line during different and separate processes, thereby allowing the portions formed first to act as a structural support during later processes that would otherwise cause undesired damage to the structures. | 2022-01-20 |
20220020771 | Three-Dimensional Memory Device and Method - In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched. | 2022-01-20 |
20220020772 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device includes a stacked structure including conductive layers and gaps respectively interposed between the conductive layers, a channel layer passing through the stacked structure, a ferroelectric layer surrounding a sidewall of the channel layer, and first dielectric patterns interposed between the ferroelectric layer and the conductive layers, respectively. The gaps extending between the first dielectric patterns. | 2022-01-20 |
20220020773 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes a stacked structure including conductive layers and insulating layers stacked alternately with each other, a channel layer passing through the stacked structure, a ferroelectric layer surrounding a sidewall of the channel layer, a first dielectric layer surrounding a sidewall of the ferroelectric layer, and sacrificial patterns interposed between the first dielectric layer and the insulating layers and including a material with a higher dielectric constant than the first dielectric layer. | 2022-01-20 |
20220020774 | MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A memory device including a word line, memory cells, source lines and bit lines is provided. The memory cells are embedded in and penetrate through the word line. The source lines and the bit lines are electrically connected the memory cells. A method for fabricating a memory device is also provided. | 2022-01-20 |
20220020775 | THREE-DIMENSIONAL FERROELECTRIC RANDOM ACCESS MEMORY DEVICES AND METHODS OF FORMING - A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a layer stack over a substrate, where the layer stack includes alternating layers of a first dielectric material and a word line (WL) material; forming first trenches extending vertically through the layer stack; filling the first trenches, where filling the first trenches includes forming, in the first trenches, a ferroelectric material, a channel material over the ferroelectric material, and a second dielectric material over the channel material; after filling the first trenches, forming second trenches extending vertically through the layer stack, the second trenches being interleaved with the first trenches; and filling the second trenches, where filling the second trenches includes forming, in the second trenches, the ferroelectric material, the channel material over the ferroelectric material, and the second dielectric material over the channel material. | 2022-01-20 |
20220020776 | MEMORY CELL ARRANGEMENT AND METHODS THEREOF - A memory cell arrangement is provided that may include: a plurality of electrode layers, wherein each of the plurality of electrode layers comprises a plurality of through holes, each of the plurality of through holes extending from a first surface to a second surface of a respective electrode layer; a plurality of electrode pillars, wherein each of the plurality of electrode pillars comprises a plurality of electrode portions, wherein each of the plurality of electrode portions is disposed within a corresponding one of the plurality of through holes; wherein the respective electrode layer and a respective electrode portion of the plurality of electrode portions form a first electrode and a second electrode of a capacitor and wherein at least one memory material portion is disposed in each of the plurality of through holes in a gap between the respective electrode layer and the respective electrode portion. | 2022-01-20 |
20220020777 | DISPLAY DEVICE - A display device includes a display panel including a first display area and a second display area, and a metal layer disposed on a rear side of the display panel. The metal layer includes a light transmitting region disposed corresponding to the second display area. The light transmitting region includes a fine pattern. | 2022-01-20 |
20220020778 | DISPLAY PANEL - A display panel and an electronic device are provided by the present disclosure, wherein the display panel includes a first area, a second area and a third area. The first area includes a plurality of first pixels and a plurality of first signal lines electrically connected with the plurality of first pixels. The second area includes a plurality of second pixels and a plurality of second signal lines electrically connected with the plurality of second pixels. The third area includes a plurality of third pixels and a plurality of third signal lines electrically connected with the plurality of third pixels. The first area, the second area, and the third area have different transmittances. | 2022-01-20 |
20220020779 | Display Module and Display Device - A display includes at least an array substrate, and the array substrate has a drive circuit layer. At least one first notch is provided on an outer edge of a lead-out side of the array substrate, and a first conductor is disposed in each first notch. A first end of the first conductor is in contact with a lead end of the drive circuit layer, and a second end of the first conductor extends along the first notch to a back side of the array substrate. | 2022-01-20 |
20220020780 | THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME, DISPLAY SUBSTRATE, AND DISPLAY DEVICE - A thin film transistor includes a base, a first electrode, an active pattern, a gate insulating layer, a gate and a second electrode. The active pattern includes a first semiconductor pattern, a second semiconductor pattern and a third semiconductor pattern. A material of one of the first semiconductor pattern and the third semiconductor pattern includes a semiconductor material and N-type doped ions, and a material of another of the first semiconductor pattern and the third semiconductor pattern includes the semiconductor material and P-type doped ions. An orthogonal projection of the gate on the base is non-overlapping with an orthogonal projection of the active pattern on the base. | 2022-01-20 |
20220020781 | SEMICONDUCTOR DEVICE, DISPLAY DEVICE INCLUDING THE SEMICONDUCTOR DEVICE, DISPLAY MODULE INCLUDING THE DISPLAY DEVICE, AND ELECTRONIC DEVICE INCLUDING THE SEMICONDUTOR DEVICE, THE DISPLAY DEVICE, AND THE DISPLAY MODULE - To provide a semiconductor device including a planar transistor having an oxide semiconductor and a capacitor. In a semiconductor device, a transistor includes an oxide semiconductor film, a gate insulating film over the oxide semiconductor film, a gate electrode over the gate insulating film, a second insulating film over the gate electrode, a third insulating film over the second insulating film, and a source and a drain electrodes over the third insulating film; the source and the drain electrodes are electrically connected to the oxide semiconductor film; a capacitor includes a first and a second conductive films and the second insulating film; the first conductive film and the gate electrode are provided over the same surface; the second conductive film and the source and the drain electrodes are provided over the same surface; and the second insulting film is provided between the first and the second conductive films. | 2022-01-20 |
20220020782 | DISPLAY SUBSTRATE, PREPARATION METHOD THEREOF AND DISPLAY DEVICE - Provided are a display substrate, a preparation method thereof, and a display device. The display substrate includes: a substrate, a thin film transistor disposed in a pixel island region of the substrate, a first signal line disposed in the pixel island region and a first connecting bridge disposed in a bridge region of the substrate, wherein the first connecting bridge is electrically connected to a gate of the thin film transistor. | 2022-01-20 |
20220020783 | DISPLAY PANEL - The present application proposes a display panel, which includes a substrate, and a first thin film transistor and a second thin film transistor disposed on the substrate at intervals, wherein a first metal layer is disposed on a side of the oxide semiconductor layer away from the third gate, a first interlayer insulating layer is disposed between the first metal layer and the oxide semiconductor layer, a second gate insulating layer is disposed on a side of the first metal layer away from the oxide semiconductor layer, and the first metal layer includes a second gate corresponding to the oxide semiconductor layer. | 2022-01-20 |
20220020784 | DIGITAL CIRCUIT HAVING CORRECTING CIRCUIT AND ELECTRONIC APPARATUS THEREOF - Provided is a digital circuit ( | 2022-01-20 |
20220020785 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device with high aperture ratio is provided. The semiconductor device includes a transistor and a capacitor having a pair of electrodes. An oxide semiconductor layer formed over the same insulating surface is used for a channel formation region of the transistor and one of the electrodes of the capacitor. The other electrode of the capacitor is a transparent conductive film. One electrode of the capacitor is electrically connected to a wiring formed over the insulating surface over which a source electrode or a drain electrode of the transistor is provided, and the other electrode of the capacitor is electrically connected to one of the source electrode and the drain electrode of the transistor. | 2022-01-20 |
20220020786 | PHOTODETECTOR AND METHOD FOR MANUFACTURING PHOTODETECTOR - A light detection device includes a semiconductor substrate. The semiconductor substrate forms an APD and a temperature compensation diode so as to be spaced apart from each other when viewed from a direction perpendicular to a main surface. The semiconductor substrate includes a peripheral carrier absorbing portion surrounding the APD when viewed from the direction perpendicular to the first main surface and configured to absorb carriers located at the periphery. A part of the peripheral carrier absorbing portion is located between the APD and the temperature compensation diode when viewed from the direction perpendicular to the main surface. | 2022-01-20 |
20220020787 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR IMAGE SENSOR, AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first type of light sensing units, where each instance of the first type of light sensing units is operable to receive a first amount of radiation; and a second type of light sensing units, where each instance of the second type of light sensing units is operable to receive a second amount of radiation, and the second type of light sensing units is arranged in an array with the first type of light sensing units to form a pixel sensor. The first amount of radiation is smaller than the second amount of radiation, and at least a first instance of the first type of light sensing units is adjacent to a second instance first type of light sensing unit. | 2022-01-20 |
20220020788 | IMAGE SENSING DEVICE INCLUDING PROTECTION DEVICE - An image sensing device comprising a plurality of unit photosensing pixels to convert light into electrical signals, eachunit photosensing pixel including a photosensor and a plurality of transistors to perform operations associated with the photosensor and a plurality of protection devices, each of which is coupled to any one of the plurality of transistors, wherein each of the plurality of protection devices includes a first region doped with a first type of conductive impurities, a second region doped with a second type of conductive impurities and surrounding the first region, and a third region doped with the first type of conductive impurities and surrounding the second region, wherein the first region includes a contact portion and a first well located below the contact portion, and wherein the contact portion has a higher doping density than the first well, and is coupled to any one of the plurality of transistors. | 2022-01-20 |
20220020789 | PHOTODETECTOR - A sensor includes a first substrate including at least a first pixel. The first pixel includes an avalanche photodiode to convert incident light into electric charge and includes an anode and a cathode. The cathode is in a well region of the first substrate. The first pixel includes an isolation region that isolates the well region from at least a second pixel that is adjacent to the first pixel. The first pixel includes a hole accumulation region between the isolation region and the well region. The hole accumulation region is electrically connected to the anode. | 2022-01-20 |
20220020790 | CELL DEEP TRENCH ISOLATION STRUCTURE FOR NEAR INFRARED IMPROVEMENT - A pixel cell includes a photodiode disposed in a pixel cell region and proximate to a front side of a semiconductor layer to generate image charge in response to incident light directed through a backside to the photodiode. A cell deep trench isolation (CDTI) structure is disposed in the pixel cell region along an optical path of the incident light to the photodiode and proximate to the backside. The CDTI structure includes a central portion extending a first depth from the backside towards the front side. Planar outer portions extend laterally outward from the central portion. The planar output portions further extend a second depth from the backside towards the front side. The first depth is greater than the second depth. Planes formed by each of the planar outer portions intersect in a line coincident with a longitudinal center line of the central portion of the CDTI structure. | 2022-01-20 |