03rd week of 2010 patent applcation highlights part 16 |
Patent application number | Title | Published |
20100012978 | NORMALLY-OFF FIELD-EFFECT SEMICONDUCTOR DEVICE - A normally-off HEMT is made by first providing a substrate having its surface partly covered with an antigrowth mask. Gallium nitride is grown by epitaxy on the masked surface of the substrate to provide an electron transit layer comprised of two flat-surfaced sections and a V-notch-surfaced section therebetween. The flat-surfaced sections are formed on unmasked parts of the substrate surface whereas the V-notch-surfaced section, defining a V-sectioned notch, is created by lateral overgrowth onto the antigrowth mask. Aluminum gallium nitride is then deposited on the electron transit layer to provide an electron supply layer which is likewise comprised of two flat-surfaced sections and a V-notch-surfaced section therebetween. The flat-surfaced sections of the electron supply layer are sufficiently thick to normally generate two-dimensional electron gas layers due to heterojunctions thereof with the first and the second flat-surfaced section of the electron transit layer. The V-notch-surfaced section of the electron supply layer is not so thick, normally creating an interruption in the two-dimensional electron gas layer. | 2010-01-21 |
20100012979 | SUBSTRATE FOR ELECTRO-OPTICAL DEVICE WITH LIGHT SHIELDING SECTION HAVING VARIOUS WIDTHS, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC APPARATUS - Disclosed is a substrate for an electro-optical device including: a substrate; a plurality of data lines and a plurality of scanning lines which intersect with other on the substrate; a pixel electrode formed in each of a plurality of pixels which configure a display region on the substrate and are defined in correspondence with intersections between the plurality of data lines and the plurality of scanning lines; a transistor provided in each of non-opening regions which discriminate between opening regions of the plurality of pixels and including a semiconductor layer including a channel region having a channel length in one direction of the display region, a data line side source/drain region electrically connected to the data line, a pixel electrode side source/drain region electrically connected to the pixel electrode, a first junction region formed between the channel region and the data line side source/drain region, and a second junction region formed between the channel region and the pixel electrode side source/drain region; and a light-shielding section which is formed above each of the semiconductor layers, extends along the one direction, and includes a first portion which covers the first junction region and a second portion which covers the second junction region and has a width larger than that of the first portion in a direction intersecting the one direction. | 2010-01-21 |
20100012980 | Contact Structures in Substrate Having Bonded Interface, Semiconductor Device Including the Same, Methods of Fabricating the Same - On embodiment of a contact structure may include a lower insulation layer on a lower substrate, an upper substrate on the lower insulation layer, a groove penetrating the upper substrate to extend into the lower insulation layer, the groove below an interface between the upper substrate and the lower insulation layer, an upper insulation layer in the groove, and a contact plug penetrating the upper insulation layer in the groove to extend into the lower insulation layer. | 2010-01-21 |
20100012981 | Semiconductor Device Portion Having Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing and Having Corresponding Non-Symmetric Diffusion Regions - A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein in a non-symmetrical manner relative to a virtual line defined to bisect the substrate portion. The semiconductor device includes a gate electrode level region including a number of conductive features defined to extend in only a first parallel direction. Adjacent ones of the number of conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level region includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. | 2010-01-21 |
20100012982 | Semiconductor Device Portion Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing and Having Corresponding Non-Symmetric Diffusion Regions - A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein in a non-symmetrical manner relative to a virtual line defined to bisect the substrate portion. The semiconductor device includes a gate electrode level region including a number of conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features separated by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. Conductive features are defined along at least four different virtual lines of extent in the first parallel direction. A width of the conductive features is less than a wavelength of light used in a photolithography process for their fabrication. | 2010-01-21 |
20100012983 | Semiconductor Device Portion Having Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having Equal Number of PMOS and NMOS Transistors - A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. The semiconductor device includes a gate electrode level region including a number of conductive features defined to extend in only a first parallel direction. Adjacent ones of the number of conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. Some of the conductive features within the gate electrode level region extend over the plurality of diffusion regions to form PMOS or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level region. | 2010-01-21 |
20100012984 | Semiconductor Device Portion Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having Equal Number of PMOS and NMOS Transistors - A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. A gate electrode level region is formed above the substrate portion to include conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a substantially equal and minimum size across the gate electrode level region. A width of the conductive features is less than a wavelength of light used in a photolithography process for their fabrication. Some of the conductive features extend over the plurality of diffusion regions to form PMOS or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level region. | 2010-01-21 |
20100012985 | Semiconductor Device Portion Having Sub-193 Nanometers -Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having At Least Eight Transistors - A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. A gate electrode level region is formed above the substrate portion to include conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent are fabricated from respective originating layout features separated from each other by an end-to-end spacing of substantially equal and minimum size across the gate electrode level region. A width of the conductive features within a 5 wavelength photolithographic interaction radius is less than a 193 nanometer wavelength of light used in a photolithography process for their fabrication. Some conductive features extend over the plurality of diffusion regions to form PMOS or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the gate electrode level region is greater than or equal to eight. | 2010-01-21 |
20100012986 | Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors - A cell of a semiconductor device includes a substrate portion formed to include a plurality of diffusion regions, including at least one p-type diffusion region and at least one n-type diffusion region separated from each other by one or more non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level of the cell. The cell also includes a number of interconnect levels formed above the gate electrode level. | 2010-01-21 |
20100012987 | Field Effect Transistor Based Sensor - The invention discloses a FET based sensor. The FET based sensor according to an embodiment of the invention includes a substrate, an InN material layer, a source terminal and a drain terminal. The InN material layer is formed over the substrate and has an upper surface. The upper surface thereon provides an analyte sensing region. The InN material layer serves as a current channel between the source terminal and the drain terminal. Thereby, ions adsorbed by the analyte sensing region induce a variation of a current flowing through the current channel, and the variation is further interpreted as a characteristic of the analyte. | 2010-01-21 |
20100012988 | METAL OXIDE SEMICONDUCTOR DEVICES HAVING IMPLANTED CARBON DIFFUSION RETARDATION LAYERS AND METHODS FOR FABRICATING THE SAME - Semiconductor devices and methods for fabricating semiconductor devices are provided. One exemplary method comprises providing a silicon-comprising substrate having a first surface, etching a recess into the first surface, the recess having a side surface and a bottom surface, implanting carbon ions into the side surface and the bottom surface, and forming an impurity-doped, silicon-comprising region overlying the side surface and the bottom surface. | 2010-01-21 |
20100012989 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device, and a method of fabricating the semiconductor device, which is able to prevent a leaning phenomenon from occurring between the adjacent storage nodes. The method includes forming a plurality of multi-layered pillar type storage nodes each of which is buried in a plurality of mold layers, wherein the uppermost layers of the multi-layered pillar type storage nodes are fixed by a support layer, etching a portion of the support layer to form an opening, and supplying an etch solution through the opening to remove the multiple mold layers. A process of depositing and etching the mold layer by performing the process 2 or more times to form the multi-layered pillar type storage node. Thus, the desired capacitance is sufficiently secured and the leaning phenomenon is avoided between adjacent storage nodes. | 2010-01-21 |
20100012990 | MOSFETS INCLUDING CRYSTALLINE SACRIFICIAL STRUCTURES - A sub-micron channel length MOSFET includes a seamless epitaxial channel region in a substrate of the MOSFET and a buried device isolation layer beneath the seamless epitaxial channel region. In some embodiments according to the invention, a buried device isolation layer includes the buried device isolation layer beneath a central portion of the seamless epitaxial channel and absent from sidewalls of source/drain regions of the MOSFET. | 2010-01-21 |
20100012991 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device, comprising: forming n-channel field-effect transistors on a silicon substrate; forming a first insulating film covering the field-effect transistors; shrinking the first insulating film; forming a second insulating film over the first insulating film; and shrinking the second insulating film, wherein the forming an insulating film covering the field-effect transistors and the shrinking the insulating film are repeated a plurality of time. | 2010-01-21 |
20100012992 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a Metal Insulator Semiconductor (MIS) transistor over a semiconductor substrate, forming a nickel silicide layer on a surface of source/drain region of the MIS transistor, the nickel silicide layer containing platinum or tungsten, forming a stress film over the surface of the MIS transistor, and selectively removing the stress film so as to expose at least a part of the nickel silicide layer on the surface of source/drain region. | 2010-01-21 |
20100012993 | SOLID-STATE IMAGING DEVICE - A solid-state imaging device includes a photodiode array having a plurality of photodiodes, read transistors each having one terminal and the other terminal of a current path, one terminal of the current path being connected to each of four photodiodes corresponding to two photodiodes adjacent in a row direction and two photodiodes adjacent in a column direction, the other terminal of the current path being connected in common to a first node, the first node provided as a set of four photodiodes being in a floating-state, read control lines to connect the gate of the read transistor corresponding to each set of the read transistors in common, and independently supplied with a read signal, and vertical signal lines supplied with a signal converted by two photodiodes adjacent in a row direction of the photodiodes for an independent period within one horizontal blanking period of image scanning. | 2010-01-21 |
20100012994 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device has the ferroelectric capacitor has: a capacitor film formed above the MOS transistor with an interlayer insulating film interposed therebetween; a first capacitor electrode electrically connected to a source region of the MOS transistor and formed in contact with one side wall of the capacitor film; and a second capacitor electrode electrically connected to a drain region of the MOS transistor and formed in contact with the other side wall of the capacitor film, and the capacitor film is composed of a film stack including a plurality of films including a first insulating film intended to orient a film formed on an upper surface thereof in a predetermined direction and a ferroelectric film formed on the first insulating film to be oriented in a direction perpendicular to the semiconductor substrate. | 2010-01-21 |
20100012995 | LOCALIZED BIASING FOR SILICON ON INSULATOR STRUCTURES - A silicon-on-insulator device has a localized biasing structure formed in the insulator layer of the SOI. The localized biasing structure includes a patterned conductor that provides a biasing signal to distinct regions of the silicon layer of the SOI. The conductor is recessed into the insulator layer to provide a substantially planar interface with the silicon layer. The conductor is connected to a bias voltage source. In an embodiment, a plurality of conductor is provided that respectively connected to a plurality of voltage sources. Thus, different regions of the silicon layer are biased by different bias signals. | 2010-01-21 |
20100012996 | DYNAMIC RANDOM ACCESS MEMORY STRUCTURE - A dynamic random access memory structure comprises a substrate having a first diffusion region and a second diffusion region, a dielectric structure overlaying the substrate, a capacitor contact plug disposed in the dielectric structure and connected to the first diffusion region, a bit-line contact plug disposed in the dielectric structure and connected to the second diffusion region, a metal silicide disposed on the capacitor contact plug, and a capacitive structure disposed on the dielectric structure and connected to the metal silicide. | 2010-01-21 |
20100012997 | 3-DIMENSIONAL FLASH MEMORY DEVICE, METHOD OF FABRICATION AND METHOD OF OPERATION - Disclosed are a flash memory device and method of operation. The flash memory device includes a bottom memory cell array and a top memory cell array disposed over the bottom memory cell array. The bottom memory cell array includes a bottom semiconductor layer, a bottom well, and a plurality of bottom memory cell units. The top memory cell array includes a top semiconductor layer, a top well, and a plurality of top memory cell units. A well bias line is disposed over the top memory cell array and includes a bottom well bias line and a top well bias line, The bottom well bias line is electrically connected to the bottom well, and the top well bias line is electrically connected to the top well. | 2010-01-21 |
20100012998 | FLASH MEMORY DEVICE WITH STACKED DIELECTRIC STRUCTURE INCLUDING ZIRCONIUM OXIDE AND METHOD FOR FABRICATING THE SAME - A dielectric structure disposed between a floating gate and a control gate of a flash memory device includes: a first dielectric layer; a third dielectric layer having a k-dielectric constant substantially the same as that of the first dielectric layer; and a second dielectric layer disposed between the first dielectric layer and the third dielectric layer, having a greater k-dielectric constant than that of the first and third dielectric layers and formed by alternately and repeatedly stacking a plurality of aluminum oxide (Al | 2010-01-21 |
20100012999 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device comprises two gate electrodes on a semiconductor substrate between device isolation regions, a common source region on the semiconductor substrate between the two gate electrodes, a drain region on the semiconductor substrate at outer sides of the two gate electrodes, a spacer on the drain region and on outer sidewalls of the two gate electrodes, a third oxide layer on inner sidewalls of the two gate electrodes, and a silicide layer on the common source region. | 2010-01-21 |
20100013000 | MEMORY APPARATUS - The memory apparatus includes a memory device including a gate insulating layer formed on a silicon substrate by sequentially stacking a tunnel oxide layer, a charge trap layer, and a block oxide layer in this order, on the silicon substrate. In addition, a gate electrode is formed on the gate insulating layer. The block oxide layer is formed by stacking a first block oxide layer and a second block oxide layer, wherein the first block oxide layer is adjacent to the charge trap layer and the second block oxide layer is adjacent to the gate electrode. The second block oxide layer is formed of a dielectric material having higher permittivity than that of the first block oxide layer and having higher electron affinity than that of the first block oxide layer. | 2010-01-21 |
20100013001 | METHOD FOR MANUFACTURING NON-VOLATILE MEMORY AND STRUCTURE THEREOF - A method for manufacturing a non-volatile memory and a structure thereof are provided. The manufacturing method comprises the following steps. Firstly, a substrate is provided. Next, a semiconductor layer is formed on the substrate. Then, a Si-rich dielectric layer is formed on the semiconductor layer. After that, a plurality of silicon nanocrystals is formed in the Si-rich dielectric layer by a laser annealing process to form a charge-storing dielectric layer. Last, a gate electrode is formed on the charge-storing dielectric layer. | 2010-01-21 |
20100013002 | NONVOLATILE STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided is an excellent nonvolatile storage device having advantageous in miniaturization and less variation in initial threshold value, and exhibiting a high writing efficiency, without an erasing failure and a retention failure. The nonvolatile storage device is characterized by including a film stack extending from between a semiconductor substrate and a gate electrode onto at least a surface of the gate electrode lying on a first impurity diffusion region side, the film stack including a charge accumulating layer and a tunnel insulating film sequentially from a gate electrode side. | 2010-01-21 |
20100013003 | NON-VOLATILE MEMORY CELL WITH A HYBRID ACCESS TRANSISTOR - An integrated circuit (IC) is disclosed. The IC comprises a substrate with a cell region defined thereon. The cell region comprises a thin gate doped well tailored for transistors with thin gate dielectric layers. The IC also includes a non-volatile memory cell in the cell region. The non-volatile memory cell has an access transistor and a storage transistor. The access transistor includes an access gate with an access gate dielectric comprising a thick gate dielectric layer on the thin gate doped well. Wells for transistors with thick gate dielectric layers have a lower dopant concentration than the thin gate doped well. | 2010-01-21 |
20100013004 | RECESSED CHANNEL TRANSISTOR AND METHOD FOR PREPARING THE SAME - A recessed channel transistor comprises a semiconductor substrate having a trench isolation structure, a gate structure having a lower block in the semiconductor substrate and an upper block on the semiconductor substrate, two doped regions positioned at two sides of the upper block and above the lower block, and an insulation spacer positioned at a sidewall of the upper block and having a bottom end sandwiched between the upper block and the doped regions. In particular, the two doped regions serves as the source and drain regions, respectively, and the lower block of the gate structure serves as the recessed gate of the recessed channel transistor. | 2010-01-21 |
20100013005 | INTEGRATED CIRCUIT INCLUDING A VERTICAL TRANSISTOR AND METHOD - An integrated circuit including a vertical transistor and method of manufacturing. In one embodiment a vertical transistor is formed in a pillar of a semiconductor substrate. A buried conductive line is separated from the semiconductor substrate by a first insulating layer in a first portion and is electrically coupled to a buried source/drain region of the vertical transistor through a contact structure. A second insulating layer is arranged above and adjacent to the contact structure. At least one of the first and second insulating layers includes a dopant. A doped region is formed in the semiconductor substrate at an interface to the at least one insulating layer. The doped region has a dopant concentration higher than a substrate dopant concentration. | 2010-01-21 |
20100013006 | SEMICONDUCTOR DEVICE - A semiconductor device has a semiconductor substrate having a surface layer and a p-type semiconductor region, wherein the surface layer includes a contact region, a channel region and a drift region, the channel region is adjacent to and in contact with the contact region, the drift region is adjacent to and in contact with the channel region and includes n-type impurities at least in part, and the p-type semiconductor region is in contact with the drift region and at least a portion of a rear surface of the channel region, a main electrode disposed on the surface layer and electrically connected to the contact region, a gate electrode disposed on the surface layer and extending from above a portion of the contact region to above at least a portion of the drift region via above the channel region, and an insulating layer covering at least the portion of the contact region and not covering at least the portion of the drift region. The gate electrode and the contact region are insulated by the insulating layer, and the gate electrode and the drift region are in direct contact to form a Schottky junction. | 2010-01-21 |
20100013007 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device ( | 2010-01-21 |
20100013008 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The invention prevents a semiconductor device from warping due to heat when it is used. The invention also prevents a formation defect such as peeling of a resist layer used as a plating mask and a formation defect of a front surface electrode. A source pad electrode connected to a source region is formed on a front surface of a semiconductor substrate forming a vertical MOS transistor. A front surface electrode is formed on the source pad -electrode by a plating method using a resist layer having openings as a mask. The semiconductor substrate formed with the front surface electrode is thinned by back-grinding. A back surface electrode connected to a drain region is formed on the back surface of the semiconductor substrate. The front surface electrode and the back surface electrode are made of metals having the same coefficients of linear expansion, preferably copper. The front surface electrode and the back surface electrode preferably have the same thicknesses or almost the same thicknesses. | 2010-01-21 |
20100013009 | Structure and Method for Forming Trench Gate Transistors with Low Gate Resistance - A field effect transistor includes body regions of a first conductivity type over a semiconductor region of a second conductivity type such that the body regions form p-n junctions with the semiconductor region. Trenches extend through the body region and terminate within the semiconductor region. Source regions of the second conductivity type extend over the body regions adjacent the trenches such that the source regions form p-n junctions with the body regions. A gate dielectric layer lines sidewalls of each trench. A metal liner lines the gate dielectric layer in each trench. A gate electrode comprising metallic material is disposed in each trench. | 2010-01-21 |
20100013010 | POWER SEMICONDUCTOR DEVICE - An impurity concentration profile in a vertical direction of a p type base contact layer of a power semiconductor device has a two-stage configuration. In other word, the impurity concentration profile is highest at an upper face of the p type base contact layer, has a local minimum value at a position other than the upper face and a lower face of the base contact layer, and has a local maximum value at a position lower than the position of the local minimum value. | 2010-01-21 |
20100013011 | VERTICAL MOSFET WITH THROUGH-BODY VIA FOR GATE - In an embodiment, set forth by way of example and not limitation, a MOSFET power chip includes a first vertical MOSFET and a second vertical MOSFET. The first vertical MOSFET includes a semiconductor body having a first surface defining a source and a second surface defining a drain and a gate structure formed in the semiconductor body near the second surface. A via is formed within the semiconductor body and is substantially perpendicular to the first surface and the second surface. The via has a first end electrically coupled to the first surface and a second end electrically coupled to the gate structure. The second vertical MOSFET includes a semiconductor body having a first surface defining a source, a second surface defining a drain and a gate structure formed in the semiconductor body near the first surface. The first surface of the first vertical MOSFET and the second surface of the second vertical MOSFET are substantially co-planar and an electrically conductive can substantially surrounds the MOSFETS and shorts the first surface of the first vertical MOSFET to the second surface of the second vertical MOSFET. | 2010-01-21 |
20100013012 | INTEGRATED COMPLEMENTARY LOW VOLTAGE RF-LDMOS - Complementary RF LDMOS transistors have gate electrodes over split gate oxides. A source spacer of a second conductivity type extends laterally from the source tap of a first conductivity type to approximately the edge of the gate electrode above the thinnest gate oxide. A body of a first conductivity type extends from approximately the bottom center of the source tap to the substrate surface and lies under most of the thin section of the split gate oxide. The source spacer is approximately the length of the gate sidewall oxide and is self aligned with gate electrode. The body is also self aligned with gate electrode. The drain is surrounded by at least one buffer region which is self aligned to the other edge of the gate electrode above the thickest gate oxide and extends to the below the drain and extends laterally under the thickest gate oxide. Both the source tap and drain are self aligned with the gate side wall oxides and are thereby spaced apart laterally from the gate electrode. | 2010-01-21 |
20100013013 | 1T/0C RAM CELL WITH A WRAPPED-AROUND GATE DEVICE STRUCTURE - A memory device and a method of forming the memory device. The memory device comprises a storage transistor at a surface of a substrate comprising a body portion between first and second source/drain regions, wherein the source/drain regions are regions of a first conductivity type. The storage transistor also comprises a gate structure that wraps at least partially around the body portion in at least two spatial planes. A bit line is connected to the first source/drain region and a word line connected to the gate structure. The memory device does not require an additional capacitive storage element. | 2010-01-21 |
20100013014 | FIELD EFFECT TRANSISTOR HAVING SOURCE AND/OR DRAIN FORMING SCHOTTKY OR SCHOTTKY-LIKE CONTACT WITH STRAINED SEMICONDUCTOR SUBSTRATE - The present invention is a field effect transistor having a strained semiconductor substrate and Schottky-barrier source and drain electrodes, and a method for making the transistor. The bulk charge carrier transport characteristic of the Schottky barrier field effect transistor minimizes carrier surface scattering, which enables the strained substrate to provide improved power and speed performance characteristics in this device, as compared to conventional devices. | 2010-01-21 |
20100013015 | METAL SOURCE/DRAIN SCHOTTKY BARRIER SILICON-ON-NOTHING MOSFET DEVICE - A Schottky barrier MOSFET (SB-MOS) device and a method of manufacturing having a silicon-on-nothing (SON) architecture in a channel region are provided. More specifically, metal source/drain SB-MOS devices are provided in combination with a channel structure comprising a semiconductor channel region such as silicon isolated from a bulk substrate by an SON dielectric layer. In one embodiment, the SON dielectric layer has a triple stack structure comprising oxide on nitride on oxide, which is in contact with the underlying semiconductor substrate. | 2010-01-21 |
20100013016 | ESD Protection Structures on SOI Substrates - An electrostatic discharge (ESD) protection circuit includes a buried oxide layer; a semiconductor layer on the buried oxide layer; and a first and a second MOS device. The first MOS device includes a first gate over the semiconductor layer; a first well region having a portion underlying the first gate; and a first source region and a first drain region in the semiconductor layer. The second MOS device includes a second gate over the semiconductor layer; and a second well region having a portion underlying the first gate. The second well region is connected to a discharging node. The first well region is connected to the discharging node through the second well region, and is not directly connected to the discharging node. The second MOS device further includes a second source region and a second drain region in the semiconductor layer and adjoining the second well region. | 2010-01-21 |
20100013017 | Method of manufacturing semiconductor device, and semiconductor device - A method of manufacturing a semiconductor device including implanting an element selected from fluorine and nitrogen, over the entire region of a semiconductor substrate; oxidizing the semiconductor substrate to thereby form a first oxide film over the surface of the semiconductor substrate; selectively removing the first oxide film in a partial region; oxidizing the semiconductor substrate in the partial region to thereby form a second oxide film thinner than the first oxide film in the partial region; and forming gates to thereby form transistors. | 2010-01-21 |
20100013018 | CMOS TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - In a complementary metal-oxide semiconductor (CMOS) transistor and a method of manufacturing the same, a semiconductor channel material having a first conductivity type is provided on a substrate. A first transistor having the first conductivity type and a second transistor having a second conductivity type are positioned on the substrate, respectively. The first transistor includes a first gate positioned on a first surface of the channel material through a medium of a gate insulation layer and a pair of ohmic contacts positioned on a second surface of the channel material and crossing over both side portions of the first gate electrode, respectively. The second transistor includes a second gate positioned on the first surface of the channel material through a medium of the gate insulation layer and a pair of Schottky contacts positioned on the second surface of the channel material and crossing over both side portions of the second gate electrode, respectively. | 2010-01-21 |
20100013019 | STRESSED DIELECTRIC DEVICES AND METHODS OF FABRICATING SAME - A structure and a method of making the structure. The structure includes a field effect transistor including: a first and a second source/drain formed in a silicon substrate, the first and second source/drains spaced apart and separated by a channel region in the substrate; a gate dielectric on a top surface of the substrate over the channel region; and an electrically conductive gate on a top surface of the gate dielectric; and a dielectric pillar of a first dielectric material over the gate; and a dielectric layer of a second dielectric material over the first and second source/drains, sidewalls of the dielectric pillar in direct physical contact with the dielectric layer, the dielectric pillar having no internal stress or an internal stress different from an internal stress of the dielectric layer. | 2010-01-21 |
20100013020 | Semiconductor device with semi-insulating substrate portions - A semiconductor substrate includes semi-insulating portions beneath openings in a patterned hardmask film formed over a semiconductor substructure to a thickness sufficient to prevent charged particles from passing through the hardmask. The semi-insulating portions include charged particles and may extend deep into the semiconductor substrate and electrically insulate devices formed on opposed sides of the semi-insulating portions. The charged particles may advantageously be protons and further substrate portions covered by the patterned hardmask film are substantially free of the charged particles. | 2010-01-21 |
20100013021 | METHOD TO REDUCE THRESHOLD VOLTAGE (Vt) IN SILICON GERMANIUM (SIGE), HIGH-K DIELECTRIC-METAL GATE, P-TYPE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS - Disclosed are embodiments of a p-type, silicon germanium (SiGe), high-k dielectric-metal gate, metal oxide semiconductor field effect transistor (PFET) having an optimal threshold voltage (Vt), a complementary metal oxide semiconductor (CMOS) device that includes the PFET and methods of forming both the PFET alone and the CMOS device. The embodiments incorporate negatively charged ions (e.g., fluorine (F), chlorine (Cl), bromine (Br), iodine (I), etc.) into the high-k gate dielectric material of the PFET only so as to selectively adjust the negative Vt of the PFET (i.e., so as to reduce the negative Vt of the PFET). | 2010-01-21 |
20100013022 | Semiconductor device with multiple gate dielectric layers and method for fabricating the same - Disclosed are a semiconductor device with dual gate dielectric layers and a method for fabricating the same. The semiconductor device includes: a silicon substrate divided into a cell region where NMOS transistors are formed and a peripheral region where NMOS and PMOS transistors are formed; a targeted silicon oxide layer formed on the silicon substrate in the cell region; an oxynitride layer formed on the silicon substrate in the peripheral region; a first gate structure formed in the cell region; a second gate structure formed on the oxynitride layer in an NMOS region of the peripheral region; and a third gate structure formed on the oxynitride layer in a PMOS region of the peripheral region. | 2010-01-21 |
20100013023 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A semiconductor device includes a first MISFET having a first conduction type channel and formed on a semiconductor substrate; a second MISFET having a second conduction type channel and formed on the semiconductor substrate; a first strain film having a first sign strain that covers a region where the second MISFET is disposed; and a second strain film having a second sign strain that covers a region where the first MISFET is disposed. In the semiconductor device, an edge of the second strain film closer to the second MISFET overlaps with part of the first strain film; and the second strain film at a portion where the second strain film overlaps with the first strain film and at a portion extending from the portion, is thinner than the second strain film at a portion that covers the first MISFET. | 2010-01-21 |
20100013024 | HIGH PERFORMANCE STRESS-ENHANCE MOSFET AND METHOD OF MANUFACTURE - The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET and varying thickness of the PFET and NFET channel. In one embodiment, the structure enhances the device performance by varying the thickness of the top Silicon layer respective to the NFET or the PFET. | 2010-01-21 |
20100013025 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a second direction, in a plan view, an n-channel MOS transistor and an expanding film are adjacent. Therefore, the n-channel MOS transistor receives a positive stress in the direction in which a channel length is extended from the expanding film. As a result, a positive tensile strain in an electron moving direction is generated in a channel of the n-channel MOS transistor. On the other hand, in the second direction, in a plan view, a p-channel MOS transistor and the expanding film are shifted from each other. Therefore, the p-channel MOS transistor receives a positive stress in the direction in which a channel length is narrowed from the expanding film. As a result, a positive compressive strain in a hole moving direction is generated in a channel of the p-channel MOS transistor. Thus, both on-currents of the n-channel MOS transistor and the p-channel MOS transistor can be improved. | 2010-01-21 |
20100013026 | INTEGRATED CIRCUITS COMPRISING RESISTORS HAVING DIFFERENT SHEET RESISTANCES AND METHODS OF FABRICATING THE SAME - The fabrication of integrated circuits comprising resistors having the same structure but different sheet resistances is disclosed herein. In one embodiment, a method of fabricating an integrated circuit comprises: concurrently forming a first resistor laterally spaced from a second resistor above or within a semiconductor substrate, the first and second resistors comprising a doped semiconductive material; depositing a dopant receiving material across the first and second resistors and the semiconductor substrate; removing the dopant receiving material from upon the first resistor while retaining the dopant receiving material upon the second resistor; and annealing the first and second resistors to cause a first sheet resistance of the first resistor to be different from a second sheet resistance of the second resistor. | 2010-01-21 |
20100013027 | Semiconductor device and method of manufacturing the same - A semiconductor device having a DRAM region and a logic region embedded together therein, including a first transistor formed in a DRAM region, and having a first source/drain region containing arsenic and phosphorus as impurities; and a second transistor formed in a logic region, and having a second source/drain region containing at least arsenic as an impurity, wherein each of the first source/drain region and the second source/drain region has a silicide layer respectively formed in the surficial portion thereof, and the first source/drain region has a junction depth which is determined by phosphorus and is deeper than the junction depth of the second source/drain region. | 2010-01-21 |
20100013028 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device with a high-voltage transistor and a low-voltage transistor includes an isolation insulating film between a first element region of the high-voltage transistor and a second element region of the low-voltage transistor, a first gate insulating film on a semiconductor substrate in the first element region, a first gate electrode on the first gate insulating film, a second gate insulating film on the semiconductor substrate in the second element region, and a second gate electrode on the second gate insulating film. The isolation insulating film includes a first isolation region adjacent to a surrounding area of the first element region and a second isolation region adjacent to a surrounding area of the second element region. A bottom of the second isolation region is lower than a bottom of the first isolation region. The first gate insulating film is thicker than the second gate insulating film. | 2010-01-21 |
20100013029 | Structure and a Method of Manufacture for Low Resistance NiSix - A device and a method for forming a metal silicide is presented. A device, which includes a gate region, a source region, and a drain region, is formed on a substrate. A metal is disposed on the substrate, followed by a first anneal, forming a metal silicide on at least one of the gate region, the source region, and the drain region. The unreacted metal is removed from the substrate. The metal silicide is implanted with atoms. The implant is followed by a super anneal of the substrate. | 2010-01-21 |
20100013030 | BIOSENSOR, MANUFACTURING METHOD THEREOF, AND BIOSENSING APPARATUS INCLUDING THE SAME - Provided is a biosensor with a three-dimensional multi-layered structure, a method for manufacturing the biosensor, and a biosensing apparatus including the biosensor. The biosensing apparatus includes: a chamber having an inlet through which a fluid containing a biomaterial enters and an outlet through which the fluid exits; and a plurality of biosensors inserted and fixed in the chamber. Each biosensor includes: a support unit having a fluid channel through which a fluid containing a biomaterial flows; and a sensing unit disposed on the support unit in such a way that the sensing unit is exposed three-dimensionally in the fluid channel of the support unit, the sensing unit being surface-treated with a reactive material that is to react with the biomaterial flowing through the fluid channel. | 2010-01-21 |
20100013031 | MEMS Substrates, Devices, and Methods of Manufacture Thereof - Micro-electromechanical system (MEMS) substrates, devices, and methods of manufacture thereof are disclosed. In one embodiment, a MEMS device includes a workpiece having an isolation ring in a top portion thereof, and a moveable element disposed within the isolation ring. | 2010-01-21 |
20100013032 | Method for Housing an Electronic Component in a Device Package and an Electronic Component Housed in the Device Package - A method for housing an electronic component in a device package includes providing a first substrate, wherein the electronic component is arranged in a component area on a first main surface of the first substrate, and wherein first contact pads are arranged outside of the component area, forming an open top frame structure around the component area on the first main surface of the first substrate, providing a second substrate having second contact pads, arranged symmetrically to the first contact pads and electrically and mechanically connecting the first main surface of the first substrate with the first main surface of the second substrate, so that the frame structure and the second substrate from a cavity or recess around the electronic component on the first substrate. | 2010-01-21 |
20100013033 | Enablement of IC devices during assembly - A method for packaging sensitive micro devices and devices formed by the method are presented. The method comprises acts of standard packaging, but with the devices' protective layers remaining intact until before sealing. Three principle acts of the method include (1) singulating the devices into individuals or subsets, (2) attaching the devices with packaging, and (3) hermetically sealing the devices. One may wire-bond the devices as well as remove the sacrificial layer before hermetically sealing. This method is especially useful for micro-electro-mechanical systems (MEMS) whereby the movable components are protected. | 2010-01-21 |
20100013034 | ELECTROMECHANICAL DEVICE COMPRISING ELECTRONIC COMPONENTS AND AT LEAST ONE NANOTUBE-BASED INTERFACE, AND MANUFACTURING METHOD - The invention relates to an electromechanical device comprising a package and at least one component surface-mounted in the package, characterized in that it also comprises at least one nanotube-based interface providing a mechanical link for vibratory and thermal filtering between said component and the package. | 2010-01-21 |
20100013035 | Integrated Circuit, Memory Module, and Method of Manufacturing an Integrated Circuit - An integrated circuit includes a plurality of magnetic tunneling junction stacks, each magnetic tunneling junction stack including a reference layer, a barrier layer and a free layer, wherein the plurality of magnetic tunneling junction stacks share a continuous common reference layer. | 2010-01-21 |
20100013036 | Thin Sacrificial Masking Films for Protecting Semiconductors From Pulsed Laser Process - The present disclosure is directed to systems and methods for protecting a semiconductor product or material from harmful effects of pulsed laser irradiation. In some embodiments, a thin sacrificial protective mask layer that expires after one laser processing operation is applied to the surface of the product or material to be laser-treated. The thin protective mask layer reflects, absorbs, or otherwise protects the underlying product or material from the energy of the laser. | 2010-01-21 |
20100013037 | SOLAR CELL AND MANUFACTURING METHOD THEREOF - A method for manufacturing a solar cell is provided. The manufacturing method includes: depositing a transparent conductive layer on a substrate; patterning the transparent conductive layer; forming a semiconductor layer including deposited on the patterned transparent conductive layer; patterning the semiconductor layer; coating a metal powder on the patterned semiconductor layer; forming a rear electrode layer on the semiconductor layer coated with the metal powder; and patterning the rear electrode layer and the semiconductor layer. This method is useful for producing a solar cell with improved light absorption efficiency. | 2010-01-21 |
20100013038 | PHOTO-SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A photo-semiconductor device comprises a photoconductive semiconductor film provided with electrodes and formed on a second substrate, the semiconductor film being formed by epitaxial growth on a first semiconductor substrate different from the second substrate, the second substrate being also provided with electrodes, the electrodes of the second substrate and the electrodes of the photoconductive semiconductor film being held in contact with each other. | 2010-01-21 |
20100013039 | Backside-illuminated imaging sensor including backside passivation - The disclosure describes embodiments of a process comprising forming a pixel on a frontside of a substrate, the substrate having a frontside, a backside, and a thickness substantially equal to a distance between the frontside and the backside. The thickness of the substrate is reduced by removing material from the backside of the substrate to allow for backside illumination of the pixel, and the backside of the substrate is treated with a hydrogen plasma to passivate the backside. The disclosure also describes embodiments of an apparatus comprising a semiconductor wafer having a frontside, a backside, and a thickness substantially equal to a distance between the frontside and the backside, and a pixel formed on the frontside, wherein the thickness of the wafer is selected and adjusted to allow for illumination of the pixel through the backside of the wafer, and wherein the backside is treated with a hydrogen plasma to passivate the backside. | 2010-01-21 |
20100013040 | PHOTODIODE - A photodiode includes: an upper spacer layer including a semiconductor transparent to incident light; a metal periodic structure provided on the upper spacer layer and arranged to induce surface plasmon, the metal periodic structure including first and second electrodes including portions arranged alternately on the upper spacer layer; a light absorption layer formed under the upper spacer layer and including a semiconductor having a refractive index higher than that of the upper spacer layer; and a lower spacer layer formed under the light absorption layer and having a refractive index smaller than that of the light absorption layer. Each of the first and second electrodes forms a Schottky barrier junction with the upper spacer layer. | 2010-01-21 |
20100013041 | MICROELECTRONIC IMAGER PACKAGES WITH COVERS HAVING NON-PLANAR SURFACE FEATURES - Several embodiments of microelectronic imager packages with covers having non-planar surface features are disclosed herein. One embodiment is directed to a imager package that includes an imager die having a plurality of photo sensors and an enclosure substantially enclosing the imager die. The enclosure has a cover attached to a base with an adhesive. The cover has a transparent central portion superimposed with the photo sensors and a peripheral portion around the central portion. The cover has a non-planar portion in the peripheral portion, and the non-planar portion is configured to increase a bonding strength between the cover and the base. | 2010-01-21 |
20100013042 | CMOS image sensor including tunable read amplifier - CMOS image sensor is realized, wherein a pre-amp amplifies the voltage of a photo detector, and a main amp amplifies the output of the pre-amp. And the pre-amp is adjustable for receiving the output of the photo detector, and also the main amp is adjustable for optimizing the output swing. With the adjustable amps, low sensitivity photo detector can be amplified more, and high sensitivity photo detector can be amplified less, which enables to adjust the gain of each amp from the low-sensitive to high-sensitive photo detector. The information for adjusting the amps is stored in the latches of the chip, wherein include laser-blown fuses or electric fuses. In doing so, the photo detector can be stacked over the access device. In particular, photo detector is repairable, wherein failed photo detector is replaced with non-failed photo detector. | 2010-01-21 |
20100013043 | CRACKSTOP STRUCTURES AND METHODS OF MAKING SAME - An integrated circuit chip and a method of fabricating an integrated circuit chip. The integrated circuit chip includes: a continuous first stress ring proximate to a perimeter of the integrated circuit chip, respective edges of the first stress ring parallel to respective edges of the integrated circuit chip; a continuous second stress ring between the first stress ring and the perimeter of the integrated circuit chip, respective edges the second stress ring parallel to respective edges of the integrated circuit chip, the first and second stress rings having opposite internal stresses; a continuous gap between the first stress ring and the second stress ring; and a set of wiring levels from a first wiring level to a last wiring level on the substrate. | 2010-01-21 |
20100013044 | THREE-DIMENSIONAL SILICON ON OXIDE DEVICE ISOLATION - A silicon-on-insulator wafer ( | 2010-01-21 |
20100013045 | Method of Integrating an Element - The present invention provides a method of integrating a structure, e.g. a fuse, for use in a semiconductor device, the method comprises several steps, the first step is providing a first layer of sacrificial material ( | 2010-01-21 |
20100013046 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - In order to improve the reliability of a semiconductor device having a fuse formed by a Damascene technique, a barrier insulating film and an inter-layer insulating film are deposited over a fourth-layer wiring and a fuse. The barrier insulating film is an insulating film for preventing the diffusion of Cu and composed of a SiCN film deposited by plasma CVD like the underlying barrier insulating film. The thickness of the barrier insulating film covering the fuse is larger than the thickness of the underlying barrier insulating film so as to improve the moisture resistance of the fuse. | 2010-01-21 |
20100013047 | INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME - An integrated circuit on a substrate comprises a buffer capacitor in a buffer region. The buffer capacitor comprises a buffer electrode arranged at least partially in a recess, and a dielectric layer disposed between the buffer electrode and the substrate. | 2010-01-21 |
20100013048 | INTERCONNECT LINE SELECTIVELY ISOLATED FROM AN UNDERLYING CONTACT PLUG - A means for selectively electrically connecting an electrical interconnect line, such as a bit line of a memory cell, with an associated contact stud and electrically isolating the interconnect line from other partially underlying contact studs for other electrical features, such as capacitor bottom electrodes. The interconnect line can be formed partially-connected to all contact studs, thereby allowing the electrical features to be formed in closer proximity to one another for higher levels of integration, and in subsequent steps of fabrication, the contact studs associated with memory cell features other than the interconnect line can be isolated from the interconnect line by the removal of a silicide cap, or the selective etching of a portion of these contact studs, and the formation of an insulating sidewall between the non-selected contact stud and the interconnect line. | 2010-01-21 |
20100013049 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A first multilayer body is formed by alternately layering dielectric films and electrode films on a substrate. Then, an end portion of the first multilayer body is processed into a staircase shape, and a first interlayer dielectric film is formed around the first multilayer body. Next, a plurality of contact holes having a diameter decreasing downward are formed in the first interlayer dielectric film so that the contact holes reach respective end portions of the electrode films. Then, a sacrificial material is buried in the contact holes. Next, a second multilayer body is formed immediately above the first multilayer body, and a second interlayer dielectric film is formed around the second multilayer body. Thereafter, a plurality of contact holes having a diameter decreasing downward are formed in the second interlayer dielectric film to communicate with the respective contact holes formed in the first interlayer dielectric film. Then, the sacrificial material is removed and a contact is buried inside the contact holes. The contact has a step difference. | 2010-01-21 |
20100013050 | Compensation Of Field Effect On Polycrystalline Resistors - A resistive circuit includes a first terminal and a second terminal and polycrystalline first and second resistive segments coupled between the first and second terminals. A third terminal A is coupled to the first resistive segment, and a third terminal B is coupled to the second resistive segment. The third terminal A has a first voltage with respect to the first terminal, and the third terminal B has a second voltage with respect to the second terminal. With this arrangement, the non-linearity of resistance of the first resistive segment at least partially compensates for non-linearity of resistance of the second resistive segment. | 2010-01-21 |
20100013051 | Method Of Forming A Bipolar Transistor And Semiconductor Component Thereof - A semiconductor component is formed using the following processes: (a) forming a first dielectric layer over the semiconductor substrate; (b) forming a base electrode for the bipolar transistor over the dielectric layer; (c) forming an oxide nitride structure over the base electrode; (d) forming a first spacer adjacent to the oxide nitride structure and the base electrode; (e) removing a top layer of the oxide nitride structure; (f) removing a first portion of the dielectric layer; (g) forming an epitaxial layer over the semiconductor substrate; (h) forming a second spacer over the epitaxial layer; and (i) forming an emitter electrode over the epitaxial layer and adjacent to the second spacer. | 2010-01-21 |
20100013052 | DUAL CHAMBER SYSTEM PROVIDING SIMULTANEOUS ETCH AND DEPOSITION ON OPPOSING SUBSTRATE SIDES FOR GROWING LOW DEFECT DENSITY EPITAXIAL LAYERS - A dual-chamber reactor can include a housing enclosing a volume having a divider therein, where the divider defines a first chamber and a second chamber. The divider can include a substrate holder that supports at least one substrate and exposes a first side of the substrate to the first chamber and a second side of the substrate to the second chamber. The first chamber can include an inlet for delivering at least one reagent to the first chamber for forming a film on the first side of the substrate, and the second chamber can include a removal device for removing material from the second side of the substrate. | 2010-01-21 |
20100013053 | METHOD FOR MANUFACTURING III-V COMPOUND SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING EPITAXIAL WAFER, III-V COMPOUND SEMICONDUCTOR SUBSTRATE, AND EPITAXIAL WAFER - The present invention provides a method for manufacturing a III-V compound semiconductor substrate, a method for manufacturing an epitaxial wafer, a III-V compound semiconductor substrate, and an epitaxial wafer, wherein the thickness of an oxide film formed on the substrate or in the wafer is controlled with high precision, and surface of the epitaxial wafer is prevented from getting rough,. The method for manufacturing a III-V compound semiconductor substrate according to the present invention includes the following steps. Initially, a substrate composed of a III-V compound semiconductor is provided. Thereafter, the resulting substrate is cleaned with an acidic solution. Subsequently, an oxide film is formed on the substrate by a wet method after the cleaning. | 2010-01-21 |
20100013054 | COMPOSITE MATERIAL SUBSTRATE - A composite material substrate having patterned structure includes a substrate, a first dielectric layer, a second dielectric layer, and a nitride semiconductor material. Herein, the first dielectric layer is stacked on the substrate, the second dielectric layer is stacked on the first dielectric layer, and the nitride semiconductor material is stacked on the second dielectric layer and is characterized by a plurality of patterns thereon. | 2010-01-21 |
20100013055 | METHOD FOR PRODUCING TRIALKYL GALLIUM - The present invention provides a method for producing a trialkyl gallium comprising the steps of reacting gallium, magnesium, and an alkyl halide in an ether, and diluting during the reaction the reaction system with an ether; a method for producing a trialkyl gallium comprising the steps of heating in a vacuum a mixture of magnesium and molten gallium, and reacting the mixture with an alkyl halide in a solvent; and a method for producing a trialkyl gallium comprising the step of reacting an alkyl metal with an alkylgallium halide compound represented by the formula | 2010-01-21 |
20100013056 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The invention prevents a fracture parallel to a cleavage plane of a supporting substrate along a groove formed in the supporting substrate before dicing. A supporting substrate is attached to a front surface of a semiconductor substrate formed with an electronic device with an adhesive layer being interposed therebetween. In this supporting substrate, dicing lines are not parallel with cleavage planes which are perpendicular to the front surface of supporting substrate, i.e., a fifth cleavage plane and a sixth cleavage plane crossing perpendicularly thereto. A groove is then formed in the supporting substrate from the front surface to the middle thereof in the direction perpendicular to the front surface, along the dicing lines inside an opening provided in the semiconductor substrate. This groove is not parallel with the fifth cleavage plane and the sixth cleavage plane. After given processes, dicing is performed to the layered body of layers from the semiconductor substrate to the supporting substrate along the dicing lines. | 2010-01-21 |
20100013057 | SEMICONDUCTOR SUBSTRATE SUITABLE FOR THE REALISATION OF ELECTRONIC AND/OR OPTOELECTRONIC DEVICES AND RELATIVE MANUFACTURING PROCESS - A semiconductive substrate ( | 2010-01-21 |
20100013058 | Semiconductor Wafer and Semiconductor Wafer Inspection Method - Affords semiconductor wafers that achieve uniformization of semiconductor films. In a semiconductor wafer ( | 2010-01-21 |
20100013059 | DIFFUSION REGION ROUTING FOR NARROW SCRIBE-LINE DEVICES - The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench. | 2010-01-21 |
20100013060 | METHOD OF FORMING A CONDUCTIVE TRENCH IN A SILICON WAFER AND SILICON WAFER COMPRISING SUCH TRENCH - A method of forming a conductive trench such as a through-silicon-via in a silicon wafer is disclosed. The method includes depositing a mask over a wafer surface; patterning the mask to expose a portion of the wafer; exposing the wafer to a first etching step in which a first portion of the trench is formed; exposing the wafer to an second etching step in which a tapered second portion of the trench is formed, where the first portion has a continuously non-increasing width from the wafer surface to the second portion; and filling the trench with a conductive material. A silicon wafer including such a conductive trench is also disclosed. | 2010-01-21 |
20100013061 | SEMICONDUCTOR STRUCTURES INCLUDING SQUARE CUTS IN SINGLE CRYSTAL SILICON - A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a buffered fluoride etch solution which undercuts the silicon to provide lateral shelves when patterned in the <100> direction. The resulting structure includes an undercut feature when patterned in the <100> direction. | 2010-01-21 |
20100013062 | NONVOLATILE MEMORY CELL - A nonvolatile memory cell is provided. A semiconductor substrate is provided. A conducting layer and a spacer layer are sequentially disposed above the semiconductor substrate. At least a trench having a bottom and plural side surfaces is defined in the conducting layer and the spacer layer. A first oxide layer is formed at the bottom of the trench. A dielectric layer is formed on the first oxide layer, the spacer layer and the plural side surfaces of the trench. A first polysilicon layer is formed in the trench. And a first portion of the dielectric layer on the spacer layer is removed, so that a basic structure for the nonvolatile memory cell is formed. | 2010-01-21 |
20100013063 | THIN-FILM DEVICE, METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - A method for manufacturing a thin-film device includes forming a separation layer on a substrate, forming a support layer of mainly clay containing silicate mineral having a layered crystal structure on the separation layer, forming a thin-film functional member on the support layer, applying an energy to the separation layer to reduce the adhesion between the substrate and the support layer, and removing the substrate from the support layer and the thin-film functional member. | 2010-01-21 |
20100013064 | SEMICONDUCTOR DEVICE PACKAGES WITH ELECTROMAGNETIC INTERFERENCE SHIELDING - Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit defining a cut-out portion disposed adjacent to a periphery of the substrate unit; (2) a grounding element disposed in the cut-out portion and at least partially extending between an upper surface and a lower surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; (4) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device and the grounding element; and (5) an EMI shield disposed adjacent to exterior surfaces of the package body. The EMI shield is electrically connected to a connection surface of the grounding element, such that the grounding element provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield. | 2010-01-21 |
20100013065 | STACKABLE MOLDED PACKAGES AND METHODS OF MAKING THE SAME - A first packaged integrated circuit (IC) includes a package substrate, at least one IC die attached to a first surface of the package substrate, a plurality of conductive members on the first surface at least partially surrounding the at least one IC die and electrically connected to the at least one IC die, an encapsulant over the first surface surrounding the at least one IC die and the plurality of conductive members, wherein at least a portion of each of the plurality of conductive members is exposed by the encapsulant. A second packaged IC may be stacked onto the first packaged IC. The second packaged IC includes at least one IC die and a plurality of conductive members, each conductive member of the plurality of conductive members of the second packaged IC is in contact with a corresponding conductive member of the plurality conductive members of the first packaged IC. | 2010-01-21 |
20100013066 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a main substrate, a semiconductor chip having a first side and a second side, the first side of the semiconductor chip disposed on the main substrate and electrically connected to the main substrate, and a conductive network formed on the second side of the semiconductor chip. | 2010-01-21 |
20100013067 | Stress Mitigation in Packaged Microchips - A package apparatus has a base coupled with a lid to form a leadframe package. The package has first and second exterior surfaces with respective first and second contact patterns. The first and second contact patterns are substantially electrically identical to permit the package to be either vertically or horizontally mounted to an underlying apparatus. | 2010-01-21 |
20100013068 | CHIP PACKAGE CARRIER AND FABRICATION METHOD THEREOF - A chip package carrier is disclosed, which includes a first circuit layer, a second circuit layer, a core layer, a third circuit layer, a first dielectric layer between the first and third circuit layers, a fourth conductive layer including at least a solder ball pad, a second dielectric layer between the second and fourth circuit layers and at least a capacitor device, wherein the core layer has at least a first through-hole; the third circuit layer is disposed above the first circuit layer and includes at least a die pad; the capacitor device is disposed in the first through-hole. The capacitor device herein includes a first pillar electrode covering the wall of the first through-hole, a cylindrical capacitor material disposed in the first pillar electrode and having a first blind hole, and a second pillar electrode disposed in the first blind hole and connected to the die pad. | 2010-01-21 |
20100013069 | SEMICONDUCTOR DEVICE, LEAD FRAME AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device and a lead frame capable of preventing development of defective mounting resulting from a burr and a method of manufacturing a semiconductor device with the lead frame are provided. The semiconductor device includes a semiconductor chip and a lead arranged on the periphery of the semiconductor chip to extend in a direction intersecting with the side surface of the semiconductor chip, so that at least an end portion on the side farther from the semiconductor chip is bonded to a mounting substrate. A groove opened on a surface bonded to the mounting substrate and an end face on the side farther from the semiconductor chip is formed in the lead over the full width in the width direction orthogonal to the thickness direction and along the end face. An embedded body made of solder is embedded in the groove. | 2010-01-21 |
20100013070 | POWER MODULE PACKAGE HAVING EXCELLENT HEAT SINK EMISSION CAPABILITY AND METHOD FOR MANUFACTURING THE SAME - A power module package includes a power circuit element, a control circuit element, a lead frame, an aluminum oxide substrate having a heat sink and an insulation layer, and a sealing resin. The control circuit element is electrically connected with the power circuit element to control chips within the power circuit element. The lead frame has external connection terminal leads in its edge and has a first surface to which the power circuit element and the control circuit element are attached and a second surface which is used as a heat transmission path. The heat sink is a plate made of metal such as aluminum and the electrical insulation layer is formed at least on an upper surface of the heat sink and made of aluminum oxide. The electrical insulation layer may be formed over an entire surface of the heat sink. Here, the insulation layer is attached to the second surface by an adhesive, on a region below where the power circuit element is attached, to the first surface of the lead frame. In addition, the sealing resin encloses the power circuit element and the control circuit element, the lead frame, and the metal oxide substrate and exposes the external connection terminals of the lead frame. | 2010-01-21 |
20100013071 | ORGANIC LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - The present invention relates to an organic light emitting device and a manufacturing method thereof. A manufacturing method of an organic light emitting device according to an exemplary embodiment of the present invention includes forming a thin film structure on a first substrate, forming a dehumidification buffer layer on a second substrate, combining the first substrate and the second substrate, and heat treating the dehumidification buffer layer to soften the dehumidification buffer layer. | 2010-01-21 |
20100013072 | STACKED PACKAGE AND METHOD FOR FORMING STACKED PACKAGE - The present invention provides an inexpensive semiconductor chip module enabling sufficient heat dissipation without complicating the manufacture process. | 2010-01-21 |
20100013073 | APPARATUS AND METHODS FOR CONSTRUCTING SEMICONDUCTOR CHIP PACKAGES WITH SILICON SPACE TRANSFORMER CARRIERS - Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration. | 2010-01-21 |
20100013074 | HIGH DENSITY STACKED DIE ASSEMBLIES, STRUCTURES INCORPORATED THEREIN AND METHODS OF FABRICATING THE ASSEMBLIES - A stacked semiconductor die assembly includes at least two partially offset semiconductor dice with bond pads located adjacent at least one peripheral side thereof supported on a redistribution element formed of a material of substantially similar CTE to that of the dice, and a paddle-less lead frame secured to the redistribution element during fabrication, including encapsulation. The assembly is configured to be substantially vertically symmetrical with respect to inner ends of lead fingers of the lead frame to facilitate uniform encapsulant flow. The semiconductor die assembly may be configured in a package with leads extending from two sides thereof, such as a thin small outline package (TSOP), or four sides thereof, such as a quad flat pack (QFP). | 2010-01-21 |
20100013075 | STACKED-TYPE SEMICONDUCTOR DEVICE PACKAGE - A stacked-type semiconductor device package is provided. The stacked-type semiconductor device package includes a plurality of stacked semiconductor chip packages with joining electrodes exposed on sides of the semiconductor chip packages and a flexible printed circuit board (flexible PCB) on which the stacked semiconductor chip packages are mounted. The flexible PCB includes a first surface having connecting electrodes corresponding to the joining electrodes of the stacked semiconductor chip packages and a second surface opposite the first surface. The flexible PCB covers the sides of the stacked semiconductor chip packages, and the connecting electrodes of the first surface are connected to the joining electrodes of the stacked semiconductor chip packages. | 2010-01-21 |
20100013076 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor device package includes a semiconductor chip having a top surface on which a conductive pad is disposed, a bottom surface opposite to the top surface, and a side surface connecting the top and bottom surfaces to each other; a first insulating layer covering the top surface of the semiconductor chip and laterally extending to the outside of the semiconductor chip; a fillet member covering a boundary where the side surface of the semiconductor chip and the first insulating layer meet each other; and a molding layer covering the bottom surface of the semiconductor chip, the fillet member, and the first insulating layer. | 2010-01-21 |
20100013077 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip having a top surface on which a first conductive pad is disposed, a bottom surface opposite to the top surface, and a side surface connecting the top and bottom surfaces to each other, a first reinforcement layer on the top surface of the semiconductor chip, a first absorption layer between the top surface of the semiconductor chip and the first reinforcement layer to absorb a stress resulting from a difference in thermal expansion coefficient between the first reinforcement layer and the semiconductor chip, and a connection terminal disposed on the first reinforcement layer and electrically connected to the first conductive pad. | 2010-01-21 |