04th week of 2014 patent applcation highlights part 14 |
Patent application number | Title | Published |
20140021448 | NAPHTHALENE-DIIMIDE-HETEROCYCLE-NAPHTHALENE DIIMIDE OLIGOMERS AS ORGANIC SEMICONDUCTORS AND TRANSISTORS THEREFROM - The various inventions and/or their embodiments disclosed herein relate to certain naphthalene diimide (NDI) compounds wherein the NDI groups are bonded to certain subclasses of bridging heteroaryl (hAr) groups, such as the “NDI-hAr-NDI” oligomeric compounds, wherein hAr is a heteroaryl group chosen to provide desirable electronic and steric properties, and the possible identities of the “R | 2014-01-23 |
20140021449 | PHOSPHORESCENT MATERIALS - Novel organic compounds containing a twisted aryl group are provided. In particular, the compounds provided contain a 2-phenylpyridine ligand having a twisted aryl group on the pyridine portion of the ligand. The compounds may be used in organic light emitting devices, particularly as emitting dopants. Devices comprising the compounds containing twisted aryl may demonstrate improved color, efficiency, stability and manufacturing. Additionally, methods are provided for making homoleptic Ir (III) compounds which may contain a twisted aryl. | 2014-01-23 |
20140021450 | LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting device is provided comprising a stack of layers including—an electro-optical layer structure ( | 2014-01-23 |
20140021451 | ORGANIC ELECTROLUMINESCENT DEVICE - An organic electroluminescent device comprises, between an anode and a cathode, a hole injection layer, a hole-transporting layer, a luminous layer and an electron-transporting layer, wherein the hole injection layer contains an arylamine compound (α) having three or more triphenylamine skeletons, the hole-transporting layer contains an arylamine compound (β) having two triphenylamine skeletons, and the electron-transporting layer contains an electron-transporting compound having an anthracene ring skeleton and a pyridoindole ring skeleton. The organic EL device emits light highly efficiently, drives on a low voltage, and features excellent durability and long life. | 2014-01-23 |
20140021452 | SCREEN FOR DISPLAYING INFORMATION FOR AN OPTICAL DEVICE - Disclosed is a screen for displaying information for an optical device which is arranged within an optical path of an optical device. The screen for displaying information includes a transparent organic light-emitting diode (TOLED) which emits light in accordance with power and an input control signal. | 2014-01-23 |
20140021453 | METHODS OF MAKING BIS-TRIDENTATE CARBENE COMPLEXES OF RUTHENIUM AND OSMIUM - Novel polydentate carbene complexes of ruthenium and formulations containing the same are provided. Organic light emitting device containing the novel polydentate carbene complexes of ruthenium in an emissive layer are also provided. The novel polydentate carbene complexes of ruthenium may be particularly useful in OLEDs to provide devices having improved performance. | 2014-01-23 |
20140021454 | DEVICE FOR SPRAYING, METHOD THEREFOR, AND ORGANIC ELECTRONIC CONSTRUCTION ELEMENT - The embodiments relate to a device and a method for spraying coatings of organic construction elements. The embodiments relate, in particular, to the spraying of coatings made up of components that do not dissolve in the same solvent, for example, and/or the spraying of a plurality of coatings one after the other. A plurality of spray heads is used, for example one after the other and/or next to one another. | 2014-01-23 |
20140021455 | LIGHT EMITTING DEVICE, DISPLAY APPARATUS, AND ELECTRONIC APPARATUS - In a display panel, a first electron injection layer is formed between an anode and a light-emitting functional layer, and a hole injection layer is formed between the anode and the first electron injection layer. In other words, the hole injection layer, the first electron injection layer, and the light-emitting functional layer are configured to be laminated on the anode in this order. An electron injection material used for the first electron injection layer is diffused into the hole injection layer, and the diffused electron injection material inhibits or promotes hole transportation of the hole injection layer, so that the amount of holes transported to a light-emitting functional layer is adjusted. As a result, the carrier balance is improved. | 2014-01-23 |
20140021456 | ORGANIC SEMICONDUCTOR POLYMER, COMPOSITION FOR ORGANIC SEMICONDUCTOR MATERIAL, AND PHOTOVOLTAIC CELL - An organic semiconductor polymer comprising a structural unit represented by the following Formula (I), a composition for organic semiconductor material, a photovoltaic cell and a polymer. | 2014-01-23 |
20140021457 | THIN FILM TRANSISTOR, ORGANIC EL LIGHT EMITTING DEVICE, AND METHOD OF FABRICATING THIN FILM TRANSISTOR - A thin film transistor according to the present disclosure including: a gate electrode above a substrate; a gate insulating layer covering the gate electrode; a semiconductor layer above the gate insulating layer; and a source electrode and a drain electrode which are above the gate insulating layer, and electrically connected to the semiconductor layer, in which the gate insulating layer includes a first area and a second area, the first area being above the gate electrode, the second area being different from an area above the gate electrode, and made of a same substance as the first area, and the first area has a higher density than a density of the second area. | 2014-01-23 |
20140021458 | ORGANIC ELECTRO-LUMINESCENCE DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME - In an organic electro-luminescence display panel, an organic EL element is formed on a substrate. In the organic EL element, a first electrode formed on the substrate and has an electrode portion and a connection portion. A planarizing layer is formed around edges of the electrode portion. The planarizing layer planarizes a boundary with the first electrode. A partitioning wall has an aperture at an inside thereof. The partitioning wall is formed to be separated from the edges of the electrode portion toward the planarizing layer. A luminescent medium layer includes at least an organic luminescent layer and formed, in the aperture of the partitioning wall, on the first electrode and the planarizing layer. A second electrode is formed to be separated by the luminescent medium layer from the first electrode. | 2014-01-23 |
20140021459 | LIGHT EMITTING DEVICE - A light emitting device is provided which can prevent a change in gate voltage due to leakage or other causes and at the same time can prevent the aperture ratio from lowering. A capacitor storage is formed from a connection wiring line, an insulating film, and a capacitance wiring line. The connection wiring line is formed over a gate electrode and an active layer of a TFT of a pixel, and is connected to the active layer. The insulating film is formed on the connection wiring line. The capacitance wiring line is formed on the insulating film. This structure enables the capacitor storage to overlap the TFT, thereby increasing the capacity of the capacitor storage while keeping the aperture ratio from lowering. Accordingly, a change in gate voltage due to leakage or other causes can be avoided to prevent a change in luminance of an OLED and flickering of screen in analog driving. | 2014-01-23 |
20140021460 | TRANSLUCENT SUBSTRATE AND SUBSTRATE OF ORGANIC LED - An organic LED element includes a transparent substrate; a light scattering layer formed on the transparent substrate; a transparent first electrode formed on the light scattering layer; an organic light emitting layer formed on the first electrode; and a second electrode formed on the organic light emitting layer, wherein the light scattering layer includes a base material made of glass, and a plurality of scattering substances dispersed in the base material, and wherein a coating layer, which is not a molten glass, is provided between the light scattering layer and the first electrode. | 2014-01-23 |
20140021461 | MATERIAL FOR ORGANIC ELECTROLUMINESCENCE ELEMENT, AND ORGANIC ELECTROLUMINESCENCE ELEMENT USING THE MATERIAL - An organic electroluminescence device comprising a compound having a specific structure having a heteroatom and an organic electroluminescence device which comprises a cathode, an anode and an organic thin film layer which comprises at least one layer comprising at least a light emitting layer and is disposed between the cathode and the anode, wherein at least one layer in the organic thin film layer comprises the above compound. The device provides excellent efficiency of light emission, forms no defects in pixels, exhibits excellent heat resistance and has a long life. | 2014-01-23 |
20140021462 | METHOD FOR MANUFACTURING ORGANIC ELECTROLUMINESCENT ELEMENT, AND ORGANIC ELECTROLUMINESCENT ELEMENT - A method for manufacturing an organic electroluminescent element comprising an anode and a cathode on/over a base, and at least three organic layers between the anode and the cathode, may include forming at least one of the organic layers by a method including applying an application liquid for the organic layer comprising a material for forming the organic layer and a solvent on the anode, the cathode or the organic layer; and heating the organic layer after the applying so as to remove 90% by mass or more of the solvent in the application liquid for the organic layer within two seconds. | 2014-01-23 |
20140021463 | ORGANIC ELECTROLUMINESCENCE ELEMENT - The organic electroluminescence element according to the present invention includes: a light-emitting layer; a first electrode layer on a first surface in a thickness direction of the light-emitting layer; a second electrode layer on a second surface in the thickness direction of the light-emitting layer; an electrically conductive layer; and an insulating layer. The light-emitting layer emits light when a predetermined voltage is applied between the first and second electrode layers. The second electrode layer includes an electrode part covering the second surface and an opening part formed in the electrode part to expose the second surface therethrough. The electrically conductive layer allows the light to pass therethrough, and formed on an exposed region of the second surface exposed through the opening part so as to be electrically connected to the electrode part and the light-emitting layer. The insulating layer is interposed between the electrode part and the second surface. | 2014-01-23 |
20140021464 | Yttrium-doped Indium Oxide Transparent Conductive Thin-Film Transistor and Method for Making Same - The present invention provides a transistor and method for making the same. The transistor has an yttrium-doped indium oxide transparent conductive thin-film which is so fabricated with the method to reduce the formation of oxygen vacancies, suppress carrier concentration effectively, and decrease maximum defect density and thus suitable to be applied to the transistor. | 2014-01-23 |
20140021465 | Coating Materials for Oxide Thin Film Transistors - The present teachings provide a coating composition (a passivation formulation) for preparing a coating material in a metal oxide thin film transistor, where the coating material comprises a polymer blend including a polymer and a stabilizing agent. Incorporation of a stabilizing agent according to the present teachings in the coating material can lead to improved device performance of the metal oxide thin film transistor, in particular, reduced shift in the threshold voltage and long-term bias-stress stability. | 2014-01-23 |
20140021466 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a gate electrode; a gate insulating film over the gate electrode; an oxide semiconductor film in contact with the gate insulating film and including a channel formation region which overlaps with the gate electrode; a source electrode and a drain electrode over the oxide semiconductor film; and an oxide insulating film over the oxide semiconductor film, the source electrode, and the drain electrode. The source electrode and the drain electrode each include a first metal film having an end portion at the end of the channel formation region, a second metal film over the first metal film and containing copper, and a third metal film over the second metal film. The second metal film is formed on the inner side than the end portion of the first metal film. | 2014-01-23 |
20140021467 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A change in electrical characteristics of a semiconductor device including an interlayer insulating film over a transistor including an oxide semiconductor as a semiconductor film is suppressed. The structure includes a first insulating film which includes a void portion in a step region formed by a source electrode and a drain electrode over the semiconductor film and contains silicon oxide as a component, and a second insulating film containing silicon nitride, which is provided in contact with the first insulating film to cover the void portion in the first insulating film. The structure can prevent the void portion generated in the first insulating film from expanding outward. | 2014-01-23 |
20140021468 | DEVICE WITH LIGHT-RESPONSIVE LAYERS - An electrical device with light-responsive layers is disclosed. One or more electrically conducting stripes, each insulated from each other, are deposited on a smooth surface of a substrate. Then metal oxide layers, separated by a composite diffusion layer, are deposited. On top of the topmost metal oxide layer another set of elongated conductive strips are disposed in contact with the topmost metal oxide layer such that junctions are formed wherever the top and bottom conducting stripes cross. The resulting device is light responsive only when a certain sign of bias voltage is applied and may be used as a photodetector. An advantage that may be realized in the practice of some disclosed embodiments of the device is that this device may be formed without the use of conventional patterning, thereby significantly reducing manufacturing difficulty. | 2014-01-23 |
20140021469 | INTEGRATED CIRCUIT INCLUDING SENSOR STRUCTURE, RELATED METHOD AND DESIGN STRUCTURE - An Integrated Circuit (IC) and a method of making the same. In one embodiment, an integrated circuit includes: a substrate; a first metal layer disposed on the substrate and including a sensor structure configured to indicate a crack in a portion of the integrated circuit; and a second metal layer disposed proximate the first metal layer, the second metal layer including a wire component disposed proximate the sensor structure. | 2014-01-23 |
20140021470 | INTEGRATED CIRCUIT DEVICE INCLUDING LOW RESISTIVITY TUNGSTEN AND METHODS OF FABRICATION - An integrated circuit device includes a semiconductor substrate and a gate electrode on the semiconductor substrate. The gate electrode structure includes an insulating layer of a dielectric material on the semiconductor substrate, an oxygen barrier layer on the insulating layer, and a tungsten (W) metal layer on the oxygen barrier layer. | 2014-01-23 |
20140021471 | MRAM SYNTHETIC ANITFEROMAGNET STRUCTURE - An MRAM bit ( | 2014-01-23 |
20140021472 | PRINTABLE MEDIUM THAT CONTAINS METAL PARTICLES AND EFFECTS ETCHING, MORE PARTICULARLY FOR MAKING CONTACT WITH SILICON DURING THE PRODUCTION OF A SOLAR CELL - A printable medium is proposed, such as can be used, for example, during the production of metal contacts for silicon solar cells which are covered with a passivation layer on a surface of a silicon substrate. A corresponding production method and a correspondingly produced solar cell are also disclosed. The printable medium contains at least one medium that etches the passivation layer and metal particles such as nickel particles, for example. By locally applying the printable medium to the passivation layer and subsequent heating, the passivation layer can be opened locally with the aid of the etching medium. As a result, the nickel particles can form a mechanical and electrical contact with the substrate surface, preferably with the formation of a nickel silicide layer. The printable medium and the production method made possible therewith are cost-effective owing to the use of nickel particles, for example, and allow both good electrical contact and avoidance of undesirable high-temperature steps. | 2014-01-23 |
20140021473 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a gate, an oxide channel layer, a gate insulating layer, a source, a drain and a dielectric stacked layer. The oxide channel layer is stacked over the gate, with the gate insulting layer disposed therebetween. The source and the drain are disposed on a side of the oxide channel layer and in parallel to each other. A portion of the oxide channel layer is exposed between the source and the drain. The dielectric stacked layer is disposed on the substrate and includes plural of first inorganic dielectric layers with a first refraction index and plural of second inorganic dielectric layers with a second refraction index that are stacked alternately. At least one of the first inorganic dielectric layers directly covers the source, the drain and the portion of the oxide channel layer. The first refraction index is smaller than the second refraction index. | 2014-01-23 |
20140021474 | MEMORY ELEMENT AND PROGRAMMABLE LOGIC DEVICE - To provide a memory element where a desired potential can be stored as data without an increase in the number of power source potentials. The memory element stores data in a node which is brought into a floating state by turning off a transistor a channel of which is formed in an oxide semiconductor layer. The potential of a gate of the transistor can be increased by capacitive coupling between the gate and a source of the transistor. With the structure, a desired potential can be stored as data without an increase in the number of power source potentials. | 2014-01-23 |
20140021475 | ARRAY SUBSTRATE, MANUFACTURING METHOD OF THE SAME, AND FABRICATING METHOD OF DISPLAY DEVICE INCLUDING THE ARRAY SUBSTRATE - An array substrate for a display device includes an insulation substrate, a gate line formed on the insulation substrate, a data line crossing the gate line to define a pixel area, a thin film transistor including a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode, a passivation layer covering the gate line, the data line and the thin film transistor and including a drain contact hole to expose the drain electrode, and a pixel electrode formed on the pixel area and being connected to the drain contact hole through the drain contact hole. Each of the data line, the source electrode and the drain electrode includes a lower layer having copper and an upper layer covering upper and side surfaces of the lower layer, and the upper layer is thinner than the lower layer. | 2014-01-23 |
20140021476 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - To provide a liquid crystal display device having high quality display by obtaining a high aperture ratio while securing a sufficient storage capacitor (Cs), and at the same time, by dispersing a load (a pixel writing-in electric current) of a capacitor wiring in a timely manner to effectively reduce the load. A scanning line is formed on a different layer from a gate electrode and the capacitor wiring is arranged so as to be parallel with a signal line. Each pixel is connected to the individually independent capacitor wiring via a dielectric. Therefore, variations in the electric potential of the capacitor wiring caused by a writing-in electric current of a neighboring pixel can be avoided, whereby obtaining satisfactory display images. | 2014-01-23 |
20140021477 | SYSTEMS, METHODS AND MATERIALS INCLUDING CRYSTALLIZATION OF SUBSTRATES VIA SUB-MELT LASER ANNEAL, AS WELL AS PRODUCTS PRODUCED BY SUCH PROCESSES - Systems, methods, and products of processes consistent with the innovations herein relate to aspects involving crystallization of layers on substrates. In one exemplary implementation, there is provided a method of fabricating a device. Moreover, such method may include placing an amorphous/poly material on a substrate and heating the material via a sub-melt laser anneal process to transform the material into crystalline form. | 2014-01-23 |
20140021478 | Display panel - A display panel includes a plurality of pads configured to provide a driver thereon, a plurality of first contacts respectively connected to the plurality of pads, a plurality of second contacts respectively provided so as to be opposed to the plurality of first contacts, a semiconductor layer configured to form a plurality of polysilicon films that are respectively extended to connect the plurality of first contacts and the plurality of second contacts to each other, and a gate metal layer different from the polysilicon layer. Each of a plurality of transistors is formed at a position where the gate metal layer traverses the polysilicon layer, and a plurality of transistor groups of the plurality of transistors are arranged in a zigzag pattern. Each of the plurality of transistor groups include three adjacent transistors of the plurality of transistors. | 2014-01-23 |
20140021479 | GAN POWER DEVICE WITH SOLDERABLE BACK METAL - A method for fabricating a vertical gallium nitride (GaN) power device can include providing a GaN substrate with a top surface and a bottom surface, forming a device layer coupled to the top surface of the GaN substrate, and forming a metal contact on a top surface of the vertical GaN power device. The method can further include forming a backside metal by forming an adhesion layer coupled to the bottom surface of the GaN substrate, forming a diffusion barrier coupled to the adhesion layer, and forming a protection layer coupled to the diffusion barrier. The vertical GaN power device can be configured to conduct electricity between the metal contact and the backside metal. | 2014-01-23 |
20140021480 | HIGH ELECTRON MOBILITY TRANSISTORS AND METHODS OF MANUFACTURING THE SAME - A HEMT according to example embodiments may include a first semiconductor layer, a second semiconductor layer configured to induce a 2-dimensional electron gas (2DEG) in the second semiconductor layer, an insulating mask layer on the second semiconductor layer, a depletion forming layer on one of a portion of the first semiconductor layer and a portion of the second semiconductor layer that is exposed by an opening defined by the insulating mask layer, a gate on the depletion forming layer, and a source and a drain on at least one of the first semiconductor layer and the second semiconductor layer. The source and drain may be spaced apart from the gate. The depleting forming layer may be configured to form a depletion region in the 2DEG. | 2014-01-23 |
20140021481 | NITRIDE-BASED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A nitride-based semiconductor device includes a buffer layer on a substrate, a nitride-based semiconductor layer on the buffer layer, at least one ion implanted layer within the nitride-based semiconductor layer, and a channel layer on the nitride-based semiconductor layer. | 2014-01-23 |
20140021482 | LIGHT EMITTING DEVICE HAVING VERTICAL STRUCTURE AND PACKAGE THEREOF - A light emitting device having a vertical structure and a package thereof, which are capable of damping impact generated in a substrate separation process, and achieving an improvement in mass productivity. The device and package include a sub-mount, a first-type electrode, a second-type electrode, a light emitting device, a zener diode, and a lens on the sub-mount. | 2014-01-23 |
20140021483 | Forming Light-Emitting Diodes Using Seed Particles - A seed layer for growing a group | 2014-01-23 |
20140021484 | Semiconductor Device - A manufacturing method provides a semiconductor device having a semiconductor body defining a source region, a body region, a drift region and a diode region. The drift region has a first drift region section and a second drift region section. The diode region is buried within the drift region, and has a semiconductor type opposite to the drift region to form a diode. The diode region is separated from the gate electrode by the first drift region section extending from the diode region in a vertical direction. The gate electrode is adjacent the body region and insulated from the body region by a gate dielectric. A source electrode is electrically connected to the source region, the body region and the diode region. A semiconductor region of a doping type opposite to the doping type of the drift region is arranged between the first drift region section and the source electrode. | 2014-01-23 |
20140021485 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A vertical channel transistor includes a pillar formed over a substrate, and a gate electrode formed on sidewalls of the pillar, wherein the pillar includes a source area, a vertical channel area over the source area, a drain area over the vertical channel area, and a leakage prevention area interposed between the vertical channel area and the drain area. | 2014-01-23 |
20140021486 | LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A light emitting diode (LED) includes a substrate and an eputaxial layer on the substrate. The epitaxial layer includes a N-type GaN-based layer, a light emitting layer, and a P-type GaN-based layer. The LED further includes a first electrode on the N-type GaN-based layer and a second electrode on the P-type GaN-based layer. The P-type GaN-based layer has a inactive portion, and the second electrode is located and covers the inactive portion. | 2014-01-23 |
20140021487 | Modular Power Converter Having Reduced Switching Loss - In one implementation, a modular power converter having a reduced switching loss includes a package, a field-effect transistor (FET) including a gate terminal, a drain terminal, and a source terminal, and fabricated on a semiconductor die situated inside the package, and a driver circuit inside the package. The driver circuit is configured to drive the gate terminal of the FET. The driver circuit is further configured to sample a drain-to-source voltage (V | 2014-01-23 |
20140021488 | NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING NITRIDE-BASED SEMICONDUCTOR DEVICE - In a nitride-based semiconductor device, an undoped gallium nitride (GaN) layer is formed on an aluminum gallium nitride (AlGaN) layer, and a silicon carbon nitride (Si | 2014-01-23 |
20140021489 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device having a high withstand voltage in which a stable withstand voltage can be obtained and a method for manufacturing the same. A JTE region having a second conductivity type is formed in a portion on an outer peripheral end side of an SiC substrate from a second conductivity type SiC region in a vicinal portion of a surface on one of sides in a thickness direction of a first conductivity type SiC epitaxial layer. A first conductivity type SiC region having a higher concentration of an impurity having the first conductivity type than that of the SiC epitaxial layer is formed in at least a vicinal portion of a surface on one of sides in a thickness direction of a portion in which the JTE regions are bonded to each other. | 2014-01-23 |
20140021490 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME - Fabrication of a termination structure in a semiconductor device increases in some cases the numbers of ion implantation processes or of photolithography processes, thus leading to an increase in fabrication costs. To overcome this problem, a semiconductor device is provided which includes an n-type drift layer formed on a semiconductor substrate; an element region formed in a surface portion of the drift layer; a recess formed in a loop in a laterally outer portion of the drift layer, spaced away a predetermined distance from the element region; and a p-type dopant region formed ranging from a bottom of the recess to a position away from the recess and toward the element region, a thickness of the dopant region where no recess is provided being greater than that where the recess is provided. | 2014-01-23 |
20140021491 | MULTI-COMPOUND MOLDING - In certain embodiments, a semiconductor package includes a leadframe, a light emitter die disposed on the leadframe, and a light detector die disposed on the leadframe adjacent to the light emitter die. In some embodiments, a first transparent molding compound is disposed over the light emitter die and a second transparent molding compound is disposed over the light detector die. The first and second transparent molding compound may be disposed such that a space between them forms a cavity between the die and above the leadframe. In other embodiments a transparent molding compound is disposed simultaneously over the light emitter and light detector die and a subsequent material removal process forms a cavity within the compound between the die. In both embodiments, an opaque molding compound is disposed in the cavity between the die, and is configured to block optical cross-talk between the light emitter and light detector die. | 2014-01-23 |
20140021492 | STRUCTURED LAMINATION TRANSFER FILMS AND METHODS - Lamination transfer films and methods for transferring a structured layer to a receptor substrate. The transfer films include a carrier substrate having a releasable surface, a sacrificial template layer applied to the releasable surface of the carrier substrate and having a non-planar structured surface, and a thermally stable backfill layer applied to the non-planar structured surface of the sacrificial template layer. The sacrificial template layer is capable of being removed from the backfill layer, such as via pyrolysis, while leaving the structured surface of the backfill layer substantially intact. | 2014-01-23 |
20140021493 | SOLID STATE LIGHTING COMPONENT PACKAGE WITH LAYER - A solid state lighting component comprising a layer having high reflectivity and/or scattering properties, the layer positioned about a solid state lighting component, and manufacturing methods of making same is disclosed. A method of increasing the luminous flux of the solid state lighting component, is also provided. | 2014-01-23 |
20140021494 | COLOR FILTER ON ARRAY SUBSTRATE AND A MANUFACTURING METHOD FOR THE SAME - A color filter on array (COA) substrate and a manufacturing method for the same are proposed. The COA substrate includes a transparent substrate, a thin film transistor (TFT), a color filter unit, and a pixel electrode. The color filter unit is disposed in a groove of the transparent substrate for transforming a beam of light sent to the color filter unit into the beam of light of a predetermined hue. The pixel electrode is disposed on the color filter unit and coupled to a drain of the TFT. The pixel electrode is used for controlling the rotational alignment of liquid crystals in a liquid crystal layer based upon the electrical level of an electrical signal transmitted to the drain when a scan impulse is received by a gate of the TFT. In addition, the color filter unit is formed in the groove, and the pixel electrode is formed on the color filter unit, implying that it is unnecessary to form a via on a passivation layer so that the drain could be connected to the pixel electrode through the via. Thus, etching the passivation layer for forming the via is omitted in the present invention. | 2014-01-23 |
20140021495 | LIGHT EMITTING DEVICE WITH PHOSPHOR WAVELENGTH CONVERSION - A light emitting device comprises: a thermally conductive substrate (MCPCB); at least one LED mounted in thermal communication with a surface of the substrate; a housing attached to the substrate and configured such the housing and substrate together define a volume that totally encloses the at least one LED, the housing comprising at least a part that is light transmissive (window); and at least one phosphor material provided on an inner surface of the housing within said volume said phosphor being operable to absorb at least a part of the excitation light emitted by the at least one light emitting diode and to emit light of a second wavelength range. The housing is attached to the substrate such that the volume is substantially water tight, preferably air/gas tight. | 2014-01-23 |
20140021496 | THIN FILM TRANSISTOR ARRAY AND EL DISPLAY EMPLOYING THEREOF - An EL display has a luminescence unit having a luminescence layer being disposed between the pair of electrodes, and a transistor array unit controlling the luminescence of the luminescence unit. An interlayer insulating film is disposed between the luminescence unit and the transistor array unit. An electrode of the luminescence unit is connected electrically to the transistor array unit via a contact hole provided in the interlayer insulation film. The transistor array unit has a wiring component made of copper or copper alloy. The wiring component has a lower layer pattern made of copper or copper alloy, and an upper layer pattern made of metal material different from that for the lower layer pattern. The upper layer pattern covers the upper surface and the side surface of the lower layer pattern. | 2014-01-23 |
20140021497 | SEMICONDUCTOR LIGHT SOURCE FOR ILLUMINATING A PHYSICAL SPACE INCLUDING A 3-DIMENSIONAL LEAD FRAME - A semiconductor light source for illuminating physical spaces may include a lead frame with multiple facets. Each facet may have one or more semiconductor light emitting devices, such as LEDs, located on it. The light source is disclosed in threaded, surface mounted, and bar light configurations. | 2014-01-23 |
20140021498 | Light Emitting Element, Light Emitting Device Using the Light Emitting Element, and Transparent Substrate Used in Light Emitting Elements - In order to improve the light extraction efficiency of a light-emitting element, the light-emitting element includes: a light-emitting layer provided between an electrode and a transparent substrate; a particle layer provided between the light-emitting layer and the transparent substrate; and an adhesive layer provided between the light-emitting layer and the particle layer, the particle layer includes particles having a refraction index that is higher than a refraction index of the transparent substrate, the adhesive layer has a refraction index that is higher than the refraction index of the transparent substrate, and the particle layer has an average thickness that is less than an average particle size of the particles. | 2014-01-23 |
20140021499 | FLEXIBLE DISPLAY APPARATUS AND METHOD OF FABRICATING THE SAME - A method of forming a flexible display apparatus includes: forming a flexible substrate on a support substrate; forming a light-emitting diode on the flexible substrate; forming a first encapsulation layer on the light-emitting diode; forming a second encapsulation layer; bonding the first encapsulation layer to the second encapsulation layer using an adhesive layer between the first encapsulation layer and the second encapsulation layer; separating the support substrate from the flexible substrate and cutting the flexible substrate to form the flexible display apparatus; and forming a polarizing plate on the second encapsulation layer. | 2014-01-23 |
20140021500 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A light emitting device and a manufacturing method thereof are provided. The light emitting device ( | 2014-01-23 |
20140021501 | Light Emitting Diode Device with Enhanced Heat Dissipation, and the Method of Preparing the Same - The present invention provides a light emitting diode device with enhanced heat dissipation, and the method of preparing the same. By forming the heat dissipating holes and trenches on the phosphor layer, and filling the heat dissipating holes and trenches on the phosphor layer with thermal conducting materials, the service life of the light emitting diode can be longer by reducing the thermal effect and improving the heat dissipation. | 2014-01-23 |
20140021502 | Light-Emitting Device - A highly reliable light-emitting device is provided, which is capable of effectively suppressing detrimental effects of sulfuric gas. A light-emitting device comprising a solid light-emitting element | 2014-01-23 |
20140021503 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes: a package which is made of a resin and includes a recess; a lead frame exposed to a bottom of the recess; a semiconductor light emitting element connected to the lead frame in the recess; a resin layer in contact with the lead frame in the recess and over the bottom of the recess; and a quantum dot phosphor layer above the resin layer and the semiconductor light emitting element, in which the resin layer includes a ceramic fine particle, and the quantum dot phosphor layer includes at least one of semiconductor fine particles having an excitation fluorescence spectrum which differs according to a particle size, and a resin holding the semiconductor fine particles dispersedly. | 2014-01-23 |
20140021504 | LIGHT EMITTING DEVICE - A light emitting device includes: a light emitting section including an active layer configured to emit light by application of a voltage; and a thin metal film disposed on a region of the light emitting section irradiated with the light. The thin metal film has a plurality of openings each having a diameter that is smaller than a wavelength of the light, and at least one phosphor is placed in each of the openings. | 2014-01-23 |
20140021505 | LIGHT-EMITTING DEVICE - This disclosure discloses a light-emitting device. The light-emitting device comprises: a substrate; an intermediate layer formed on the substrate; a transparent bonding layer; a first semiconductor window layer bonded to the semiconductor layer through the transparent bonding layer; and a light-emitting stack formed on the first semiconductor window layer. The intermediate layer has a refractive index between the refractive index of the substrate and the refractive index of the first semiconductor window layer. | 2014-01-23 |
20140021506 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A light emitting device includes a support member, a light emitting element, and an underfill material. The support member includes an insulating member and positive and negative electrically conductive wirings arranged on the insulating member. The electrically conductive wirings are insulated and separated from each other by an insulating region arranged between the positive and negative electrically conductive wirings. The insulating separation region includes a first region disposed on an outer side with respect to the light emitting element and a second region disposed directly under the light emitting element. The first region includes an underfill arranging portion in which an interval between the electrically conductive wirings is wider than in the second region. The underfill material is arranged to extend from the underfill arranging portion to the second region in a space formed between the support member and the light emitting element. | 2014-01-23 |
20140021507 | Optoelectronic Semiconductor Chip and Method for Producing Optoelectronic Semiconductor Chips - An optoelectronic semiconductor chip has a semiconductor body and a substrate on which the semiconductor body is disposed. The semiconductor body has an active region disposed between a first semiconductor layer of a first conductor type and a second semiconductor layer of a second conductor type. The first semiconductor layer is disposed on the side of the active region facing the substrate. The first semiconductor layer is electrically conductively connected to a first termination layer that is disposed between the substrate and the semiconductor body. An encapsulation layer is disposed between the first termination layer and the substrate and, in plan view of the semiconductor chip, projects at least in some regions over a side face which delimits the semiconductor body. | 2014-01-23 |
20140021508 | Thyristor-Based, Dual-Polarity Blocking Photo-Conductive Semiconductor Switch (PCSS) For Short Pulse Switching And Methods - A system and method utilizing thyristor-based Photo-Conductive Semiconductor Switches (PCSS) for short pulse switching in high power microwave and/or broadband electromagnetic pulse generation is disclosed. The PCSS consists of thyristor-type NPNP structure having multiple emitter regions enclosed by the base region and multiple emitter shorts to divert leakage currents for voltage holding. The PCSS also includes an optical aperture comprised of patterned metallic grids for light illumination and current collection. The device structure is so constructed that there is only one single bevel around the peripheral. The thyristor-based PCSS have dual polarities of voltage blocking and have better efficiency for light requirement to operate at longer pulse duration compared to diode-based and bulk-semiconductor-based PCSS. | 2014-01-23 |
20140021509 | SEMICONDUCTOR CONFIGURATION HAVING REDUCED ON-STATE RESISTANCE - A semiconductor configuration, which includes an epitaxial layer of the first conductivity type disposed on a highly doped substrate of first conductivity type; a layer of a second conductivity type introduced into the epitaxial layer; and a highly doped layer of the second conductivity type provided at the surface of the layer of the second conductivity type. Between the layer of the second conductivity type and the highly doped substrate of the first conductivity type, a plurality of Schottky contacts, which are in the floating state, are provided mutually in parallel in the area of the epitaxial layer. | 2014-01-23 |
20140021510 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A higher electron mobility transistor (HEMT) and a method of manufacturing the same are disclosed. According to example embodiments, the HEMT may include a channel supply layer on a channel layer, a source electrode and a drain electrode that are on at least one of the channel layer and the channel supply layer, a gate electrode between the source electrode and the drain electrode, and a source pad and a drain pad. The source pad and a drain pad electrically contact the source electrode and the drain electrode, respectively. At least a portion of at least one of the source pad and the drain pad extends into a corresponding one of the source electrode and drain electrode that the at least one of the source pad and the drain pad is in electrical contact therewith. | 2014-01-23 |
20140021511 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A high electron mobility transistor (HEMT) according to example embodiments includes a channel layer, a channel supply layer on the channel layer, a source electrode and a drain electrode on at least one of the channel layer and the channel supply layer, a gate electrode between the source electrode and the drain electrode, and a Schottky electrode forming a Schottky contact with the channel supply layer. An upper surface of the channel supply layer may define a Schottky electrode accommodation unit. At least part of the Schottky electrode may be in the Schottky electrode accommodation unit. The Schottky electrode is electrically connected to the source electrode. | 2014-01-23 |
20140021512 | METHODS OF MANUFACTURING THE GALLIUM NITRIDE BASED SEMICONDUCTOR DEVICES - Gallium nitride (GaN) based semiconductor devices and methods of manufacturing the same. The GaN-based semiconductor device may include a heterostructure field effect transistor (HFET) or a Schottky diode, arranged on a heat dissipation substrate. The HFET device may include a GaN-based multi-layer having a recess region; a gate arranged in the recess region; and a source and a drain that are arranged on portions of the GaN-based multi-layer at two opposite sides of the gate (or the recess region). The gate, the source, and the drain may be attached to the heat dissipation substrate. The recess region may have a double recess structure. While such a GaN-based semiconductor device is being manufactured, a wafer bonding process and a laser lift-off process may be used. | 2014-01-23 |
20140021513 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A compound semiconductor device includes a substrate; a compound semiconductor layer formed on the substrate; a first insulating film formed on the compound semiconductor layer; a second insulating film formed on the first insulating film; and a gate electrode, a source electrode, and a drain electrode, each being formed on the compound semiconductor layer, wherein the gate electrode is formed of a first opening filled with a first conductive material via at least a gate insulator, and the first opening is formed in the first insulating film and configured to partially expose the compound semiconductor layer, and wherein the source electrode and the drain electrode are formed of a pair of second openings filled with at least a second conductive material, and the second openings are formed in at least the second insulating film and the first insulating film and configured to partially expose the compound semiconductor layer. | 2014-01-23 |
20140021514 | NITRIDE-BASED SEMICONDUCTOR DEVICE - A nitride-based semiconductor diode includes a substrate, a first semiconductor layer disposed on the substrate, and a second semiconductor layer disposed on the first semiconductor layer. The first and second semiconductor layers include a nitride-based semiconductor. A first portion of the second semiconductor layer may have a thickness thinner than a second portion of the second semiconductor layer. The diode may further include an insulating layer disposed on the second semiconductor layer, a first electrode covering the first portion of the second semiconductor layer and forming an ohmic contact with the first semiconductor layer and the second semiconductor layer, and a second electrode separated from the first electrode, the second electrode forming an ohmic contact with the first semiconductor layer and the second semiconductor layer. | 2014-01-23 |
20140021515 | MICROMECHANICAL STRUCTURE, IN PARTICULAR SENSOR ARRANGEMENT, AND CORRESPONDING OPERATING METHOD - A micromechanical structure, in particular a sensor arrangement, includes at least one micromechanical functional layer, a CMOS substrate region arranged below the at least one micromechanical functional layer, and an arrangement of one or more contact elements. The CMOS substrate region has at least one configurable circuit arrangement. The arrangement of one or more contact elements is arranged between the at least one micromechanical functional layer and the CMOS substrate region and is electrically connected to the micromechanical functional layer and the circuit arrangement. The configurable circuit arrangement is designed in such a way that the one or more contact elements are configured to be selectively connected to electrical connection lines in the CMOS substrate region. | 2014-01-23 |
20140021516 | BIOSENSORS INTEGRATED WITH A MICROFLUIDIC STRUCTURE - A biosensor with a microfluidic structure surrounded by an electrode and methods of forming the electrode around the microfluidic structure of the biosensor are provided. A method includes forming a gate or electrode in a first layer. The method further includes forming a trench in a second layer. The method further includes forming a first metal layer in the trench such that the first metal layer is in electrical contact with the gate or the electrode. The method further includes forming a sacrificial material in the trench. The method further includes forming a second metal layer over the sacrificial material and in contact with the first metal layer. The method further includes removing the sacrificial material such that a microfluidic channel is formed surrounded by the first and the second metal layers. | 2014-01-23 |
20140021517 | Semiconductor Device and Fabrication Method Thereof - A semiconductor device and a method for fabricating the semiconductor device are disclosed. An isolation structure is formed in a substrate and a gate stack is formed atop the isolation structure. A spacer is formed adjoining a sidewall of the gate stack and extends beyond an edge of the isolation structure. The disclosed method provides an improved method for protecting the isolation structure by using the spacer. The spacer can prevent the isolation structure from being damaged by chemicals, therefor, to enhance contact landing and upgrade the device performance. | 2014-01-23 |
20140021518 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A display device includes: a first substrate; a photo transistor on the first substrate; and a switching transistor connected to the photo transistor. The photo transistor includes a light blocking film on the first substrate, a first gate electrode on the light blocking film and in contact with the light blocking film, a first semiconductor layer on the first gate electrode and overlapping the light blocking film, and a first source electrode and a first drain electrode on the first semiconductor layer. The switching transistor includes a second gate electrode on the first substrate, a second semiconductor layer on the second gate electrode and overlapping the second gate electrode, and a second source electrode and a second drain electrode on the second semiconductor layer. The first semiconductor layer and the second semiconductor layer are at a same layer of the display device, and each includes crystalline silicon germanium. | 2014-01-23 |
20140021519 | UNIT PIXEL OF IMAGE SENSOR AND PHOTO DETECTOR THEREOF - A unit pixel of an image sensor and a photo detector are disclosed. The photo detector of the present invention configured to absorb light can include: a light-absorbing part configured to absorb light by being formed in a floated structure; an oxide film being in contact with one surface of the light-absorbing part; a source being in contact with one side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; a drain facing the source so as to be in contact with the other side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; and a channel interposed between the source and the drain and configured to form flow of an electric current between the source and the drain. | 2014-01-23 |
20140021520 | SEMICONDUCTOR STORAGE DEVICE - A memory includes a semiconductor substrate. Magnetic tunnel junction elements are provided above the semiconductor substrate. Each of the magnetic tunnel junction elements stores data by a change in a resistance state, and the data is rewritable by a current. Cell transistors are provided on the semiconductor substrate. Each of the cell transistors is in a conductive state when the current is applied to the corresponding magnetic tunnel junction element. Gate electrodes are included in the respective cell transistors. Each of the gate electrodes controls the conductive state of the corresponding cell transistor. In active areas, the cell transistors are provided, and the active areas extend in an extending direction of intersecting the gate electrodes at an angle of (90-atan(1/3)) degrees. | 2014-01-23 |
20140021521 | MOS CAPACITOR, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR DEVICE USING THE SAME - A MOS capacitor, a method of fabricating the same, and a semiconductor device using the same are provided. The MOS capacitor is arranged in an outermost cell block of the semiconductor device employing an open bit line structure. The MOS capacitor includes a first electrode arranged in a semiconductor substrate, a dielectric layer arranged on a semiconductor substrate, and a second electrode arranged on the dielectric layer and including a dummy bit line. | 2014-01-23 |
20140021522 | CHIP PACKAGES WITH POWER MANAGEMENT INTEGRATED CIRCUITS AND RELATED TECHNIQUES - Chip packages having power management integrated circuits are described. Power management integrated circuits can be combined with on-chip passive devices, and can provide voltage regulation, voltage conversion, dynamic voltage scaling, and battery management or charging. The on-chip passive devices can include inductors, capacitors, or resistors. Power management using a built-in voltage regulator or converter can provide for immediate adjustment of the voltage range to that which is needed. This improvement allows for easier control of electrical devices of different working voltages and decreases response time of electrical devices. Related fabrication techniques are described. | 2014-01-23 |
20140021523 | DRAM WITH DUAL LEVEL WORD LINES - A top semiconductor layer and conductive cap structures over deep trench capacitors are simultaneously patterned by an etch. Each patterned portion of the conductive cap structures constitutes a conductive cap structure, which laterally contacts a semiconductor material portion that is one of patterned remaining portions of the top semiconductor layer. Gate electrodes are formed as discrete structures that are not interconnected. After formation and planarization of a contact-level dielectric layer, passing gate lines are formed above the contact-level dielectric layer in a line level to provide electrical connections to the gate electrodes. Gate electrodes and passing gate lines that are electrically connected among one another constitute a gate line that is present across two levels. | 2014-01-23 |
20140021524 | NON-VOLATILE MEMORY DEVICES HAVING AIR GAPS AND METHODS OF MANUFACTURING THE SAME - Disclosed are non-volatile memory devices and methods of manufacturing the same. The non-volatile memory device includes device isolation patterns defining active portions in a substrate and gate structures disposed on the substrate. The active portions are spaced apart from each other in a first direction and extend in a second direction perpendicular to the first direction. The gate structures are spaced apart from each other in the second direction and extend in the first direction. Each of the device isolation patterns includes a first air gap, and each of a top surface and a bottom surface of the first air gap has a wave-shape in a cross-sectional view taken along the second direction. | 2014-01-23 |
20140021525 | NONVOLATILE SEMICONDUCTOR MEMORY TRANSISTOR, NONVOLATILE SEMICONDUCTOR MEMORY, AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory transistor included in a nonvolatile semiconductor memory includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the substrate side, a hollow pillar-shaped floating gate arranged so as to surround the outer periphery of the channel region in such a manner that a tunnel insulating film is interposed between the floating gate and the channel region, and a hollow pillar-shaped control gate arranged so as to surround the outer periphery of the floating gate in such a manner that an inter-polysilicon insulating film is interposed between the control gate and the floating gate. The inter-polysilicon insulating film is arranged so as to be interposed between the floating gate and the upper, lower, and inner side surfaces of the control gate. | 2014-01-23 |
20140021526 | ELECTRONIC DEVICE INCLUDING A TUNNEL STRUCTURE - An electronic device can include a tunnel structure that includes a first electrode, a second electrode, and tunnel dielectric layer disposed between the electrodes. In a particular embodiment, the tunnel structure may or may not include an intermediate doped region that is at the primary surface, abuts a lightly doped region, and has a second conductivity type opposite from and a dopant concentration greater than the lightly doped region. In another embodiment, the electrodes have opposite conductivity types. In a further embodiment, an electrode can be formed from a portion of a substrate or well region, and the other electrode can be formed over such portion of the substrate or well region. | 2014-01-23 |
20140021527 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a charge storage structure and a gate. The charge storage structure is formed on a substrate. The gate is formed on the charge storage structure. The gate includes a lower portion formed of silicon and an upper portion formed of metal silicide. The upper portion of the gate has a width greater than that of the lower portion of the gate. | 2014-01-23 |
20140021528 | SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor region; a plurality of stacked structures each of which is disposed on the semiconductor region and has a tunnel insulating film, a charge storage layer, an upper insulating layer, and a control electrode stacked sequentially; an element isolation insulating layer disposed on side faces of the plurality of stacked structures; and a source-drain region disposed on the semiconductor region and among the plurality of stacked structures. The element isolation insulating layer includes at least one of SiO | 2014-01-23 |
20140021529 | FLASH MEMORY DEVICE WITH WORD LINES OF UNIFORM WIDTH AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing a semiconductor device, the method including: forming a bit line in a semiconductor substrate; forming a plurality of word lines which intersect with the bit line at predetermined intervals on the semiconductor substrate; eliminating a portion of the plurality of word lines; forming an interlayer insulating film on the semiconductor substrate; and forming a metal plug which penetrates through the interlayer insulating film and is coupled to the bit line in a region where the portion of the plurality of word lines was eliminated. | 2014-01-23 |
20140021530 | ELECTRONIC SYSTEMS HAVING SUBSTANTIALLY VERTICAL SEMICONDUCTOR STRUCTURES - An electronic system has first and second substantially vertical semiconductor structures. A first string of series-coupled first memory cells is adjacent to the first semiconductor structure, and a second string of series-coupled second memory cells is adjacent to the second semiconductor structure. | 2014-01-23 |
20140021531 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a stacked structure, a select gate electrode, a semiconductor pillar, a memory layer, and a select gate insulating film. The stacked structure includes a plurality of electrode films stacked in a first direction and an interelectrode insulating film provided between the electrode films. The select gate electrode is stacked with the stacked structure along the first direction and includes a plurality of select gate conductive films stacked in the first direction and an inter-select gate conductive film insulating film provided between the select gate conductive films. The semiconductor pillar pierces the stacked structure and the select gate electrode in the first direction. The memory layer is provided between the electrode films and the semiconductor pillar. The select gate insulating film is provided between the select gate conductive films and the semiconductor pillar. | 2014-01-23 |
20140021532 | VERTICAL TUNNEL FIELD EFFECT TRANSISTOR (FET) - Among other things, one or more techniques for forming a vertical tunnel field effect transistor (FET), and a resulting vertical tunnel FET are provided herein. In an embodiment, the vertical tunnel FET is formed by forming a core over a first type substrate region, forming a second type channel shell around a circumference greater than a core circumference, forming a gate dielectric around a circumference greater than the core circumference, forming a gate electrode around a circumference greater than the core circumference, and forming a second type region over a portion of the second type channel shell, where the second type has a doping opposite a doping of the first type. In this manner, line tunneling is enabled, thus providing enhanced tunneling efficiency for a vertical tunnel FET. | 2014-01-23 |
20140021533 | SELF-ALIGNED PROCESS TO FABRICATE A MEMORY CELL ARRAY WITH A SURROUNDING-GATE ACCESS TRANSISTOR - A memory array including a plurality of memory cells. In one embodiment, each memory cell is coupled to an electrically conductive gate material. A word line is coupled to the gate material at a contact interface level. A pair of pillars is comprised of an insulating material that extends below the contact interface level. Also, a method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes depositing and etching gate material to partially fill a space between the pillars and to form a word line for the memory cells, forming a pair of pillars comprised of an insulating material and depositing a gate contact between the pair of pillars such that the gate contact electrically couples the gate material at a contact interface level and the insulating material extends below the contact interface level. | 2014-01-23 |
20140021534 | INTEGRATION OF HIGH VOLTAGE TRENCH TRANSISTOR WITH LOW VOLTAGE CMOS TRANSISTOR - A method of forming a device is disclosed. A substrate defined with a device region is provided. A gate having an upper and a lower portion is formed in a trench in the substrate in the device region. The upper portion forms a gate electrode and the lower portion forms a gate field plate. First and second surface doped regions are formed adjacent to the gate. The gate field plate introduces vertical reduced surface (RESURF) effect in a drift region of the device. | 2014-01-23 |
20140021535 | SEMICONDUCTOR DEVICE HAVING VERTICAL GATES AND FABRICATION THEREOF - A method for forming a semiconductor device with a vertical gate is disclosed, including providing a substrate, forming a recess in the substrate, forming a gate dielectric layer on a sidewall and a bottom of the recess, forming an adhesion layer in the recess and on the gate dielectric layer, wherein the adhesion layer is a metal silicide nitride layer, and forming a gate layer in the recess and on the adhesion layer. | 2014-01-23 |
20140021536 | LATERAL DEVICES CONTAINING PERMANENT CHARGE - A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges are embedded in the insulation region, sufficient to cause inversion in the insulation region. | 2014-01-23 |
20140021537 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for forming the same includes a pillar formed over a semiconductor substrate, a buried bit line formed below the semiconductor substrate, a vertical gate formed over a sidewall of the pillar, an insulation film pattern formed to expose one side of the vertical gate disposed between the pillars, and a word line coupled to the exposed vertical gate. The vertical gate is formed to cover a portion of a sidewall of the pillar with a metal material, a word line overlaps with some parts of the vertical gate, and some parts of the pillar are shifted to be coupled to the vertical gate. | 2014-01-23 |
20140021538 | Replacement Gate Fin First Wire Last Gate All Around Devices - In one aspect, a method of fabricating a nanowire FET device includes the following steps. A wafer is provided. At least one sacrificial layer and silicon layer are formed on the wafer in a stack. Fins are patterned in the stack. Dummy gates are formed over portions of the fins which will serve as channel regions, and wherein one or more portions of the fins which remain exposed will serve as source and drain regions. A gap filler material is deposited surrounding the dummy gates and planarized. The dummy gates are removed forming trenches in the gap filler material. Portions of the silicon layer (which will serve as nanowire channels) are released from the fins within the trenches. Replacement gates are formed within the trenches that surround the nanowire channels in a gate all around configuration. A nanowire FET device is also provided. | 2014-01-23 |
20140021539 | Power Transistor with High Voltage Counter Implant - Presented herein is a field effect transistor device, optionally a lateral power transistor, and a method for forming the same, comprising providing a substrate, creating a doped buried layer, and creating a primary well in the substrate on the buried layer. A drift drain may be created in the primary well and a counter implant region implanted in the primary well and between the drift drain and the buried layer. The primary well may comprise a first and second implant region with the second implant region at a depth less than the first. The counter implant may be at a depth between the first and second implant regions. The primary well and counter implant region may comprise dopants of the same conductivity type, or both p+-type dopants. A gate may be formed over a portion of a drift drain. | 2014-01-23 |
20140021540 | LDMOS SENSE TRANSISTOR STRUCTURE FOR CURRENT SENSING AT HIGH VOLTAGE - An integrated circuit includes a high voltage n-channel MOS power transistor integrated with a high voltage n-channel MOS blocking transistor. The power transistor and the blocking transistor have electrically coupled drain contact regions. In one embodiment, a drain area of the power transistor is separate from a drain area of the blocking transistor. In another embodiment, the drain area of the power transistor is contiguous with the drain area of the blocking transistor. The power transistor and the blocking transistor have drain extensions with drift areas. The power transistor drift area is laterally adjacent to both sides of the blocking transistor drift area. The drift areas are aligned so that breakdown does not occur between the power transistor and the blocking transistor. The body of the blocking transistor is isolated from the substrate. | 2014-01-23 |
20140021541 | SEMICONDUCTOR DEVICE - A semiconductor device includes a second conductive-type deep well configured above a substrate. The deep well includes an ion implantation region and a diffusion region. A first conductive-type first well is formed in the diffusion region. A gate electrode extends over portions of the ion implantation region and of the diffusion region, and partially overlaps the first well. The ion implantation region has a uniform impurity concentration whereas the impurity concentration of the diffusion region varies from being the highest concentration at the boundary interface between the ion implantation region and the diffusion region to being the lowest at the portion of the diffusion region that is the farthest away from the boundary interface. | 2014-01-23 |
20140021542 | SEMICONDUCTOR DEVICE - A semiconductor device includes a second conductive-type deep well configured above a substrate. The deep well includes an ion implantation region and a diffusion region. A first conductive-type first well is formed in the diffusion region. A gate electrode extends over portions of the ion implantation region and of the diffusion region, and partially overlaps the first well. The ion implantation region has a uniform impurity concentration whereas the impurity concentration of the diffusion region varies from being the highest concentration at the boundary interface between the ion implantation region and the diffusion region to being the lowest at the portion of the diffusion region that is the farthest away from the boundary interface. | 2014-01-23 |
20140021543 | LOW THRESHOLD VOLTAGE METAL OXIDE SEMICONDUCTOR - A semiconductor device includes a source region disposed with a semiconductor substrate; a drain region disposed with the semiconductor substrate; a gate region disposed onto the semiconductor substrate and positioned between the source region and the drain region. The semiconductor device also includes a gate oxide region disposed onto the semiconductor substrate in contact with the gate region and a well region implanted onto the semiconductor substrate and under the gate region and the gate oxide region. The gate oxide region has a lower outer edge portion that contacts the well region. | 2014-01-23 |
20140021544 | Double Diffused Drain Metal Oxide Semiconductor Device and Manufacturing Method Thereof - The present invention discloses a double diffused drain metal oxide semiconductor (DDDMOS) device and a manufacturing method thereof. The DDDMOS device is formed in a substrate, and includes a first well, a gate, a diffusion region, a source, and a drain. A low voltage device is also formed in the substrate, which includes a second well and a lightly doped drain (LDD) region, wherein the first well and the diffusion region are formed by process steps which also form the second well and the LDD region in the low voltage device, respectively. | 2014-01-23 |
20140021545 | POCKET COUNTERDOPING FOR GATE-EDGE DIODE LEAKAGE REDUCTION - A method of fabricating a Metal-Oxide Semiconductor (MOS) transistor includes providing a substrate having a substrate surface doped with a second dopant type and a gate stack over the substrate surface, and a masking pattern on the substrate surface which exposes a portion of the substrate surface for ion implantation. A first pocket implantation uses the second dopant type with the masking pattern on the substrate surface. At least one retrograde gate edge diode leakage (GDL) reduction pocket implantation uses the first dopant type with the masking pattern on the substrate surface. The first pocket implant and retrograde GDL reduction pocket implant are annealed. After annealing, the first pocket implant provides first pocket regions and the retrograde GDL reduction pocket implant provides an overlap with the first pocket regions to form a first counterdoped pocket portion within the first pocket regions. | 2014-01-23 |
20140021546 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate of a first conductivity type, a first region of a second conductivity type formed in the semiconductor substrate, a second region of the first conductivity type formed in the first region, a source region of the second conductivity type formed in the second region, a drain region of the second conductivity type formed in the first region, a first junction part including a part of a border between the first region and the second region, which is on the side of the drain region, a second junction part including a part of the border between the first region and the second region, which is at a location different from the first junction part, a gate electrode formed above the first junction, and a conductor pattern formed above the second junction part and being electrically independent from the gate electrode. | 2014-01-23 |
20140021547 | INTEGRATED CIRCUIT INCLUDING TRANSISTOR STRUCTURE ON DEPLETED SILICON-ON-INSULATOR, RELATED METHOD AND DESIGN STRUCTURE - An Integrated Circuit (IC) and a method of making the same. In one embodiment, the IC includes: a substrate; a first semiconductor layer disposed on the substrate; a shallow trench isolation (STI) extending through the first semiconductor layer to within a portion of the substrate, the STI substantially separating a first n+ region and a second n+ region; and a gate disposed on a portion of the first semiconductor layer and connected to the STI, the gate including: a buried metal oxide (BOX) layer disposed on the first semiconductor layer and connected to the STI; a cap layer disposed on the BOX layer; and a p-type well component disposed within the first semiconductor layer and the substrate, the p-type well component connected to the second n+ region. | 2014-01-23 |