04th week of 2014 patent applcation highlights part 15 |
Patent application number | Title | Published |
20140021548 | SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE WITH SELECTIVELY PLACED SUB-INSULATOR LAYER VOID(S) AND METHOD OF FORMING THE SOI STRUCTURE - Disclosed is a semiconductor-on-insulator (SOI) structure (e.g., an SOI field effect transistor (FET)) and method of forming the SOI structure so as to have sub-insulator layer void(s) selectively placed so that capacitance coupling between a first section of a semiconductor layer and the substrate will be less than capacitance coupling between a second section of the semiconductor layer and the substrate. The first section may contain a first device and the second section may contain a second device. Alternatively, the first and second sections may comprise different regions of the same device. For example, in an SOI FET, sub-insulator layer voids can be selectively placed in the substrate below the source, drain and/or body contact diffusion regions, but not below the channel region so that capacitance coupling between the these various diffusion regions and the substrate will be less than capacitance coupling between the channel region and the substrate. | 2014-01-23 |
20140021549 | Method of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled Rectifier Principle - An exemplary semiconductor memory cell is provided to include: a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; a gate positioned between the first and second regions; a buried layer region in electrical contact with the floating body region, below the first and second regions, spaced apart from the first and second regions; and a substrate region configured to inject charge into the floating body region to maintain the state of the memory cell; wherein an amount of charge injected into the floating body region is a function of a charge stored in the floating body region. | 2014-01-23 |
20140021550 | Transistor Structures And Integrated Circuitry Comprising An Array of Transistor Structures - This invention includes a capacitorless one transistor DRAM cell that includes a pair of spaced source/drain regions received within semiconductive material. An electrically floating body region is disposed between the source/drain regions within the semiconductive material. A first gate spaced is apart from and capacitively coupled to the body region between the source/drain regions. A pair of opposing conductively interconnected second gates are spaced from and received laterally outward of the first gate. The second gates are spaced from and capacitively coupled to the body region laterally outward of the first gate and between the pair of source/drain regions. Methods of forming lines of capacitorless one transistor DRAM cells are disclosed. | 2014-01-23 |
20140021551 | SEMICONDUCTOR DEVICES AND METHOD OF MANUFACTURING THE SAME - Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device includes active portions defined in a semiconductor substrate, a device isolation pattern in a trench formed between the active portions, a gate electrode in a gate recess region crossing the active portions and the device isolation pattern, a gate dielectric layer between the gate electrode and an inner surface of the gate recess region, and a first ohmic pattern and a second ohmic pattern on each of the active portions at both sides of the gate electrode, respectively. The first and second ohmic patterns include a metal-semiconductor compound, and a top surface of the device isolation pattern at both sides of the gate recess region is recessed to be lower than a level of a top surface of the semiconductor substrate. | 2014-01-23 |
20140021552 | Strain Adjustment in the Formation of MOS Devices - A method includes forming a gate stack over a semiconductor substrate, and forming a gate spacer on a sidewall of the gate stack. After the step of forming the gate spacer, the gate spacer is etched to reduce a thickness of the gate spacer. A strained layer is then formed. The strained layer includes a portion on an outer sidewall of the gate spacer, and a portion over the gate stack. | 2014-01-23 |
20140021553 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method for fabricating a semiconductor device includes defining a curved active region by forming a plurality of trenches over a semiconductor substrate, forming an insulating layer to fill the plurality of trenches, and forming a pair of gate lines crossing the curved active region, so that it is possible to prevent leaning of an active region by forming a curved active region. | 2014-01-23 |
20140021554 | SOURCE/DRAIN-TO-SOURCE/DRAIN RECESSED STRAP AND METHODS OF MANUFACTURE OF SAME - A structure and a method of making the structure. The structure includes first and second semiconductor regions in a semiconductor substrate and separated by a region of trench isolation in the semiconductor substrate; a first gate electrode extending over the first semiconductor region; a second gate electrode extending over the second semiconductor region; a trench contained in the region of trench isolation and between and abutting the first and second semiconductor regions; and an electrically conductive strap in the trench, the strap electrically connecting the first and second semiconductor regions. | 2014-01-23 |
20140021555 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device according to an embodiment includes forming element isolation regions and active areas on a surface of a semiconductor substrate. A plurality of gate electrodes are formed above the active areas. Recesses that recess below surfaces of the element isolation regions are formed in the active areas by selectively etching the active areas between the gate electrodes. An interlayer dielectric film is deposited on the active areas, the element isolation regions, and the gate electrodes. A contact holes are formed on the recesses by etching the interlayer dielectric film using anisotropic etching. A bottom of each contact holes is widened by further etching the interlayer dielectric film on an inner wall of each contact hole using isotropic etching. Contacts contacting the recesses in the active areas are formed by embedding a conductive material in the contact holes. | 2014-01-23 |
20140021556 | SPACER SHAPER FORMATION WITH CONFORMAL DIELECTRIC FILM FOR VOID FREE PMD GAP FILL - An integrated circuit may be formed by removing source/drain spacers from offset spacers on sidewalls of MOS transistor gates, forming a contact etch stop layer (CESL) spacer layer on lateral surfaces of the MOS transistor gates, etching back the CESL spacer layer to form sloped CESL spacers on the lateral surfaces of the MOS transistor gates with heights of ¼ to ¾ of the MOS transistor gates, forming a CESL over the sloped CESL spacers, the MOS transistor gates and the intervening substrate, and forming a PMD layer over the CESL. | 2014-01-23 |
20140021557 | APPARATUS FOR FORWARD WELL BIAS IN A SEMICONDUCTOR INTEGRATED CIRCUIT - There is provided a semiconductor Integrated Circuit device having forward well biasing, in which at least one protection device is connected between a supply voltage and a forward well bias voltage. | 2014-01-23 |
20140021558 | Dummy Gate for a High Voltage Transistor Device - The present disclosure provides a semiconductor device. The semiconductor device includes a first doped region and a second doped region both formed in a substrate. The first and second doped regions are oppositely doped. The semiconductor device includes a first gate formed over the substrate. The first gate overlies a portion of the first doped region and a portion of the second doped region. The semiconductor device includes a second gate formed over the substrate. The second gate overlies a different portion of the second doped region. The semiconductor device includes a first voltage source that provides a first voltage to the second gate. The semiconductor device includes a second voltage source that provides a second voltage to the second doped region. The first and second voltages are different from each other. | 2014-01-23 |
20140021559 | SEMICONDUCTOR DEVICE AND A METHOD OF INCREASING A RESISTANCE VALUE OF AN ELECTRIC FUSE - Provided is a semiconductor device having an electric fuse structure which receives the supply of an electric current to be permitted to be cut without damaging portions around the fuse. An electric fuse is electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the supply of an electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers. | 2014-01-23 |
20140021560 | HIGH VOLTAGE DEVICE WITH A PARALLEL RESISTOR - Provided is a high voltage semiconductor device. The high voltage semiconductor device includes a transistor having a gate, a source, and a drain. The source and the drain are formed in a doped substrate and are separated by a drift region of the substrate. The gate is formed over the drift region and between the source and the drain. The transistor is configured to handle high voltage conditions that are at least a few hundred volts. The high voltage semiconductor device includes a dielectric structure formed between the source and the drain of the transistor. The dielectric structure protrudes into and out of the substrate. Different parts of the dielectric structure have uneven thicknesses. The high voltage semiconductor device includes a resistor formed over the dielectric structure. The resistor has a plurality of winding segments that are substantially evenly spaced apart. | 2014-01-23 |
20140021561 | Microfabrication of High Quality Three Dimensional Structures Using Wafer-Level Glassblowing of Fused Quartz and Ultra Low Expansion Glasses - A high temperature micro-glassblowing process and a novel inverted-wineglass architecture that provides self-aligned stem structures. The fabrication process involves the etching of a fused quartz substrate wafer. A TSG or fused quartz device layer is then bonded onto the fused quartz substrate, creating a trapped air pocket or cavity between the substrate and the TSG device layer. The substrate and TSG device layer | 2014-01-23 |
20140021562 | MEMS DEVICE, ELECTRONIC MODULE, ELECTRONIC APPARATUS, AND MOBILE UNIT - A MEMS device includes: a base substrate; a first wiring disposed on the base substrate using a first structure; a second wiring disposed on the base substrate using the first structure and a second structure connected to the first structure; and a MEMS element connected with the first wiring and the second wiring and arranged on the base substrate, wherein the first wiring and the second wiring include a crossing portion where the first wiring and the second wiring cross each other, and at the crossing portion, the first structure of the first wiring and the second structure of the second wiring cross each other. | 2014-01-23 |
20140021563 | Pressure Resistently Encapsulated, Pressure Difference Sensor - A pressure difference sensor includes a capsule, which has a ceramic capsule body. The capsule has a transducer seat in its interior, wherein there is arranged in the transducer seat a semiconductor pressure measuring transducer core, which has a measuring membrane body and at least one support body. The measuring membrane body is connected pressure-tightly with the at least one support body, which has a pressure inlet opening. Ducts extend respectively from an outer surface of the capsule into the transducer seat, wherein the pressure inlet opening communicates with the first duct A side of the measuring membrane is contactable with a pressure through the pressure inlet opening, wherein the support body contacts a joint, which surrounds the first pressure inlet opening and the opening of the first duct into the transducer seat and is connected pressure-tightly with a wall of the transducer seat, and wherein a second side of the measuring membrane is hydraulically isolated from its first side and communicates with the second duct. | 2014-01-23 |
20140021564 | MICROELECTROMECHANICAL GYROSCOPE WITH ENHANCED REJECTION OF ACCELERATION NOISES - An integrated microelectromechanical structure is provided with a driving mass, anchored to a substrate via elastic anchorage elements and designed to be actuated in a plane with a driving movement; and a first sensing mass and a second sensing mass, suspended within, and coupled to, the driving mass via respective elastic supporting elements so as to be fixed with respect thereto in said driving movement and to perform a respective detection movement in response to an angular velocity. In particular, the first and the second sensing masses are connected together via elastic coupling elements, configured to couple their modes of vibration. | 2014-01-23 |
20140021565 | SENSOR PACKAGE - A sensor package has a semiconductor sensor chip, and a package body that has a semiconductor sensor chip mounting region on which the semiconductor sensor chip is mounted. The package body being a resin injection molded product. A groove is formed in a rear surface on an opposite side to a surface, on which the semiconductor sensor chip is mounted, so as to surround the semiconductor sensor chip mounting region. A coupling section is formed in the rear surface to couple a resin portion inside the groove and a resin portion outside the groove. | 2014-01-23 |
20140021566 | MAGNETIC DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a magnetic memory device and a method of fabricating the same. The device may include a magnetic tunnel junction including a lower magnetic structure, an upper magnetic structure, and a tunnel barrier interposed therebetween. The tunnel barrier may have a width greater than that of the lower magnetic structure. | 2014-01-23 |
20140021567 | MAGNENTIC RESISTANCE MEMORY APPARATUS HAVING MULTI LEVELS AND METHOD OF DRIVING THE SAME - A magnetic resistance memory apparatus capable of implementing various levels and a method of driving the same are provided. The magnetic resistance memory apparatus includes a first magnetic device that includes a fixed layer having a fixed magnetization direction, a tunnel layer disposed on the fixed layer, and a first free layer disposed on the tunnel layer having a variable magnetization direction, and a second magnetic device disposed on the first magnetic device including a plurality of free layers insulated with a spacer layer interposed. | 2014-01-23 |
20140021568 | MAGNENTIC RESISTANCE MEMORY APPARATUS HAVING MULTI LEVELS AND METHOD OF DRIVING THE SAME - A magnetic resistance memory apparatus capable of implementing various levels and a method of driving the same are provided. The magnetic resistance memory apparatus includes a first magnetic device that includes a fixed layer having a fixed magnetization direction, a tunnel layer disposed on the fixed layer, and a first free layer disposed on the tunnel layer having a variable magnetization direction, and a second magnetic device disposed on the first magnetic device including a plurality of free layers insulated with a spacer layer interposed. | 2014-01-23 |
20140021569 | SPIN-FILTER AND DETECTOR COMPRISING THE SAME - A spin-filter for detection of angular momentum of electrons, wherein the spin-filter ( | 2014-01-23 |
20140021570 | METHODS OF INTEGRATED SHIELDING INTO MTJ DEVICE FOR MRAM - Methods and apparatus for shielding a shielding a non-volatile memory, such as shielding a magnetic tunnel junction (MTJ) device from a magnetic flux are provided. In an example, a shielding layer is formed adjacent to an electrode of an MTJ device, such that the shielding layer substantially surrounds a surface of the electrode, and a metal line is coupled to the shielding layer. The metal line can be coupled to the shielding layer by a via. | 2014-01-23 |
20140021571 | Single-chip bridge-type magnetic field sensor and preparation method thereof - The present invention discloses a design and manufacturing method for a single-chip magnetic sensor bridge. The sensor bridge comprises four magnetoresistive elements. The magnetization of the pinned layer of each of the four magnetoresistive elements is set in the same direction, but the magnetization directions of the free layers of the magnetoresistive elements on adjacent arms of the bridge are set at different angles with respect to the pinned layer magnetization direction. The absolute values of the angles of the magnetization directions of the free layers of all four magnetoresistive elements are the same with respect with their pinning layers. The disclosed magnetic biasing scheme enables the integration of a push-pull Wheatstone bridge magnetic field sensor on a single chip with better performance, lower cost, and easier manufacturability than conventional magnetoresistive sensor designs. | 2014-01-23 |
20140021572 | PHOTODIODE DEVICE AND METHOD FOR PRODUCTION THEREOF - The photodiode device has an electrically conductive cathode layer ( | 2014-01-23 |
20140021573 | SOLID-STATE IMAGING DEVICE AND MANUFACTURING METHOD OF SOLID-STATE IMAGING DEVICE - A light receiving layer is formed with an array of photodiodes for accumulating signal charge produced by photoelectric conversion of incident light. A wiring layer provided with electrodes and wiring for controlling the photodiodes is formed behind the light receiving layer in a traveling direction of the incident light. In the light receiving layer, there is formed a projection and depression structure in which a pair of inclined surfaces have symmetric inclination directions and each inclined surface corresponds to each photodiode. Each inclined surface makes the incident light enter each photodiode by a light amount corresponding to an incident angle. | 2014-01-23 |
20140021574 | SOLID-STATE IMAGING DEVICE - According to one embodiment, provided are a first photoelectric conversion layer provided for a first wavelength band, a second photoelectric conversion layer provided for a second wavelength band, and a color separation element adapted to separate an incident light into a transmission light including the first wavelength band and a reflection light including the second wavelength band, wherein an angle of incidence of the incident light with respect to a reflection surface of the color separation element is set so that a vertically polarized light and a horizontally polarized light are included in the reflection light. | 2014-01-23 |
20140021575 | PHOTODIODE ARRAY MODULE AND MANUFACTURING METHOD FOR SAME - This photodiode array module includes a first semiconductor substrate | 2014-01-23 |
20140021576 | MINIATURE THERMOELECTRIC ENERGY HARVESTER AND FABRICATION METHOD THEREOF - A miniature thermoelectric energy harvester and a fabrication method thereof Annular grooves are fabricated on a low-resistivity silicon substrate to define silicon thermoelectric columns, an insulating layer is fabricated on the annular grooves, a thermoelectric material is filled in the annular grooves to form annular thermoelectric columns, and then metal wirings, passivation layers and supporting substrates are fabricated, thereby completing the fabrication process. The silicon thermoelectric column using a silicon base material simplifies the fabrication process. The fabrication of the thermocouple structure is one thin-film deposition process, which simplifies the process. The use of silicon as a component of the thermocouple has a high Seebeck coefficient. The use of vertical thermocouples improves the stability. Since the thermocouple structure is bonded to the upper supporting substrate and lower supporting substrate by wafer-level bonding, the fabrication efficiency is improved. | 2014-01-23 |
20140021577 | SEMICONDUCTOR STRUCTURES AND DEVICES AND METHODS OF FORMING THE SAME - Methods of forming semiconductor structures that include bodies of a semiconductor material disposed between rails of a dielectric material are disclosed. Such methods may include filling a plurality of trenches in a substrate with a dielectric material and removing portions of the substrate between the dielectric material to form a plurality of openings. In some embodiments, portions of the substrate may be undercut to form a continuous void underlying the bodies and the continuous void may be filled with a conductive material. In other embodiments, portions of the substrate exposed within the openings may be converted to a silicide material to form a conductive material under the bodies. For example, the conductive material may be used as a conductive line to electrically interconnect memory device components. Semiconductor structures and devices formed by such methods are also disclosed. | 2014-01-23 |
20140021578 | VERTICAL ELECTRONIC FUSE - An electronic fuse structure including a first M | 2014-01-23 |
20140021579 | INTEGRATED CIRCUIT WITH A FIN-BASED FUSE, AND RELATED FABRICATION METHOD - Methods of fabricating an integrated circuit with a fin-based fuse, and the resulting integrated circuit with a fin-based fuse are provided. In the method, a fin is created from a layer of semiconductor material and has a first end and a second end. The method provides for forming a conductive path on the fin from its first end to its second end. The conductive path is electrically connected to a programming device that is capable of selectively directing a programming current through the conductive path to cause a structural change in the conductive path to increase resistance across the conductive path. | 2014-01-23 |
20140021580 | SEMICONDUCTOR DEVICES HAVING E-FUSE STRUCTURES AND METHODS OF FABRICATING THE SAME - A semiconductor device includes: an e-fuse gate, a floating pattern between the e-fuse gate and an e-fuse active portion, a blocking dielectric pattern between the floating pattern and the e-fuse gate, and an e-fuse dielectric layer between the floating pattern and the e-fuse active portion. The floating pattern includes a first portion between the e-fuse gate and the e-fuse active portion and a pair of second portions extended upward along both sidewalls of the e-fuse gate from both edges of the first portion. | 2014-01-23 |
20140021581 | LOW COST ANTI-FUSE STRUCTURE - An anti-fuse structure is provided in which an anti-fuse material liner is embedded within one of the openings provided within an interconnect dielectric material. The anti-fuse material liner is located between a first conductive metal and a second conductive metal which are also present within the opening. A diffusion barrier liner separates the first conductive metal from any portion of the interconnect dielectric material. The anti-fuse structure is laterally adjacent an interconnect structure that is formed within the same interconnect dielectric material as the anti-fuse structure. | 2014-01-23 |
20140021582 | CONFIGURABLE PASSIVE COMPONENTS - A wafer of passive components is diced to leave a flat passive chip. The flat passive chip has bond pads for passive components on a same side of the flat passive chip. The flat passive chip is stacked onto an active chip. The passive components are wirebonded together to connect the passive components in series or parallel, resulting in the flat passive chip having an overall passive characteristic equal to a target characteristic. | 2014-01-23 |
20140021583 | PACKAGE STRUCTURES INCLUDING A CAPACITOR AND METHODS OF FORMING THE SAME - A package includes a die, an encapsulant, and a capacitor. The package has a package first side and a package second side. The die has a die first side corresponding to the package first side, and has a die second side corresponding to the package second side. The die first side is opposite the die second side. The encapsulant surrounds the die. The capacitor includes a first plate and a second plate in the encapsulant, and opposing surfaces of the first plate and the second plate extend in a direction from the package first side to the package second side. The external conductive connectors are attached to at least one of the package first side and the package second side. | 2014-01-23 |
20140021584 | PROCESS-COMPATIBLE DECOUPLING CAPACITOR AND METHOD FOR MAKING THE SAME - Provided is decoupling capacitor device. The decoupling capacitor device includes a first dielectric layer portion that is deposited in a deposition process that also deposits a second dielectric layer portion for a non-volatile memory cell. Both portions are patterned using a single mask. A system-on-chip (SOC) device is also provided, the SOC include an RRAM cell and a decoupling capacitor situated in a single inter-metal dielectric layer. Also a method for forming a process-compatible decoupling capacitor is provided. The method includes patterning a top electrode layer, an insulating layer, and a bottom electrode layer to form a non-volatile memory element and a decoupling capacitor. | 2014-01-23 |
20140021585 | CREATING DEEP TRENCHES ON UNDERLYING SUBSTRATE - A semiconductor structure and method of fabricating the same are disclosed. In an embodiment, the structure includes a first substrate having a buried plate or plates in the substrate. Each buried plate includes at least one buried plate contact, and a plurality of deep trench capacitors disposed about the at least one buried plate contact. A first oxide layer is disposed over the first substrate. The deep trench capacitors and buried plate contacts in the first substrate may be accessed for use in a variety of memory and decoupling applications. | 2014-01-23 |
20140021586 | METHOD FOR MANUFACTURING A POLYCRYSTALLINE DIELECTRIC LAYER - A method manufactures a capacitor having polycrystalline dielectric layer between two metallic electrodes. The dielectric layer is formed by a polycrystalline growth of a dielectric metallic oxide on one of the metallic electrodes. At least one polycrystalline growth condition of the dielectric oxide is modified during the formation of the polycrystalline dielectric layer, which results in a variation of the polycrystalline properties of the dielectric oxide within the thickness of said layer. | 2014-01-23 |
20140021587 | LOCAL WIRING FOR A BIPOLAR JUNCTION TRANSISTOR INCLUDING A SELF-ALIGNED EMITTER REGION - Aspects of the invention provide for a bipolar transistor of a self-aligned emitter. In one embodiment, the invention provides a method of forming local wiring for a bipolar transistor with a self-aligned sacrificial emitter, including: performing an etch to remove the sacrificial emitter to form an emitter opening between two nitride spacers; depositing an in-situ doped emitter into the emitter opening; performing a recess etch to partially remove a portion of the in-situ doped emitter; depositing a silicon dioxide layer over the recessed in-situ doped emitter; planarizing the silicon dioxide layer via chemical mechanical polishing; etching an emitter trench over the recessed in-situ doped emitter; and depositing tungsten and forming a tungsten wiring within the emitter trench via chemical mechanical polishing. | 2014-01-23 |
20140021588 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD - The object to provide a semiconductor device comprising a highly-integrated SGT-based CMOS inverter circuit is achieved by forming an inverter which comprises: a first transistor including; an first island-shaped semiconductor layer; a first gate insulating film; a gate electrode; a first first-conductive-type high-concentration semiconductor layer arranged above the first island-shaped semiconductor layer; and a second first-conductive-type high-concentration semiconductor layer arranged below the first island-shaped semiconductor layer, and a second transistor including; a second gate insulating film surrounding a part of the periphery of the gate electrode; a second semiconductor layer in contact with a part of the periphery of the second gate insulating film; a first second-conductive-type high-concentration semiconductor layer arranged above the second semiconductor layer; and a second second-conductive-type high-concentration semiconductor layer arranged below the second semiconductor layer. | 2014-01-23 |
20140021589 | Semiconductor Photocatalyst Coated with Graphitic Carbon Film and Method of Fabricating the Same - A semiconductor of which a substance such as a semiconductor photocatalyst is uniformly coated on the surface thereof with a graphitic carbon film and a method of fabricating the same are disclosed. According to the inventive method, a graphitic carbon film having a thickness of 1 nm or less is uniformly formed on the surface of the semiconductor by performing hydrothermal synthesis and pyrolysis on glucose, so as to keep the original structure crystallinity of the semiconductor photocatalyst to be a support of the carbon film. | 2014-01-23 |
20140021590 | Method of Manufacturing Semiconductor Devices Using Ion Implantation - A manufacturing method provides a semiconductor device with a substrate layer and an epitaxial layer adjoining the substrate layer. The epitaxial layer includes first columns and second columns of different conductivity types. The first and second columns extend along a main crystal direction along which channeling of implanted ions occurs from a first surface into the epitaxial layer. A vertical dopant profile of one of the first and second columns includes first portions separated by second portions. In the first portions a dopant concentration varies by at most 30%. In the second portions the dopant concentration is lower than in the first portions. The ratio of a total length of the first portions to the total length of the first and second portions is at least 50%. The uniform dopant profiles improve device characteristics. | 2014-01-23 |
20140021591 | EMI SHIELDING SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR STACK STRUCTURE - A semiconductor element is provided, including: a substrate having a plurality of first conductive through holes and second conductive through holes formed therein; a redistribution layer formed on the substrate and having a plurality of conductive pads electrically connected to the first conductive through holes; and a metal layer formed on the redistribution layer and electrically connected to the second conductive through holes. The metal layer further has a plurality of openings for the conductive pads of the redistribution layer to be exposed from the openings without electrically connecting the first metal layer. As such, the metal layer and the second conductive through holes form a shielding structure that can prevent passage of electromagnetic waves into or out of the redistribution layer or side surfaces of the semiconductor element, thereby effectively shield electromagnetic interference. | 2014-01-23 |
20140021592 | LED LEAD FRAME STRUCTURE AND METHOD OF MANUFACTURING LED LEAD FRAME - A LED lead frame structure and a method of manufacturing LED lead frames are disclosed, in which the LED lead frame structure includes a metal base and insulating casings. The metal base has a plurality of lead areas, and two holes are formed on two opposing sides of each lead area. The insulating casings are formed on the lead areas respectively. | 2014-01-23 |
20140021593 | LOWER SEMICONDUCTOR MOLDING DIE, SEMICONDUCTOR PACKAGE, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A semiconductor package may include a circuit board chip having a through-hole, a semiconductor device mounted on the circuit board chip, and an encapsulant. The encapsulant encapsulates the semiconductor device, fills the through-hole and has an external pattern that is the complement of a mold within which the encapsulant was formed. The external pattern on one side of the package reflects a mold shape that retards the flow of encapsulant material relative to the flow of encapsulant material on the opposite side of the package. | 2014-01-23 |
20140021594 | Packaging Structures and Methods for Semiconductor Devices - Packaging structures and methods for semiconductor devices are disclosed. In one embodiment, a substrate for packaging a semiconductor device includes a core substrate, an insulating material disposed over the core substrate, and conductive lines disposed in the insulating material. Contact pads are disposed over the insulating material and the conductive lines. The contact pads are disposed in an integrated circuit mounting region of the core substrate. A solder mask define (SMD) material is disposed over the insulating material. Portions of the contact pads are exposed through openings in the SMD material. A stress-relief structure (SRS) is disposed in the SMD material proximate the contact pads. The SRS is disposed entirely in the integrated circuit mounting region of the core substrate. | 2014-01-23 |
20140021595 | SEMICONDUCTOR COMPONENT SUPPORT AND SEMICONDUCTOR DEVICE - A semiconductor component support is provided which includes a component support portion for a semiconductor component to be mounted on the semiconductor component support portion. The component support portion includes a metal part that includes an opening in plan view. The opening of the metal part includes first and second sections. The second section communicates with the first section, and is arranged outside the first section. The second section is wider than the first section. The first section can be at least partially positioned directly under a mount-side main surface of the semiconductor component. | 2014-01-23 |
20140021596 | WAFER-LEVEL DEVICE PACKAGING - The present invention relates to a semiconductor device packaged at the wafer level such that an entire packaged device is formed prior to separation of individual devices. The semiconductor device package includes a semiconductor chip having one or more bonding pads associated with the chip and a protective layer bonded over the semiconductor chip. An insulation layer is positioned on at least side edges and a lower surface of the semiconductor chip. Interconnection/bump metallization is positioned adjacent one or more side edges of the semiconductor chip and is electrically connected to at least one bonding pad. A compact image sensor package can be formed that is vertically integrated with a digital signal processor and memory chip along with lenses and a protective cover. | 2014-01-23 |
20140021597 | High Speed Signal Conditioning Package - A package and integrated circuit assembly is configured to perform signal conditioning on a signal. The assembly includes a line card having line card contacts that correspond to conductors in the line card connector. Two or more integrated circuits are configured to perform signal conditioning on the signal and the two or more integrated circuits are configured within a package into at least a first row and a second row on the package. The package includes a grid array of bonding pads to electrically connect to the two or more integrated circuits through bond wires or down bonds such that the structure of the grid array corresponds in physical arrangement or bond pad pitch to the line card contacts. This assembly also includes an electrical connection from the two or more integrated circuits to the line card through the package. | 2014-01-23 |
20140021598 | METHODS AND ARRANGEMENTS RELATING TO SEMICONDUCTOR PACKAGES INCLUDING MULTI-MEMORY DIES - In an embodiment, there is provided a packaging arrangement comprising a substrate; a multi-memory die coupled to the substrate, wherein the multi-memory die comprises multiple individual memory dies, and each of the multiple individual memory dies is defined as an individual memory die within a wafer of semiconductor material during production of memory dies, and the multi-memory die is created by singulating the wafer of semiconductor material into memory dies, where at least one of the memory dies is the multi-memory die that includes the multiple individual memory dies that are still physically connected together; and a semiconductor die coupled to the multi-memory die and the substrate, wherein the semiconductor die is configured as a system on a chip, wherein at least one of the multi-memory die and the semiconductor die is attached to the substrate. | 2014-01-23 |
20140021599 | THREE-DIMENSIONAL INTEGRATED CIRCUITS AND FABRICATION THEREOF - A three-dimensional integrated circuit is disclosed, including a first interposer including through substrate vias (TSV) therein and circuits thereon; a plurality of first active dies disposed on a first side of the first interposer, a plurality of first intermediate interposers, each including through substrate vias (TSV), disposed on the first side of the first interposer, and a second interposer including through substrate vias (TSV) therein and circuits thereon supported by the first intermediate interposers. | 2014-01-23 |
20140021600 | REDISTRIBUTION LAYER (RDL) WITH VARIABLE OFFSET BUMPS - An integrated circuit (IC) chip is disclosed including a plurality of metal vertical interconnect accesses (vias) in a back end of line (BEOL) layer, a redistribution layer (RDL) on the BEOL layer, the BEOL layer having a plurality of bond pads, each bond pad connected to at least one corresponding metal via through the RDL; and a solder bump connected to each bond pad, wherein each solder bump is laterally offset from the corresponding metal via connected to the bond pad towards a center of the IC chip by an offset distance, wherein the offset distance is non-uniform across the IC chip. In one embodiment, the offset distance for each solder bump is proportionate to a distance between the center of the IC chip and the center of the corresponding solder bump pad structure for that solder bump. | 2014-01-23 |
20140021601 | SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR STRUCTURE THEREOF - A semiconductor manufacturing method includes providing a carrier; forming a first photoresist layer; forming plural core portions; removing the first photoresist layer; forming a second photoresist layer; forming a plurality of connection portions, each of the plurality of connection portions includes a first connection layer and a second connection layer and connects to each of the core portions to form a hybrid bump, wherein each of the first connection layers comprises a base portion, a projecting portion and an accommodating space, each base portion comprises an upper surface, each projecting portion is protruded to the upper surface and located on top of each core portion, each accommodating space is located outside each projecting portion, the second connection layers cover the projecting portions and the upper surfaces, and the accommodating spaces are filled by the second connection layers; removing the second photoresist layer to reveal the hybrid bumps. | 2014-01-23 |
20140021602 | SUBSTRATE FOR SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE HAVING THE SAME - A substrate for a semiconductor package includes: a first dielectric having a first surface and a second surface which faces away from the first surface and possesses waveform shaped portions, and formed with first holes penetrating the first and second surfaces; and circuit traces formed over the second surface of the first dielectric and having waveform shaped portions disposed over the waveform shaped portions of the second surface of the first dielectric. The waveform shaped portions of the second surface of the first dielectric and the waveform shaped portions of the circuit traces form a stress-resistant structure. | 2014-01-23 |
20140021603 | USING AN INTERCONNECT BUMP TO TRAVERSE THROUGH A PASSIVATION LAYER OF A SEMICONDUCTOR DIE - A semiconductor die, which includes a first semiconductor device, a first passivation layer, and a first interconnect bump, is disclosed. The first passivation layer is over the first semiconductor device, which includes a first group of device fingers. The first interconnect bump is thermally and electrically connected to each of the first group of device fingers. Additionally, the first interconnect bump protrudes through a first opening in the first passivation layer. | 2014-01-23 |
20140021604 | INTEGRATED CIRCUIT DEVICES WITH BUMP STRUCTURES THAT INCLUDE A PROTECTION LAYER - Disclosed herein is a device that includes first and second spaced-apart conductive pads positioned in a layer of insulating material, first and second under-bump metallization layers that are conductively coupled to the first and second conductive pads, respectively, and first and second spaced-apart conductive bumps that are conductively coupled to the first and second under-bump metallization layers, respectively. Additionally, the device includes, among other things, a passivation layer positioned above the layer of insulating material between the first and second spaced-apart conductive bumps, and a protective layer positioned on the passivation layer, wherein the protective layer extends between and contacts the first and second under-bump metallization layers, the material of the protective layer being one of silicon dioxide, silicon oxyfluoride (SiOF), silicon nitride (SiN), and silicone carbon nitride (SiCN). | 2014-01-23 |
20140021605 | Package on Package Devices and Methods of Packaging Semiconductor Dies - Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a first packaged die and a second packaged die coupled to the first packaged die. Metal stud bumps are disposed between the first packaged die and the second packaged die. The metal stud bumps include a stick region, a first ball region coupled to a first end of the stick region, and a second ball region coupled to a second end of the stick region. The metal stud bumps include a portion that is partially embedded in a solder joint. | 2014-01-23 |
20140021606 | CONTROL OF SILVER IN C4 METALLURGY WITH PLATING PROCESS - A solder structure for joining an IC chip to a package substrate, and method of forming the same are disclosed. In an embodiment, a structure is formed which includes a wafer having a plurality of solder structures disposed above the wafer. A ball limiting metallurgy (BLM) layer disposed beneath each of the solder structures, above the wafer. At least one of the plurality of solder structures has a first composition, and at least another of the plurality of solder structures has a second composition. | 2014-01-23 |
20140021607 | SOLDER VOLUME COMPENSATION WITH C4 PROCESS - An integrated circuit (IC) chip including solder structures for connection to a package substrate, an IC chip package, and a method of forming the same are disclosed. In an embodiment, an IC chip is provided comprising a wafer having a plurality of solder structures disposed above the wafer. A ball limiting metallurgy (BLM) layer is disposed between each of the plurality of solder structures and the wafer. At least one of the plurality of solder structures has a first diameter and a first height, and at least one other solder structure has a second diameter and a second height. The differing heights and volumes of solder structures facilitate solder volume compensation for chip join improvement on the IC chip side rather than the package side. | 2014-01-23 |
20140021608 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package includes a first semiconductor chip including a first chip pad located on an upper surface thereof, a second semiconductor chip offset-stacked on the upper surface of the first semiconductor chip and including a second chip pad located on an upper surface thereof, a chip coupling ball located on a first board pad of the first semiconductor chip, a chip coupling bump located on a second board pad of the second semiconductor chip, and a chip connection wire connecting the chip coupling ball and the chip coupling bump. The chip connection wire has a chip connection curve part with a reverse curve shape. | 2014-01-23 |
20140021609 | WIRING SUBSTRATE, METHOD FOR MANUFACTURING WIRING SUBSTRATE, ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE - A wiring substrate includes: a substrate; an insulator formed in the substrate and having a through hole; an electrode formed in the substrate and provided within the through hole; and a conductor bonded to the electrode and provided within the through hole, wherein the through hole has a shape that is widened toward a direction away from the substrate, and the conductor is configured to cover the entire top surface of the electrode and has a shape that is widened toward the direction away from the substrate. | 2014-01-23 |
20140021610 | CHIP PACKAGE AND A METHOD FOR MANUFACTURING A CHIP PACKAGE - A chip package is provided, the chip package including: first encapsulation structure; first passivation layer formed over first encapsulation structure and first electrically conductive layer formed over first passivation layer; at least one chip arranged over first electrically conductive layer and passivation layer wherein at least one chip contact pad contacts first electrically conductive layer; at least one cavity formed in first encapsulation structure, wherein at least one cavity exposes a portion of first passivation layer covering at least one chip contact pad; second encapsulation structure disposed over first encapsulation structure and covering at least one cavity, wherein a chamber region over at least one chip contact pad is defined by at least one cavity and second encapsulation structure; wherein second encapsulation structure includes an inlet and outlet connected to chamber region, wherein inlet and outlet control an inflow and outflow of heat dissipating material to and from chamber region. | 2014-01-23 |
20140021611 | Novel Copper Etch Scheme for Copper Interconnect Structure - The present disclosure is directed to a method of manufacturing an interconnect structure in which a low-k dielectric layer is formed over a semiconductor substrate followed by formation of a copper or copper alloy layer over the low-k dielectric layer. The copper or copper alloy layer is patterned and etched to form a copper body having recesses, which are then filled with a low-k dielectric material. The method allows for formation of a damascene structures without encountering the various problems presented by non-planar features and by porus low-K dielectric damage. | 2014-01-23 |
20140021612 | SEMICONDUCTOR DEVICE AND FABRICATING PROCESS FOR THE SAME - A semiconductor device and a fabricating process for the same are provided. The semiconductor device includes a base layer having a part of a reactive material; and a self-assembled protecting layer of a self-assembled molecule reacting with the reactive material formed over the part. | 2014-01-23 |
20140021613 | MULTI-LAYER BARRIER LAYER FOR INTERCONNECT STRUCTURE - A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate. An adhesion barrier layer is formed to line the recess. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. The recess is filled with a fill layer. | 2014-01-23 |
20140021614 | Hybrid interconnect scheme including aluminum metal line in low-k dielectric - A device includes a first low-k dielectric layer, and a copper-containing via in the first low-k dielectric layer. The device further includes a second low-k dielectric layer over the first low-k dielectric layer, and an aluminum-containing metal line over and electrically coupled to the copper-containing via. The aluminum-containing metal line is in the second low-k dielectric layer. | 2014-01-23 |
20140021615 | MULTI-LAYER BARRIER LAYER STACKS FOR INTERCONNECT STRUCTURES - The present disclosure is generally directed to multi-layer barrier layer stacks for interconnect structures that may be used to reduce mechanical stress levels between the interconnect structure and a dielectric material layer in which the interconnect structure is formed. One illustrative method disclosed herein includes forming a recess in a dielectric layer of a substrate and forming an adhesion barrier layer including an alloy of tantalum and at least one transition metal other than tantalum to line the recess, wherein forming the adhesion barrier layer includes creating a first stress level across a first interface between the adhesion barrier layer and the dielectric layer. The method also includes forming a stress-reducing barrier layer including tantalum over the adhesion barrier layer, wherein the stress-reducing barrier layer reduces the first stress level to a second stress level less than the first stress level, and filling the recess with a fill layer. | 2014-01-23 |
20140021616 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to the components. The interconnects are configured to extend from the central area to the edge surface while bridging over the crack stop structure. | 2014-01-23 |
20140021617 | SEMICONDUCTOR SUBSTRATE AND METHOD OF FABRICATING THE SAME - A semiconductor substrate is provided, including: a substrate; a plurality of conductive through vias embedded in the substrate; a first dielectric layer formed on the substrate; a metal layer formed on the first dielectric layer; and a second dielectric layer formed on the metal layer. As such, when a packaging substrate is disposed on the second dielectric layer, the metal layer provides a reverse stress to balance thermal stresses caused by the first and second dielectric layers, thereby preventing warpage of the semiconductor substrate. | 2014-01-23 |
20140021618 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SAME - To provide a semiconductor device having improved reliability by improving a coupling property between a semiconductor chip and a bonding wire. A redistribution layer is comprised of a Cu film, an Ni film, and a Pd film which have been formed successively from the side of a semiconductor substrate. The Pd film on the uppermost surface is used as an electrode pad and a bonding wire made of Cu is coupled to the upper surface of the Pd film. The thickness of the Pd film is made smaller than that of the Ni film and the thickness of the Ni film is made smaller than that of the Cu film. The Cu film, the Ni film, and the Pd film have the same pattern shape in a plan view. | 2014-01-23 |
20140021619 | PAD STRUCTURE AND INTEGRATED CIRCUIT CHIP WITH SUCH PAD STRUCTURE - An integrated circuit chip includes a substrate; at least one inter-metal dielectric layer over the substrate; a topmost metal layer overlying the inter-metal dielectric layer; a bonding pad in the topmost metal layer, the bonding pad comprising a central thinner portion and a peripheral thicker portion surrounding the central thinner portion; and a passivation layer covering the peripheral thicker portion. | 2014-01-23 |
20140021620 | POWER DEVICE AND POWER DEVICE MODULE - According to example embodiments of inventive concepts, a power device includes a semiconductor structure having a first surface facing a second surface, an upper electrode, and a lower electrode. The upper electrode may include a first contact layer that is on the first surface of the semiconductor structure, and a first bonding pad layer that is on the first contact layer and is formed of a metal containing nickel (Ni). The lower electrode may include a second contact layer that is under the second surface of the semiconductor structure, and a second bonding pad layer that is under the second contact layer and is formed of a metal containing Ni. | 2014-01-23 |
20140021621 | PACKAGED SEMICONDUCTOR DIE WITH POWER RAIL PADS - A packaged semiconductor die has a die support mounting surface mounted to a die support having external connectors. A die connection pad surface opposite to die supporting mount surface has associated die connection pads that are circuit nodes of the semiconductor die. The die connection pad surface also has a power rail pad. The power rail pad has a surface area larger than surface areas of the die connection pads. Bond wires electrically couple the power rail pad to two or more of the die connection pads. | 2014-01-23 |
20140021622 | OPTIMIZATION METALLIZATION FOR PREVENTION OF DIELECTRIC CRACKING UNDER CONTROLLED COLLAPSE CHIP CONNECTIONS - A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads. | 2014-01-23 |
20140021623 | METHOD OF FORMING ELECTRIC CONTACT INTERFACE REGIONS OF AN ELECTRONIC DEVICE - A method for forming electrical-contact interface regions on a wafer including a silicon-carbide substrate having a surface with at least one conductive region facing the surface. The method includes forming a first and a second resist layer; forming; removing portions of the second resist layer to form a through opening partially aligned to the conductive region; removing, selective portions of the first resist layer to expose the surface of the substrate; removing portions of the first resist layer that extend laterally staggered with respect to the through opening; depositing a nickel layer on the wafer to form a nickel region on the substrate in an area corresponding to the conductive region; removing the first and second resist layers; and carrying out a step of thermal treatment of the wafer to form nickel-silicide regions in electrical contact with the conductive region. | 2014-01-23 |
20140021624 | MOUNTING STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor-device mounting structure includes a first semiconductor device and a plate-shaped second semiconductor device connected to the first semiconductor device. The first semiconductor device includes a flexible board, an electronic component, and a sealing resin. The flexible board includes a bendable flexible portion and a hard portion. The flexible portion is bent at a boundary with the hard portion, along a shape of the electronic component such that the flexible board covers the electronic component. The flexible board and the electronic component are sealed with the sealing resin. The first semiconductor device is provided vertical to the second semiconductor device such that the hard portion is provided parallel to the second semiconductor device. | 2014-01-23 |
20140021625 | WIRING SUBSTRATE, METHOD FOR MANUFACTURING THE WIRING SUBSTRATE, AND SEMICONDUCTOR PACKAGE - A wiring substrate includes an insulating layer including a reinforcement member and having a first surface and a second surface positioned on an opposite side of the first surface, an electrode pad exposed from the first surface, a layered body including first insulating layers and being formed on the second surface, the first insulating layers having a first insulating material as a main component, another layered body including second insulating layers and being formed on the layered body, the second insulating layers having a second insulating material as a main component, and another electrode pad exposed from a surface of the another layered body that is opposite to the layered body. The number of the first insulating layers is equal to that of the second insulating layers. The first insulating layers have a thermal expansion coefficient that is greater than that of the second insulating layers. | 2014-01-23 |
20140021626 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF MANUFACTURING A LIQUID CRYSTAL DISPLAY DEVICE - A liquid crystal display device ( | 2014-01-23 |
20140021627 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device is provided with a semiconductor element having a plurality of electrodes, a plurality of terminals electrically connected to the plurality of electrodes, and a sealing resin covering the semiconductor element. The sealing resin covers the plurality of terminals such that a bottom surface of the semiconductor element in a thickness direction is exposed. A first terminal, which is one of the plurality of terminals, is disposed in a position that overlaps a first electrode, which is one of the plurality of electrodes, when viewed in the thickness direction. The semiconductor device is provided with a conductive connection member that contacts both the first terminal and the first electrode. | 2014-01-23 |
20140021628 | METHOD FOR FORMING INTERLAYER CONNECTORS IN A THREE-DIMENSIONAL STACKED IC DEVICE - A method is used with an IC device including a stack of dielectric/conductive layers to form interlayer connectors extending from a surface of the device to the conductive layers. Contact openings are created through a dielectric layer to a first conductive layer. N etch masks, with 2 | 2014-01-23 |
20140021629 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy. | 2014-01-23 |
20140021630 | HIGH PERFORMANCE IC CHIP HAVING DISCRETE DECOUPLING CAPACITORS ATTACHED TO ITS IC SURFACE - In the present invention, discrete decoupling capacitors are mounted on the surface of an IC chip. Since a discrete capacitor can provide the capacitance of the magnitude μF, the attached capacitors can serve as the local power reservoir to decouple the external power ground noise caused by wirebonds, packages, and other system components. | 2014-01-23 |
20140021631 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a supporting substrate; a semiconductor substrate that includes a first surface in which at least one layer is formed and a second surface that is positioned on an opposite side to the first surface, and is pasted to a surface of the supporting substrate with adhesive such that the first surface faces the supporting substrate side; a protective film that is formed on the second surface of the semiconductor substrate and on a surface of the adhesive extending outwardly from a region between the supporting substrate and the semiconductor substrate, and including a perimeter part that is positioned outside a perimeter part of the adhesive, and positioned inside a perimeter part of the supporting substrate; and an electrode material that is formed so as to be embedded in a penetration hole that penetrates the protective film and the semiconductor substrate. | 2014-01-23 |
20140021632 | VERTICAL TYPE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A vertical type semiconductor device includes a pillar structure protruding from a top surface of a substrate of a cell array region. Word lines extend while surrounding the pillar structure. Word line contacts contact edges of the word lines functioning as pad portions. An insulating interlayer pattern is provided on the substrate of a peripheral circuit region, which is disposed at an outer peripheral portion of the cell array region. A first contact plug contacts the substrate of the peripheral circuit region. A second contact plug contacts a top surface of the first contact plug and has a top surface aligned on the same plane with the top surfaces of the word line contacts. The first and second contact plugs are stacked in the peripheral circuit region, so the failure of the vertical type semiconductor device is reduced. | 2014-01-23 |
20140021633 | Integrated Circuit Device Having Through-Silicon-Via Structure and Method of Manufacturing the Same - An integrated circuit device including a through-silicon-via (TSV) structure and methods of manufacturing the same are provided. The integrated circuit device may include the TSV structure penetrating through a semiconductor structure. The TSV structure may include a first through electrode unit including impurities of a first concentration and a second through electrode unit including impurities of a second concentration greater than the first concentration. | 2014-01-23 |
20140021634 | Method of Manufacturing a Semiconductor Device with a Carrier Having a Cavity and Semiconductor Device - A method includes providing a carrier having a first cavity, providing a dielectric foil with a metal layer attached to the dielectric foil, placing a first semiconductor chip in the first cavity of the carrier, and applying the dielectric foil to the carrier. | 2014-01-23 |
20140021635 | MICROELECTRIC PACKAGE UTILIZING MULTIPLE BUMPLESS BUILD-UP STRUCTURES AND THROUGH-SILICON VIAS - A microelectronic package having a first bumpless build-up layer structure adjacent an active surface and sides of a microelectronic device and a second bumpless build-up layer structure adjacent a back surface of the microelectronic device, wherein conductive routes are formed through the first bumpless build-up layer from the microelectronic device active surface to conductive routes in the second bumpless build-up layer structure and wherein through-silicon vias adjacent the microelectronic device back surface and extending into the microelectronic device are electrically connected to the second bumpless build-up layer structure conductive routes. | 2014-01-23 |
20140021636 | SEMICONDUCTOR PACKAGE WITH SINGLE SIDED SUBSTRATE DESIGN AND MANUFACTURING METHODS THEREOF - A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer. | 2014-01-23 |
20140021637 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, a doped zone, a polysilicon layer and an elongate plug structure. The doped zone is within the semiconductor substrate. The polysilicon layer is disposed in a trench electrically isolated from the semiconductor substrate by an insulating layer. The elongate plug structure extends in a lateral direction in or above the semiconductor substrate. The elongate plug structure provides electrical connection between the doped zone and the polysilicon layer. | 2014-01-23 |
20140021638 | EMBEDDED INTEGRATED CIRCUIT PACKAGE AND METHOD FOR MANUFACTURING AN EMBEDDED INTEGRATED CIRCUIT PACKAGE - A embedded integrated circuit package is provided, the embedded integrated circuit package including: at least one chip arranged over a chip carrier, the at least one chip including a plurality of chip contact pads; encapsulation material formed over the chip carrier and at least partially surrounding the at least one chip; a plurality of electrical interconnects formed through the encapsulation material, wherein each electrical interconnect is electrically connected to a chip contact pad; and a structure formed between the electrical interconnects of the embedded integrated circuit package, wherein the structure increases the creepage resistance between the electrical interconnects. | 2014-01-23 |
20140021639 | Vertical System Integration - The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs. | 2014-01-23 |
20140021640 | METHOD FOR ELECTRICALLY CONNECTING VERTICALLY POSITIONED SUBSTRATES - A method and arrangement are disclosed for electrically connecting a contact of a first substrate to a contact of a second substrate, whereby the first substrate is positioned relative the second substrate. The method includes providing the first substrate with its contact facing towards the second substrate, providing the second substrate with its contact facing away from the first substrate, bonding a bonding medium to the contact of the first substrate, bonding the bonding medium to the first substrate thereby forming a loop, electrically connecting the contact of the second substrate to the bonding medium, and providing the second substrate with the contact on a nose or tongue extending from an edge of the second substrate. The first substrate can be positioned below the second substrate, with a contact of the first substrate connected to a contact of the second substrate. | 2014-01-23 |
20140021641 | MICROELECTRONIC PACKAGES HAVING CAVITIES FOR RECEIVING MICROELECTRONIC ELEMENTS - Packaged microelectronic elements are provided which include a dielectric element, a cavity, a plurality of chip contacts and a plurality of package contacts, and microelectronic elements having a plurality of bond pads connected to the chip contacts. | 2014-01-23 |
20140021642 | PLUGS FOR CARBURETORS - In accordance with one implementation, a carburetor includes a body having a fluid passage formed therein and a counterbore located along the fluid passage. The counterbore has a first sealing surface and a central axis, and the body further includes a second sealing surface located radially closer to the central axis than is the first sealing surface. The carburetor also includes a plug affixed to the body at the counterbore and in contact with both of the first and second sealing surfaces. Engagement of the plug with the two sealing surfaces may improve the connection between the plug and carburetor body. In at least some implementations, the plug may be held in place without aid of an adhesive or other secondary connector or connection aid. | 2014-01-23 |
20140021643 | SYSTEM FOR BUILDING FORMWORK FOR CONCRETE STAIRS AND RELATED METHODS - The present invention provides a system to build formworks for building concrete stairs which is durable and reusable, which can be rapidly mounted and dismantled on site and which is adjustable to a variety of flight of stairs having different widths, rises and pitches. The system comprises (a) at least one side plate which can be releasably secured to a supporting structure on a footing; the side plate defining a side of at least one stair and defining the depth of a tread of said stair; (b) at least one riser member for defining the rise of the at least one stair; the riser member being complementary to the side plate; and (c) means for fastening the riser member to the side plate; wherein the side plate and riser member are reusable. | 2014-01-23 |
20140021644 | Dies and Methods for Improving Physical Properties of Stretch Film - Dies and methods of extruding stretch film are provided, wherein the die includes at least an upper die lip and a lower die lip; the upper and lower die lips at least partially define a die gap; and at least one of the die lips includes a channel. Another die disclosed includes at least a die gap; and at least one jet for directing a stream of air onto the polymer as it is extruded through the die gap. Stretch films and methods for extruding stretch films are provided, wherein selected areas of the polymer extruded through the die have a gauge that exceeds the film's base gauge. The film includes at least a layer of film having a base gauge and a plurality of strength bands running longitudinally along a length of the film; and have a gauge that is greater than the base gauge. | 2014-01-23 |
20140021645 | METHOD OF LAYERED CONSTRUCTION OF POLYMERIC MATERIAL THROUGH OPEN-CELL POROUS MATERIAL MATRIX - A method for constructing layers of polymers through a core of open cell porous material such as metal foams is provided comprising the use of temporary filler material to fill certain volumes within the cellular material. This is followed by filling the remaining volume with polymeric material. The temporary filler material is then removed revealing a layer of a composite of polymer and cellular material as well as a layer of unfilled cellular material. The process can then be repeated to create other layers using same or different polymer. | 2014-01-23 |
20140021646 | Window Trim Apparatus and Methods - Window trim apparatus are provided that include scored grooves made by methods other than extrusion. Also provided are methods and apparatus for manufacturing and using same. | 2014-01-23 |
20140021647 | PLURAL-COMPONENT, COMPOSITE-MATERIAL HIGHWAY DOWEL BAR FABRICATION METHODOLOGY - A method for making a plural-component, composite-material, highway dowel-bar including (1) preparing an elongate core train possessing endo-abutting, longitudinally alternating, (a) elongate, high-shear-strength, cylindrical cores having a common cross section, and (b) elongate, but shorter, cylindrical, fibre-reinforced plastic-resin end-plug blanks having opposite ends, and each having a cross section matching the cross section of the cores, (2) using the core train as a longitudinally moving mandrel, pultrusion-forming a fibre-reinforced plastic-resin sleeve continuously and bondedly around the core train so as to produce a pultrusion-result, intermediate, dowel-bar product, and (3) following pultrusion-forming, cross-cutting the intermediate, dowel-bar product at each longitudinal location therein which is intermediate the opposite ends of the end-plug blanks, thereby to form completed dowel bars. | 2014-01-23 |