04th week of 2020 patent applcation highlights part 55 |
Patent application number | Title | Published |
20200027708 | SPUTTERING DEVICE - The purpose of the present invention is to improve uniformity of film deposition by a plasma-based sputtering device. Provided is a sputtering device | 2020-01-23 |
20200027709 | MICROCHANNEL PLATE AND ELECTRON MULTIPLIER TUBE - A microchannel plate is provided with a substrate including a front surface, a rear surface, and a side surface, a plurality of channels penetrating from the front surface to the rear surface of the substrate, a first film provided on at least an inner wall surface of the channel, a second film provided on at least a part of the first film, and electrode layers provided on the front surface and the rear surface of the substrate. The first film is made of MgO, the second film is made of SiO | 2020-01-23 |
20200027710 | THERMIONIC WAVE GENERATOR (TWG) - Energy conversion systems that may employ control grid electrodes, acceleration grid electrodes, inductive elements, multi-stage anodes, and emissive carbon coatings on the cathode and anode are described. These and other characteristics may allow for advantageous thermal energy to electrical energy conversion. | 2020-01-23 |
20200027711 | PLANAR ION SOURCES FOR SPECTROMETERS - An apparatus for separating and analyzing ions includes a detector, a planar ion drift tube coupled to the detector and having a width, and a planar ion source. The planar ion source is coupled to the ion drift tube on an end of the ion drift tube opposite the detector and has a span greater than or equal to the width of the ion drift tube to ionize an analyte gas and fragment the analyte gas ions prior to admittance to the ion drift tube. Chemical detectors and methods of chemical detection are also described. | 2020-01-23 |
20200027712 | ISOTOPE MASS SPECTROMETER - An isotope mass spectrometer including: an electron cyclotron resonance ion source, a front-end analysis device, a back-end analysis device and an ion detector; where the electron cyclotron resonance ion source is connected with the front-end analysis device, and is used for generating ion beams of multivalent charge states; the front-end analysis device is connected with the back-end analysis device, selects and separates the ion beams, and receives ion beams of constant, microscale and trace levels; the back-end analysis device is connected with the ion detector, and is used for eliminating a background of an isotope to be measured at an ultratrace level; and the ion detector is used for receiving ion beams of the ultratrace level, and carrying out energy measurement and separation on the ion beams of the ultratrace level, so as to obtain the isotope to be measured at the ultratrace level. | 2020-01-23 |
20200027713 | Apparatuses for Detecting Constituents in a Sample and Method of Using the Same - An apparatus for detecting constituents in a sample includes first and second drift tubes defining first and second drift regions and a controllable electric field device within a fragmentation region coupled to the first and second drift tubes. The apparatus also includes a first ion shutter positioned between the first drift and fragmentation regions. The apparatus further includes a control system configured to regulate the first ion shutter, thereby facilitating injection of a selected portion of ions from the first drift region into the fragmentation region. The control system is also configured to regulate the controllable device to modify the selected portion of ions to generate predetermined ion fragments within the fragmentation region, thereby facilitating injection of a selected portion of the predetermined fragmented ions into the second drift region. A method of detecting constituents in a sample is facilitated through such an apparatus. | 2020-01-23 |
20200027714 | QUADRUPOLE MASS ANALYZER AND METHOD OF MASS ANALYSIS - A quadrupole mass analyzer according to the present invention optimizes a stability band formation mode of a quadrupole system, so as to facilitate passing of ions and blocking of excessive ions, thereby improving the mass resolution without reducing the ion transmission efficiency. The solution of the present invention avoids the superimposition of high-frequency AC signals needed in the ion two-direction resonance frequency control in the prior art, and can effectively reduce the risk of quadrupole working performance reduction caused by the non-linear distortion of an RF voltage caused by bandwidth limitation in a fast RF circuit. In addition, a scanning speed of an ion-controlled electric field required by the quadrupole mass spectrometry can also be controlled faster because of reduction of limit bandwidth of various needed AC excitation signals. It is advantageous to obtain high-speed quadrupole scanning mass spectrometry performance. | 2020-01-23 |
20200027715 | GLASS-METAL FEEDTHROUGH - A glass-metal feedthrough consists of an external conductor, a glass material and an internal conductor. The internal conductor has a coefficient of expansion α | 2020-01-23 |
20200027716 | Method of Manufacturing an Insulation Layer on Silicon Carbide and Semiconductor Device - A method of manufacturing an insulation layer on a silicon carbide substrate, the method including preparing a surface of a silicon carbide substrate, forming a first part of an insulation layer on the surface of the silicon carbide substrate at a temperature below 400° Celsius, and forming a second part of the insulation layer by depositing a dielectric film on the first part of the insulation layer. | 2020-01-23 |
20200027717 | IN-SITU DEPOSITION PROCESS - Embodiments of the present disclosure provide methods and apparatus for forming a desired material layer on a substrate between, during, prior to or after a patterning process. In one embodiment, a method for forming a material layer on a substrate includes pulsing a first gas precursor onto a surface of a substrate, attaching a first element from the first gas precursor onto the surface of the substrate, maintaining a substrate temperature less than about 110 degrees Celsius, pulsing a second gas precursor onto the surface of the substrate, and attaching a second element from the second gas precursor to the first element on the surface of the substrate. | 2020-01-23 |
20200027718 | Minimization of Carbon Loss in ALD SiO2 Deposition on Hardmask Films - A method for defining thin film layers on a surface of a substrate includes exposing the surface of the substrate to a first precursor via a first plasma to allow the first precursor to be absorbed by the surface of the substrate. A second precursor that is different from the first precursor is applied to the surface of the substrate via a second plasma. The second precursor is a Carbon dioxide precursor that releases sufficient oxygen radicals to react with the first precursor to form an oxide film layer on the surface of the substrate. | 2020-01-23 |
20200027719 | Varying Temperature Anneal for Film and Structures Formed Thereby - Semiconductor device structures having dielectric features and methods of forming dielectric features are described herein. In some examples, the dielectric features are formed by an ALD process followed by a varying temperature anneal process. The dielectric features can have high density, low carbon concentration, and lower k-value. The dielectric features formed according to the present disclosure has improved resistance against etching chemistry, plasma damage, and physical bombardment in subsequent processes while maintaining a lower k-value for target capacitance efficiency. | 2020-01-23 |
20200027720 | METHOD FOR DOPING LAYER, THIN FILM TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for doping a layer, a thin film transistor and a method for fabricating the thin film transistor. The method comprises: forming a layer to be doped on a substrate by a first patterning process, wherein the layer comprises a first region, a second region and a third region, the first region is arranged in a middle region, the third region is arranged in an edge region, the second region is arranged between the first region and the third region; forming a first blocking layer and a second blocking layer on the layer in this order by a second patterning process, wherein an orthographic projection region of the first blocking layer on the layer exactly covers the first region, and an orthographic projection region of the second blocking layer on the layer exactly covers the first region and the second region; perform a first doping on the layer with an ion beam perpendicular to the substrate, to realize doping of the third region; rotating the substrate by a preset angle in a direction parallel to the ion beam, so that the second blocking layer does not shield the second region, and performing a second doping on the layer with the ion beam to realize. | 2020-01-23 |
20200027721 | METHOD FOR CLEANING SEMICONDUCTOR WAFER - A method for cleaning a semiconductor wafer, including: inserting a semiconductor wafer into a hydrofluoric acid tank filled with hydrofluoric acid to immerse the semiconductor wafer in the hydrofluoric acid; pulling out the semiconductor wafer from the hydrofluoric acid tank; and then inserting the semiconductor wafer into an ozone water tank filled with ozone water to immerse the semiconductor wafer in the ozone water for cleaning. The semiconductor wafer is inserted into the ozone water tank at a rate of 20000 mm/min or more at least after a lower end of the semiconductor wafer comes into contact with the ozone water until the semiconductor wafer is completely immersed in the ozone water. A method for cleaning a semiconductor wafer which can prevent and remove contaminant from re-adhering in a method in which a semiconductor wafer is cleaned by immersion in hydrofluoric acid and then cleaned by immersion in ozone water. | 2020-01-23 |
20200027722 | LASER ANNEALING DEVICE, LASER ANNEALING METHOD, AND MASK - Provided are a laser annealing device, laser annealing method, and mask which make it possible to reduce display blurriness at a mask-joining boundary. The laser annealing device is equipped with a mask in which a plurality of opening blocks, which include a plurality of openings arranged in the column direction parallel to the scanning direction, are arranged in the row direction which is perpendicular to the scanning direction. The laser annealing device moves the mask and/or substrate in a direction parallel to the scanning direction, and each time the mask and/or substrate move to a prescribed position in the direction perpendicular to the scanning direction, performs processing for irradiating a plurality of prescribed substrate regions with a laser beam through the plurality of openings. Furthermore, at least one pair comprising adjacent two opening blocks is provided in a manner such that the position of the openings in a first opening block which is one block among the pair and the position of the openings in a second opening block which is the other block among the pair are offset in the direction parallel to the scanning direction. | 2020-01-23 |
20200027723 | METHOD FOR MANUFACTURING DEVICE - According to one embodiment, a method for manufacturing a device includes a first process, a second process, a third process, and a fourth process. The first process includes providing a structure body at a first surface of a substrate. The substrate is light-transmissive and has a second surface. A light transmissivity of the structure body is lower than a light transmissivity of the substrate. The second process includes providing a negative-type photoresist at the second surface. The third process includes irradiating the substrate with light to expose a portion of the photoresist. The light is irradiated in a first direction from the first surface toward the second surface. The light passes through the substrate. The fourth process includes developing the photoresist to remain the portion of the photoresist in a state of being adhered to the second surface and to remove other portion of the photoresist. | 2020-01-23 |
20200027724 | APPARATUS AND METHOD FOR TREATING SUBSTRATE - An apparatus for treating a substrate comprises a chamber having a processing space in which a process of treating the substrate is performed and a fluid supply unit that supplies a treating fluid into the chamber. The fluid supply unit comprises a supply line, at least one orifice provided in the supply line, and a first heater provided on the orifice or upstream of the orifice. The first heater heats the treating fluid passing through the orifice to a set temperature or more. | 2020-01-23 |
20200027725 | REMOTE PLASMA BASED DEPOSITION OF BORON NITRIDE, BORON CARBIDE, AND BORON CARBONITRIDE FILMS - A boron nitride, boron carbide, or boron carbonitride film can be deposited using a remote plasma chemical vapor deposition (CVD) technique. A boron-containing precursor is provided to a reaction chamber, where the boron-containing precursors has at least one boron atom bonded to a hydrogen atom. Radical species, such as hydrogen radical species, are provided from a remote plasma source and into the reaction chamber at a substantially low energy state or ground state. A hydrocarbon precursor may be flowed along with the boron-containing precursor, and a nitrogen-containing plasma species may be introduced along with the radical species from the remote plasma source and into the reaction chamber. The boron-containing precursor may interact with the radical species along with one or both of the hydrocarbon precursor and the nitrogen-containing precursor to deposit the boron nitride, boron carbide, or boron carbonitride film. | 2020-01-23 |
20200027726 | Low Temperature High-Quality Dielectric Films - Techniques for deposition of high-density dielectric films for patterning applications are described. More particularly, a method of processing a substrate is provided. The method includes flowing a precursor-containing gas mixture into a processing volume of a processing chamber having a substrate positioned on an electrostatic chuck. The substrate is maintained at a pressure between about 0.1 mTorr and about 10 Torr. A plasma is generated at the substrate level by applying a first RF bias to the electrostatic chuck to deposit a dielectric film on the substrate. The dielectric film has a refractive index in a range of about 1.5 to about 3. | 2020-01-23 |
20200027727 | METHOD FOR MANUFACTURING EPITAXIAL SILICON WAFER AND EPITAXIAL SILICON WAFER - A manufacturing method of an epitaxial silicon wafer uses a silicon wafer containing phosphorus, having a resistivity of less than 1.0 mΩ·cm. The silicon wafer has a main surface to which a (100) plane is inclined and a [100] axis that is perpendicular to the (100) plane and inclined at an angle ranging from 0°5′ to 0°25′ with respect to an axis orthogonal to the main surface. The manufacturing method includes: annealing the silicon wafer at a temperature from 1200 degrees C. to 1220 degrees C. for 30 minutes or more under argon gas atmosphere (argon-annealing step); etching a surface of the silicon wafer (prebaking step); and growing the epitaxial film at a growth temperature ranging from 1100 degrees C. to 1165 degrees C. on the surface of the silicon wafer (epitaxial film growth step). | 2020-01-23 |
20200027728 | SUBSTRATE PACKAGE WITH GLASS DIELECTRIC - Embodiments may relate to a semiconductor package that includes a die and a glass core coupled with the die. The glass core may include a cavity with an interconnect structure therein. The interconnect structure may include pads on a first side that are coupled with the die, and pads on a second side opposite the first side. Other embodiments may be described and/or claimed. | 2020-01-23 |
20200027729 | OXIDE SEMICONDUCTOR LAYER AND PREPARATION METHOD THEREOF, DEVICE, SUBSTRATE AND MEANS - The present disclosure provides an oxide semiconductor layer and a preparation method thereof, device, substrate, and means, and belongs to the field of semiconductor technologies. The method includes: forming an oxide semiconductor layer having multiply types of regions on a substrate, at least two types of the multiple types of regions having different thicknesses, and adjusting an oxygen content of at least one type of regions in the multiply types of regions, so that the oxygen content and the thickness in the multiple types of regions are positively correlated. | 2020-01-23 |
20200027730 | FILM FORMING METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A film forming method of forming an oxide film on a substrate, wherein the oxide film has germanium doped therein and comprises a property of a conductor or a semiconductor, is disclosed herein. The film forming method may include supplying mist of a solution to a surface of the substrate while heating the substrate, wherein an oxide film material including a constituent element of the oxide film and an organic germanium compound may be dissolved in the solution. | 2020-01-23 |
20200027731 | FILM FORMING METHOD AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A film forming method of forming a gallium oxide film doped with tin on a substrate is disclosed herein. The film forming method may include supplying mist of a solution to a surface of the substrate while heating the substrate, wherein a gallium compound and a tin chloride (IV) pentahydrate are dissolved in the solution. | 2020-01-23 |
20200027732 | METHOD FOR MANUFACTURING SILICON SINGLE CRYSTAL, FLOW STRAIGHTENING MEMBER, AND SINGLE CRYSTAL PULLING DEVICE - A manufacturing method of monocrystalline silicon includes: disposing a flow regulator including a body in a form of an annular plate, provided under a heat shield, surrounding monocrystalline silicon; controlling an internal pressure of a chamber to 20 kPa or more during growth of monocrystalline silicon; keeping the flow regulator spaced from a dopant-added melt; and introducing inert gas into between the monocrystalline silicon and the heat shield to divide the inert gas into a first flow gas and a second flow gas. | 2020-01-23 |
20200027733 | DIRECTIONAL DEPOSITION FOR PATTERNING THREE-DIMENSIONAL STRUCTURES - A method for patterning a three-dimensional structure is provided. The method may include providing a substrate, the substrate including the three-dimensional structure, and directing a depositing species from a deposition source to the three-dimensional structure, wherein a layer forms on the three-dimensional structure. The method may further include directing angled ions to the three-dimensional structure from an ion source, wherein the angled ions impinge on a first region of the layer and do not impinge on a second region of the layer. As such, the first region may form a densified layer portion having a first density, and the second region may form an undensified layer portion having a second density, less than the first density. | 2020-01-23 |
20200027734 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed are semiconductor devices and methods of manufacturing the same. The method comprises alternately stacking a plurality of dielectric layers and a plurality of first semiconductor layers to form a mold structure on a substrate, forming a hole penetrating the mold structure, forming on the substrate a second semiconductor layer filling the hole, and irradiating a laser onto the second semiconductor layer. | 2020-01-23 |
20200027735 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME - A semiconductor structure and a method for forming same are provided. The forming method includes: providing a base; forming a core layer on the base; forming sacrificial spacers on sidewalls of the core layer, the sacrificial spacer located on one side of the core layer being a first sacrificial spacer, the sacrificial spacer located on the other side of the core layer being a second sacrificial spacer; forming a first mask spacer on a sidewall of the first sacrificial spacer; removing the core layer, and forming an opening in the sacrificial spacers; forming a second mask spacer on a sidewall of the second sacrificial spacer exposed by the opening; removing the sacrificial spacers; and etching the base using the first mask spacer and the second mask spacer as masks to form a target pattern. The present disclosure reduces the process difficulty of a photolithography process, improves operability of the process, and also helps ensure that the shape and size of the target pattern can meet process requirements, so that device performance and performance uniformity can be improved. | 2020-01-23 |
20200027736 | METHODS TO PROTECT NITRIDE LAYERS DURING FORMATION OF SILICON GERMANIUM NANO-WIRES IN MICROELECTRONIC WORKPIECES - Embodiments are described herein that form silicon germanium nano-wires while reducing or eliminating erosion of nitride layers (e.g., masks and spacers) caused during selective etching of silicon with respect to silicon germanium during formation of silicon germanium nano-wires. oxide layers are used to protect nitride layers during formation of silicon germanium (SiGe) nano-wires. In particular, multilayer spacers including oxide/nitride/oxide layers are formed to protect the nitride layers during selective silicon etch processes that are used to form silicon germanium nano-wires, for example, for field effect transistors (FETs). The multilayer spacers allow for target levels of erosion to be achieved for the nitride layers. | 2020-01-23 |
20200027737 | PLATING INTERCONNECT FOR SILICON CHIP - A system, method, and silicon chip package for providing connections between a die of a silicon chip package and external leads of the silicon chip package is disclosed. The connections are formed using a pre-mold etched with a trace pattern. The trace pattern provides rigid traces that connect the die with the external leads. | 2020-01-23 |
20200027738 | Tungsten Deposition Without Barrier Layer - Methods for depositing a metal film without the use of a barrier layer are disclosed. Some embodiments comprise forming an amorphous nucleation layer comprising one or more of silicon or boron and forming a metal layer on the nucleation layer. | 2020-01-23 |
20200027739 | LED WAFER PROCESSING METHOD - An LED wafer is formed from a sapphire substrate having a front side. A plurality of crossing division lines are formed on the front side of the sapphire substrate to thereby define a plurality of separate regions where a plurality of LEDs are respectively formed. An LED wafer processing method includes preparing a V-blade having an annular cutting edge whose outer circumferential portion has a V-shaped cross section, rotatably mounting the V-blade in a cutting unit, holding the LED wafer on a holding table with the back side of the LED wafer exposed upward, and then relatively moving the cutting unit and the holding table to form a chamfered portion on the back side of the LED wafer along an area corresponding to each division line formed on the front side of the LED wafer. | 2020-01-23 |
20200027740 | SELECTIVE CYCLIC DRY ETCHING PROCESS OF DIELECTRIC MATERIALS USING PLASMA MODIFICATION - In some embodiments, a selective cyclic (optionally dry) etching of a first surface of a substrate relative to a second surface of the substrate in a reaction chamber by chemical atomic layer etching comprises forming a modification layer using a first plasma and etching the modification layer. The first surface comprises carbon and/or nitride and the second surface does not comprise carbon and/or nitride. | 2020-01-23 |
20200027741 | GAS PHASE ETCH WITH CONTROLLABLE ETCH SELECTIVITY OF SILICON-GERMANIUM ALLOYS - A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a substrate having a working surface exposing a silicon-germanium alloy and at least one other material, the silicon-germanium alloy represented as Si | 2020-01-23 |
20200027742 | ABATEMENT AND STRIP PROCESS CHAMBER IN A DUAL LOADLOCK CONFIGURATION - Embodiments of the present invention provide a dual load lock chamber capable of processing a substrate. In one embodiment, the dual load lock chamber includes a chamber body defining a first chamber volume and a second chamber volume isolated from one another. Each of the lower and second chamber volumes is selectively connectable to two processing environments through two openings configured for substrate transferring. The dual load lock chamber also includes a heated substrate support assembly disposed in the second chamber volume. The heated substrate support assembly is configured to support and heat a substrate thereon. The dual load lock chamber also includes a remote plasma source connected to the second chamber volume for supplying a plasma to the second chamber volume. | 2020-01-23 |
20200027743 | METHOD OF PRODUCING ETCHING MASK, ETCHING MASK PRECURSOR, AND OXIDE LAYER, AND METHOD OF MANUFACTURING THIN FILM TRANSISTOR - The etching mask | 2020-01-23 |
20200027744 | SYSTEM AND METHOD FOR LIGHT FIELD CORRECTION OF COLORED SURFACES IN AN IMAGE - A computer-implemented method for correcting a makeup or skin effect to be rendered on a surface region of an image of a portion of a body of a person. The method and system correcting the makeup or skin effect by accounting for image-specific light field parameters, such as a light profile estimate and minimum light field estimation, and rendering the corrected the makeup or skin effect on the image to generate a corrected image. | 2020-01-23 |
20200027745 | CONTROL OF CURRENT COLLAPSE IN THIN PATTERNED GAN - A GaN device is formed on a semiconductor substrate having a plurality of recessed regions formed in a surface thereof. A seed layer, optional buffer layer, and gallium nitride layer such as a carbon-doped gallium nitride layer are successively deposited within the recessed regions. Improved current collapse response of the GaN device is attributed to maximum length and width dimensions of the multilayer stack. | 2020-01-23 |
20200027746 | PRE-CLEANING FOR ETCHING OF DIELECTRIC MATERIALS - An etching process is provided that includes a pre-clean process to remove a surface oxide of a dielectric material. The removal of the oxide can be executed through a thermal reaction and/or plasma process before the etch process. In some embodiments, the removal of the oxide increases etch process control and reproducibility and can improve the selectivity versus oxides. | 2020-01-23 |
20200027747 | PATTERN TRANSFER TECHNIQUE AND METHOD OF MANUFACTURING THE SAME - A photo-free lithography process with low cost, high throughput, and high reliability is provided. A template mask is bonded to a production workpiece and comprises a plurality of openings defining a pattern. An etch is performed into the production workpiece, through the plurality of openings, to transfer the pattern of the template mask to the production workpiece. The template mask is de-bonded from the production workpiece. A system for performing the photo-free lithography process is also provided. | 2020-01-23 |
20200027748 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device of the present invention includes a substrate having a drift layer, metal wiring formed on an upper surface of the substrate, and an electrode formed on a back surface of the substrate, wherein the lifetime of carriers in the drift layer satisfies the following expression 1: | 2020-01-23 |
20200027749 | WET ETCHING OF SAMARIUM SELENIUM FOR PIEZOELECTRIC PROCESSING - A subtractive forming method for piezoresistive material stacks includes applying an etch chemistry to an exposed first portion of a piezoresistive material stack. The etch chemistry includes a citric acid component for removing a first element of a piezoelectric layer of the piezoresistive material stack selectively to a surface oxide. At least one second element of the piezoelectric layer remains. The method further includes heating the piezoresistive material stack after said applying the etch chemistry to vaporize the at least one second element. A second portion of the piezoresistive material stack is protected from the removal and the heating by a mask. | 2020-01-23 |
20200027750 | Semiconductor Device and Method of Manufacture - An interposer substrate is manufactured with a scribe line between adjacent regions. In an embodiment a separate exposure reticle is utilized to pattern the scribe line. The exposure reticle to pattern the scribe line will create an exposure region which overlaps and overhangs the exposure regions utilized to form adjacent regions. | 2020-01-23 |
20200027751 | Method for Producing Power Semiconductor Module Arrangement - A method for producing a power semiconductor module arrangement having a base plate and a contact element configured to, when the base plate is arranged in a housing, provide an electrical connection between an inside and an outside of the housing, includes: connecting an electrically insulating first layer to the base plate; and connecting the contact element to the first layer. Connecting the first layer to the base plate includes forming a third layer on the base plate or on the first layer and mounting the first layer on the base plate such that the third layer attaches the first layer to the base plate. Connecting the contact element to the first layer includes forming a second layer on the first layer or on the contact element and mounting the contact element on the first layer such that the second layer attaches the contact element to the first layer. | 2020-01-23 |
20200027752 | Apparatus and Method for Bending a Substrate - A method includes placing a substrate on a first curved surface of a first bending tool, using a second bending tool with a second surface to apply pressure to the substrate, thereby pressing the substrate onto the first curved surface and bending the substrate, and removing the bended substrate from the first bending tool. | 2020-01-23 |
20200027753 | ASSEMBLY OF A CARRIER AND A PLURALITY OF ELECTRICAL CIRCUITS FIXED THERETO, AND METHOD OF MAKING THE SAME - A method of obtaining an elongate carrier ( | 2020-01-23 |
20200027754 | SEALING SHEET AND SEMICONDUCTOR-DEVICE MANUFACTURING METHOD - A sealing sheet is provided which is used for sealing of a semiconductor chip embedded in a substrate or a semiconductor chip on a pressure sensitive adhesive sheet in a method of manufacturing a semiconductor device. The method includes a treatment step using an alkaline solution. The sealing sheet includes at least an adhesive layer having curability. The adhesive layer is formed of an adhesive composition that contains a thermoset resin, a thermoplastic resin, and an inorganic filler. The inorganic filler is surface-treated with a surface treatment agent having a minimum coverage area of less than 550 m | 2020-01-23 |
20200027755 | TEMPORARY-FIXING SUBSTRATE AND METHOD FOR MOLDING ELECTRONIC COMPONENT - A temporary-fixing substrate includes a fixing face for adhering and temporary-fixing a plurality of electronic parts with a resin mold and a bottom face on the opposite side of the fixing face. The temporary-fixing substrate is composed of a translucent ceramic material, scratches are distributed on the fixing face, and intergranular boundaries and polished surfaces of crystal grains forming the translucent ceramic material are exposed to the bottom face. The density of scratches on the bottom face is lower than the density of scratches on the fixing face. | 2020-01-23 |
20200027756 | RESIN MOLDING APPARATUS INCLUDING RELEASE FILM FEEDER - A resin molding apparatus including a release film feeder configured to feed a release film is provided. The release film feeder including a feeding roller around which the release film is wound, a gripper configured to grip an end portion of the release film fed from the feeding roller, a support table configured to support the release film fed by a horizontal movement of the gripper in an X direction, the support table configured to horizontally move at least one of in the X direction or in a Y direction perpendicular to the X direction, the X and Y directions defining a surface parallel to a surface of the support table, and a position detecting sensor on the support table and configured to detect position information of the release film may be provided. | 2020-01-23 |
20200027757 | Die Transfer Method and Die Transfer System Thereof - A die transfer method and a die transfer system thereof are disclosed. The die transfer method includes the following steps: providing a wafer to generate a plurality of dies; transferring a plurality of dies to a surface of a substrate to fix the plurality of dies on the surface of the substrate; aligning the substrate with a target substrate, wherein the target substrate has a landing site and the position of at least one die corresponds to the position of the landing site; in an air environment or a liquid environment, executing lyophilic or lyophobic treatment as compared to the periphery respectively to a bonding surface between the at least one die and the landing site of the target substrate; transferring the at least one die onto the landing site of the target substrate; and fixing the at least one die at the landing site. | 2020-01-23 |
20200027758 | SUBSTRATE PROCESSING APPARATUS - The substrate processing apparatus includes a processing chamber including an outer chamber configured to hold a processing liquid and an inner chamber capable of surrounding the substrate held by the substrate holder; a liquid delivery pipe having one end coupled to a bottom of the inner chamber and other end coupled to the outer chamber; a pump configured to suck the processing liquid from the inner chamber through the liquid delivery pipe and to deliver the processing liquid to the outer chamber through the liquid delivery pipe; and a guide cover having a through-hole in which the substrate holder can be inserted. The guide cover is located below an upper end of the outer chamber and above the inner chamber. | 2020-01-23 |
20200027759 | SUBSTRATE PROCESSING APPARATUS - The substrate processing apparatus includes a processing chamber including an outer chamber configured to hold a processing liquid and an inner chamber capable of surrounding the substrate held by the substrate holder; a liquid delivery pipe having one end coupled to a bottom of the inner chamber and other end coupled to the outer chamber; a pump configured to suck the processing liquid from the inner chamber through the liquid delivery pipe and to deliver the processing liquid to the outer chamber through the liquid delivery pipe; and a guide cover having a through-hole in which the substrate holder can be inserted. The guide cover is located below an upper end of the outer chamber and above the inner chamber. | 2020-01-23 |
20200027760 | BRUSH CLEANING APPARATUS, CHEMICAL-MECHANICAL POLISHING (CMP) SYSTEM AND WAFER PROCESSING METHOD - The present disclosure, in some embodiments, relates to a brush cleaning apparatus. The brush cleaning apparatus includes a wafer support configured to support a wafer. The brush cleaning apparatus also includes a cleaning brush including a porous material coupled to a core material. An uppermost surface of the porous material defines a planar cleaning surface. A first nozzle is configured to apply a first cleaning liquid directly between the wafer and the planar cleaning surface of the cleaning brush. | 2020-01-23 |
20200027761 | APPARATUS AND METHOD FOR TREATING SUBSTRATE - A method for treating a substrate includes a substrate treating step of treating the substrate by dispensing a treating liquid onto the substrate while rotating the substrate supported on a support plate in a processing space of a processing vessel and a vessel cleaning step of cleaning the processing vessel by dispensing a cleaning solution onto a jig while rotating the jig supported on the support plate. In the substrate treating step, the substrate is clamped to the support plate by a first vacuum pressure applied to the substrate. The vessel cleaning step includes a first clamping step of clamping the jig to the support plate by applying a second vacuum pressure to the jig. The first vacuum pressure and the second vacuum pressure are different from each other. | 2020-01-23 |
20200027762 | Silicon Carbide Substrate Heating - A system and method for heating silicon carbide substrates is disclosed. The system includes a heating element that utilizes LEDs that emit light at wavelengths between 600 nm and 650 nm. This wavelength is better absorbed by silicon carbide. In certain embodiments, collimating optics are disposed between the LEDs and the silicon carbide substrate. The collimating optics may increase the allowable distance between the LEDs and the substrate. In other embodiments, a diffuser is disposed between the LEDs and the substrate. In addition, a method of heating a substrate is disclosed. The relationship between absorption coefficient and wavelength is determined for the substrate. Based on this relationship, an optimal wavelength or range of wavelengths is selected. The substrate is then heated using an LED emitting light at the optimal wavelengths. | 2020-01-23 |
20200027763 | PARTICLE BEAM INSPECTION APPARATUS - An improved particle beam inspection apparatus, and more particularly, a particle beam inspection apparatus including an improved load lock unit is disclosed. An improved load lock system may comprise a plurality of supporting structures configured to support a wafer and a conditioning plate including a heat transfer element configured to adjust a temperature of the wafer. The load lock system may further comprise a gas vent configured to provide a gas between the conditioning plate and the wafer and a controller configured to assist with the control of the heat transfer element. | 2020-01-23 |
20200027764 | DEVICE AND METHOD FOR CONTACTLESSLY TRANSFERRING AT LEAST PARTLY FERROMAGNETIC ELECTRONIC COMPONENTS FROM A CARRIER TO A SUBSTRATE - The device and method according to the invention are used to transfer an electronic ferromagnetic component from a carrier to a substrate using a magnetic assembly. The magnetic assembly is designed and arranged to aid in the correct positioning of the at least partly ferromagnetic electronic component on the substrate. The magnetic field generated by the magnetic assembly produces a magnetic force oriented from the carrier towards the substrate, said magnetic force aiding the transfer of the component from the carrier to the substrate such that a significantly increased positioning accuracy of the component is achieved compared to a transfer without said magnetic force. | 2020-01-23 |
20200027765 | DIAGNOSTIC SYSTEM OF SUBSTRATE TRANSFER HAND - A diagnostic system of a substrate transfer hand including a base part coupled to a hand tip portion of a robot arm and a substrate holding part coupled to the base part to hold a substrate, includes a camera which is secured to the base part and takes an image of the substrate holding part; and a diagnostic device which obtains image information of the image taken by the camera and diagnoses normality of the substrate holding part based on the image information. | 2020-01-23 |
20200027766 | PACKAGE ASSEMBLY FOR THIN WAFER SHIPPING AND METHOD OF USE - A package assembly for thin wafer shipping using a wafer container and a method of use are disclosed. The package assembly includes a shipping container and a wafer container having a bottom surface and a plurality of straps attached thereto placed within the shipping container. The package assembly further includes upper and lower force distribution plates provided within the shipping container positioned respectively on a top side and bottom side thereof. | 2020-01-23 |
20200027767 | CARRIER, VACUUM SYSTEM AND METHOD OF OPERATING A VACUUM SYSTEM - A carrier for use in a vacuum system is described. The carrier includes: a magnet arrangement including one or more first permanent magnets; one or more second permanent magnets; and a magnet device configured to change a magnetization of the one or more first permanent magnets. The carrier may be used for carrying a mask device or a substrate in the vacuum system. Further, a vacuum system and a method of operating a vacuum system are described. | 2020-01-23 |
20200027768 | METHOD AND SUBSTRATE HOLDER FOR CONTROLLED BONDING OF SUBSTRATES - A method and a device for bonding a first substrate with a second substrate at mutually facing contact faces of the substrates. | 2020-01-23 |
20200027769 | CERAMIC HYBRID INSULATOR PLATE - The present disclosure generally relates to an electrostatic chuck for processing substrates. The electrostatic chuck includes a facilities plate and an insulator disposed between a cooling base and a ground plate. A support body is coupled to the cooling base for supporting a substrate thereon. A ring is configured to surround the insulator. The ring is formed from a material that is resistant to degradation from exposure to a manufacturing process. The ring optionally includes an extension configured to surround the facilities plate. | 2020-01-23 |
20200027770 | COMPOSITE SINTERED BODY, ELECTROSTATIC CHUCK MEMBER, ELECTROSTATIC CHUCK DEVICE, AND METHOD FOR PRODUCING COMPOSITE SINTERED BODY - A composite sintered body is a ceramic composite sintered body which includes metal oxide which is a main phase, and silicon carbide which is a sub-phase, in which crystal grains of the silicon carbide are dispersed in crystal grains of the metal oxide and at crystal grain boundaries of the metal oxide, and a proportion of the crystal grains of the silicon carbide dispersed in the crystal grains of the metal oxide is 25% or more in an area ratio with respect to a total crystal grains of the silicon carbide. | 2020-01-23 |
20200027771 | TEMPORARY-FIXING SUBSTRATE AND METHOD FOR TEMPORARILY FIXING ELECTRONIC COMPONENT - A temporary-fixing substrate includes a fixing face for adhering and temporary fixing a plurality of electronic parts by a resin mold on the fixing face and a bottom face on the opposite side of the fixing face. The temporary-fixing substrate is warped so that the fixing face is of a convex shape curved upwardly from the temporary-fixing substrate viewed in a cross section of the temporary-fixing substrate. The following formula (1) is satisfied, provided that W is assigned to a width of the fixing face viewed in the cross section of the temporary-fixing substrate, and provided that W | 2020-01-23 |
20200027772 | DIE MATRIX EXPANDER WITH PARTITIONED SUBRING - A die matrix expander includes a subring including ≥3 pieces, and a wafer frame supporting a dicing tape having an indentation for receiving pieces of the subring. The subring prior to expansion sits below a level of the wafer frame and has an outer diameter 2020-01-23 | |
20200027773 | METHODS FOR EDGE TRIMMING OF SEMICONDUCTOR WAFERS AND RELATED APPARATUS - Methods and apparatus for pre-treating semiconductor wafers before edge trimming to enhance wafer edge quality prior to thinning the semiconductor wafers from an initial thickness, and increasing yield post-thinning of the pre-treated, edge trimmed semiconductor wafers. | 2020-01-23 |
20200027774 | Support Table, Support Table Assembly, Processing Arrangement, and Methods Thereof - According to various embodiments, a support table may include: a baseplate including a support structure, the support structure defining a support region over the baseplate to support at least one of a workpiece or a workpiece carrier therein; and one or more light-emitting components disposed between the baseplate and the support region. The one or more light-emitting components are configured to emit light into the support region. | 2020-01-23 |
20200027775 | DIE PLACEMENT AND COUPLING APPARATUS - A die placement and coupling apparatus may include a die bonding attachment. The die placement and coupling apparatus may include a compliant head unit that may be adapted to optionally couple with a semiconductor die. The compliant head unit may include a die attach surface that may include a layer of compliant material. The layer of compliant material may be coupled to the compliant head unit. The die attach surface may be adapted to mate with the semiconductor die when the semiconductor die is coupled with the compliant head unit. The layer of compliant material may be adapted to yield in response to an applied force. The die placement and coupling apparatus may include a vacuum port in communication with the die attach surface. The port may be adapted to have a vacuum applied to the port, and the vacuum temporarily holds the semiconductor die to the die attach surface. | 2020-01-23 |
20200027776 | SUBSTRATE PLACING PART THAT IS ARRANGED IN SUBSTRATE PROCESSING APPARATUS - An embodiment of a substrate placing part relates to a substrate placing part that is arranged in a substrate processing apparatus. The substrate placing part is divided into a plurality of inner sections that have an inner heating wire and an outer heating wire; and an outer section that is arranged in an edge thereof, that surrounds the inner sections, and that includes the outer heating wire, wherein the inner heating wire is disposed in the same inner section and has a first gap in at least a partial section thereof, the respective inner heating wires disposed in the different inner sections are disposed to have a second gap in a part in which the inner heating wires are parallel to one another, the inner heating wire and the outer heating wire are disposed to have a third gap in a part in which the inner heating wire and the outer heating wire are parallel to one another, and the first gap may be smaller than the second gap. | 2020-01-23 |
20200027777 | METHOD AND DEVICE FOR POWER RAIL IN A FIN TYPE FIELD EFFECT TRANSISTOR - A method of forming a semiconductor device may include providing a semiconductor device structure. The semiconductor device structure may include semiconductor fins pitched at a fin pitch on a substrate and a mask, disposed over the semiconductor fins, the mask defining a plurality of openings. The semiconductor device structure may further include an isolation oxide disposed on the substrate, between the semiconductor fins. The method may further include directing angled ions into the at least one of the plurality of openings. The angled ions may form at least one trench between at least one pair of the semiconductor fins, in the substrate below the isolation oxide between the at least one pair of the semiconductor fins. Furthermore, a width within the substrate of the at least one trench is greater than a minimum fin pitch and greater than a width of the at least one trench above the substrate. | 2020-01-23 |
20200027778 | HIGH RESISTIVITY SILICON-ON-INSULATOR STRUCTURE AND METHOD OF MANUFACTURE THEREOF - A multilayer structure is provided, the multilayer structure comprising a semiconductor on insulator structure comprises an insulating layer that enhances the stability of the underlying charge trapping layer. | 2020-01-23 |
20200027779 | SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE STRUCTURES - A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure. | 2020-01-23 |
20200027780 | METHOD FOR FORMING A MULTI-LEVEL INTERCONNECT STRUCTURE - A method is provided for forming a multi-level interconnect structure on a semiconductor substrate, e.g., for use in an integrated circuit, comprising forming on the substrate a first interconnection level comprising a first dielectric layer and a first set of conductive structures arranged in the first dielectric layer, forming on the first interconnection level a second interconnection level comprising a second dielectric layer and a second set of conductive structures arranged in the second dielectric layer, and forming on the second interconnection level a third interconnection level. | 2020-01-23 |
20200027781 | ETCH-STOP LAYER TOPOGRAPHY FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION - Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a plurality of conductive interconnect lines in and spaced apart by an inter-layer dielectric (ILD) layer above a substrate. Individual ones of the plurality of conductive interconnect lines have an upper surface below an upper surface of the ILD layer. An etch-stop layer is on and conformal with the ILD layer and the plurality of conductive interconnect lines, the etch-stop layer having a non-planar upper surface with an uppermost portion of the non-planar upper surface over the ILD layer and a lowermost portion of the non-planar upper surface over the plurality of conductive interconnect lines. | 2020-01-23 |
20200027782 | METHODS FOR MANUFACTURING AN INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICES - Generally, embodiments described herein relate to methods for manufacturing an interconnect structure for semiconductor devices, such as in a dual subtractive etch process. An embodiment is a method for semiconductor processing. A titanium nitride layer is formed over a substrate. A hardmask layer is formed over the titanium nitride layer. The hardmask layer is patterned into a pattern. The pattern is transferred to the titanium nitride layer, where the transferring comprises etching the titanium nitride layer. After transferring the pattern to the titanium nitride layer, the hardmask layer is removed, where the removal comprises performing an oxygen-containing ash process. | 2020-01-23 |
20200027783 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a first wiring layer, the first wiring layer including a first metal wiring and a first interlayer insulating film wrapping the first metal wiring on a substrate, forming a first via layer, the first via layer including a first via that is in electrical connection with the first metal wiring, and a second interlayer insulating film wrapping the first via on the first wiring layer, and forming a second wiring layer, the second wiring layer including a second metal wiring that is in electrical connection with the first via, and a third interlayer insulating film wrapping the second metal wiring on the first via layer, wherein the third interlayer insulating film contains deuterium and is formed through chemical vapor deposition using a first gas containing deuterium and a second gas containing hydrogen. | 2020-01-23 |
20200027784 | INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME - An integrated circuit device includes a substrate, a landing pad on the substrate, and a through-via structure passing through the substrate and connected to the landing pad. The through-via structure may include a conductive plug, a first conductive barrier layer covering a sidewall and a lower surface of the conductive plug, and a second conductive barrier layer covering a sidewall of the first conductive barrier layer. | 2020-01-23 |
20200027785 | Selective and Self-Limiting Tungsten Etch Process - Methods of dep-etch in semiconductor devices (e.g. V-NAND) are described. A metal layer is deposited in a feature. The metal layer is removed by low temperature atomic layer etching by oxidizing the surface of the metal layer and etching the oxide in a layer-by-layer fashion. After removal of the metal layer, the features are filled with a metal. | 2020-01-23 |
20200027786 | SEMICONDUCTOR DEVICE - A semiconductor device includes gates extending in a first direction on a substrate, each gate of the gates including a gate insulation layer, a gate electrode, and a first spacer, first contact plugs contacting the substrate between adjacent ones of the gates, the first contact plugs being spaced apart from sidewalls of corresponding ones of the gates, a second contact plug contacting an upper surface of a corresponding gate electrode, the second contact plug being between first contact plugs, and an insulation spacer in a gap between the second contact plug and an adjacent first contact plug, the insulation spacer contacting sidewalls of the second contact plug and the adjacent first contact plug, and upper surfaces of the second contact plug and the adjacent first contact plug being substantially coplanar with each other. | 2020-01-23 |
20200027787 | SEMICONDUCTOR DEVICE WITH LOCAL CONNECTION - A first TS is coupled to first S/D over first fin, second TS coupled to second S/D over first fin, third TS coupled to third S/D over second fin, fourth TS coupled to fourth S/D over second fin, gate metal over first and second fins, and gate cap over gate metal. First TS cap is on first TS, second TS cap on second TS, third TS cap on third TS, and fourth TS cap on fourth TS. ILD is formed on top of gate cap and first through fourth TS caps. First opening is through ILD and second TS cap such that part of gate metal is exposed, after removing part of gate cap. Second opening is through ILD to expose another part of gate metal. Combined gate metal contact and local metal connection is formed in first opening and individual gate metal contact is formed in second opening. | 2020-01-23 |
20200027788 | FORMATION METHOD OF DAMASCENE STRUCTURE - A method for forming a semiconductor device is provided. The method includes forming a first dielectric layer over a semiconductor substrate and forming a first conductive feature extending into the first dielectric layer. The first conductive feature has a planar top surface. The method also includes forming a second dielectric layer over the first conductive feature. The method further includes forming a hole in the second dielectric layer to expose the planar top surface of the first conductive feature. In addition, the method includes partially removing the first conductive feature from the planar top surface of the first conductive feature to form a curved surface of the first conductive feature. The method further includes forming a second conductive feature to fill the hole after the curved surface of the first conductive feature is formed. | 2020-01-23 |
20200027789 | INDUCTOR STRUCTURE FOR INTEGRATED CIRCUIT - The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first plurality of conductive interconnect layers arranged within a first inter-level dielectric (ILD) structure disposed on a first surface of a first substrate. A second plurality of conductive interconnect layers are arranged within a second ILD structure disposed on a first surface of a second substrate. The second substrate is separated from the first substrate by the first ILD structure. The first plurality of conductive interconnect layers and the second plurality of conductive interconnect layers define an inductor having one or more turns. | 2020-01-23 |
20200027790 | INDUCTOR STRUCTURE FOR INTEGRATED CIRCUIT - The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a first conductive wire within a first dielectric structure formed on a first surface of a first substrate. A through-substrate-via (TSV) is formed to extend though the first substrate. A second conductive wire is formed within a second dielectric structure formed on a second surface of the first substrate opposing the first surface. The TSV electrically couples the first conductive wire and the second conductive wire. The first conductive wire, the second conductive wire, and the TSV define an inductor that wraps around an axis. | 2020-01-23 |
20200027791 | Optimizing Junctions of Gate All Around Structures with Channel Pull Back - Techniques for optimizing junctions of a gate-all-around nanosheet device are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of first/second nanosheets including a first/second material as a stack on a wafer; forming a dummy gate(s) on the stack; patterning the stack into a fin stack(s) beneath the dummy gate(s); etching the fin stack(s) to selectively pull back the second nanosheets in the fin stack(s) forming pockets in the fin stack(s); filling the pockets with a strain-inducing material; burying the dummy gate(s) in a dielectric material; selectively removing the dummy gate(s) forming a gate trench(es) in the dielectric material; selectively removing either the first nanosheets or the second nanosheets from the fin stack(s); and forming a replacement gate(s) in the gate trench(es). A nanosheet device is also provided. | 2020-01-23 |
20200027792 | METHOD AND STRUCTURE FOR FORMING TRANSISTORS WITH HIGH ASPECT RATIO GATE WITHOUT PATTERNING COLLAPSE - A method for fabricating transistors comprises forming a fin above a semiconductor substrate; forming an isolation region with a dielectric material, the top surface of the isolation dielectric below the top of fin surface; depositing a dummy gate layer above the isolation region and surrounding the fin, a dummy gate hardmask layer on top of the dummy gate layer, a first hardmask material on top of the dummy gate hardmask layer above the fin and a second hardmask material on top of the dummy gate hardmask layer above the isolation region, the first hardmask material having a greater lateral etch than the second hardmask material; applying a gate patterning mask spaced equidistantly apart on top of the first and second hardmask materials; and etching the transistor to simultaneously form narrow active gates above and surrounding the fin and wide dummy gates above the isolation region. | 2020-01-23 |
20200027793 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure and a dielectric layer disposed on an upper surface of the isolation insulating layer. Both the first fin structure and the second fin structure are disposed over the substrate, and extend in a first direction in plan view. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction. The first and second fin structures not covered by the gate structure are recessed below the upper surface of the isolation insulating layer. The source/drain structure is formed over the recessed first and second fin structures. A void is formed between the source/drain structure and the dielectric layer. | 2020-01-23 |
20200027794 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a method of manufacturing a semiconductor device, a fin structure having a bottom portion, an intermediate portion disposed over the bottom portion and an upper portion disposed over the intermediate portion is formed. The intermediate portion is removed at a source/drain region of the fin structure, thereby forming a space between the bottom portion and the upper portion. An insulating layer is formed in the space. A source/drain contact layer is formed over the upper portion. The source/drain contact layer is separated by the insulating layer from the bottom portion of the fin structure. | 2020-01-23 |
20200027795 | GATE SPACER FORMATION FOR SCALED CMOS DEVICES - Disclosed are methods of forming a CMOS device. One non-limiting method may include providing a gate structure atop a substrate, and forming a first spacer over the gate structure. The method may include removing the first spacer from just an upper portion of the gate structure by performing an angled reactive ion etch or angled implantation disposed at a non-zero angle of inclination with respect to a perpendicular to a plane of the substrate. The method may further include forming a second spacer over the upper portion of the gate structure and the first spacer along a lower portion of the gate structure. A thickness of the first spacer and the second spacer along the lower portion of the gate structure may be greater than a thickness of the second spacer along the upper portion of the gate structure. | 2020-01-23 |
20200027796 | CONTROLLING ACTIVE FIN HEIGHT OF FINFET DEVICE USING ETCH PROTECTION LAYER TO PREVENT RECESS OF ISOLATION LAYER DURING GATE OXIDE REMOVAL - Semiconductor devices and methods are provided to fabricate fin field-effect transistor (FinFET) devices having uniform fin height profiles. For example, uniformity of fin height profiles for FinFET devices is obtained by implementing a gate oxide removal process which is designed to prevent etching of an isolation layer (e.g., a shallow trench isolation layer) formed of an oxide material during removal of, e.g., sacrificial gate oxide layers of dummy gate structures during a replacement metal gate process. | 2020-01-23 |
20200027797 | MANUFACTURING METHOD AND EVALUATION METHOD FOR SiC DEVICE - Provided is a manufacturing method for a SiC device including: performing an ion implantation process of implanting ions in an epitaxial layer of a SiC epitaxial wafer that has the epitaxial layer; and performing an evaluation process of evaluating a defect of the SiC epitaxial wafer after the ion implantation process, in which the evaluation process includes a surface inspection process of inspecting a surface of the SiC epitaxial wafer, a PL inspection process of irradiating a region that includes the defect detected in the surface inspection to perform photoluminescence measurement after the surface inspection process, and a determination process of determining a degree of the defect from a surface defect image detected in the surface inspection and a PL defect image detected in the PL inspection process. | 2020-01-23 |
20200027798 | WAFER LEVEL TESTING OF OPTICAL COMPONENTS - A system may include a wafer that includes ICs and defines cavities. Each cavity may be formed in a BEOL layer of the wafer and proximate a different IC. The system may also include an interposer that includes a transparent layer configured to permit optical signals to pass through. The interposer may also include at least one waveguide located proximate the transparent layer. The at least one waveguide may be configured to adiabatically couple at least one optical signal out of the multiple ICs. Further, the interposer may include a redirecting element optically coupled to the at least one the waveguide. The redirecting element may be located proximate the transparent layer and may be configured to receive the at least one optical signal from the at least one waveguide. The redirecting element may also be configured to vertically redirect the at least one optical signal towards the transparent layer. | 2020-01-23 |
20200027799 | METHOD AND SYSTEM FOR THERMAL CONTROL OF DEVICES IN AN ELECTRONICS TESTER - A tester apparatus is provided. Slot assemblies are removably mounted to a frame. Each slot assembly allows for individual heating and temperature control of a respective cartridge that is inserted into the slot assembly. A closed loop air path is defined by the frame and a heater and cooler are located in the closed loop air path to cool or heat the cartridge with air. Individual cartridges can be inserted or be removed while other cartridges are in various stages of being tested or in various stages of temperature ramps. | 2020-01-23 |
20200027800 | SEMICONDUCTOR MEMORY AND METHOD OF MANUFACTURING THE SEMICONDUCTOR MEMORY - A semiconductor memory according to an embodiment includes first and second areas, an active region, a non-active region, a first stacked body, a plurality of first pillars, a first contact, a second stacked body, and a second contact. The active region includes part of each of the first and second areas. The non-active region includes part of each of the first and second areas. The second stacked body is in the non-active region. The second stacked body includes second insulators and second conductors which are alternately stacked. A second contact is in contact with a second conductor in a first interconnect layer and a second conductor in a second interconnect layer. | 2020-01-23 |
20200027801 | TEST STRUCTURE FOR INLINE DETECTION OF INTERLAYER METAL DEFECTS - A integrated circuit structure has a first test structure with a first set of un-landed vias. The first set of un-landed vias has a first side for each of the first set of un-landed vias proximate to a first BEOL layer (first back-end-of-line layer) of a chip and spaced apart, by a first gap, from the first BEOL layer. Each of the first set of un-landed vias has a first depth that is smaller than a landed depth of a chip via conductively connecting the first BEOL layer to a second BEOL layer of the chip. The first set of un-landed vias also has a second side for each of the first set of un-landed vias opposite the first side and connected to the second BEOL layer. | 2020-01-23 |
20200027802 | METHODS AND SYSTEMS TO IMPROVE PRINTED ELECTRICAL COMPONENTS AND FOR INTEGRATION IN CIRCUITS - Methods and systems to improve printed electrical components and for integration in circuits are disclosed. Passive components, e.g., capacitors, resistors and inductors, can be printed directly into a solid ceramic block using additive manufacturing. A grounded conductive plane or a conductive cage may be placed between adjacent electrical components, or around each component, to minimize unwanted parasitic effects in the circuits, such as, e.g., parasitic capacitance or parasitic inductance. Resistors may be printed in non-traditional shapes, for example, S-shape, smooth S-shape, U-shape, V-shape, Z-shape, zigzag-shape, and any other acceptable alternative configurations. The flexibility in shapes and sizes of the printed resistors allows optimal space usage of the ceramic block. The present invention also discloses an electrical component comprising combined predetermined values of capacitance, resistance and inductance. The integration and adjustability of a multi-property device can provide significant advantages in electronics manufacturing. | 2020-01-23 |
20200027803 | Methods and Apparatus for Package with Interposers - An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure. | 2020-01-23 |
20200027804 | ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR PACKAGE STRUCTURE - An electronic device includes an insulating layer, a metal layer and at least one electrical connecting element. The insulating layer has a top surface and a bottom surface opposite to the top surface, and defines an opening extending between the top surface and the bottom surface. The metal layer is disposed in the opening of the insulating layer and has a top surface and a bottom surface opposite to the top surface. The bottom surface of the metal layer is substantially coplanar with the bottom surface of the insulating layer. The electrical connecting element is attached to the bottom surface of the metal layer through a seed layer. | 2020-01-23 |
20200027805 | SEMICONDUCTOR CHIP, METHOD FOR MOUNTING SEMICONDUCTOR CHIP, AND MODULE IN WHICH SEMICONDUCTOR CHIP IS PACKAGED - A semiconductor chip includes a single-crystal substrate and a metal electrode on the bottom surface of the substrate. The metal electrode has a region in which a first metal is exposed and a region in which a second metal is exposed, the second metal having a standard electrode potential different from that of the first metal. | 2020-01-23 |
20200027806 | Package Structure and Method - In an embodiment, a device includes: a substrate having a first side and a second side opposite the first side; an interconnect structure adjacent the first side of the substrate; and an integrated circuit device attached to the interconnect structure; a through via extending from the first side of the substrate to the second side of the substrate, the through via being electrically connected to the integrated circuit device; an under bump metallurgy (UBM) adjacent the second side of the substrate and contacting the through via; a conductive bump on the UBM, the conductive bump and the UBM being a continuous conductive material, the conductive bump laterally offset from the through via; and an underfill surrounding the UBM and the conductive bump. | 2020-01-23 |
20200027807 | POWER MODULE - A power module, including: a first conductor, disposed at a first reference plane; a second conductor, disposed at a second reference plane, wherein projections of the first and second conductors on the first reference plane have a first overlap area; a third conductor, disposed at a third reference plane; a plurality of first switches, first ends of which are coupled to the first conductor; and a plurality of second switches, first ends of which are coupled to second ends of the first switches through the third conductor, and second ends of the second switches are coupled to the second conductor, wherein projections of minimum envelope areas of the first and second switches on the first reference plane have a second overlap area, and the first and second overlap areas have an overlap region. Heat sources of the power module are evenly distributed and its parasitic inductance is low. | 2020-01-23 |