04th week of 2017 patent applcation highlights part 53 |
Patent application number | Title | Published |
20170025268 | SUBSTRATE LIQUID PROCESSING APPARATUS, SUBSTRATE LIQUID PROCESSING METHOD, AND STORAGE MEDIUM - Disclosed is a substrate liquid processing apparatus including: a processing bath in which a processing liquid is stored; a chemical liquid component supply unit that supplies chemical liquid components; a concentration detecting unit that detects a concentration of the chemical liquid components; and a controller configured to perform a first control as a feedback control that replenishes the processing liquid with the chemical liquid components such that the concentration of the chemical liquid components contained in the processing liquid within the processing bath does not become less than a predetermined allowable lower limit, based on the concentration of the chemical liquid components detected by the concentration detecting unit. In addition, the controller performs a second control that replenishes the processing liquid with the chemical liquid components in a predetermined amount required to offset a reduction in concentration of the chemical liquid components caused by the introduction of the substrate. | 2017-01-26 |
20170025269 | WAFER PROCESSING METHOD - A wafer processing method includes a wafer holding step of holding a wafer having devices formed on the front side, a protective film forming step of forming a water-soluble protective film on the front side of the wafer, a laser beam applying step of applying a laser beam to the wafer along streets, a cleaning step of cleaning the wafer to then remove the protective film, and a foreign matter removing step of removing foreign matter from the wafer when a predetermined period of time has elapsed after cleaning. This period of time is set as a period of time until a phosphorus containing reaction product produced at a laser processed portion is evaporated to react with water in the air, thereby producing the foreign matter containing phosphorus on bumps formed on each device. | 2017-01-26 |
20170025270 | METHOD TO FABRICATE A HIGH PERFORMANCE CAPACITOR IN A BACK END OF LINE (BEOL) - A method can include applying a patterned mask over a semiconductor structure, the semiconductor structure having a dielectric layer, forming using the patterned mask a material formation trench intermediate first and second spaced apart metal formations formed in the dielectric layer, and disposing a dielectric material formation in the material formation trench. | 2017-01-26 |
20170025271 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - A method of manufacturing a semiconductor device includes: providing a substrate having an oxide film; performing, a predetermined number of times, a cycle of non-simultaneously performing supplying a precursor gas to the substrate, supplying a carbon-containing gas to the substrate, and supplying a nitrogen-containing gas to the substrate, or performing, a predetermined number of times, a cycle of non-simultaneously performing supplying a precursor gas to the substrate and supplying a gas containing carbon and nitrogen to the substrate, or performing, a predetermined number of times, a cycle of non-simultaneously performing supplying a precursor gas containing carbon to the substrate and supplying a nitrogen-containing gas to the substrate, the oxide film being used as an oxygen source to form a nitride layer containing oxygen and carbon as a seed layer; and forming a nitride film containing no oxygen and carbon as a first film on the seed layer. | 2017-01-26 |
20170025272 | Masking methods for ALD processes for electrode-based devices - Masking methods for atomic-layer-deposition processes for electrode-based devices are disclosed, wherein solder is used as a masking material. The methods include exposing electrical contact members of an electrical device having an active device region and a barrier layer formed by atomic layer deposition. This includes depositing solder elements on the electrical contact members, then forming the barrier layer using atomic layer deposition, wherein the barrier layer covers the active device region and also covers the solder elements that respectively cover the electrical contact members. The solder elements are then melted, which removes respective portions of the barrier layer covering the solder elements. Similar methods are employed for exposing contacts when forming layered capacitors. | 2017-01-26 |
20170025273 | TWO-DIMENSIONAL MATERIAL HARD MASK, METHOD OF MANUFACTURING THE SAME, AND METHOD OF FORMING MATERIAL LAYER PATTERN USING THE HARD MASK - A 2D material hard mask includes hydrogen, oxygen, and a 2D material layer having a layered crystalline structure. The 2D material layer may be a material layer including one of a carbon structure (for example, a graphene sheet) and a non-carbon structure. | 2017-01-26 |
20170025274 | NEUTRAL HARD MASK AND ITS APPLICATION TO GRAPHOEPITAXY-BASED DIRECTED SELF-ASSEMBLY (DSA) PATTERNING - A material stack is formed on the surface of a semiconductor substrate. The top layer of the material stack comprises at least an organic planarization layer. A neutral hard mask layer is formed on the top of the organic planarization layer. The neutral hard mask layer is neutral to the block copolymers used for direct self-assembly. A plurality of template etch stacks are then formed on top of the neutral hard mask layer. After formation of the template etch stacks, neutrality recovery is performed on the neutral hard mask layer and the top portions of the template etch stacks, the vertical sidewalls of the template etch stacks being substantially unaffected by the neutrality recovery. A template for DSA is thus obtained. | 2017-01-26 |
20170025275 | WAFER THINNING METHOD - Disclosed herein is a wafer thinning method for thinning a wafer formed from an SiC substrate having a first surface and a second surface opposite to the first surface. The wafer thinning method includes an annular groove forming step of forming an annular groove on the second surface of the SiC substrate in an annular area corresponding to the boundary between a device area and a peripheral marginal area in the condition where a thickness corresponding to the finished thickness of the wafer after thinning is left, and a separation start point forming step of applying the laser beam to the second surface as relatively moving a focal point and the SiC substrate to thereby form a modified layer and cracks inside the SiC substrate at the predetermined depth. | 2017-01-26 |
20170025276 | WAFER THINNING METHOD - Disclosed herein is a wafer thinning method for thinning a wafer formed from an SiC substrate having a first surface and a second surface opposite to the first surface. The wafer thinning method includes a separation start point forming step of applying the laser beam to the second surface as relatively moving the focal point and the SiC substrate to thereby form a modified layer parallel to the first surface and cracks inside the SiC substrate at the predetermined depth, thus forming a separation start point, and a wafer thinning step of applying an external force to the wafer, thereby separating the wafer into a first wafer having the first surface of the SiC substrate and a second wafer having the second surface of the SiC substrate at the separation start point. | 2017-01-26 |
20170025277 | Masking For High Temperature Implants - A method for the selective implantation of a workpiece is disclosed. In place of conventional photoresist, a two layer structure is used. The first layer, referred to as the protective layer, is applied directly to the workpiece and protects the workpiece from harmful etching processes. Additionally, the protective layer has limited ability to stop ions from impacting the workpiece. The second layer, referred to as the blocking layer, which is formed on a portion of the protective layer, is used to block ions from impacting the underlying workpiece. Advantageously, the blocking layer may be selectively etched without affecting the protective layer. Additionally, the protective layer can be removed without affecting the underlying workpiece. Through the use of this two layer technique, high temperature selective implants may be performed on a variety of different semiconductor devices. | 2017-01-26 |
20170025278 | Semiconductor Structures Having T-Shaped Electrodes - A semiconductor structure having a T-shaped electrode. The electrode has a top portion and a narrower stem portion extending from the top portion to a surface of a substrate. A solid dielectric layer has side portions juxtaposed and abutting sidewalls of a lower portion of the stem of electrode. A bottom surface of the top portion is spaced from an upper surface portion by a non-solid dielectric, such as air. | 2017-01-26 |
20170025279 | METHOD FOR GROWING GRAPHENE ON SURFACE OF GATE ELECTRODE AND METHOD FOR GROWING GRAPHENE ON SURFACE OF SOURCE/DRAIN SURFACE - The present invention provides a method for growing graphene on a surface of a gate electrode and a method for growing graphene on a surface of a source/drain electrode, in which a low-temperature plasma enhanced vapor deposition process is adopted to grow a graphene film, of which a film thickness is controllable, on a gate electrode or a source/drain electrode that contains copper, and completely coincides with a pattern of the gate electrode or the source/drain electrode. The manufacturing temperature of graphene is relatively low so that it is possible not to damage the structure of a thin-film transistor to the greatest extents and the supply of carbon sources that is used wide, having low cost and a simple manufacturing process, where existing PECVD facility of a thin-film transistor manufacturing line can be used without additional expense. The gate electrode or the source/drain electrode is covered with graphene and is prevented from contact with moisture and oxygen thereby overcoming the problem of a conventional TFT manufacturing process that a gate electrode or a source/drain electrode that contains copper is readily susceptible to oxidization. Further, the high electrical conductivity of graphene makes it possible not to affect the electrical performance of the entire device. | 2017-01-26 |
20170025280 | FORMATION OF BORON-DOPED TITANIUM METAL FILMS WITH HIGH WORK FUNCTION - A method for forming a Boron doped metallic film, such as Titanium Boron Nitride, is disclosed. The method allows for creation of the metallic film with a high work function and low resistivity, while limiting the increase in effective oxide thickness. The method comprises a thin metallic layer deposition step as well as a Boron-based gas pulse step. The Boron-based gas pulse deposits Boron and allows for the removal of excess halogens within the metallic film. The steps may be repeated in order to achieve a desired thickness of the metallic film. | 2017-01-26 |
20170025281 | Passivation of Nonlinear Optical Crystals - A laser system includes a nonlinear optical (NLO) crystal, wherein the NLO crystal is annealed within a selected temperature range. The NLO crystal is passivated with at least one of hydrogen, deuterium, a hydrogen-containing compound or a deuterium-containing compound to a selected passivation level. The system further includes at least one light source, wherein at least one light source is configured to generate light of a selected wavelength and at least one light source is configured to transmit light through the NLO crystal. The system further includes a crystal housing unit configured to house the NLO crystal. | 2017-01-26 |
20170025282 | METHOD AND APPARATUS FOR DRY GAS PHASE CHEMICALLY ETCHING A STRUCTURE - According to the invention there is provided a method of dry gas phase chemically etching a structure comprising the steps of: positioning the structure in an etch chamber, the structure comprising a first material and a second material, wherein the first material is selected from silicon, molybdenum, germanium, SiGe and tungsten, the second material is silicon dioxide or silicon nitride, and at least one surface of the first material is exposed so as to be contactable by a gas phase chemical etchant; etching the first material with a noble gas fluoride or halogen fluoride gas phase chemical etchant; and exposing the etch chamber to water vapour so that the step of etching the first material is performed in the presence of water vapour. | 2017-01-26 |
20170025283 | POLISHING APPARATUS AND SEMICONDUCTOR MANUFACTURING METHOD - A polishing apparatus according to an embodiment includes a first polishing part, a second polishing part, and an annular part. The second polishing part includes a mounting surface for a semiconductor substrate, and rubs the semiconductor substrate mounted on the mounting surface while pressing the semiconductor substrate against the first polishing part. The annular part includes a support part provided in the second polishing part, and a plurality of convex portions that project from the support part toward the first polishing part, are arranged in a circumferential direction around the mounting surface while being supported by the support part, and are movable in a radial direction of the semiconductor substrate. | 2017-01-26 |
20170025284 | METHOD FOR FORMING PATTERNS OF SEMICONDUCTOR DEVICE - A method for forming patterns of a semiconductor device includes preparing an etch target layer defined with a first region and a second region; forming a regular first feature which is positioned over the etch target layer in the first region and a random feature which is positioned over the etch target layer in the second region; forming a regular second feature over the regular first feature; forming first and second cutting barriers which expose a portion of the random feature, over the random feature; cutting the regular first feature using the regular second feature, to form a regular array feature; cutting the random feature using the first cutting barrier and the second cutting barrier, to form a random array feature; and etching the etch target layer by using the regular array feature and the random array feature, to form a regular array pattern and a random array pattern. | 2017-01-26 |
20170025285 | HIGH-K AND P-TYPE WORK FUNCTION METAL FIRST FABRICATION PROCESS HAVING IMPROVED ANNEALING PROCESS FLOWS - Embodiments are directed to a method of forming portions of a fin-type field effect transistor (FinFET). The method includes forming at least one fin, and forming a dielectric layer over at least a portion of the at least one fin. The method further includes forming a work function layer over at least a portion of the dielectric layer. The method further includes forming a source region or a drain region adjacent the at least one fin, and performing an anneal operation, wherein the anneal operation anneals the dielectric layer and either the source region or the drain region, and wherein the work function layer provides a protection function to the at least a portion of the dielectric layer during the anneal operation. | 2017-01-26 |
20170025286 | METHOD OF ADJUSTING CHANNEL WIDTHS OF SEMICONDUCTIVE DEVICES - A method of adjusting channel widths of semiconductive devices includes providing a substrate divided into a first region and a second region, wherein the substrate comprises numerous fins. A first implantation process is performed on the fins within the first region. Then, a second implantation process is performed on the fins within the second region, wherein the first implantation process and the second implantation process are different from each other in at least one of the conditions comprising dopant species, dopant dosage or implantation energy. After that, part of the fins within the first region and the second region are removed simultaneously to form a plurality of first recesses within the first region and a plurality of second recesses within the second region. Finally, a first epitaxial layer and a second epitaxial layer are formed to fill up each first recess and each second recess, respectively. | 2017-01-26 |
20170025287 | High-efficiency line-forming optical systems and methods using a serrated spatial filter - High-efficiency line-forming optical systems and methods that employ a serrated aperture are disclosed. The line-forming optical system includes a laser source, a beam conditioning optical system, a first aperture device, and a relay optical system that includes a second aperture device having the serrated aperture. The serrated aperture is defined by opposing serrated blades configured to reduce intensity variations in a line image formed at an image plane as compared to using an aperture having straight-edged blades. | 2017-01-26 |
20170025288 | SEMICONDUCTOR CLEANER SYSTEMS AND METHODS - In an embodiment, the present invention discloses a EUV cleaner system and process for cleaning a EUV carrier. The cuv cleaner system comprises separate dirty and cleaned environments, separate cleaning chambers tor different components of the double container carrier, gripper arms tor picking and placing different components using a same robot handler, gripper arms for holding different components at different locations, horizontal spin cleaning and drying for outer container, hot water and hot air (70C) cleaning process, vertical nozzles and rasterizing megasonic nozzles for cleaning inner container with hot air nozzles for drying, separate vacuum decontamination chambers for outgassing different components, for example, one for inner and one for outer container with high vacuum (eg., <10 | 2017-01-26 |
20170025289 | PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - The present invention provides a plasma processing apparatus having a radio frequency power supply supplying time-modulated radio frequency power which is controllable widely with high precision, and a plasma processing method using the plasma processing apparatus. The plasma processing apparatus includes: a vacuum chamber; a first radio frequency power supply for generating plasma in the vacuum chamber; a sample holder disposed in the vacuum chamber, on which a sample is placed; and a second radio frequency power supply supplying radio frequency power to the sample holder, wherein at least one of the first radio frequency power supply and the second radio frequency power supply supplies time-modulated radio frequency power, one of parameters of controlling the time-modulation has two or more different control ranges, and one of the control ranges is a control range for a high-precision control. | 2017-01-26 |
20170025290 | LOAD LOCK APPARATUS AND SUBSTRATE PROCESSING SYSTEM - A load lock apparatus having a load lock chamber, which is connected to a vacuum transfer chamber configured to transfer a substrate under a vacuum pressure state via a communication hole which is opened and closed by a gate valve, and configured to be capable of switching an inner pressure into an atmospheric pressure state and the vacuum pressure state, is provided. The load lock apparatus includes a load lock chamber main body in which a substrate container having an attachable/detachable cover is carried, wherein the communication hole is formed in a side surface of the load lock chamber; and a cover attaching/detaching mechanism installed at a height position vertically arranged with the communication hole in the load lock chamber; and an elevating mechanism including a mounting table on which the substrate container is loaded and configured to lift and lower the mounting table. | 2017-01-26 |
20170025291 | MULTI-CHAMBER FURNACE FOR BATCH PROCESSING - A multi-chamber furnace for processing at least 100 substrates is provided. Reactor housings define a plurality of laterally spaced reactor chambers that are individually configured to accommodate up to about 50 substrates. Substrate holders correspond to the reactor chambers, and are configured to support and vertically stack substrates arranged in the corresponding reactor chambers. Heaters correspond to the reactor chambers and are configured to heat the corresponding reactor chambers. A method for batch processing substrates using the multi-chamber furnace is also provided. | 2017-01-26 |
20170025292 | LITHOGRAPHY APPARATUS, AND ARTICLE MANUFACTURING METHOD - Provided is a lithography apparatus that performs a patterning on a substrate. The lithography apparatus includes a processor configured to perform processing of assigning, to each of a plurality of substrates sequentially carried in from a first external apparatus, order information indicating an carrying-in order of the plurality of substrates; a plurality of units configured to respectively perform patternings of the plurality of substrates in parallel; and a transmitting device configured to transmit, to a second external apparatus, the order information corresponding to a substrate, of the plurality of substrates, carried out after being patterned thereon by one of the plurality of units. | 2017-01-26 |
20170025293 | SUBSTRATE PROCESSING APPARATUS - Provided is a substrate processing apparatus, and more particularly, a batch-type substrate processing apparatus where processes can be performed independently on a plurality of substrates. The substrate processing apparatus includes a substrate boat including a plurality of partition plates and a plurality of connection rods, an internal reaction tube, a gas supply unit, and an exhaust unit, and a plurality of substrates are loaded to be separated from the partition plates. | 2017-01-26 |
20170025294 | SUBSTRATE STORING CONTAINER - The tip face | 2017-01-26 |
20170025295 | PACKAGE ASSEMBLY FOR THIN WAFER SHIPPING AND METHOD OF USE - A package assembly for thin wafer shipping using a wafer container and a method of use are disclosed. The package assembly includes a shipping container and a wafer container having a bottom surface and a plurality of straps attached thereto placed within the shipping container. The package assembly further includes upper and lower force distribution plates provided within the shipping container positioned respectively on a top side and bottom side thereof. | 2017-01-26 |
20170025296 | GAS PURGE APPARATUS, LOAD PORT APPARATUS, INSTALLATION STAND FOR PURGING CONTAINER, AND GAS PURGE METHOD - In a gas purge apparatus, a load port apparatus, an installation stand for a purging container, and a gas purge method, the inside of the purging container can be filled with a cleaning gas without inclining the purging container. A control means drives a nozzle driving mechanism to move a purge nozzle toward a purge port based on a fixing detection signal detected by a fixing detection sensor showing that the purging container is fixed on a table. | 2017-01-26 |
20170025297 | GAS PURGE UNIT - A gas purge unit introduces a cleaning gas into a container with a main opening there through for taking a housed object in and out. The gas purge unit includes a blowout member and a supply portion. The blowout member with a cylindrical shape has an elongated hollow extending in a longitudinal direction and a discharge portion of a porous body connecting between the elongated hollow and the outside to discharge the cleaning gas. The supply portion is connected to the elongated hollow through a connection hole formed at one end of the blowout member to supply the cleaning gas to the elongated hollow. | 2017-01-26 |
20170025298 | GAS PURGE APPARATUS, LOAD PORT APPARATUS, INSTALLATION STAND FOR PURGING CONTAINER, AND GAS PURGE METHOD - In a gas purge apparatus, a load port apparatus, an installation stand for a purging container, and a gas purge method, the inside of the purging container is filled with a cleaning gas until just before transportation, and a placement failure does not happen to the next purging container to be placed. A purge nozzle is moved to a direction separating from a purge port after detecting a movement of a table on which the purging container is installed to an undock position and a stop of a feeding of the cleaning gas. | 2017-01-26 |
20170025299 | GAS PURGE UNIT, LOAD PORT APPARATUS, AND INSTALLATION STAND FOR PURGING CONTAINER - A gas purge unit includes an intake nozzle | 2017-01-26 |
20170025300 | SYSTEM ARCHITECTURE FOR VACUUM PROCESSING - A system for processing substrates in plasma chambers, such that all substrates transport and loading/unloading operations are performed in atmospheric environment, but processing is performed in vacuum environment. The substrates are transported throughout the system on carriers. The system's chambers are arranged linearly, such that carriers move from one chamber directly to the next. A conveyor, placed above or below the system's chambers, returns the carriers to the system's entry area after processing is completed. Loading and unloading of substrates may be performed at one side of the system, or loading can be done at the entry side and unloading at the exit side. | 2017-01-26 |
20170025301 | A METHOD FOR MANUFACTURING A HANDLE SUBSTRATE FOR THE TEMPORARY BONDING OF A SUBSTRATE - This process includes steps: a) providing a carrier substrate including a receiving face; b) depositing a nonstick coating on the receiving face, the nonstick coating including a central region and a peripheral region; and c) trimming the carrier substrate so as to remove the peripheral region of the nonstick coating and to form a recess on the periphery of the carrier substrate, in order to obtain the handle wafer. Also relates to a process for temporarily bonding a substrate to a handle wafer fabricated using the process described above. Furthermore relates to a handle wafer fabricated using the process described above. | 2017-01-26 |
20170025302 | PRE-PACKAGE AND METHODS OF MANUFACTURING SEMICONDUCTOR PACKAGE AND ELECTRONIC DEVICE USING THE SAME - Methods of fabricating semiconductor packages are provided. One of the methods includes forming a protection layer including metal on a first surface of a substrate to cover a semiconductor device disposed on the first surface of the substrate, attaching a support substrate to the protection layer by using an adhesive member, processing a second surface of the substrate opposite to the protection layer to remove a part of the substrate, and detaching the support substrate from the substrate. | 2017-01-26 |
20170025303 | BASE FOR BACK GRIND TAPES, AND BACK GRIND TAPE - A substrate for back grind tape of the present invention includes a substrate film having a Young's modulus of 600 MPa or more; and a buffer layer provided on one face of the substrate film, the buffer layer formed of a urethane-containing cured material and having a peak temperature of tan 6 of 60° C. or lower. | 2017-01-26 |
20170025304 | METHOD FOR ESTABLISHING MAPPING RELATION IN STI ETCH AND CONTROLLING CRITICAL DIMENSION OF STI - The present invention provides a method for controlling a critical dimension of shallow trench isolations in a STI etch process, comprises the following steps: before the STI etch process, pre-establishing a mapping relation between a post-etch and pre-etch critical dimension difference of a BARC layer and a thickness of the BARC layer; and during the STI etch process after coating the BARC layer, measuring the thickness of the BARC layer and determining a trimming time for a hard mask layer according to a critical dimension difference corresponding to the measured thickness in the mapping relation and a critical dimension of a photoresist pattern, then performing a trimming process for the hard mask layer lasting the trimming time to make a critical dimension of the hard mask layer equal to a required critical dimension of an active area, and etching a substrate to form shallow trenches with a predetermined critical dimension. | 2017-01-26 |
20170025305 | SHALLOW TRENCH ISOLATION REGIONS MADE FROM CRYSTALLINE OXIDES - A method of manufacturing a semiconductor device that involves etching a trench in a semiconductor substrate, epitaxially growing a crystalline structure in the trench and forming semiconductor structures on either side of the crystalline structure. Crystalline oxides may include rare earth oxides, aluminum oxides or Perovskites. | 2017-01-26 |
20170025306 | METHODS FOR PREPARING LAYERED SEMICONDUCTOR STRUCTURES AND RELATED BONDED STRUCTURES - Methods for preparing silicon-on-insulator structures and related intermediate structures are disclosed. In some embodiments, a single crystal silicon seed crystal is bonded to an amorphous silicon layer disposed on a substrate and the amorphous layer is crystallized to form a monocrystalline silicon layer. | 2017-01-26 |
20170025307 | METHODS FOR PREPARING LAYERED SEMICONDUCTOR STRUCTURES - Methods for preparing layered semiconductor structures are disclosed. The methods may involve pretreating an ion-implanted donor wafer by annealing the ion-implanted donor wafer to cause a portion of the ions to out-diffuse prior to wafer bonding. The donor structure may be bonded to a handle structure and cleaved without re-implanting ions into the donor structure. | 2017-01-26 |
20170025308 | METHOD OF CLEANING BOTTOM OF VIA HOLE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In a method of cleaning a bottom of a via hole, a copper oxide on a surface of an underlying Cu wiring exposed at the bottom of the via hole is removed before forming a Cu wiring in a trench and the via hole extended between the trench and the underlying Cu wiring. The trench and the via hole are formed in a predetermined pattern in an interlayer insulating film of a substrate. Reducing species containing a metal in a state capable of reducing the copper oxide is supplied to the bottom of the via hole. The metal has a higher oxidation tendency than Cu and an oxide of the metal has a lower electrical resistance than the copper oxide. The copper oxide is removed by reducing the copper oxide and the oxide of the metal is generated through a reaction between the metal in the reducing species and the copper oxide. | 2017-01-26 |
20170025309 | Contact Plug without Seam Hole and Methods of Forming the Same - A method includes forming a metallic layer over a Metal-Oxide-Semiconductor (MOS) device, forming reverse memory posts over the metallic layer, and etching the metallic layer using the reverse memory posts as an etching mask. The remaining portions of the metallic layer include a gate contact plug and a source/drain contact plug. The reverse memory posts are then removed. After the gate contact plug and the source/drain contact plug are formed, an Inter-Level Dielectric (ILD) is formed to surround the gate contact plug and the source/drain contact plug. | 2017-01-26 |
20170025310 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is provided. The method includes forming of an interlayer insulating film on a semiconductor substrate; etching the interlayer insulating film to form a contact hole and an alignment hole wider than the contact hole; depositing a first metal layer having a thickness thicker than a half of the width of the contact hole and thinner than a half of the width of the alignment hole; etching the first metal layer so that a bottom surface of the alignment hole are exposed and the first metal layer remains covering a bottom surface of the contact hole; treating the semiconductor substrate based on the position of the alignment hole; and cutting a part of the semiconductor substrate including the alignment hole to divide a semiconductor device having the contact hole from the semiconductor substrate. | 2017-01-26 |
20170025311 | Method and Apparatus for Plasma Dicing a Semi-conductor Wafer - The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a clamping electrode for electrostatically clamping the work piece to the work piece support; providing a mechanical partition between the plasma source and the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma. | 2017-01-26 |
20170025312 | FinFETs with Multiple Threshold Voltages - A device includes a substrate, a semiconductor fin over the substrate, and a gate dielectric layer on a top surface and sidewalls of the semiconductor fin. A gate electrode is spaced apart from the semiconductor fin by the gate dielectric layer. The gate electrode includes a top portion over and aligned to the semiconductor fin, and a sidewall portion on a sidewall portion of the dielectric layer. The top portion of the gate electrode has a first work function, and the sidewall portion of the gate electrode has a second work function different from the first work function. | 2017-01-26 |
20170025313 | Method and Structure for FinFET Device - The present disclosure provides a method, which includes forming a first fin structure and a second fin structure over a substrate, which has a first trench positioned between the first and second fin structures. The method also includes forming a first dielectric layer within the first trench, recessing the first dielectric layer to expose a portion of the first fin structure, forming a first capping layer over the exposed portion of the first fin structure and the recessed first dielectric layer in the first trench, forming a second dielectric layer over the first capping layer in the first trench while the first capping layer covers the exposed portion of the first fin feature and removing the first capping layer from the first fin structure. | 2017-01-26 |
20170025314 | SEMICONDUCTOR DEVICES COMPRISING MULTIPLE CHANNELS AND METHOD OF MAKING SAME - The disclosed technology generally relates to semiconductor devices, and more particularly to transistor devices comprising multiple channels. In one aspect, a method of fabricating a transistor device comprises forming on the substrate a plurality of vertically repeating layer stacks each comprising a first layer, a second layer and a third layer stacked in a predetermined order, wherein each of the first, second and third layers is formed of silicon, silicon germanium or germanium and has a different germanium concentration compared to the other two of the first, second and third layers. The method additionally includes selectively removing the first layer with respect to the second and third layers from each of the layer stacks, such that a gap interposed between the second layer and the third layer is formed in each of the layer stacks. The method further includes selectively removing the second layer from each of the layer stacks with respect to the third layer, wherein removing the second layer comprises at least partially removing the second layer through the gap, thereby defining the channels comprising a plurality of vertically arranged third layers. | 2017-01-26 |
20170025315 | METHODS AND STRUCTURE TO FORM HIGH K METAL GATE STACK WITH SINGLE WORK-FUNCTION METAL - A method for forming a replacement metal gate structure sharing a single work function metal for both the N-FET and the P-FET gates. The method oppositely dopes a high-k material of the N-FET and P-FET gate, respectively, using a single lithography step. The doping allows use of a single work function metal which in turn provides more space in the metal gate opening so that a bulk fill material may occupy more volume of the opening resulting in a lower resistance gate. | 2017-01-26 |
20170025316 | METHOD FOR DETERMINING A BONDING CONNECTION IN A COMPONENT ARRANGEMENT AND TEST APPARATUS - The application relates to a method for determining a bonding connection ( | 2017-01-26 |
20170025317 | X-RAY INSPECTION APPARATUS - An x-ray inspection system including a cabinet containing an x-ray source, a sample support for supporting a sample to be inspected, and an x-ray detector; an air mover configured to force air into the cabinet through an air inlet above the sample support, where the air mover and cabinet are configured to force air through the cabinet from the air inlet past the sample support to an air outlet in the cabinet below the sample support, and an assembly for positioning the sample support relative to the x-ray source and x-ray detector. The sample support includes an upper surface extending in a horizontal plane and the sample positioning assembly includes a vertical positioning mechanism for moving the sample support in a vertical direction, orthogonal to the horizontal plane, and a first horizontal positioning mechanism for moving the sample support and vertical positioning mechanism in a first horizontal direction. | 2017-01-26 |
20170025318 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - This invention enhances reliability of an electrical test. A semiconductor device manufacturing method in which a potential (first potential) is supplied by bringing a plurality of first and second test terminals into contact with a plurality of leads, respectively in the step of supplying the potential to the leads (first leads) to carry out the electrical test. The first test terminals come into contact with the leads, individually, and the second test terminals come into contact with the leads in one batch. | 2017-01-26 |
20170025319 | Robust High Performance Semiconductor Package - A semiconductor package includes a suspended substrate having one or more semiconductor devices thereon, a metallic case covering the suspended substrate, the suspended substrate being supported by a plurality of mechanical leads on opposing sides of the semiconductor package, at least one of the plurality of mechanical leads having a coefficient of thermal expansion (CTE) that substantially matches a CTE of the suspended substrate, where at least one of the plurality of mechanical leads is electrically connected to the suspended substrate, and where the plurality of mechanical leads absorb mechanical shocks so as to prevent damage to the semiconductor package. The semiconductor package also includes a thermal gel between the suspended substrate and the metallic case. The suspended substrate can be a printed circuit board. The metallic case includes mounting ears for transferring heat away from the semiconductor package. | 2017-01-26 |
20170025320 | RESIN-ENCAPSULATD SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A first resin encapsulated body ( | 2017-01-26 |
20170025321 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - In a method for manufacturing a semiconductor device, a resin layer including an inorganic filler is molded on a surface of a substrate which includes semiconductor elements attached thereto by an adhesive, and terminals electrically connected to the semiconductor elements on another surface thereof. The molded substrate is cut so as to expose a conductive body electrically connected to an external terminal maintainable at ground potential. The surface of the resin layer of the substrate is sputter-etched in a vacuum environment, in a state where a plurality of the cut substrates is provided in a tray so that the surface of the substrate faces the tray. A metal layer is sputtered so as to be electrically connected to the conductive body on the surface and the cut surface in a state where the substrate is provided in the tray while maintaining the vacuum environment after sputter-etching. | 2017-01-26 |
20170025322 | FAN-OUT WAFER LEVEL PACKAGING STRUCTURE - A semiconductor device includes a first die including a first pad and a first passivation layer, a second die including a second pad and a second passivation layer, and an encapsulant surrounding the first die and the second die. Surfaces of the first die are not coplanar with corresponding surfaces of the second die. A dielectric layer covers at least portions of the first passivation layer and the second passivation layer, and further covers the encapsulant between the first die and the second die. The encapsulant has a first surface. The dielectric layer has a second surface adjacent to the first passivation layer, the second passivation layer and the encapsulant, and further has a third surface opposite the second surface. The semiconductor device further includes a redistribution layer electrically connected to the first pad and the second pad and disposed above the third surface of the dielectric layer. | 2017-01-26 |
20170025323 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A bonding member is a member shaped in a sheet and made of electrically-insulating resin. A semiconductor module includes a heatsink and a cooler that are electrically insulated from each other by the bonding member. The bonding member includes a central portion and a peripheral portion. A heat conductivity in a normal direction of the central portion is greater than a heat conductivity in the normal direction of the peripheral portion. Further, a heat conductivity in a surface direction of the peripheral portion is greater than a heat conductivity in the surface direction of the central portion. Further, the heat conductivity in the normal direction of the central portion is greater than the heat conductivity in the surface direction of the central portion. | 2017-01-26 |
20170025324 | THIN FILM CAPACITOR AND SEMICONDUCTOR DEVICE - The present invention provides a thin film capacitor including a first electrode layer, a second electrode layer, and a dielectric layer provided between the first electrode layer and the second electrode layer, wherein a ratio (S/S | 2017-01-26 |
20170025325 | SEMICONDUCTOR PACKAGE WITH AN ENHANCED THERMAL PAD - A semiconductor package having a substrate, a thermal pad, and a semiconductor die is disclosed. The thermal pad may have a heat conductive body extending through the substrate. The semiconductor die may be disposed on the thermal pad and in thermal communication with the thermal pad. The thermal pad of the semiconductor package may also have an interlock structure. The interlock structure may provide a mechanical interlock between the thermal pad and the substrate. In addition, a wireless communication device is also disclosed. | 2017-01-26 |
20170025326 | ELECTRONIC PART COOLER - A cooler with a cooler main body that, in one configuration, includes a first wall portion forming a cooling surface that cools an electronic component, a second wall portion disposed opposing the first wall portion, and a side wall portion that connects a periphery of the first wall portion and a periphery of the second wall portion. In the configuration, cooling fins are attached to an inner wall surface of the first wall portion, a refrigerant introduction pipe and refrigerant introduction flow path for supplying refrigerant to the cooling fins and a refrigerant discharge pipe and refrigerant discharge flow path for ejecting refrigerant from the cooling fins are included, and protruding portions and are provided on the first wall portion side of the refrigerant introduction flow path. | 2017-01-26 |
20170025327 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - In accordance with an embodiment, a semiconductor component includes a support having first and second device receiving structures. A semiconductor device configured from a III-N semiconductor material is coupled to the support, wherein the semiconductor device has opposing surfaces. A first bond pad extends from a first portion of the first surface, a second bond pad extends from a second portion of the first surface, and a third bond pad extends from a third portion of the first surface. The first bond pad is coupled to the first device receiving portion, the drain bond pad is coupled to the second device receiving portion, and the third bond pad is coupled to the third lead. In accordance with another embodiment, a method includes coupling a semiconductor chip comprising a III-N semiconductor substrate material to a support. | 2017-01-26 |
20170025328 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - In accordance with an embodiment, a semiconductor component includes a support having a side in which a device receiving structure and an interconnect structure are formed and a side from which a plurality of leads extends. A semiconductor device having a control terminal and first and second current carrying terminals and configured from a III-N semiconductor material is mounted to the device receiving structure. The control terminal of the first electrical interconnect is coupled to a first lead by a first electrical interconnect. A second electrical interconnect is coupled between the first current carrying terminal of the semiconductor device and a second lead. The second current carrying terminal of the first semiconductor device is coupled to the device receiving structure or to the interconnect structure. | 2017-01-26 |
20170025329 | LEAD FRAME AND METHOD FOR MANUFACTURING SAME - Provided is a lead frame including: one or more solder bonding regions containing copper material or copper plating; and a molding resin adhesion region containing a copper oxide film. The solder bonding regions are exposed on a surface of the lead frame. Further, provided is a lead frame manufacturing method including: forming a resist film in a molding resin adhesion region that is included in a surface of a lead frame member made of copper, or that is included in a surface of a copper-plated lead frame member; forming a plating film by performing a metal plating process on one or more solder bonding regions included in the surface of the lead frame member; removing the resist film; and forming a copper oxide film by oxidizing the molding resin adhesion region. | 2017-01-26 |
20170025330 | SEMICONDUCTOR DEVICE - A semiconductor device includes a center semiconductor chip with a plurality of die pads, a plurality of lead frames, and a plurality of connecting components. The lead frame encapsulates the center semiconductor chip. Each connecting components establishes an electrical connection between the center semiconductor chip and the lead frame. At least one of the center semiconductor chip, the lead frame, and the connecting component forms an indicator. | 2017-01-26 |
20170025331 | LEAD FRAME, SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING LEAD FRAME, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A lead frame according to one embodiment includes a lead part including an inner lead and an outer lead connected to the inner lead, and a frame unit supporting the lead part. The inner lead has a terminal portion having a facing surface and a back surface in the opposite side from the facing surface. The facing surface faces a conductive pattern of a wiring board. An outer region of the terminal portion is provided with a solder thickness ensuring portion where the facing surface is depressed toward the back surface | 2017-01-26 |
20170025332 | Flippable Leadframe for Packaged Electronic System Having Vertically Stacked Chips and Components - A leadframe ( | 2017-01-26 |
20170025333 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - In accordance with an embodiment, a semiconductor component includes a support having a first device receiving structure, a second device receiving structure, a first lead, a second lead, and a third lead. A first semiconductor chip is coupled to the first device receiving structure and a second semiconductor chip is coupled to the first semiconductor chip and the second device receiving structure. The first semiconductor chip is configured from a silicon semiconductor material and has a gate bond pad, a source bond pad, and a drain bond pad, and the second semiconductor chip is configured from a gallium nitride semiconductor chip and has a gate bond pad, a source bond pad, and a drain bond pad. In accordance with another embodiment, a method for manufacturing a semiconductor component includes coupling a first semiconductor chip to a support and coupling a second semiconductor chip to the support. | 2017-01-26 |
20170025334 | HEATSINK VERY-THIN QUAD FLAT NO-LEADS (HVQFN) PACKAGE - Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device having enhanced heat dissipation. The method comprises providing a lead frame array, of a first thickness, with a plurality of die placement areas each die placement area with bond pad landings, the bond bad landings situated about a die placement area on one or multiple sides, the bond pad landings having upper surfaces and opposite lower surfaces, placing a heat sink assembly of a second thickness, having at least two mounting tabs of the first thickness, in each die placement area and attaching the at least two mounting tabs onto corresponding bond pad landings serving as anchor pads, die bonding a device die on the heat sink device assembly, conductively bonding device die bond pads to corresponding bond pad landings, and encapsulating the wire bonded device die, heat sink assembly and lead frame array in a molding compound. | 2017-01-26 |
20170025335 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - In accordance with an embodiment, a semiconductor component is provided that includes a leadframe having a device receiving area, one or more leadframe leads and at least one insulated metal substrate bonded to a first portion of the device receiving area. A first semiconductor device is mounted to a first insulated metal substrate, the first semiconductor device configured from a III-N semiconductor material. A first electrical interconnect is coupled between the first current carrying terminal of the first semiconductor device and a second portion of the die receiving area. In accordance with another embodiment, method includes providing a first semiconductor chip comprising a III-N semiconductor substrate material and a second semiconductor chip comprising a silicon based semiconductor substrate. The first semiconductor chip is mounted on a first substrate and the second semiconductor chip on a second substrate. The first semiconductor chip is electrically coupled to the second semiconductor chip. | 2017-01-26 |
20170025336 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - In accordance with an embodiment, a semiconductor component includes a support having a first device receiving structure and a second device receiving structure and a contact extension that is common to the first and second device receiving structures. The first device receiving structure includes a device receiving area and the second device receiving structure includes a drain contact area. A III-N based semiconductor chip has a drain bond pad bonded to the drain contact area and a source bond pad bonded to the contact extension and a gate bond pad bonded to an interconnect. A portion of the silicon based semiconductor chip is bonded to the support device receiving area. In accordance with another embodiment, a method for manufacturing the semiconductor component includes coupling a III-N based semiconductor chip to a portion of the support a silicon based semiconductor chip to another portion of the support. | 2017-01-26 |
20170025337 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - In accordance with an embodiment, a semiconductor component includes a support and a plurality of leads. An insulated metal substrate having a first portion and a second portion bonded to the support. A semiconductor chip comprising a III-N semiconductor material is bonded to the first portion of the insulated metal substrate and a first electrical interconnect is coupled between a drain bond pad the first portion of the insulated metal substrate. A second semiconductor chip is bonded to the first electrical interconnect. A second electrical interconnect coupled between a lead of the plurality of leads and the second semiconductor chip. In accordance with another embodiment, a method of manufacturing a semiconductor component includes coupling a first semiconductor chip to a first electrically conductive layer and coupling a second semiconductor chip to a second electrically conductive layer. | 2017-01-26 |
20170025338 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - In accordance with an embodiment, a semiconductor component includes a support having first and second device receiving structures. A semiconductor device configured from a III-N semiconductor material is coupled to the support, wherein the semiconductor device has opposing surfaces. A first bond pad extends from a first portion of the first surface, a second bond pad extends from a second portion of the first surface, and a third bond pad extends from a third portion of the first surface. The first bond pad is coupled to the first device receiving portion, the drain bond pad is coupled to the second device receiving portion, and the third bond pad is coupled to the third lead. In accordance with another embodiment, a method includes coupling a semiconductor chip comprising a III-N semiconductor substrate material to a support. | 2017-01-26 |
20170025339 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component includes a support having a lead integrally formed thereto. An insulated metal substrate is mounted to a surface of the support and a semiconductor chip is mounted to the insulated metal substrate. A III-N based semiconductor chip is mounted to the insulated metal substrate, where the III-N based semiconductor chip has a gate bond pad, a drain bond pad, and a source bond pad. A silicon based semiconductor chip is mounted to the III-N based semiconductor chip. In accordance with an embodiment the silicon based semiconductor chip includes a device having a gate bond pad, a drain bond pad, and a source bond pad. The drain bond pad of the III-N based semiconductor chip may be bonded to the substrate or to a lead. In accordance with another embodiment, the silicon based semiconductor chip is a diode. | 2017-01-26 |
20170025340 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - In accordance with an embodiment, a semiconductor component includes a support having a first device receiving structure, a second device receiving structure, a first lead and a second lead. A first semiconductor chip is coupled to the first device receiving structure and a second semiconductor chip is coupled to the first semiconductor chip and the second device receiving structure. The first semiconductor chip is configured from a silicon semiconductor material and has a gate bond pad, a source bond pad, and a drain bond pad, and the second semiconductor chip is configured from a gallium nitride semiconductor chip and has a gate bond pad, a source bond pad, and a drain bond pad. In accordance with another embodiment, a method for manufacturing a semiconductor component includes coupling a first semiconductor chip to a support and coupling a second semiconductor chip to the support. | 2017-01-26 |
20170025341 | METHODS AND APPARATUS FOR PROVIDING AN INTERPOSER FOR INTERCONNECTING SEMICONDUCTOR CHIPS - Methods and apparatus are provide for an interposer for interconnecting one or more semiconductor chips with an organic substrate in a semiconductor package, the interposer including: a first glass substrate having first and second opposing major surfaces, the first glass substrate having a first coefficient of thermal expansion (CTE1); a second glass substrate having first and second opposing major surfaces, the second glass substrate having a second coefficient of thermal expansion (CTE2); and an interface disposed between the first and second glass substrates and joining the second major surface of the first glass substrate to the first major surface of the second glass substrate, where CTE1 is less than CTE2, the first major surface of the first glass substrate operates to engage the one or more semiconductor chips, and the second major surface of the second glass substrate operates to engage the organic substrate. | 2017-01-26 |
20170025342 | CHIP PACKAGE STRUCTURE - A chip package structure including a molding compound, a carrier board, a chip, a plurality of conductive pillars and a circuit board is provided. The carrier board includes a substrate and a redistribution layer. The substrate has a first surface and a second surface. The redistribution layer is disposed on the first surface. The chip and the conductive pillars are disposed on the redistribution layer. The molding compound covers the chip, the conductive pillars, and the redistribution layer. The circuit board is connected with the carrier board, wherein the circuit board is disposed on the molding compound, such that the chip is located between the substrate and the circuit board, and the chip and the redistribution layer are electrically connected with the circuit board through the conductive pillars. Heat generated by the chip is transmitted through the substrate from the first surface to the second surface to dissipate. | 2017-01-26 |
20170025343 | CIRCUIT SUBSTRATE, SEMICONDUCTOR PACKAGE AND PROCESS FOR FABRICATING THE SAME - A circuit substrate has the following elements. A stacked circuit structure has a first surface and a second surface opposite thereto surface. A first patterned inner conductive layer is disposed on the first surface and has multiple pads. A first patterned outer conductive layer is disposed on the patterned inner conductive layer and has multiple conductive pillars, wherein each of the first conductive pillar is located on the corresponding first pad. The first dielectric layer covers the first surface, the first patterned inner conductive layer and the first patterned outer conductive layer, and has multiple first concaves, wherein the first concave exposes the top and side of the corresponding first conductive pillar. A semiconductor package structure applied the above circuit substrate and a process for fabricating the same are also provided here. | 2017-01-26 |
20170025344 | SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING SEMICONDUCTOR MODULE - A semiconductor module includes an insulated circuit board that includes an insulating substrate, a first conductive plate arranged on a first principal surface of the insulating substrate and within the outer edges of the insulating substrate, and a second conductive plate arranged within the outer edges of the insulating substrate on a second principal surface of the insulating substrate that faces the first principal surface. Furthermore, boundary edges between the first principal surface of the insulating substrate and the side faces of the first conductive plate are covered by an ion gel that contains an ionic liquid. | 2017-01-26 |
20170025345 | VIA PATTERN TO REDUCE CROSSTALK BETWEEN DIFFERENTIAL SIGNAL PAIRS - An integrated circuit (IC) system includes an IC coupled to a package. The package, in turn, is coupled to a ball grid array. The integrated circuit is electrically coupled to the ball grid array by a plurality of package through-hole (PTH) vias that penetrate through the package. Each PTH via includes a conductive element associated with a differential signaling pair. The conductive elements within a given differential signaling pair are disposed in the package at specific locations, relative to other conductive elements in other differential signaling pairs, to reduce crosstalk between those differential signaling pairs. At least one advantage of technique described herein is that the conductive elements within the package can be densely packed together without inducing excessive crosstalk. Therefore, the package can support a large number of differential signaling pairs, allowing high-throughput data communication. | 2017-01-26 |
20170025346 | Method for Interconnect Scheme - A method of fabricating a semiconductor device is disclosed. The method includes forming a first dielectric layer over a substrate, forming a first trench in the first dielectric layer, forming a metal line in the first trench, removing a first portion of the metal line to form a second trench and removing a second portion of the metal line to form a third trench. A third portion of the metal line is disposed between the second and third trenches. The method also includes forming a second dielectric layer in the second and third trenches. | 2017-01-26 |
20170025347 | METHODS AND STRUCTURES FOR BACK END OF LINE INTEGRATION - Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions. | 2017-01-26 |
20170025348 | APPARATUSES INCLUDING STAIR-STEP STRUCTURES AND METHODS OF FORMING THE SAME - Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from of the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. Apparatuses such as memory devices including laterally adjacent first and second regions each of which including contact regions of a different portion of a plurality of conductive materials and related methods of forming such devices are also disclosed. | 2017-01-26 |
20170025349 | SEMICONDUCTOR WAFERS WITH THROUGH SUBSTRATE VIAS AND BACK METAL, AND METHODS OF FABRICATION THEREOF - An embodiment of a semiconductor wafer includes a semiconductor substrate, a plurality of through substrate vias (TSVs), and a conductive layer. The TSVs extend between first and second substrate surfaces. The TSVs include a first subset of trench via(s) each having a primary axis aligned in a first direction, and a second subset of trench via(s) each having a primary axis aligned in a second and different direction. The TSVs form an alignment pattern in an alignment area of the substrate. The conductive layer is directly connected to the second substrate surface and to first ends of the TSVs. Using the TSVs for alignment, the conductive layer may be patterned so that a portion of the conductive layer is directly coupled to the TSVs, and so that the conductive layer includes at least one conductive material void (e.g., in alignment with a passive component at the first substrate surface). | 2017-01-26 |
20170025350 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device according to an embodiment includes: a pair of insulating members separated from each other, the pair of insulating members extending in a first direction; a plurality of electrode films and a plurality of inter-layer insulating films disposed between the pair of insulating members and stacked alternately along a second direction, the second direction intersecting the first direction; a plurality of semiconductor pillars extending in the second direction and piercing the plurality of electrode films and the plurality of inter-layer insulating films; and a charge storage film disposed between one of the semiconductor pillars and one of the electrode films. An end portion on one of the insulating members side of a first electrode film of the electrode films is thicker than a central portion of the first electrode film between the pair of insulating members. | 2017-01-26 |
20170025351 | SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA COVERED BY A SOLDER BALL - The semiconductor device comprises a semiconductor substrate ( | 2017-01-26 |
20170025352 | ANTIFUSE STRUCTURES AND METHODS OF MAKING SAME - An antifuse structure includes a first electrode layer, an inter-metal dielectric layer over the first electrode layer, and a via in the inter-metal dielectric layer. The via penetrates through the inter-metal dielectric layer exposing a portion of the first electrode layer. An antifuse layer is deposited in the via and over the portion of the first electrode layer. A second electrode is disposed in the via and over the antifuse layer. An interconnect layer may be deposited over the inter-metal dielectric layer and in electrical contact with the second electrode in the via. | 2017-01-26 |
20170025353 | INTEGRATED CIRCUIT - An integrated circuit according to an embodiment includes: an anti-fuse element including a first terminal and a second terminal; a fuse element including a third terminal connected to the second terminal, and a fourth terminal; a first wiring line connected to the first terminal of the anti-fuse element; and a drive circuit configured to supply a plurality of potentials to the first terminal of the anti-fuse element, the drive circuit being connected to the first wiring line, the potentials being different from each other. | 2017-01-26 |
20170025354 | Contact Plug Extension for Bit Line Connection - An integrated circuit connection structure includes a contact plug extending vertically in a first dielectric, a conductive line formed of a metal extending horizontally in the first dielectric, and a contact plug extension that extends between a top surface of the contact plug and the conductive line. The plug extension is formed of the metal, has a bottom surface that lies in contact with the top surface of the contact plug, and is bounded on at least one side by a portion of a second dielectric material. | 2017-01-26 |
20170025355 | METHODS OF FORMING UNDER DEVICE INTERCONNECT STRUCTURES - Methods of forming microelectronic interconnect under device structures are described. Those methods and structures may include forming a device layer in a first substrate, forming at least one routing layer in a second substrate, and then coupling the first substrate with the second substrate, wherein the first substrate is bonded to the second substrate. | 2017-01-26 |
20170025356 | METHOD AND STRUCTURE FOR WAFER LEVEL PACKAGING WITH LARGE CONTACT AREA - A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the first packaging layer thickness to expose the second packaging layer filling the grooves and forming a plurality of contact pads overlaying the first packaging layer thereafter cutting through the second packaging layer in the grooves to form individual package. | 2017-01-26 |
20170025357 | Semiconductor Chip Having a Dense Arrangement of Contact Terminals - A semiconductor chip includes a semiconductor body having an active device region, one or more metallization layers insulated from the semiconductor body and configured to carry one or more of ground, power and signals to the active device region, and a plurality of contact terminals formed in or disposed on an outermost one of the metallization layers and configured to provide external electrical access to the semiconductor chip. A minimum distance between adjacent ones of the contact terminals is defined for the semiconductor chip. One or more groups of adjacent ones of the contact terminals have an electrical or functional commonality and a pitch less than the defined minimum distance. A single shared solder joint can connect two or more of the contact terminals of the semiconductor chip to one or more of contact terminals of a substrate such as a circuit board, an interposer or another semiconductor chip. | 2017-01-26 |
20170025358 | MULTI-LAYER SUBSTRATE WITH AN EMBEDDED DIE - The present disclosure relates to a multi-layer substrate structure with an embedded die to miniaturize designs and improve performance. The multi-layer substrate structure includes a core layer having a cavity and a die mounted within the cavity. The die has a die body, a die conductive element on a top surface of the die body, and a dielectric layer over the die conductive element. The multi-layer substrate structure also includes a substrate conductive element formed over a portion of a top surface of the core layer and extending over at least a portion of the die conductive element. Overlapping portions of the die conductive element and the substrate conductive element are separated by the dielectric layer and form an electronic component. | 2017-01-26 |
20170025359 | Fan-out POP Structure with Inconsecutive Polymer Layer - A package includes a device die, a molding material molding at least a portion of the device die therein, and a through-via substantially penetrating through the molding material. The package further includes a dielectric layer contacting the through-via and the molding material, and a die attach film attached to a backside of the device die. The die attach film includes a portion extending in the dielectric layer. | 2017-01-26 |
20170025360 | SEMICONDUCTOR INTERCONNECT STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor interconnect structure and a manufacturing method thereof are provided. The semiconductor interconnect structure includes a barrier metal layer, a copper metal layer, and a compound thin film. The barrier metal layer is formed on an interconnect trench, the copper metal layer is formed on the barrier metal layer, and the compound thin film is formed on a surface of the copper metal layer, wherein the compound thin film contains organocopper and amorphous carbon. Therefore, the resulting semiconductor interconnect structure has reduced resistivity. | 2017-01-26 |
20170025361 | SELF SHIELDED SYSTEM IN PACKAGE (SiP) MODULES - A system in package (SiP) is disclosed that uses an EMI shield to inhibit EMI or other electrical interference on the components within the SiP. A metal shield may be formed over the SiP. The metal shield may be electrically coupled to a ground layer in a printed circuit board (PCB) to form the EMI shield around the SiP. The substrate of the SiP may include at least some metallization along vertical walls in the end portions of the substrate. The metallization may provide a large contact area for coupling the metal shield to a ground ring coupled to the ground layer in the PCB. The metallization along the vertical walls in the end portions of the substrate may be formed as through-metal vias in a common substrate before singulation to form the SiP. | 2017-01-26 |
20170025362 | SHIELDED MODULE HAVING COMPRESSION OVERMOLD - A method for fabricating a radio-frequency (RF) module is disclosed, the method including forming or providing a first assembly that includes a packaging substrate and an RF component mounted thereon, the first assembly further including one or more shielding-wirebonds formed relative to the RF component, and forming an overmold over the packaging substrate to substantially encapsulate the RF component and the one or more shielding-wirebonds, the overmold formed by compression molding that includes reducing a volume of melted resin in a direction having a component perpendicular to a plane defined by the packaging substrate. | 2017-01-26 |
20170025363 | SEMICONDUCTOR DEVICE PACKAGE INTEGRATED WITH COIL FOR WIRELESS CHARGING AND ELECTROMAGNETIC INTERFERENCE SHIELDING, AND METHOD OF MANUFACTURING THE SAME - The present disclosure relates to a semiconductor device package which includes a carrier, an electronic component disposed on the carrier, and a package body disposed on the carrier and encapsulating the electronic component. A shield is disposed on the package body. The shield includes multiple non-magnetic conductive layers, multiple insulating layers and multiple magnetic conductive layers. At least one of the insulating layers is located between each non-magnetic conductive layer and a neighboring magnetic conductive layer. | 2017-01-26 |
20170025364 | Electric Magnetic Shielding Structure in Packages - A package includes a device die, a molding material molding the device die therein, and a through-via penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via. A metal ring is close to edges of the package, wherein the metal ring is coplanar with the redistribution line. | 2017-01-26 |
20170025365 | SELF-DESTRUCTING CHIP - Embodiments herein provide for a self-destructing chip including at least a first die and a second die. The first die includes an electronic circuit, and the second die is composed of one or more polymers that disintegrates at a first temperature. The second die defines a plurality of chambers, wherein a first subset of the chambers contain a material that reacts with oxygen in an exothermic manner. A second subset of the chambers contain an etchant to etch materials of the first die. In response to a trigger event, the electronic circuit is configured to expose the material in the first subset of chambers to oxygen in order to heat the second die to at least the first temperature, and is configured to release the etchant from the second subset of the chambers to etch the first die. | 2017-01-26 |
20170025366 | DEVICE FOR PREVENTION OF INTEGRATED CIRCUIT CHIP COUNTERFEITING - A timer including a sensor and a radiation source is used to prevent counterfeiting of integrated circuits. The timer confirms the date code of the integrated circuit resulting in a more secure supply chain. | 2017-01-26 |
20170025367 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes an integrated circuit and a guard ring. The integrated circuit includes a first circuit and a second circuit separated from the first circuit. The guard ring is disposed around the first circuit and between the first circuit and the second circuit. The guard ring includes an outer ring, an inner ring, and two connectors. The outer ring is disposed around the first circuit and has a first gap. The inner ring is disposed between the outer ring and the first circuit and has a second gap. The two connectors connect the outer ring and the inner ring. The outer ring, the inner ring, and the two connectors form a closed loop. | 2017-01-26 |