04th week of 2010 patent applcation highlights part 14 |
Patent application number | Title | Published |
20100019231 | Organic Electronic Device - This invention generally relates to organic electronic devices and to methods for their fabrication. More particularly we will describe organic thin film transistor (TFT) structures and their fabrication. | 2010-01-28 |
20100019232 | ORGANIC LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a method of manufacturing an organic light emitting device. The method includes forming an electron injection layer by vacuum co-depositing an organic semiconductor material having an electron mobility of about 1×10 | 2010-01-28 |
20100019233 | SEMICONDUCTOR COMPOSITE FILM, METHOD FOR FORMING SEMICONDUCTOR COMPOSITE FILM, THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING THIN FILM TRANSISTOR, AND ELECTRONIC APPARATUS - A semiconductor composite film includes a semiconductor thin film layer containing an organic semiconductor material, an insulating thin film layer formed from a polymer material phase-separated from the organic semiconductor material in the film thickness direction, and a fine particle material dispersed in at least one of the semiconductor thin film layer and the insulating thin film layer. | 2010-01-28 |
20100019234 | ORGANIC THIN FILM TRANSISTOR AND ORGANIC THIN FILM LIGHT EMITTING TRANSISTOR - An organic thin film transistor including a substrate having thereon at least three terminals of a gate electrode, a source electrode and a drain electrode, an insulator layer and an organic semiconductor layer, with a current between a source and a drain being controlled upon application of a voltage to the gate electrode, wherein the organic semiconductor layer includes a specified organic compound having an aromatic heterocyclic group in the center thereof; and an organic thin film light emitting transistor utilizing an organic thin film transistor, wherein the organic thin film transistor is one in which light emission is obtained utilizing a current flowing between the source and the drain, and the light emission is controlled upon application of a voltage to the gate electrode, and is made high with respect to the response speed and has a large ON/OFF ratio, are provided. | 2010-01-28 |
20100019235 | ORGANIC ELECTROLUMINESCENCE ELEMENT AND PRODUCTION METHOD THEREOF - A method of producing an organic EL element that allows easier patterning of the organic EL layer and reduction of the damage of the electrode layer caused by the organic EL layer and is superior in emission characteristics. Also provided is an organic electroluminescence element, including a substrate, a first electrode layer, a wettability variable layer, an organic EL layer, and a second electrode layer sequentially laminated. The wettability variable layer changes its wettability under the action of a photocatalyst caused by energy irradiation, is inactive to the energy, and has on the surface, a wettability variable pattern having an organopolysiloxane-containing lyophilic region and a liquid repellent region containing a fluorine-containing organopolysiloxane. | 2010-01-28 |
20100019236 | ORGANIC LIGHT EMITTING DEVICE - It is an object of the present invention to provide an organic light emitting device having a long-life optical output. The organic light emitting device according to the present invention is provided with an emission layer including at least a host material, a light emitting material, and another material, wherein the another material has a smaller ionization potential than and almost the same hole mobility as or a greater hole mobility than an ionization potential and a hole mobility of a compound which forms an emission layer-side-interface. | 2010-01-28 |
20100019237 | Siloxane-Polymer Dielectric Compositions and Related Organic Field-Effect Transistors - Dielectric compositions comprising siloxane and polymeric components, as can be used in a range of transistor and related device configurations. | 2010-01-28 |
20100019238 | HYDRAZINE-FREE SOLUTION DEPOSITION OF CHALCOGENIDE FILMS - A method of depositing a film of a metal chalcogenide including the steps of: contacting an isolated hydrazinium-based precursor of a metal chalcogenide and a solvent having therein a solubilizing additive to form a solution of a complex thereof; applying the solution of the complex onto a substrate to produce a coating of the solution on the substrate; removing the solvent from the coating to produce a film of the complex on the substrate; and thereafter annealing the film of the complex to produce a metal chalcogenide film on the substrate. Also provided is a process for preparing an isolated hydrazinium-based precursor of a metal chalcogenide as well as a thin-film field-effect transistor device using the metal chalcogenides as the channel layer. | 2010-01-28 |
20100019239 | METHOD OF FABRICATING ZTO THIN FILM, THIN FILM TRANSISTOR EMPLOYING THE SAME, AND METHOD OF FABRICATING THIN FILM TRANSISTOR - Provided are a method of fabricating a zinc-tin-oxide (ZTO) thin film, a thin film transistor employing the same, and a method of fabricating a thin film transistor. The method of fabricating a ZTO thin film includes depositing zinc oxide and tin oxide at a deposition temperature of 450° C. or lower so that a zinc-to-tin atomic ratio is 4:1 or greater, to form an amorphous ZTO thin film. In the thin film transistor, the ZTO thin film is used as a channel layer. | 2010-01-28 |
20100019240 | RESISTIVE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A resistive memory device includes: a bottom electrode formed over a substrate; and an insulation layer having a hole structure formed over the substrate structure. Herein, the hole structure exposes the bottom electrode, has sidewalls of positive slope, and has a bottom width equal to or smaller than a width of the bottom electrode; a resistive layer formed over the hole structure; and an upper electrode formed over the resistive layer. | 2010-01-28 |
20100019241 | SEMICONDUCTOR DEVICE, FABRICATION METHOD THEREOF, AND PHOTOMASK - There is provided a semiconductor device including a wafer and a focus monitoring pattern formed on the wafer. The focus monitoring pattern has at least one pair of first and second patterns. The first pattern has an unexposed region surrounded by an exposed region and the second pattern has an exposed region surrounded by an unexposed region. In addition, the present invention provides a method of fabricating a semiconductor device comprising the steps of forming at least one pair of first and second patterns on a wafer. The first pattern has an unexposed region surrounded by an exposed region and the second pattern has an exposed region surrounded by an unexposed region. The method further comprises checking a focusing condition on exposure by measuring widths of the first and second patterns formed on the wafer. | 2010-01-28 |
20100019242 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF, SOI SUBSTRATE AND DISPLAY DEVICE USING THE SAME, AND MANUFACTURING METHOD OF THE SOI SUBSTRATE - A polycrystalline Si thin film and a single crystal Si thin film are formed on an SiO | 2010-01-28 |
20100019243 | THIN FILM TRANSISTOR SUBSTRATE, ELECTRONIC APPARATUS, AND METHODS FOR FABRICATING THE SAME - A TFT substrate includes a substrate and at least a TFT disposed thereon. The TFT includes a semiconductor island and at least a gate. The semiconductor island has a source region, a drain region, and a channel region interposed therebetween. The semiconductor island has sub-grain boundaries. The gate corresponds to the channel region. A first included angle between an extending direction of the gate and a line connecting the centroid of the source region with the centroid of the drain region is not substantially equal to 90 degrees. A second included angle between the sub-grain boundaries in the channel region and the line connecting the centroid of the source region with the centroid of the drain region is not substantially equal to 0 degree or 90 degrees. Additionally, a method of fabricating a TFT substrate, an electronic apparatus, and a method of fabricating the electronic apparatus are also provided. | 2010-01-28 |
20100019244 | METHOD FOR FABRICATING THIN FILM PATTERN, LIQUID CRYSTAL DISPLAY PANEL AND METHOD FOR FABRICATING THEREOF USING THE SAME - A method of fabricating a thin film pattern according to an embodiment of the present invention comprises forming an organic material pattern on a substrate, forming a metal material of liquid phase on a substrate provided with the organic material pattern, hardening the metal material of liquid phase, and removing the metal material located on the organic material pattern, allowing some metal material to be left at an area non-overlapped with the organic material pattern. | 2010-01-28 |
20100019245 | LIGHT EMITTING DEVICE - The invention provides a light emitting device which is capable of displaying on both sides, has a small volume, and is capable of being used as a module. A light emitting element represented by an EL element and the like is used in a pixel portion, and two pixel portions are provided in one light emitting device. A first pixel portion has a structure to emit light only from a counter electrode side of the light emitting element. A second pixel portion has a structure to emit light only from a pixel electrode side of the light emitting element. That is, in the first pixel portion and the second pixel portion, directions of light emission are reverse in front and back. | 2010-01-28 |
20100019246 | THIN FILM TRANSISTOR SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a thin film transistor array panel includes; forming a gate line including a gate electrode and a height increasing member on a substrate, forming a gate insulating layer on the gate line and the height increasing member, forming a semiconductor, a data line including a source electrode, and a drain electrode facing the source electrode and overlapping at least a portion of the height increasing member on the gate insulating layer, forming a first insulating layer on the gate insulating layer, a data line and the drain electrode, forming a light-blocking member on a portion of the first insulating layer corresponding to the gate line and the data line, forming a color filter in an area bound by the light-blocking member, forming a second insulating layer on the light-blocking member and the color filter, and patterning the second insulating layer, the light-blocking member or the color filter, and the first insulating layer to form a contact hole exposing a portion of the drain electrode aligned with the height increasing member. | 2010-01-28 |
20100019247 | Light emitting device using gan led chip - A light emitting device is constituted by flip-chip mounting a GaN-based LED chip | 2010-01-28 |
20100019248 | GALLIUM NITRIDE MATERIAL DEVICES INCLUDING CONDUCTIVE REGIONS AND METHODS ASSOCIATED WITH THE SAME - Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others. | 2010-01-28 |
20100019249 | JFET Devices with Increased Barrier Height and Methods of Making Same - Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a doped silicon-carbide gate, while other embodiments include a JFET with a metal gate. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET. | 2010-01-28 |
20100019250 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device and a method of forming thereof has a base body has a field stopping layer, a drift layer, a current spreading layer, a body region, and a source contact region layered in the order on a substrate. A trench that reaches the field stopping layer or the substrate is provided. A gate electrode is provided in the upper half section in the trench. In a section deeper than the position of the gate electrode in the trench, an insulator is buried that has a normal value of insulation breakdown electric field strength equal to or greater than the value of the insulation breakdown electric field strength of the semiconductor material of the base body. This inhibits short circuit between a gate and a drain due to insulation breakdown of an insulator film at the bottom of the trench to realize a high breakdown voltage in a semiconductor device using a semiconductor material such as SiC. The sidewall surfaces of the trench located below the gate electrode is inclined to form a trapezoidal profile. | 2010-01-28 |
20100019251 | Semiconductor Light Emitting Device - A semiconductor light emitting device is provided. The semiconductor light emitting device comprises a substrate and a light emitting structure. The substrate comprises a plurality of discontinuous fusion spots on at least one side surface thereof. The light emitting structure comprises a plurality of compound semiconductor layers on the substrate. | 2010-01-28 |
20100019252 | Nanowire-Based Light-Emitting Diodes and Light-Detection Devices With Nanocrystalline Outer Surface - Embodiments of the present invention are directed to nanowire ( | 2010-01-28 |
20100019253 | AC LIGHT EMITTING DIODE - Disclosed herein is an AC light emitting diode. The light emitting diode comprises a plurality of light emitting cells two-dimensionally arranged on a single substrate. Wires electrically connect the light emitting cells to one another to thereby form a serial array of the light emitting cells. Further, the light emitting cells are spaced apart from one another by distances within a range of 10 to 30 D, and the serial array is operated while connected to an AC power source. Accordingly, the excellent operating characteristics and light output power can be secured in an AC light emitting diode with a limited size. | 2010-01-28 |
20100019254 | SEMICONDUCTOR LIGHT EMITTING DEVICE, LIGHTING MODULE, LIGHTING APPARATUS, AND MANUFACTURING METHOD OF SEMICONDUCTOR LIGHT EMITTING DEVICE - An LED bare chip which is one type of a semiconductor light emitting device ( | 2010-01-28 |
20100019255 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - There is provided a semiconductor light-emitting device capable of an attempt to further decrease a leakage current in a current-blocking layer and including (A) a light-emitting portion ( | 2010-01-28 |
20100019256 | LIGHT EMITTING DEVICE WITH ELECTRON BLOCKING COMBINATION LAYER - A light emitting device with an electron blocking combination layer comprises an active layer, an n-type GaN layer, a p-type GaN layer, and an electron blocking combination layer which has two Group III-V semiconductor layers with different band gaps that can be deposited periodically and repeatedly on the active layer to block overflowing electrons from the active layers. | 2010-01-28 |
20100019257 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - There are provided a nitride semiconductor light emitting device having a structure enabling enhanced external quantum efficiency by effectively taking out light which is apt to repeat total reflection within a semiconductor lamination portion and a substrate and attenuate, and a method for manufacturing the same. A semiconductor lamination portion ( | 2010-01-28 |
20100019258 | SEMICONDUCTOR LIGHT EMITTING DEVICE - There is provided a semiconductor light emitting device that can easily dissipate heat, improve current spreading efficiency, and reduce defects by blocking dislocations occurring when a semiconductor layer is grown to thereby increase reliability. A semiconductor light emitting device including a substrate, a light emitting structure having an n-type semiconductor layer, an active layer, and a p-type semiconductor layer sequentially laminated, and an n-type electrode and a p-type electrode formed on the n-type semiconductor layer and the p-type semiconductor layer, respectively, according to an aspect of the invention may include: a metal layer formed in the n-type semiconductor layer and contacting the n-type electrode. | 2010-01-28 |
20100019259 | LED Semiconductor Body and Use of an LED Semiconductor Body - An LED semiconductor body includes at least one first radiation-generating active layer and at least one second radiation-generating active layer, wherein the LED semiconductor body has a photonic crystal. | 2010-01-28 |
20100019260 | SEMICONDUCTOR LIGHT EMITTING DEVICE INCLUDING A WINDOW LAYER AND A LIGHT-DIRECTING STRUCTURE - A device includes a semiconductor structure comprising a light emitting layer disposed between an n-type region and a p-type region. The semiconductor structure is disposed between a window layer and a light-directing structure. The light-directing structure is configured to direct light toward the window layer; examples of suitable light-directing structures include a porous semiconductor layer and a photonic crystal. An n-contact is electrically connected to the n-type region and a p-contact is electrically connected to the p-type region. The p-contact is disposed in an opening formed in the semiconductor structure. | 2010-01-28 |
20100019261 | SILICON NANOPARTICLE WHITE LIGHT EMITTING DIODE DEVICE - Multiple films of red-green-blue (RGB) luminescent silicon nanoparticles are integrated in a cascade configuration as a top coating in an ultraviolet/blue light emitting diode (LED) to convert it to a white LED. The configuration of RGB luminescent silicon nanoparticle films harnesses the short wavelength portion of the light emitted from the UV/blue LED while transmitting efficiently the longer wavelength portion. The configuration also reduces damaging heat and/or ultraviolet effects to both the device and to humans. | 2010-01-28 |
20100019262 | WHITE-EMITTING PHOSPHORS AND LIGHTING APPARATUS USING THE SAME - A phosphor has a general formula of (M | 2010-01-28 |
20100019263 | ROUGH STRUCTURE OF OPTOELECTRONIC DEVICE AND FABRICATION THEREOF - A dual-scale rough structure, in which a plurality of islands are grown on a semiconductor layer by heavily doping a dopant during epitaxy of a semiconductor layer of an optoelectronics device, is provided. A plurality of pin holes are formed on the islands by lowering the epitaxial temperature. The pin holes are distributed over the top and sidewall surfaces of the islands so that the total internal reflection within the optoelectronics device can be significantly reduced so as to enhance the brightness thereof. Compared with traditional technologies, the process method of the present invention has the advantages of producing less pollution, being able to perform easily, reducing manufactured cost, increasing the efficiency of light extraction, and increasing the effective area of the dual-scale emitting surface, which is not a smooth surface, of the structure. | 2010-01-28 |
20100019264 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device including a second electrode layer; a light emitting unit including a plurality of compound semiconductor layers under one portion of the second electrode layer; a first insulating layer under the other portion of the second electrode; an electrostatic protection unit including a plurality of compound semiconductor layer under the first insulating layer; a first electrode layer electrically connecting the light emitting unit to the electrostatic protection unit; and a wiring layer electrically connecting the electrostatic protection unit to the second electrode layer. | 2010-01-28 |
20100019265 | LIGHT-EMITTING APPARATUS WITH SHAPED WAVELENGTH CONVERTER - Proposed is a light-emitting apparatus | 2010-01-28 |
20100019266 | Arrangement for Generating Mixed Light and Method for Producing Such an Arrangement - An arrangement and a method for producing such an arrangement serve for generating mixed light. In this case, a semiconductor chip that emits an electromagnetic primary radiation has a luminescence conversion element in the beam path of the primary radiation. Furthermore, the arrangement includes a connecting element and a carrier element, wherein the carrier element carries and shapes the luminescence conversion element and the connecting element. | 2010-01-28 |
20100019267 | LED OF SIDE VIEW TYPE AND THE METHOD FOR MANUFACTURING THE SAME - A side view type light emitting diode (LED) and a method of manufacturing the same are disclosed. In one embodiment, the LED includes i) a pair of lead frames, ii) a reflector surrounding the lead frames, wherein a groove is defined in the reflector, wherein the reflector comprises a plurality of walls surrounding the groove, and wherein at least two walls of the groove face each other, iii) an LED chip mounted in the groove and electrically connected to the lead frames and iv) a lens array contained in the groove. | 2010-01-28 |
20100019268 | Optoelectronic Semiconductor Chip - An optoelectronic semiconductor chip ( | 2010-01-28 |
20100019269 | LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A light-emitting device and method of manufacturing the same provides a substrate, a semiconductor layer formed on the substrate and configured to generate light, and a transparent electrode layer formed on the semiconductor layer and configured to transmit the light generated from the semiconductor layer. The amount of a material of which the transparent electrode layer is made decreases gradually as it goes from the bottom to the top. | 2010-01-28 |
20100019270 | LIGHT EMITTING DEVICE AND DISPLAY - A light emitting diode having a mount lead having a cup and a lead, an LED chip mounted in the cup of said mount lead with one of electrodes being electrically connected to said mount lead, a coating material filling the cup of said mount lead to cover said LED chip; a molding material covering said LED chip, said coating material and the cup of said mount lead, and a phosphor absorbing a part of light emitted by said LED chip and emitting light of wavelength different from that of the absorbed light, wherein said phosphor is located in said coating material, and wherein said molding material is shaped to form a concave lens. | 2010-01-28 |
20100019271 | EPOXY RESIN COMPOSITION FOR OPTICAL SEMICONDUCTOR ELEMENT ENCAPSULATION AND OPTICAL SEMICONDUCTOR DEVICE USING THE SAME - The present invention relates to an epoxy resin composition for optical semiconductor element encapsulation, the epoxy resin composition including following components (A) to (C): | 2010-01-28 |
20100019272 | LIGHT EMITTING DIODE - A light emitting diode having a substrate, an electron injection layer, an active layer, a hole injection layer, a first pad electrically connected to the hole injection layer, and a second pad electrically connected to the electron injection layer. The hole injection layer includes an activated region and a patterned non-activated region. The first pad is disposed upon the non-activated region and the first pad and the non-activated region are overlapping in the vertical direction. | 2010-01-28 |
20100019273 | METHOD FOR PRODUCING STRUCTURED SUBSTRATE, STRUCTURED SUBSTRATE, METHOD FOR PRODUCING SEMICONDUCTOR LIGHT EMITTING DEVICE, SEMICONDUCTOR LIGHT EMITTING DEVICE, METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, METHOD FOR PRODUCING DEVICE, AND DEVICE - A semiconductor light emitting device or a semiconductor device produced using a nitride type III-V group compound semiconductor substrate on which a plurality of second regions made of a crystal having a second average dislocation density are regularly arranged in a first region made of a crystal having a first average dislocation density so as to produce the structured substrate, the second average dislocation density being greater than the first average dislocation density, a light emitting region of the semiconductor light emitting device or an active region of the semiconductor device is formed in such a manner that it does not pass through any one of the second regions. | 2010-01-28 |
20100019274 | Semiconductor device - A semiconductor device includes an insulating film formed over a semiconductor substrate, a Zener diode formed above the insulating film, an interlayer film formed above the Zener diode, and a gate aluminum and a source aluminum formed above the interlayer film. The Zener diode is connected between the gate aluminum and the source aluminum. The Zener diode is formed by alternately joining an N type region and a P type region concentrically. The gate electrode includes a gate pad section. A planar shape of the Zener diode is substantially similar to a planer shape of the gate pad section. The gate pad section extends for a predetermined distance from an outermost edge of the P type region of the Zener diode to outside. | 2010-01-28 |
20100019275 | SEMICONDUCTOR PHOTO DETECTOR - A semiconductor photo detector of the present invention includes a layer structure, having a selective etching layer of a first-type conductivity, a field-relaxing layer of the first-type conductivity, a multiplier layer, a field-relaxing layer of a second-type conductivity, a light absorption layer of the second-type conductivity, a selective etching layer of the second-type conductivity, a buffer layer of the second-type conductivity, a contact layer of the second-type conductivity, and an electrode in the side of the second-type conductivity, which are sequentially deposited over a semiconductor substrate, and having a second mesa formed on the semiconductor substrate and a first mesa formed on the second mesa, wherein the first mesa includes the buffer layer of the second-type conductivity, the contact layer of the second-type conductivity, and the electrode in the side of the second-type conductivity, wherein the second mesa includes the layer of the first-type conductivity, the multiplier layer, the light absorption layer of the second-type conductivity, and the selective etching layer of the second-type conductivity, wherein an outer periphery of the second mesa is located outside of the outer periphery of the first mesa in two-dimensional view, and wherein surfaces of the first mesa and the second mesa is covered by a passivation film. | 2010-01-28 |
20100019276 | ALL AROUND GATE TYPE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An all around gate type semiconductor device improves mobility of electrons and holes by using a silicon germanium pillar and a silicon layer surrounding the silicon germanium pillar as a vertical channel. A gate electrode is formed to surround the vertical channel. When a semiconductor device is used as a nMOSFET, the silicon layer strained by silicon germanium is used as the channel to increase electron mobility. When the semiconductor device is used as a pMOSFET, the silicon germanium pillar is used as the channel to increase hole mobility. Thus, the semiconductor device can enhance current supply capacity regardless of transistor type. | 2010-01-28 |
20100019277 | EPITAXIAL SUBSTRATE FOR FIELD EFFECT TRANSISTOR - The present invention provides an epitaxial substrate for field effect transistor. In the epitaxial substrate for field effect transistor, a nitride-based Group III-V semiconductor epitaxial crystal containing Ga is interposed between the ground layer and the operating layer, and the nitride-based Group III-V semiconductor epitaxial crystal comprises the following (i), (ii) and (iii). (i) a first buffer layer containing Ga or Al and containing a high resistivity crystal layer having added thereto compensation impurity element present in the same period as Ga in the periodic table and having small atomic number; (ii) a second buffer layer containing Ga or Al, laminated on the operating layer side of the first buffer layer; and (iii) a high purity epitaxial crystal layer containing acceptor impurities in a slight amount such that non-addition or depletion state can be maintained, provided between the high resistivity layer and the operating layer. | 2010-01-28 |
20100019278 | Multilayer Structure Comprising A Substrate and A Layer Of Silicon and Germanium Deposited Heteroepitaxially Thereon, and A Process For Producing It - A multilayer structure, comprises a substrate and a layer of silicon and germanium (SiGe layer) deposited heteroepitaxially thereon having the composition Si | 2010-01-28 |
20100019279 | Integrated HEMT and Lateral Field-Effect Rectifier Combinations, Methods, and Systems - Integrated high efficiency lateral field effect rectifier and HEMT devices of GaN or analogous semiconductor material, methods for manufacturing thereof, and systems which include such integrated devices. The lateral field effect rectifier has an anode containing a shorted ohmic contact and a Schottky contact, and a cathode containing an ohmic contact, while the HEMT preferably has a gate containing a Schottky contact. Two fluorine ion containing regions are formed directly underneath both Schottky contacts in the rectifier and in the HEMT, pinching off the (electron gas) channels in both structures at the hetero-interface between the epitaxial layers. | 2010-01-28 |
20100019280 | Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks - A cell of a semiconductor device is disclosed to include a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. The gate electrode level includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. The cell also includes a number of interconnect levels formed above the gate electrode level. | 2010-01-28 |
20100019281 | Cell of Semiconductor Device Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks - A cell of a semiconductor device is disclosed to include a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. The gate electrode level includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. A width of the conductive features within the gate electrode level is measured perpendicular to the first parallel direction and is less than a wavelength of light used in a photolithography process to fabricate the conductive features. The cell also includes a number of interconnect levels formed above the gate electrode level. | 2010-01-28 |
20100019282 | Cell of Semiconductor Device Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks - A cell of a semiconductor device is disclosed to include a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. The gate electrode level includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. A width size of the conductive features within a five wavelength photolithographic interaction radius within the gate electrode level is less than a wavelength of light of 193 nanometers. The cell also includes a number of interconnect levels formed above the gate electrode level. | 2010-01-28 |
20100019283 | Cell of Semiconductor Device Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors - A cell of a semiconductor device includes a substrate portion including a plurality of diffusion regions, including at least one p-type diffusion region and at least one n-type diffusion region separated by one or more non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features is fabricated from a respective originating rectangular-shaped layout feature. A width of the conductive features is less than a wavelength of light used in a photolithography process for their fabrication. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level. The cell also includes a number of interconnect levels formed above the gate electrode level. | 2010-01-28 |
20100019284 | Cell of Semiconductor Device Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors - A cell of a semiconductor device includes a substrate portion formed to include at least one p-type diffusion region and at least one n-type diffusion region separated by non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. A width of the conductive features is less than a wavelength of light used in a photolithography process for their fabrication. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. The cell also includes a number of interconnect levels formed above the gate electrode level. | 2010-01-28 |
20100019285 | Cell of Semiconductor Device Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors - A cell of a semiconductor device includes a substrate portion formed to include at least one p-type diffusion region and at least one n-type diffusion region separated by non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. A width size of the conductive features within a five wavelength photolithographic interaction radius within the gate electrode level is less than a wavelength of light of 193 nanometers. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. The cell also includes a number of interconnect levels formed above the gate electrode level. | 2010-01-28 |
20100019286 | Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing - A cell of a semiconductor device is disclosed to include a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Adjacent ones of the number of conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. The cell also includes a number of interconnect levels formed above the gate electrode level. | 2010-01-28 |
20100019287 | Cell of Semiconductor Device Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing - A cell of a semiconductor device is disclosed to include a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal and minimized across the gate electrode level region. The gate electrode level includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. A width of the conductive features within a five wavelength photolithographic interaction radius is less than a wavelength of light of 193 nanometers as used in a photolithography process for their fabrication. | 2010-01-28 |
20100019288 | Cell of Semiconductor Device Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing - A cell of a semiconductor device is disclosed to include a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. A width of the conductive features is less than a wavelength of light used in a photolithography process for their fabrication. | 2010-01-28 |
20100019289 | Junction Field Effect Transistor Using Silicide Connection Regions and Method of Fabrication - A junction field effect transistor comprises a semiconductor substrate and a well region formed in the substrate. A source region of a first conductivity type is formed in the well region. A drain region of the first conductivity type is formed in the well region and spaced apart from the source region. A channel region of the first conductivity type is located between the source region and the drain region and formed in the well region. A gate region of a second conductivity type is formed in the well region. The transistor further includes first, second, and third connection regions. The first connection region is in ohmic contact with the source region and formed of silicide. The second connection region is in ohmic contact with the drain region and formed of silicide. The third connection region in ohmic contact with the gate region. | 2010-01-28 |
20100019290 | Junction Field Effect Transistor Using a Silicon on Insulator Architecture - A junction field effect transistor comprises a silicon-on-insulator architecture. A front gate region and a back gate region are formed in a silicon region of the SOI architecture. The silicon region has a thin depth such that the back gate region has a thin depth, and whereby a depletion region associated with the back gate region recedes substantially up to an insulating layer of the SOI architecture. | 2010-01-28 |
20100019291 | JFET Devices with PIN Gate Stacks and Methods of Making the Same - Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a PIN gate stack. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET. | 2010-01-28 |
20100019292 | Transistor having a metal nitride layer pattern, etchant and methods of forming the same - A transistor having a metal nitride layer pattern, etchant and methods of forming the same is provided. A gate insulating layer and/or a metal nitride layer may be formed on a semiconductor substrate. A mask layer may be formed on the metal nitride layer. Using the mask layer as an etching mask, an etching process may be performed on the metal nitride layer, forming the metal nitride layer pattern. An etchant, which may have an oxidizing agent, a chelate agent and/or a pH adjusting mixture, may perform the etching. The methods may reduce etching damage to a gate insulating layer under the metal nitride layer pattern during the formation of a transistor. | 2010-01-28 |
20100019293 | PIN PHOTODIODE AND MANUFACTURING METHOD OF SAME - The objective of this invention is to provide a semiconductor device containing a photodiode and having stable, high sensitivity with respect to short wavelength light near 405 nm, and a manufacturing method for said semiconductor device. PIN photodiode ( | 2010-01-28 |
20100019294 | METHOD AND APPARATUS FOR DECREASING STORAGE NODE PARASITIC CHARGE IN ACTIVE PIXEL IMAGE SENSORS - Methods, systems and apparatuses for an imager that improve the quality of a captured image. The imager includes a pixel having a photosensor that generates charge in response to receiving electromagnetic radiation and a storage region that stores the generated charge. A protection region assists in keeping undesirable charge from reaching the storage region. | 2010-01-28 |
20100019295 | SINGLE PHOTON AVALANCHE DIODES - A CMOS single photon avalanche diode (SPAD) design uses conventional, or at least known, CMOS processes to produce a device having a breakdown region in which the main p-n junction is formed of a deep n-well layer, and optionally on the other side, a p-add layer. The SPAD may also have a guard ring region which comprises the p-epi layer without any implant. The SPAD may have curved or circular perimeters. A CMOS chip comprises SPADs as described and other NMOS devices all sharing the same deep n-well. | 2010-01-28 |
20100019296 | IMAGE SENSOR HAVING NANODOT - An image sensor includes a plurality of pixels disposed in an array, each pixel comprising a first region and a second region, the first region and the second region separated from each other in a semiconductor layer, and doped with impurities having different conductivities from each other, a photoelectric conversion region formed between the first and second regions, and at least one metal nanodot that focuses an incident light onto the photoelectric conversion region. | 2010-01-28 |
20100019297 | Multi-Stacked Spin Transfer Torque Magnetic Random Access Memory and Method of Manufacturing the Same - A spin transfer torque magnetic random access memory (STT-MRAM) device comprises adjacent magnetic tunneling junctions (MTJ), respectively, formed in different layers, thereby preventing interference between the MTJs and securing thermal stability. | 2010-01-28 |
20100019298 | Assemblies Comprising Magnetic Elements And Magnetic Barrier Or Shielding - The invention includes a method of forming a semiconductor construction, such as an MRAM construction. A block is formed over a semiconductor substrate. First and second layers are formed over the block, and over a region of the substrate proximate the block. The first and second layers are removed from over the block while leaving portions of the first and second layers over the region proximate the block. At least some of the first layer is removed from under the second layer to form a channel over the region proximate the block. A material, such as a soft magnetic material, is provided within the channel. The invention also includes semiconductor constructions. | 2010-01-28 |
20100019299 | Memory device - A memory device includes a MOS transistor including a gate structure, a first impurity region, a second impurity region, and a floating body positioned between the first and the second impurity regions on a semiconductor substrate including a buried oxide layer. The memory device includes a charge storage structure of the non-volatile memory device electrically connected to the second impurity region of the MOS transistor. | 2010-01-28 |
20100019300 | MULTILAYER INTEGRATED CIRCUIT HAVING AN INDUCTOR IN STACKED ARRANGEMENT WITH A DISTRIBUTED CAPACITOR - Some embodiments provide a multilayer integrated circuit, including: a semiconductor substrate including a plurality of channels extending into the substrate from a surface of the substrate; a distributed capacitor including a plurality of gates formed on the surface of the substrate over the channels, and further including an insulator between the gates and the channels, the gates being spaced apart along the surface of the substrate; an interconnect layer formed over the distributed capacitor, the interconnect layer including a plurality of conductors, at least a first conductor being connected to at least some of the gates and at least a second conductor being connected to at least some of the channels; and an inductor formed over the interconnect layer, the inductor including at least conductor arranged on a layer. | 2010-01-28 |
20100019301 | Dynamic random access memory structure - A dynamic random access memory structure includes a recessed-gate transistor disposed in the substrate; a trench capacitor structure disposed in the substrate and electrically connected to a first source/drain of the recessed-gate transistor; a first conductive structure disposed on and contacting the trench capacitor structure; a stack capacitor structure disposed on and contacting the first conductive structure, wherein a bottom electrode of the trench capacitor structure and a top electrode of the stack capacitor structure are electrically connected to serve as a common electrode; and a bit line disposed above a second source/drain of the recessed-gate transistor and electrically connected to the second source/drain, wherein the top of the bit line is lower than the top of the gate conductive layer of the recessed-gate transistor. | 2010-01-28 |
20100019302 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor device and a method of manufacturing the same, a substrate is defined into active and non-active regions by a device isolation layer and a recessed portion is formed on the active region. A gate electrode includes a gate insulation layer on an inner sidewall and a bottom of the recessed portion, a lower electrode on the gate insulation layer and an inner spacer on the lower electrode in the recessed portion, and an upper electrode that is positioned on the inner spacer and connected to the lower electrode. Source and drain impurity regions are formed at surface portions of the active region of the substrate adjacent to the upper electrode. Accordingly, the source and drain impurity regions are electrically insulated by the inner spacer in the recessed portion of the substrate like a bridge, to thereby sufficiently prevent gate-induced drain leakage (GIDL) at the gate electrode. | 2010-01-28 |
20100019303 | METHOD FOR FORMING CONDUCTIVE PATTERN, SEMICONDUCTOR DEVICE USING THE SAME AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - A method for fabricating conductive patterns includes forming a conductive layer over a substrate, etching the conductive layer to a first thickness to form first patterns, forming spacers on sidewalls of the first patterns, and etching the conductive layer to a second thickness using the spacers as an etch barrier to form second patterns. Thus, conductive patterns can be formed with vertical sidewalls without being damaged, and lean and collapse of the conductive patterns are prevented. | 2010-01-28 |
20100019304 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes bodies electrically floating; sources; drains; gate electrodes, each of which is adjacent to one side surface of the one of the bodies via a gate dielectric film; plates, each of which is adjacent to the other side surface of the one of the bodies via a plate dielectric film; first bit lines on the drains, the first bit lines including a semiconductor with a same conductivity type as that of the drains; and emitters on the semiconductor of the first bit lines, the emitters including a semiconductor with an opposite conductivity type to that of the semiconductor of the first bit lines, wherein the emitters are stacked above the bodies and the drains. | 2010-01-28 |
20100019305 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device of the present invention includes a semiconductor substrate, a plurality of floating gate electrodes formed in a memory cell forming region of the semiconductor substrate, a word line electrically connecting the floating gate electrodes and a conductor portion formed on the word line so as to reduce a resistance of the word line. | 2010-01-28 |
20100019306 | Semiconductor Fabrication - This document discloses devices fabricated on a semiconductor substrate and methods of fabricating the same. The devices can be memory cells having a tunnel window that is defined by dry-etching oxide to expose the semiconductor substrate and growing a tunnel oxide layer on the exposed semiconductor substrate. The semiconductor substrate can be decontaminated and/or repaired by exposing the semiconductor substrate to an optical irradiated energy source having a predefined energy that is sufficient to break molecular bonds of the contaminants and exposing the semiconductor substrate to a temperature that is sufficient to recrystallize the crystal lattice of the substrate. | 2010-01-28 |
20100019307 | METHOD OF FABRICATING FLASH MEMORY DEVICE - A method of fabricating a flash memory which increases a coupling ratio between a floating gate and a control gate in a cell. The method comprises sequentially forming a tunnel oxide film, and polysilicon and first insulation films for a floating gate on an active area of a semiconductor substrate; forming a photoresist as a mask on the first insulation film, and performing an etching process using the photoresist as the mask; forming a hard mask by depositing a second insulation film for prevention of oxidation on the semiconductor substrate; forming an STI by using the hard mask; oxidizing sidewalls of the STI and gap-filling the STI; forming a floating gate by removing the second insulation film remaining as the hard mask; and sequentially forming an ONO film and a control gate on the floating gate. | 2010-01-28 |
20100019308 | ELECTRICALLY PROGRAMMABLE DEVICE WITH EMBEDDED EEPROM AND METHOD FOR MAKING THEREOF - An electrically programmable device with embedded EEPROM and method for making thereof. The method includes providing a substrate including a first device region and a second device region, growing a first gate oxide layer in the first device region and the second device region, and forming a first diffusion region in the first device region and a second diffusion region and a third diffusion region in the second device region. Additionally, the method includes implanting a first plurality of ions to form a fourth diffusion region in the first device region and a fifth diffusion region in the second device region. The fourth diffusion region overlaps with the first diffusion region. | 2010-01-28 |
20100019309 | MULTI-LEVEL FLASH MEMORY STRUCTURE - A multi-level flash memory structure comprises a semiconductor substrate having a protrusion, a plurality of storage structures separated by the protrusion, a dielectric layer overlying the storage structures and the protrusion of the semiconductor substrate, a gate structure positioned on the dielectric layer, and several diffusion regions positioned at the sides of the protrusion. Each of the storage structures includes a charge-trapping site and an insulation structure isolating the charge-trapping site from the semiconductor substrate. | 2010-01-28 |
20100019310 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a semiconductor substrate; a stacked body provided on the semiconductor substrate and having a plurality of insulator layers and a plurality of conductive layers alternately stacked; a semiconductor layer provided inside a through-hole formed so as to pass through the stacked body and extending in a stacking direction of the insulator layers and the conductive layers; and a charge trap layer provided between the conductive layer and the semiconductor layer. A lower part in the semiconductor layer is narrower than an upper part therein, and at least the lowermost layer in the conductive layers is thinner than the uppermost layer therein. | 2010-01-28 |
20100019311 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - This semiconductor memory device comprises a semiconductor substrate, a plurality of tunnel insulator films formed on the semiconductor substrate along a first direction and a second direction orthogonal to the first direction with certain spaces in each directions, a plurality of charge accumulation layers formed on the plurality of tunnel insulator films, respectively, a plurality of element isolation regions formed on the semiconductor substrate, the plurality of element isolation regions including a plurality of trenches formed along the first direction between the plurality of tunnel insulator films, a plurality of element isolation films filled in the plurality of trenches, a plurality of inter poly insulator films formed over the plurality of element isolation regions and on the upper surface and side surfaces of the plurality of charge accumulation layer along the second direction in a stripe shape, a plurality of air gaps formed between the plurality of element isolation films filled in the plurality of trenches and the plurality of inter poly insulator films and a plurality of control gate electrodes formed on the plurality of inter poly insulator films. | 2010-01-28 |
20100019312 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor region, a tunnel insulating film formed on a surface of the semiconductor region, a charge-storage insulating film formed on a surface of the tunnel insulating film and containing silicon and nitrogen, a block insulating film formed on a surface of the charge-storage insulating film, and a control gate electrode formed on a surface of the block insulating film, wherein the tunnel insulating film has a first insulating film formed on the surface of the semiconductor region and containing silicon and oxygen, a second insulating film formed on a surface of the first insulating film, and a third insulating film formed on a surface of the second insulating film and containing silicon and oxygen, and a charge trap state in the second insulating film has a lower density than that in the charge-storage insulating film. | 2010-01-28 |
20100019313 | SEMICONDUCTOR CIRCUIT INCLUDING A LONG CHANNEL DEVICE AND A SHORT CHANNEL DEVICE - A semiconductor circuit is provided that includes a short channel device, and a long channel device that is electrically isolated from the short channel device. The long channel device comprises a plurality of first gate electrodes, a first source region adjacent one of the plurality of first gate electrodes, a first drain region adjacent another of the plurality of first gate electrodes, and a plurality of common source/drain regions positioned between adjacent ones of the plurality of first gate electrodes. The first gate electrodes each overlie portions of a layer of high-dielectric constant (k) gate insulator material. Each of the first gate electrodes are electrically coupled to at least one of the other first gate electrodes. | 2010-01-28 |
20100019314 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - Generally, a power MOSFET mainly includes an active region occupying most of an internal region (a region where a gate electrode made of polysilicon or the like is integrated), and a surrounding gate contact region (where the gate electrode made of polysilicon or the like is derived outside a source metal covered region to make contact with a gate metal) (see FIG. | 2010-01-28 |
20100019315 | SEMICONDUCTOR DEVICE HAVING A DEVICE ISOLATION TRENCH - A method for manufacturing a semiconductor device includes forming a semiconductor substrate to have a SOI structure by an epitaxial process for forming a gate while forming an insulating film pattern in a bottom where a device isolation trench is formed. The method thereby increases the process margin for forming a device isolation film and prevents the punch-through phenomenon to improve electrical characteristics of semiconductor devices and increase product yield. | 2010-01-28 |
20100019316 | Method of fabricating super trench MOSFET including buried source electrode - A method of fabricating a trench MOSFET, the lower portion of the trench containing a buried source electrode which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions. | 2010-01-28 |
20100019317 | Managing Integrated Circuit Stress Using Stress Adjustment Trenches - Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors. | 2010-01-28 |
20100019318 | DEVICE FOR ESD PROTECTION CIRCUIT - A LDNMOS device for an ESD protection circuit including a P-type substrate and an N-type deep well region is provided. The P-type substrate includes a first area and a second area. The N-type deep well region is in the first and second areas of the P-type substrate. The LDNMOS device further includes a gate electrode disposed on the P-type substrate between the first and second areas, a P-type implanted region disposed in the first area of the P-type substrate, an N-type grade region disposed in the N-type deep well region of the first area, an N-type first doped region disposed in the N-type grade region, a P-type body region disposed in the N-type deep well region of the second area, an N-type second doped region disposed in the P-type body region, and a P-type doped region disposed in the P-type body region and adjacent to the N-type second doped region. | 2010-01-28 |
20100019319 | Manufacturing method of thin-film transistor, thin-film transistor sheet, and electric circuit - A thin-film transistor, a thin-film transistor sheet, an electric circuit, and a manufacturing method thereof are disclosed, the method comprising the steps of forming a semiconductor layer by providing a semiconductive material on a substrate, b) forming an insulating area, which is electrode material-repellent, by providing an electrode material-repellent material on the substrate, and c) forming a source electrode on one end of the insulating area and a drain electrode on the other end of the insulating area, by providing an electrode material. | 2010-01-28 |
20100019320 | Direct Contact to Area Efficient Body Tie Process Flow - A process flow for fabricating shallow trench isolation (STI) devices with direct body tie contacts is provided. The process flow follows steps similar to standard STI fabrication methods except that in one of the etching steps, body tie contacts are etched through the nitride layer and STI oxide layer, directly to the body tie. This process flow provides a direct body tie contact to mitigate floating body effects but also eliminates hysteresis and transient upset effects common in non-direct body tie contact configurations, without the critical alignment requirements and critical dimension control of the layout. | 2010-01-28 |
20100019321 | MULTIPLE-GATE MOS TRANSISTOR USING Si SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - Provided are a multiple-gate MOS (metal oxide semiconductor) transistor and a method of manufacturing the same. The transistor includes a single crystalline active region having a channel region having an upper portion of a streamlined shape (∩) obtained by patterning an upper portion of a bulk silicon substrate with an embossed pattern, and having a thicker and wider area than the channel region; a nitride layer formed at both side surfaces of the single crystalline active region to expose an upper portion of the single crystalline active region at a predetermined height; and a gate electrode formed to be overlaid with the exposed upper portion of the single crystalline active region of the channel region. | 2010-01-28 |
20100019322 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING - A semiconductor device and method is provided that has a stress component for increased device performance. The method integrates a stress material into a trench used typically for an isolation structure. The method includes forming an isolation trench through a SOI layer and an underlying BOX layer. The method further includes filling the isolation trench with stress material having characteristics different than the BOX layer. | 2010-01-28 |
20100019323 | Semiconductor Device and Method of Manufacturing the Same - Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device comprises a gate electrode on a semiconductor substrate having a device isolation region, a first drain spacer on one side of the gate electrode, a second drain spacer next to the first drain spacer, a first source spacer on an opposite side of the gate electrode and a portion of the semiconductor substrate where a source region is to be formed, a second source spacer on side and top surfaces of the first source spacer, and LDDs adjacent to the first drain spacer and below the first source spacers, wherein the LDD below the first source spacer is thinner than the LDD adjacent to the first drain spacer. | 2010-01-28 |
20100019324 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - By ion-implanting an inert gas, for example, nitrogen into a polycrystalline silicon film in an nMIS forming region from an upper surface of the polycrystalline silicon film down to a predetermined depth, an upper portion of the polycrystalline silicon film is converted to an amorphous form to form an amorphous/polycrystalline silicon film. And then, an n-type impurity, for example, phosphorous is ion-implanted into the amorphous/polycrystalline silicon film to form an n-type amorphous/polycrystalline silicon film, the n-type amorphous/polycrystalline silicon film is processed to form a gate electrode having a gate length shorter than 0.1 μm, a sidewall formed of an insulating film is formed on a side wall of the gate electrode, and a source/drain diffusion layer is formed. Thereafter, a cobalt silicide (CoSi | 2010-01-28 |
20100019325 | SEMICONDUCTOR DEVICE - In a semiconductor device, a contact stopper film having a stress is provided to cover a group of MISFETs arranged in a gate-length direction. The stopper film has an extension part that extends by a length L=1 μm or more toward the outside of the gate electrode of the MISFET located the endmost part of the MISFET group. | 2010-01-28 |
20100019326 | COMPLEMENTARY BIPOLAR SEMICONDUCTOR DEVICE - A complementary bipolar semiconductor device (CBi semiconductor device) comprising a substrate of a first conductivity type, active bipolar transistor regions in the substrate, in which the base, emitter and collector of vertical bipolar transistors are arranged, vertical epitaxial-base npn bipolar transistors in a first subset of the active bipolar transistor regions, vertical epitaxial-base pnp bipolar transistors in a second subset of the active bipolar transistor regions, collector contact regions which are respectively arranged adjoining an active bipolar transistor region, and shallow field insulation regions which respectively laterally delimit the active bipolar transistor regions and the collector contact regions, wherein arranged between the first or the second or both the first and also the second subset of active bipolar transistor regions on the one hand and the adjoining collector contact regions on the other hand is a respective shallow field insulation region of a first type with a first depthwise extent in the direction of the substrate interior and shallow field insulation regions of a second type of a second greater depthwise extent than the first depthwise extent of the active bipolar transistor regions delimit the active bipolar transistor regions and collector contact regions viewed in cross-section at their sides facing away from each other. | 2010-01-28 |
20100019327 | Semiconductor Device and Method of Fabricating the Same - Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having first and second active areas defined thereon by isolation layers, a first gate electrode in the first active area, in which the first gate electrode includes a first silicide, and a second gate electrode in the second active area, in which the second gate electrode includes a second silicide having a composition ratio of silicon different from a composition ratio of silicon of the first silicide. | 2010-01-28 |
20100019328 | Semiconductor Resistor Formed in Metal Gate Stack - A semiconductor process and apparatus fabricate a metal gate electrode ( | 2010-01-28 |
20100019329 | Method and apparatus to reduce thermal variations within an integrated circuit die using thermal proximity correction - A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal. | 2010-01-28 |
20100019330 | DEVICE STRUCTURES WITH A SELF-ALIGNED DAMAGE LAYER AND METHODS FOR FORMING SUCH DEVICE STRUCTURES - Device structures with a self-aligned damage layer and methods of forming such device structures. The device structure first and second doped regions of a first conductivity type defined in the semiconductor material of a substrate. A third doped region of opposite conductivity type laterally separates the first doped region from the second doped region. A gate structure is disposed on a top surface of the substrate and has a vertically stacked relationship with the third doped region. A first crystalline damage layer is defined within the semiconductor material of the substrate. The first crystalline damage layer has a first plurality of voids surrounded by the semiconductor material of the substrate. The first doped region is disposed vertically between the first crystalline damage layer and the top surface of the substrate. The first crystalline damage layer does not extend laterally into the third doped region. | 2010-01-28 |