04th week of 2010 patent applcation highlights part 15 |
Patent application number | Title | Published |
20100019331 | HALL-EFFECT MAGNETIC SENSORS WITH IMPROVED MAGNETIC RESPONSIVITY AND METHODS FOR MANUFACTURING THE SAME - A Hall-effect magnetic sensor comprises a p-type Hall element and an n-type epitaxial Hall element. The p-type element can be implanted directly on top of the n-type element. The merged Hall elements can be biased in parallel to provide a nearly zero-bias depletion layer throughout for isolation. Electrical contacts to the n-type element can be diffused down through the p-type element and positioned to partially obstruct current flow in the p-type element. Electrical contacts can be diffused into the p-type element. Each bias contact of the p-type element can be connected to respective bias contacts of the n-type element in a parallel fashion. Then, an output signal can be taken at the sense contacts of the n-type element in order to provide improved magnetic responsivity. Further provided is a method for manufacturing the Hall-effect magnetic sensor. | 2010-01-28 |
20100019332 | METHODS AND APPARATUS FOR INTEGRATED CIRCUIT HAVING ON CHIP CAPACITOR WITH EDDY CURRENT REDUCTIONS - Methods and apparatus for providing an integrated circuit including a substrate having a magnetic field sensor, first and second conductive layers generally parallel to the substrate, and a dielectric layer disposed between the first and second conductive layers such that the first and second conductive layers and the dielectric layer form a capacitor, wherein a slot is formed in at least one of the first and second conductive layers proximate the magnetic field sensor for reducing eddy currents in the first and second conductive layers. | 2010-01-28 |
20100019333 | Low resistance tunneling magnetoresistive sensor with composite inner pinned layer - A high performance TMR sensor is fabricated by employing a composite inner pinned (AP1) layer in an AP2/Ru/AP1 pinned layer configuration. In one embodiment, there is a 10 to 80 Angstrom thick lower CoFeB or CoFeB alloy layer on the Ru coupling layer, a and 5 to 50 Angstrom thick Fe or Fe alloy layer on the CoFeB or CoFeB alloy, and a 5 to 30 Angstrom thick Co or Co rich alloy layer formed on the Fe or Fe alloy. A MR ratio of about 48% with a RA of <2 ohm-um | 2010-01-28 |
20100019334 | Materials, Fabrication Equipment, and Methods for Stable, Sensitive Photodetectors and Image Sensors Made Therefrom - Optically sensitive devices include a device comprising a first contact and a second contact, each having a work function, and an optically sensitive material between the first contact and the second contact. The optically sensitive material comprises a p-type semiconductor, and the optically sensitive material has a work function. Circuitry applies a bias voltage between the first contact and the second contact. The optically sensitive material has an electron lifetime that is greater than the electron transit time from the first contact to the second contact when the bias is applied between the first contact and the second contact. The first contact provides injection of electrons and blocking the extraction of holes. The interface between the first contact and the optically sensitive material provides a surface recombination velocity less than 1 cm/s. | 2010-01-28 |
20100019335 | Materials, Fabrication Equipment, and Methods for Stable, Sensitive Photodetectors and Image Sensors Made Therefrom - Optically sensitive devices include a device comprising a first contact and a second contact, each having a work function, and an optically sensitive material between the first contact and the second contact. The optically sensitive material comprises an n-type semiconductor, and the optically sensitive material has a work function. Circuitry applies a bias voltage between the first contact and the second contact. The optically sensitive material has an electron lifetime that is greater than the electron transit time from the first contact to the second contact when the bias is applied between the first contact and the second contact. The first contact provides injection of electrons and blocking the extraction of holes. The interface between the first contact and the optically sensitive material provides a surface recombination velocity less than 1 cm/s. | 2010-01-28 |
20100019336 | MEMS DEVICES HAVING OVERLYING SUPPORT STRUCTURES AND METHODS OF FABRICATING THE SAME - Embodiments of MEMS devices comprise a conductive movable layer spaced apart from a conductive fixed layer by a gap, and supported by rigid support structures, or rivets, overlying depressions in the conductive movable layer, or by posts underlying depressions in the conductive movable layer. In certain embodiments, portions of the rivet structures extend through the movable layer and contact underlying layers. In other embodiments, the material used to form the rigid support structures may also be used to passivate otherwise exposed electrical leads in electrical connection with the MEMS devices, protecting the electrical leads from damage or other interference. | 2010-01-28 |
20100019337 | PHOTOELECTRIC CONVERSION ELEMENT AND MANUFACTURING METHOD OF PHOTOELECTRIC CONVERSION ELEMENT - An object is to provide a photoelectric conversion element having a side surface with different taper angles by conducting etching of a photoelectric conversion layer step-by-step. A pin photodiode has a high response speed compared with a pn photodiode but has a disadvantage of large dark current. One cause of the dark current is considered to be conduction through an etching residue which is generated in etching and deposited on a side surface of the photoelectric conversion layer. Leakage current of the photoelectric conversion element is reduced by forming a structure in which a side surface has two different tapered shapes, which conventionally has a uniform surface, so that the photoelectric conversion layer has a side surface of a p-layer and a side surface of an n-layer, which are not in the same plane. | 2010-01-28 |
20100019338 | STACK TYPE SEMICONDUCTOR CHIP PACKAGE HAVING DIFFERENT TYPE OF CHIPS AND FABRICATION METHOD THEREOF - A stack type semiconductor chip package includes a first wafer mold, a protection substrate, and a second wafer mold that are stacked in a wafer level process. The first wafer mold includes a first chip having first pads and a first mold layer encapsulating the first chip. The protection substrate is placed on the first wafer mold, is mechanically bonded with the first wafer mold using a first adhesive layer, and includes wiring layers facing the first pads. The second wafer mold is placed under the first wafer mold, is mechanically bonded with the first wafer mold using a second adhesive layer, and includes a second chip having second pads, and a second mold layer encapsulating the second chip. First vias electrically connect the wiring layers of the protection substrate with the second pads. Second vias electrically connect the wiring layers of the protection substrate with external connection terminals. | 2010-01-28 |
20100019339 | MOLDED OPTICAL PACKAGE WITH FIBER COUPLING FEATURE - Apparatuses and methods directed to an integrated circuit package having an optical component are disclosed. The package may include an integrated circuit die having at least one light sensitive region disposed on a first surface thereof. By way of example, the die may be a laser diode that emits light through the light sensitive region, or a photodetector that receives and detects light through the light sensitive region. An optical concentrator may be positioned adjacent the first surface of the first die. The optical concentrator includes a lens portion positioned adjacent the light sensitive region and adapted to focus light. | 2010-01-28 |
20100019340 | Back illuminated photodetector and method for manufacturing the same - The present invention provides a back illuminated photodetector having a sufficiently small package as well as being capable of suppressing the scattering of to-be-detected light and method for manufacturing the same. A back illuminated photodiode 1 comprises an N-type semiconductor substrate | 2010-01-28 |
20100019341 | BURIED ASYMMETRIC JUNCTION ESD PROTECTION DEVICE - An improved lateral bipolar electrostatic discharge (ESD) protection device ( | 2010-01-28 |
20100019342 | SEMICONDUCTOR DEVICE - In a semiconductor device having a pn-junction diode structure that includes anode diffusion region including edge area, anode electrode on anode diffusion region, and insulator film on edge area of anode diffusion region, the area of anode electrode above anode diffusion region with insulator film interposed between anode electrode and anode diffusion region is narrower than the area of insulator film on edge area of anode diffusion region. | 2010-01-28 |
20100019343 | SEMICONDUCTOR DEVICE - A semiconductor device comprises: a first transistor in a substrate; a second transistor in said substrate; and a further device in said substrate, wherein the second transistor and the further device are arranged to operate at a second voltage which is higher than a first voltage, wherein the first voltage is the (normal) voltage of operation of the first transistor, and wherein the first transistor is isolated from the second voltage. | 2010-01-28 |
20100019344 | NOVEL POLY RESISTOR AND POLY EFUSE DESIGN FOR REPLACEMENT GATE TECHNOLOGY - A semiconductor device and method for fabricating a semiconductor device is disclosed. The semiconductor device comprises a semiconductor substrate; an active region of the substrate, wherein the active region includes at least one transistor; and a passive region of the substrate, wherein the passive region includes at least one resistive structure disposed on an isolation region, the at least one resistive structure in a lower plane than the at least one transistor | 2010-01-28 |
20100019345 | Integrated Circuit with an Active Area Line Having at Least One Form-Supporting Element and Corresponding Method of Making an Integrated Circuit - An integrated circuit is described. The integrated circuit may have: an active area line formed of a material of a semiconductor substrate with a first longitudinal direction parallel to an upper surface of the semiconductor substrate; wherein the active area line has at least one form-supporting element extending in a second longitudinal direction parallel to the upper surface of the semiconductor substrate; and wherein the second longitudinal direction is arranged with regard to the first longitudinal direction in an angle unequal to 0 degree and unequal to 180 degree. | 2010-01-28 |
20100019346 | IC HAVING FLIP CHIP PASSIVE ELEMENT AND DESIGN STRUCTURE - IC and design structure including various ways of raising a passive element such as an inductor off the surface of the substrate to improve the performance of the passive element are presented. A first wafer may be provided, and passive elements diced from a second wafer. The passive elements are flipped, and then aligned to be bonded on the first wafer such that the passive elements are raised a distance off the first wafer because of the presence of chip connections such as C4 solder bumps. A gap between the passive elements and the first wafer can be filled with underfill or air. If air is used, a hermetic seal around the gap can be created using chip connections such as C4 solder bumps or other known bonding means to seal the gap. | 2010-01-28 |
20100019347 | Under Bump Metallization for On-Die Capacitor - Various on-chip capacitors and methods of making the same are disclosed. In one aspect, a method of manufacturing a capacitor is provided that includes forming a first conductor structure on a semiconductor chip and forming a passivation structure on the first conductor structure. An under bump metallization structure is formed on the passivation structure. The under bump metallization structure overlaps at least a portion of the first conductor structure to provide a capacitor. | 2010-01-28 |
20100019348 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - After the formation of a first interlayer insulating, an etching stopper film made of SiON is formed thereon. Subsequently, a contact hole extending from the upper surface of the etching stopper film and reaching a high concentration impurity region is formed, and a first plug is formed by filling W into the contact hole. Next, a ferroelectric capacitor, a second interlayer insulating film, and the like are formed. Thereafter, a contact hole extending from the upper surface of the interlayer insulating film and reaching the first plug is formed. Then, the contact hole is filled with W to form a second plug. With this, even when misalignment occurs, the interlayer insulating film is prevented from being etched. | 2010-01-28 |
20100019349 | METHOD FOR FABRICATING CONDUCTING PLATES FOR A HIGH-Q MIM CAPACITOR - A method of forming one or more capacitors on or in a substrate and a capacitor structure resulting therefrom is disclosed. The method includes forming a trench in the substrate, lining the trench with a first copper-barrier layer, and substantially filling the trench with a first copper layer. The first copper layer is substantially chemically isolated from the substrate by the first copper-barrier layer. A second copper-barrier layer is formed over the first copper layer and a first dielectric layer is formed over the second copper-barrier layer. The dielectric layer is substantially chemically isolated from the first copper layer by the second copper-barrier layer. A third copper-barrier layer is formed over the dielectric layer and a second copper layer is formed over the third copper-barrier layer. The second copper layer is formed in a non-damascene process. | 2010-01-28 |
20100019350 | Resonant operating mode for a transistor - The PN junctions of a transistor are biased for operation in the active mode but an initial flow of current reverses the bias of the base-emitter junction causing the transistor to conduct a resonant current with a voltage less than the forward junction voltage of said base-emitter. | 2010-01-28 |
20100019351 | VARACTORS WITH ENHANCED TUNING RANGES - A varactor may have a first terminal connected to a gate. The gate may be formed from a p-type polysilicon gate conductor. The gate may also have a gate insulator formed from a layer of insulator such as silicon oxide. The gate insulator may be located between the gate conductor and a body region. Source and drain contact regions may be formed in a silicon body region. The body region and the source and drain may be doped with n-type dopant. The varactor may have a second terminal connected to the n-type source and drain. A control voltage may be used to adjust the level of capacitance produced by the varactor between the first and second terminals. A positive control voltage may produce a larger capacitance than a negative control voltage. Application of the negative control voltage may produce a depletion layer in the p+ polysilicon gate layer. | 2010-01-28 |
20100019352 | PROCESS FOR SMOOTHENING III-N SUBSTRATES - A process for preparing smoothened III-N, in particular smoothened III-N substrate or III-N template, wherein III denotes at least one element of group III of the Periodic System, selected from Al, Ga and In, utilizes a smoothening agent comprising cubic boron nitride abrasive particles. The process provides large-sized III-N substrates or III-N templates having diameters of at least 40 mm, at a homogeneity of very low surface roughness over the whole substrate or wafer surface. In a mapping of the wafer surface with a white light interferometer, the standard deviation of the rms-values is 5% or lower, with a very good crystal quality at the surface or in surface-near regions, measurable, e.g., by means of rocking curve mappings and/or micro-Raman mappings. | 2010-01-28 |
20100019353 | Semiconductor device and method for manufacturing the same - A semiconductor device and a method for manufacturing the same prevents copper from being exposed to a surface of a passivation film after a copper metal line formation, to avoid contamination of processing equipment and the process environment. The method includes providing a substrate with a scribe lane and a chip area in which metal wiring layers are formed, forming a dielectric film, forming a conductive film on the dielectric film in a chip area and an alignment mark on the dielectric film in a scribe lane, forming passivation films, exposing the conductive film by removing the passivation films in a bonding pad portion in a chip area, forming another conductive film in the bonding pad portion to electrically connect with the conductive film, forming another passivation film, and selectively removing the passivation films. | 2010-01-28 |
20100019354 | SEMICONDUCTOR CHIP SHAPE ALTERATION - The invention is directed to an improved semiconductor chip that reduces crack initiation and propagation into the active area of a semiconductor chip. A semiconductor wafer includes dicing channels that separate semiconductor chips and holes through a portion of a semiconductor chip, which are located at the intersection of the dicing channels. Once diced from the semiconductor wafer, semiconductor chips are created without ninety degree angle corners. | 2010-01-28 |
20100019355 | Multi-Level Nanowire Structure And Method Of Making The Same - A method for making a multi-level nanowire structure includes establishing a first plurality of nanowires on a substrate surface, wherein at least some of the nanowires are i) aligned at a predetermined crystallographically defined angle with respect to the substrate surface, ii) aligned substantially perpendicular with respect to the substrate surface, or iii) combinations of i and ii. An insulating layer is established between the nanowires of the first plurality such that one of two opposed ends of at least some of the nanowires positioned i) at the predetermined crystallographically defined angle, ii) substantially perpendicular with respect to the substrate surface, or iii) combinations of i and ii is exposed. Regions are grown from each of the exposed ends, and such regions coalesce to form a substantially continuous layer on the insulating layer. A second plurality of nanowires is established on the substantially continuous layer. | 2010-01-28 |
20100019356 | Semiconductor device and manufacturing method therefor - The present invention relates to a semiconductor device. The semiconductor device includes a fluorocarbon film formed on a substrate and a film containing metal formed on the fluorocarbon film, wherein the content amount of fluorine atom on the fluorocarbon film, which contacts the film containing metal, is in a predetermined range. | 2010-01-28 |
20100019357 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A gate insulating film having a high dielectric constant, a semiconductor device provided with the gate insulating film, and a method for manufacturing such film and device are provided. The semiconductor device is provided with a group 14 (IVB) semiconductor board and a first oxide layer. The first oxide layer is composed of MO | 2010-01-28 |
20100019358 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING - A semiconductor device and method is provided that has an oxygen diffusion barrier layer between a high-k dielectric and BOX. The method includes depositing a diffusion barrier layer on a BOX layer and gate structure and etching a portion of the diffusion barrier layer from sidewalls of the gate structure. The method further includes depositing a high-k dielectric on the diffusion barrier layer and the gate structure. | 2010-01-28 |
20100019359 | Semiconductor Device and Method of Forming Shielding Along a Profile Disposed in Peripheral Region Around the Device - A semiconductor device has a semiconductor die with a peripheral region around the die. A first insulating material is deposited in the peripheral region. A conductive via is formed through the first insulating material. A conductive layer is formed over the semiconductor die. The conductive layer is electrically connected between the conductive via and a contact pad of the semiconductor die. A second insulating layer is deposited over the first insulating layer, conductive layer, and semiconductor die. A profile is formed in the first and second insulating layers in the peripheral region. The profile is tapered, V-shaped, truncated V-shape, flat, or vertical. A shielding layer is formed over the first and second insulating layers to isolate the semiconductor die from inter-device interference. The shielding layer conforms to the profile in the peripheral region and electrically connects the shielding layer to the conductive via. | 2010-01-28 |
20100019360 | INTEGRATED CIRCUIT PACKAGE WITH ETCHED LEADFRAME FOR PACKAGE-ON-PACKAGE INTERCONNECTS - Methods, systems, and apparatuses for integrated circuit packages, and for package stacking, are provided. An electrically conductive frame is attached to a first surface of a substrate. The electrically conductive frame includes a perimeter ring portion, a plurality of leads, and a plurality of interconnect members positioned within a periphery formed by the perimeter ring portion. Each interconnect member is coupled to the perimeter ring portion by a respective lead. A first end of each interconnect member is coupled to the first surface of the substrate. An encapsulating material is applied to the first surface of the substrate, without covering a second end of each interconnect member with the encapsulating material. The perimeter ring portion is removed from the electrically conductive frame to isolate the plurality of interconnect members. A first integrated circuit package is formed in this manner. A second integrated circuit package may be mounted to the first package. Signals of the first package may be electrically coupled with the second package at the exposed second ends of the interconnect members. Side surfaces of the interconnect members may be exposed at sides of the first package. | 2010-01-28 |
20100019361 | Multi Lead Frame Power Package - According to an embodiment of the invention, a system, operable to facilitate dissipation of thermal energy, includes a mold compound, a die, a first lead frame, and a second lead frame. The die is disposed within the mold compound, and in operation generates thermal energy. The first lead frame is disposed at least partially within the mold compound and is operable to facilitate transmission of a signal. The second lead frame is disposed at least partially within the compound, at least partially separated from the first lead frame, and is operable to facilitate a dissipation of thermal energy. | 2010-01-28 |
20100019362 | ISOLATED STACKED DIE SEMICONDUCTOR PACKAGES - Semiconductor packages that contain isolated stacked dies and methods for making such devices are described. The semiconductor package contains both a first die with a first integrated circuit and a second die with a second integrated circuit that is stacked onto the first die while also being isolated from the first die. The first and second dies are connected using differing arrays of metal strips that serve as interposers between the first and second dies. This configuration provides a thinner semiconductor package since wire-bonding is not used. As well, since the integrated circuit devices in the first and second dies are isolated from each other, local heating and/or hot spots are diminished or prevented in the semiconductor package. Other embodiments are also described. | 2010-01-28 |
20100019363 | SEMICONDUCTOR SYSTEM-IN-PACKAGE AND METHOD FOR MAKING THE SAME - Semiconductor devices that contain a system in package and methods for making such packages are described. The semiconductor device with a system in package (SIP) contains a first IC die, passive components, and discrete devices that are contained in a lower level of the package. The SIP also contains a second IC die that is vertically separated from the first IC die by an array of metal interposers, thereby isolating the components of the first IC die from the components of the second IC die. Such a configuration provides more functionality within a single semiconductor package while also reducing or eliminating local heating in the package. Other embodiments are also described. | 2010-01-28 |
20100019364 | SAW DEBRIS REDUCTION IN MEMS DEVICES - An improved MEMS device and method of making. Channels are formed in a first substrate around a plurality of MEMS device areas previously formed on the first substrate. Then, a plurality of seal rings are applied around the plurality of MEMS device areas and over at least a portion of the formed channels. A second substrate is attached to the first substrate, then the seal ring surrounded MEMS device areas are separated from each other. The channels include first and second cross-sectional areas. The first cross-sectional area is sized to keep saw debris particles from entering the MEMS device area. | 2010-01-28 |
20100019365 | DICING/DIE BONDING FILM - The invention relates to a dicing die-bonding film having a pressure-sensitive adhesive layer and a die bonding adhesive layer being sequentially laminated on a supporting substrate, wherein said pressure-sensitive adhesive layer has a thickness of 10 to 80 μm, and has a storage elastic modulus at 23° C. of 1×10 | 2010-01-28 |
20100019366 | Package for an Integrated Circuit - According to various illustrative embodiments of the present invention, a device for an integrated circuit includes a monolithic frame having a plurality of alignment features disposed thereon, the monolithic frame having a mounting surface disposed thereon for the integrated circuit, the monolithic frame also having a thermal interface area disposed thereon for the integrated circuit. The device also includes an electrical interface capable of providing an electrical connection for the integrated circuit, the plurality of alignment features being substantially independent of the electrical interface, and an adhesive layer disposed between the monolithic frame and the electrical interface. | 2010-01-28 |
20100019367 | METHOD OF FORMING A MOLDED ARRAY PACKAGE DEVICE HAVING AN EXPOSED TAB AND STRUCTURE - In one embodiment, a method for forming a molded flat pack style package includes attaching electronic chips to an array lead frame, which includes a plurality of elongated flag portions with tab portions and a plurality of leads. The method further includes connecting the electronic chips to specific leads, and then molding the array lead frame while leaving portions of the leads exposed to form a molded array structure. The molded array structure is then separated to provide molded flat pack style packages having exposed leads for insertion mount and exposed tab portions. In an alternative embodiment, the separation step produces a no-lead configuration with exposed tab portions. | 2010-01-28 |
20100019368 | SEMICONDUCTOR CHIP PACKAGE, STACKED PACKAGE COMPRISING SEMICONDUCTOR CHIPS AND METHODS OF FABRICATING CHIP AND STACKED PACKAGES - A semiconductor chip package includes a substrate having a cavity, a stacked package comprising the semiconductor chip package, and methods of fabricating the chip and the stacked packages. According to an example embodiment, the semiconductor chip package includes a substrate comprising a substrate body having a first main surface, a second main surface, and a cavity that defines an opening in the first main surface, and a layer of electrically conductive material integral with the substrate body. The layer of electrically conductive material constitutes an interconnection pattern of the substrate. The semiconductor chip packages further includes a semiconductor chip disposed within the cavity and mounted to the substrate. The chip includes electrical contacts in the form of pads and the pads face in a direction towards the bottom of the cavity such that the chip has a flip-chip orientation with respect to the substrate. The pads are electrically conductively bonded to respective portions of the interconnection pattern. | 2010-01-28 |
20100019369 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADFRAME SUBSTRATE - An integrated circuit package system is provided. A dual-type leadframe having first and second rows of leads is formed. A first row of bumps is formed on an integrated circuit chip. Solder paste is placed on the first row of leads, and the first row of bumps is pressed into the solder paste on the first row of leads. The solder paste is reflow soldered to form solder and connect the integrated circuit chip to the first row of leads, and the integrated circuit chip, the first row of bumps, the solder, and the leadframe are encapsulated. | 2010-01-28 |
20100019370 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A semiconductor device and manufacturing method. One embodiment provides a semiconductor chip. An encapsulating material covers the semiconductor chip. A metal layer is over the semiconductor chip and the encapsulating material. At least one of a voltage generating unit and a display unit are rigidly attached to at least one of the encapsulating material and the metal layer. | 2010-01-28 |
20100019371 | SEMICONDUCTOR DEVICE CAPABLE OF SUPPRESSING WARPING IN A WAFER STATE AND MANUFACTURING METHOD THEREOF - In this manufacturing method of a semiconductor device, after a sealing film is applied over an entire surface of a semiconductor wafer and hardened, a second groove for forming a side-section protective film is formed in the sealing film and on the top surface side of the semiconductor wafer. In other words, the sealing film is formed in a state where a groove that causes strength reduction has not been formed on the top surface side of the semiconductor wafer. Since the second groove is formed on the top surface side of the semiconductor wafer after the sealing film is formed, the semiconductor wafer is less likely to warp when the sealing film, made of liquid resin, is hardened. | 2010-01-28 |
20100019372 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor device package includes a semiconductor chip including a conductive pad, a die pad on which the semiconductor chip is mounted and having a first thickness, a lead pattern including a first portion disposed adjacent to the edge of the die pad and having the first thickness and a second portion having a second thickness greater than the first thickness, a heat radiation member disposed on the die pad and the lead pattern and including a groove formed at its bottom surface, and a conductive line disposed to electrically connect the conductive pad to the lead pattern corresponding to the conductive pad and partially inserted into the groove. | 2010-01-28 |
20100019373 | UNIVERSAL SUBSTRATE FOR SEMICONDUCTOR PACKAGES AND THE PACKAGES - A universal substrate for semiconductor packages and the package are revealed. The universal substrate comprises a substrate core, two peripheral rows of bonding fingers and a central row of redistribution fingers disposed on the substrate core, and a solder mask formed on the substrate core. The redistribution fingers are located between two rows of the bonding fingers. The solder mask has an opening to expose the redistribution fingers. A plurality of exhaust grooves are formed on the solder mask without penetrating through the solder mask where one end of the exhaust grooves connects to the opening and the other end extends toward the edges of the substrate core without connecting to another opening exposing the bonding fingers to be the releasing channels of gases generated during die-attaching processes. When disposing larger IC chips, the issue of residue bubbles trapped in the covered opening and the issue of contaminations of bonding fingers by the die-bonding adhesives can be eliminated. In one of the embodiment, the traces connecting to the redistribution fingers can be overlapped with the exhaust grooves without being exposed from the solder mask to enhance the design flexibility of the exhaust grooves. | 2010-01-28 |
20100019374 | BALL GRID ARRAY PACKAGE - A thermally conductive ball grid array (BGA) package for integrated circuits having improved ground path employs a printed circuit substrate. The substrate has an array of solder balls disposed on the bottom side. There is an opening in the substrate corresponding to the integrated circuit die. A grounding ring covers the vertical walls of the opening and includes an upper ground collar on the top side of the substrate and a lower ground collar on the bottom side of the substrate. A thermally and electrically conductive heat spreader is attached to the lower ground collar on the bottom side of the BGA package, covering the opening in the substrate. The integrated circuit die is mounted on the heat spreader, with the active side up, within the opening in the substrate. Ground pads on the active side of the die are attached to the upper ground collar by wire bonds, to provide a continuous ground path from the ground pads to the heat spreader. Molded plastic covers the semiconductor device and the top side of the substrate. | 2010-01-28 |
20100019375 | Housing for a semiconductor component - A housing for a semiconductor component, in which the housing has a plurality of pins which are provided at the edge of the housing at distances, the pins each having a width, a thickness and a length. In order to create a housing for a semiconductor component whose characteristic frequencies are outside a range in which the characteristic frequencies of the housing negatively influence the semiconductor component, either at least one of the distances lies outside the range of 1.24 mm to 1.30 mm, at least one of the widths lies outside the range of 0.33 mm to 0.51 mm, at least one of the thicknesses lies outside the range of 0.23 to 0.32 mm, or at least one of the lengths lies outside the range of 2.05 to 4.12 mm. | 2010-01-28 |
20100019376 | HIGH FREQUENCY CERAMIC PACKAGE AND FABRICATION METHOD FOR THE SAME - A high frequency ceramic package includes: a first conductive pattern placed on the top surface of a ceramic RF substrate; a second conductive pattern placed on the bottom surface of the ceramic RF substrate; a through hole for passing through the top surface and bottom surface of the ceramic RF substrate; a through hole metal layer which is filled up in the through hole and which connects the first conductive pattern and the second conductive pattern; a ceramic seal ring placed on the ceramic RF substrate; an insulating adhesive bond placed on the ceramic seal ring; and a ceramic cap placed on the insulating adhesive bond, wherein the second conductive pattern is used as an external terminal, and between the ceramic cap and the top surfaces of the ceramic seal ring is sealed with the insulating adhesive bond and it is simple for structure and excellent in high frequency characteristics. | 2010-01-28 |
20100019377 | SEGMENTATION OF A DIE STACK FOR 3D PACKAGING THERMAL MANAGEMENT - An apparatus to reduce a thermal penalty of a three-dimensional (3D) die stack for use in a computing environment is provided and includes a substrate installed within the computing environment, a first component to perform operations of the computing environment, which is coupled to the substrate in a stacking direction, a set of second components to perform operations of the computing environment, each of which is coupled to the first component and segmented with respect to one another to form a vacated region, a thermal interface material (TIM) disposed on exposed surfaces of the first and second components, and a lid, including a protrusion, coupled to the substrate to overlay the first and second components such that the protrusion extends into the vacated region and such that surfaces of the lid and the protrusion thermally communicate with the first and second components via the TIM. | 2010-01-28 |
20100019378 | SEMICONDUCTOR MODULE AND A METHOD FOR PRODUCING AN ELECTRONIC CIRCUIT - A semiconductor module has at least one die, made of silicon carbide, in which semiconductor components are patterned. The die includes at least one exposed surface for contacting an external heat sink. | 2010-01-28 |
20100019379 | EXTERNAL HEAT SINK FOR BARE-DIE FLIP CHIP PACKAGES - An integrated circuit package includes a substrate having opposing first and second surfaces, a flip chip integrated circuit die, and a heat sink. A first surface of die is mounted to the first surface of the substrate by a plurality of electrically conductive solder bumps. The heat sink has a first surface that includes a recessed region extending along a length of the heat sink in the first surface and that includes first and second supporting portions separated by the recessed region. The first and second supporting portions are attached to the first surface of the substrate such that the die is positioned in the recessed region. A second surface of the die is attached to a surface of the recessed region. | 2010-01-28 |
20100019380 | INTEGRATED CIRCUIT WITH MICRO-PORES CERAMIC HEAT SINK - An integrated circuit includes an integrated circuit device, a micro-pores ceramic heat sink and a heat conductive medium. The micro-pores ceramic heat sink is placed on a surface of the integrated circuit device. The heat conductive medium is placed in between the integrated circuit device and the micro-pores ceramic heat sink with one surface joined to the integrated circuit device and the other surface to the micro-pores ceramic heat sink. | 2010-01-28 |
20100019381 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device and method of manufacturing a semiconductor device. One embodiment provides an electrically conductive carrier. A semiconductor chip is placed over the carrier. An electrically insulating layer is applied over the carrier and the semiconductor chip. The electrically insulating layer has a first face facing the carrier and a second face opposite to the first face. A first through-hole is in the electrically insulating layer. Solder material is deposited in the first through-hole and on the second face of the electrically insulating layer. | 2010-01-28 |
20100019382 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A technique permitting the reduction in size of a semiconductor device is provided. In a BGA type semiconductor device with a semiconductor chip flip-chip-bonded onto a wiring substrate, bump electrodes of the semiconductor chip are coupled to lands formed at an upper surface of the wiring substrate. The lands at the upper surface of the wiring substrate are coupled electrically to solder balls formed on a lower surface of the wiring substrate. Therefore, the lands include first type lands with lead-out lines coupled thereto and second type lands with lead-out lines not coupled thereto but with vias formed just thereunder. The lands are arrayed in six or more rows at equal pitches in an advancing direction of the rows. However, a row-to-row pitch is not made an equal pitch. In land rows which are likely to cause a short-circuit, the pitch between adjacent rows is made large, while in land rows which are difficult to cause a short-circuit, the pitch between adjacent rows is made small. By so doing, both prevention of a short-circuit and improvement of the layout density of lands are attained at a time. | 2010-01-28 |
20100019383 | METHOD OF FORMING WIRING ON A PLURALITY OF SEMICONDUCTOR DEVICES FROM A SINGLE METAL PLATE, AND A SEMICONDUCTOR CONSTRUCTION ASSEMBLY FORMED BY THE METHOD - In this manufacturing method of a semiconductor device, a metal plate having a plurality of projection electrodes in each of a plurality of semiconductor device formation areas is prepared. Next, the projection electrodes of each of the semiconductor formation areas are aligned corresponding to external connection electrodes of each semiconductor construction, and each semiconductor construction is separately arranged on the projection electrodes in the semiconductor device formation areas. Next, an insulating layer formation sheet is arranged on the metal plate, and the metal plate and the insulating layer formation sheet are joined by heat pressing. Then, the metal plate is patterned and a plurality of upper layer wirings that connect to the projection electrodes is formed. | 2010-01-28 |
20100019384 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THEREOF, CIRCUIT BOARD AND ELECTRONIC APPARATUS - A semiconductor device is provided comprising: a semiconductor element including a plurality of electrodes; first wirings coupled to the electrodes and directed toward a center of the semiconductor element from a portion coupled to the electrodes; second wirings coupled between the first wirings and external terminals, the second wirings being directed to an outer area of the semiconductor element relative to the center; and at least one resin layer formed between the first wirings and the second wirings. | 2010-01-28 |
20100019385 | Implementing Reduced Hot-Spot Thermal Effects for SOI Circuits - Methods and structures are provided for implementing reduced hot spot thermal effects for silicon-on-insulator (SOI) circuits. A silicon-on-insulator (SOI) structure includes a silicon substrate layer, a thin buried oxide (BOX) layer carried by the silicon substrate layer, an active layer carried by the thin BOX layer, and a pad oxide layer carried by the active layer. A thermal conductive path is built to reduce thermal effects of a hotspot area in the active layer and extends from the active layer to the backside of the SOI structure. A trench etched from the topside to the active layer, and is filled with a thermal connection material. A thermal connection from a backside of the SOI structure includes an opening etched into the silicon substrate layer from the backside and filled with a thermal connection material. | 2010-01-28 |
20100019386 | ELECTRICAL CONDUCTOR LINE HAVING A MULTILAYER DIFFUSION BARRIER FOR USE IN A SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - An electrical conductor having a multilayer diffusion barrier of use in a resultant semiconductor device is presented. The electrical conductor line includes an insulation layer, a diffusion barrier, and a metal line. The insulation layer is formed on a semiconductor substrate and having a metal line forming region. The diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and has a multi-layered structure made of TaN layer, an Mo | 2010-01-28 |
20100019387 | Semiconductor device and fabrication method of the same - A semiconductor device which comprises an SOI substrate having an insulating layer between a semiconductor substrate layer and a semiconductor layer in a surface of which a semiconductor element is formed, and at least one external terminal provided, via an insulating film, on a surface of the semiconductor substrate layer and electrically connected to the semiconductor element. The semiconductor device further comprises a contact portion constituted by a conductive film reaching through the insulating film to electrically connect to the semiconductor substrate layer; and a potential fixing electrode provided, via the insulating film, on the surface of the semiconductor substrate layer and connected to the contact portion. | 2010-01-28 |
20100019388 | METHOD FOR AN INTEGRATED CIRCUIT CONTACT - A process for forming vertical contacts in the manufacture of integrated circuits and devices eliminating the need for precise mask alignment and allowing the etching of the contact hole controlled independent of the etching of the interconnect trough that may be repeated during the formation of multilevel integrated circuits. The process includes forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. | 2010-01-28 |
20100019389 | ELECTRIC LINKAGE IN A SEMICONDUCTOR ELECTRONIC DEVICE BETWEEN A NANOMETRIC CIRCUIT ARCHITECTURE AND STANDARD ELECTRONIC COMPONENTS - A semiconductor electronic device that includes a semiconductor substrate having a top surface; a seed layer positioned on the substrate and having a notched wall extending transversely with respect to the substrate top surface, the wall defining a first recess extending into the seed layer with a height equal to a thickness of the seed layer; a first conductive nanowire in contact with the notched wall, the first conductive nanowire having a contact portion extending into the first recess and covering opposite sidewalls and a bottom of the first recess; a first insulating nanowire in contact with a sidewall of the first conductive nanowire; an insulating layer on the contact portion of the first conductive nanowire and having a first window substantially in correspondence with the contact portion of the first conductive nanowire; and a first conductive die on the insulating layer that includes a conductive contact extending into the first window and contacting the contact portion of the first conductive nanowire. | 2010-01-28 |
20100019390 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR CHIP, MANUFACTURING METHODS THEREOF, AND STACK PACKAGE - A manufacturing method includes sequentially forming first and second material layers having different etch selectivities in a laminated fashion, patterning the second material layer, to form an etch mask, etching the first material layer using the etch mask, to form a via hole in the first material layer, forming a photo mask over the etch mask such that a region larger than the via hole is exposed through the photo mask, etching the etch mask using the photo mask, removing the photo mask, and forming a metal material over the first material layer, to fill the via hole. Accordingly, it is possible to prevent formation of a side wall undercut in a deep via etching process, and thus to ease subsequent processes for forming an oxide barrier film, a barrier metal film, and a metal layer. | 2010-01-28 |
20100019391 | Semiconductor Device - This application relates to a semiconductor device comprising a first chip comprising a first electrode on a first face of the first chip, and a second chip attached to the first electrode, wherein the second chip comprises a transformer comprising a first winding and a second winding. | 2010-01-28 |
20100019392 | STACKED DIE PACKAGE HAVING REDUCED HEIGHT AND METHOD OF MAKING SAME - A stacked die package is disclosed. The stacked die package includes a wire-bond die that is electrically coupled to other components via one or more wire bonds and a flip-chip die that is coupled to the top surface of the wire-bond die via one or more solder joints. The wire-bond die is formed underneath the flip-chip die. A space defined by the height of the loops of the one or more wire-bonds overlap a space defined by the thickness of one or more solder joints. | 2010-01-28 |
20100019393 | PACKAGING STRUCTURE FOR INTEGRATION OF MICROELECTRONICS AND MEMS DEVICES BY 3D STACKING AND METHOD FOR MANUFACTURING THE SAME - A packaging structure for integration of microelectronics and MEMS devices by 3D stacking is disclosed, which comprises: an ASIC unit, comprising a first substrate and a circuit layout formed on a surface of the first substrate, wherein a cavity is formed on the other surface and at least a through hole is formed on the ASIC unit; and a MEMS unit, comprising a second substrate and a micro sensor disposed on the second substrate; wherein the micro sensor is disposed in the cavity and there is a conductive material filling the through hole so that the ASIC unit and the MEMS unit can be electrically connected to each other when the ASIC unit is attached onto the MEMS unit. | 2010-01-28 |
20100019394 | IC CHIP MOUNTING PACKAGE - In one embodiment of the present invention, an IC chip mounting package includes a film base member and an IC chip connected via an interposer. Connecting terminals on the film base member side of the interposer are provided so as to have a pitch larger than that of connecting terminals of the IC. A device hole is opened to the film base member, and the IC chip is provided in the device hole. A distance between an inner lead leading end and a periphery of the device hole is set as not less than 10 μm. | 2010-01-28 |
20100019395 | METHOD AND APPARATUS FOR IMPROVEMENTS IN CHIP MANUFACTURE AND DESIGN - A method of securing a bond pad in to a semiconductor chip having an upper top metal surface which includes one or more holes, the method comprising the steps of forming a passivation layer over the upper metal surface, which passivation layer has holes therein substantially corresponding to the or each hole in the upper metal layer and being substantially the same size or smaller than the holes in the upper metal layer; forming the bond pad over the passivation layer; characterised in that the step of forming the bond pad comprises introducing some of the material from the bond pad into the holes in the passivation layer and upper metal layer when forming the bond pad, securing the bond pad to the passivation layer by allowing said material to flow under the surface thereof and attach thereto without attaching to the upper metal layer to thereby form a securing means. | 2010-01-28 |
20100019396 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device may be fabricated according to a method that reduces stain difference of a passivation layer in the semiconductor device. The method may include forming top wiring patterns in a substrate, depositing a primary undoped silicate glass (USG) layer on the top wiring patterns to fill a gap between the top wiring patterns, and coating a SOG layer on the substrate on which the primary USG layer has been deposited. Next, the SOG layer on the surface of the substrate may be removed until the primary USG layer is exposed, and a secondary USG layer may be deposited on the substrate on which the primary USG layer has been exposed. | 2010-01-28 |
20100019397 | ELECTRICAL CONNECTIONS FOR MULTICHIP MODULES - Conductive lines are formed on a wafer containing multiple circuits. The conductive lines are isolated from the circuits formed within the wafer. Chips are mounted on the wafer and have their chip pads connected to the conductive lines of the wafer. The wafer may then be protected with a packaging resin and singulated | 2010-01-28 |
20100019398 | STRUCTURED SEMICONDUCTOR ELEMENT FOR REDUCING CHARGING EFFECTS - A semiconductor circuit element for reducing undesirable charging effects for a connection element of test structures for semiconductor circuits is disclosed. A surface of a semiconductor circuit element has interconnect structures that are electrically insulated from the remainder of the surface of the semiconductor circuit element, where exclusively the interconnect structures are connected to semiconductor circuit elements arranged downstream. | 2010-01-28 |
20100019399 | POLYORGANOSILOXANE COMPOSITION - Disclosed is a polyorganosiloxane composition containing the following components (a)-(c). (a) 100 parts by mass of a polyorganosiloxane obtained by mixing at least one silanol compound represented by the general formula (1) below, at least one alkoxysilane compound represented by the general formula (2) below, and at least one catalyst selected from the group consisting of compounds represented by the general formula (3) below, compounds represented by the general formula (4) below and Ba(OH) | 2010-01-28 |
20100019400 | WVT DESIGN FOR REDUCED MASS AND IMPROVED SEALING RELIABILITY - A membrane humidifier for a fuel cell system is disclosed wherein the membrane humidifier includes a plurality of membrane layers, a first pair of spaced apart sealing bars disposed between a first membrane layer and a second membrane layer adjacent to perimeter edges thereof to form a first flow channel, a second pair of spaced apart sealing bars disposed between the second membrane layer and a third membrane layer adjacent to perimeter edges thereof to form a second flow channel, and a plurality of supports, wherein a first support is disposed adjacent the second planar layer and extending between the second pair of spaced apart sealing bars, and a second support is disposed adjacent the third planar layer and extending between the second pair of spaced apart sealing bars. | 2010-01-28 |
20100019401 | METHOD FOR MANUFACTURING OPTICAL WAVEGUIDE - A resin layer | 2010-01-28 |
20100019402 | MOLDING METHOD FOR AN OPTICAL ELEMENT AND OPTICAL ELEMENT MOLDING APPARATUS - In a molding apparatus in which upper and lower dies are held in a bearing, there are provided pipes for introducing N | 2010-01-28 |
20100019403 | PRODUCTION AND RECOVERY OF POLYMERIC MICRO- AND NANOPARTICLES CONTAINING BIOACTIVE MACROMOLECULES - The present invention describes a method to encapsulate bioactive macromolecules, as example but not limited for, peptidic drugs, into polymeric particles sizing less than 10 μm of diameter Particle production is based on emulsification/internal gelation procedure and comprises a formation of a water-in-oil emulsion followed by solubilization of dispersed insoluble calcium complex triggering gelation of said polymer dispersed in internal phase, by ionic cross-linking with free calcium ions. Finally, resulting gelled particles dispersed in the oil phase are recovered by partition phases coupled with high speed centrifugation cycles. In this case, the present invention describes a precise methodology to recover said gelled polymeric particles after particle production and includes an addition of acetate buffer solution at predetermined pH, dehydrating agents and residual oil dissolvent agent, at predetermined concentration, followed by high speed centrifugation cycles. This method of production and recovery was applied to the macromolecule, insulin, and demonstrated that the bioactivity of said peptidic drug was preserved. | 2010-01-28 |
20100019404 | Installation and a Method for Scraping a Bed-Plate of a Compounder - An installation for fabricating a mass of rubber comprises a vessel for compounding the mass of rubber. The vessel includes an outlet opening for the mass of rubber; a gate for closing the opening and movable between a position in which the opening is closed, and a position in which the opening is disengaged; scraper means for scraping the rubber adhering to a so-called internal surface of the gate, this device including a movable scraper member comprising an edge designed to scrape the rubber adhering to the internal surface; and synchronization means for synchronizing the movements of the gate and of the scraper member. | 2010-01-28 |
20100019405 | Tool for a Resin Transfer Moulding Method - A tool for a resin transfer moulding method comprises a cavity, a resin trap and a transition region, wherein the cavity is designed such that a component can be accommodated in it. Furthermore, the resin trap is integrated in the tool, and the transition region is designed such that with it a connection between the cavity and the resin trap can be established. | 2010-01-28 |
20100019406 | METHOD FOR ROTATIONAL MOULDING OF A CYLINDRICAL PRODUCT - A method for rotational moulding of a cylindrical product, preferably a soft PVC plastic fender, comprising a) arranging an open-end ( | 2010-01-28 |
20100019407 | Small Volume In Vitro Sensor and Methods of Making - A sensor utilizing a non-leachable or diffusible redox mediator is described. The sensor includes a sample chamber to hold a sample in electrolytic contact with a working electrode, and in at least some instances, the sensor also contains a non-leachable or a diffusible second electron transfer agent. The sensor and/or the methods used produce a sensor signal in response to the analyte that can be distinguished from a background signal caused by the mediator. The invention can be used to determine the concentration of a biomolecule, such as glucose or lactate, in a biological fluid, such as blood or serum, using techniques such as coulometry, amperometry, and potentiometry. An enzyme capable of catalyzing the electrooxidation or electroreduction of the biomolecule is typically provided as a second electron transfer agent. | 2010-01-28 |
20100019408 | MINUTE FLOW PATH STRUCTURE BODY AND DIE - A fine channel device containing a fine channel substrate that includes a fine channel for channeling fluids, and through holes, wherein the fine channel and the through holes are interconnected via an interconnection portion, as well as a mold that is equipped with pins forming the through holes in the fine channel substrate, wherein the positions of the pins and the number pins be altered as desired. | 2010-01-28 |
20100019409 | Method for fabricating a hollow replica of a pre-existing object and converting the replica into a lighted interchanging aesthetic display device - A fabrication method involving unique steps for creating a hollow replica of a pre-existing object and then converting the replica into an aesthetically pleasing light show display device having internal lighted interchanging lights that illuminate the device producing a light-show that is eye-catching, soothing and mesmerizing. | 2010-01-28 |
20100019410 | Resin for Thermal Imprinting - A cyclic-olefin-based thermoplastic resin for thermal imprint to be used in the production of a sheet or a film which contains at least one of skeletons represented by the following chemical equation 1 or the following chemical equation 2 in a main chain. The glass transition temperature Tg (° C.) and the value ([M]) of MFR at 260° C. satisfy the following equation 1, and [M]<30. The thermal imprint characteristics (transferability, mold release characteristic, and the like) are superior and the productivity (throughput) is improved. | 2010-01-28 |
20100019411 | METHOD OF MOLDING COMPOSITE MOLDED ARTICLE AND MOLD SYSTEM USED FOR SAME - [Problem] To provide a method of molding a composite molded article enabling compression molding without requiring a large sized injection molding machine and a mold system used for that. | 2010-01-28 |
20100019412 | METHOD OF MANUFACTURING A THERMAL INSULATION ARTICLE - A method of manufacturing a thermal insulation article may include positioning, between opposing mold walls, a first layer comprising a ceramic matrix composite (CMC) material and a second layer comprising a plurality of tiles. The method may further include moving the opposing mold walls together to compress together the first and second layers, and curing the compressed together first and second layers to produce the thermal insulation article. | 2010-01-28 |
20100019413 | MOLDED FIBER LID FOR A CONTAINER - A container lid formed of cellulose material is provided for mating with a base container to securely hold various items, such as food items. The container lid includes a body having a main portion and a perimeter, and a skirt extending substantially around the perimeter of the body. The skirt includes a shoulder and an intermediate member connected with the shoulder. The intermediate member extends inwardly towards the base container when mating therewith. The intermediate member and skirt cooperatively form a channel or undercut for receiving the base container so that the base container and lid may be interlocked together. | 2010-01-28 |
20100019414 | Method and Device for the Production of Plastic Packaging Containers - A method and a device for the manufacture of plastic packagings, the same being manufactured by stretch blowing a bottle-like preliminary packaging which is, after completion, treated by means of a laser and thus reshaped to the final packaging. Also, a plastic container manufactured according to this method and with this device. | 2010-01-28 |
20100019415 | METHOD FOR MAKING A FORMING STRUCTURE - A method for making a forming structure. The steps of the method include providing a forming unit, providing a backing film, providing a foraminous element, employing liquid photosensitive resin to form the forming structure, and laser machining a plurality of generally columnar protrusions into the forming structure. | 2010-01-28 |
20100019416 | Acoustic Pannelling Part for a Vehicle - A cover part for a vehicle, especially an underbody cover, has a porous core layer and at least one cover layer on each side, wherein the porous core layer is constructed such that it has acoustic transparency or an acoustically absorbent effect. Here, the porous core layer is made either from a thermoplastic matrix with embedded reinforcement fibers, especially glass fibers, whose melting point temperature is higher than the melting point temperature of the plastic matrix, or from a foam, which is either open-cell or closed-cell and perforated. The acoustically absorbent porous core layer is occupied on one or both sides with one or more acoustically transparent or absorbent covering layers. | 2010-01-28 |
20100019417 | DEVICE AND METHOD FOR CURING HEARING AID HOUSINGS - A device and a method for curing plastic moldings are particularly suited for curing hearing aid housings. A light source emits curing light and a holder, at least partially transparent to curing light, holds the plastic moldings. The holder has an elongate light guiding element, which is transparent to curing light, which has an emission portion for emitting curing light in a number of spatial directions, and which is formed in such a way that at least the emission portion can protrude into a convex curvature or an interior space of a plastic molding that is being held by the holder. The light guiding element guides curing light emitted from the light source to the emission portion and emits from there. The light guiding element may have a holding portion for holding the plastic molding. The holding portion and the emission portion may spatially overlap. The method includes a step of irradiating the plastic molding with curing light simultaneously on the outside and the inside by the light source and by the light guiding element. Particularly uniform curing without localized temperature peaks is achieved. | 2010-01-28 |
20100019418 | METHOD FOR MANUFACTURING A REVOLVING SHAFT ASSEMBLY - A method for manufacturing a revolving shaft assembly includes the steps of: 1) offering a plurality of first nonmetallic powder; 2) offering a plurality of second nonmetallic powder; 3) offering a mold cavity and filling the first and second nonmetallic powder in the mold cavity to form a green piece, wherein a plurality of pores is defined in the green piece; 4) heating the green piece at a temperature between 1100° C. and 1550° C. to sinter the nonmetallic powder to obtain a sintered product; 5) dipping the sintered product in lubricant oil to make the lubricant oil enter the pores of the sintered product to thereby obtain a final desired product. | 2010-01-28 |
20100019419 | CHROMIA-ALUMINA REFRACTORY - A refractory composition comprising at least 50 weight percent chromic oxide (Cr | 2010-01-28 |
20100019420 | UPPER NOZZLE/PLATE INTEGRAL UNIT AND METHOD OF SPLITTING THE SAME - Disclosed is an upper nozzle/plate integral unit comprising an upper nozzle and an upper plate integrated together, which is capable of being easily split into the upper nozzle and the upper plate after use, while adequately maintaining a thickness of a joint between the upper nozzle and the upper plate during use. A metal casing | 2010-01-28 |
20100019421 | MUD GUN CAP - A mud gun cap is provided. The mud gun cap includes a flame resistant outer face, a ring and a mounting device wherein the mud gun cap connects to a mud gun nozzle to protect the mud gun nozzle from deterioration because of contact with molten iron and slag. The mud gun cap also prevents, or at least reduces the amount of, mud falling out of the nozzle while the mud gun nozzle is rotated into operation position. | 2010-01-28 |
20100019422 | Countercurrent direct-heating-type heat exchanger - The countercurrent direct-heating-type heat exchanger that is able to suppress drift in the case when a fluid to be heated is supplied, to prevent local abrasion of the members and also to carry out efficient heat exchange. | 2010-01-28 |
20100019423 | Method for the monobloc sizing for the tempering casings and device for implementing the method - A device for implementing a method of sizing a cylindrical part following shaping, by plastic deformation, of a metallic material that has maximum structural shrinkage at a maximum-shrinkage temperature between a first temperature and a second temperature, which is lower than the first temperature, is disclosed. The method includes placing the part in a shaft furnace, heating the part to the first temperature, lowering and fitting into the part an internal-sizing tool with an outer diameter greater than an inner diameter of the part at maximum structural shrinkage, transporting the assembly formed by the part and the sizing tool to a tempering vessel, cooling the part to a temperature below said second temperature, and extracting the internal-sizing tool. The method applies to the manufacture of turbomachine casings. | 2010-01-28 |
20100019424 | MOUNT DEVICES AND METHODS FOR MEASURING FORCE - Devices and methods are provided to facilitate measurement of forces acting on locations connecting a subframe portion and a body portion of a vehicle, such devices and methods include mount devices having an inner member, an outer member, at least one sensor, a sleeve and an annular member. The sensor is disposed within an annular chamber formed between the inner member and the outer member. The sensor is attached to at least one of the inner member and the outer member. The sensor is configured to measure force exerted on the mount device during use of a vehicle. Vehicles including these mount devices are also provided. | 2010-01-28 |
20100019425 | VIBRATIONAL ENERGY ABSORBING APPARATUS - A vibrational energy absorbing apparatus | 2010-01-28 |
20100019426 | SPRING/SEAL ELEMENT - The present invention relates to a spring element. The spring element includes a metal ring with a central aperture and radial pleats formed on the metal ring. The radial pleats flatten when pressure is applied axially to compress the ring such that the metal ring increases in effective diameter. The seal element may be used to radially seal an annular bore. | 2010-01-28 |
20100019427 | CLAMPING DEVICE OF INDEXING DEVICE FOR MACHINE TOOL - A clamping device for holding an indexed angular position of a main shaft includes a clamp section non-rotatable relative to the main shaft, and a pressing mechanism including a clamp piston displaceable in an axial direction of the main shaft and causing a fluid pressure received by the clamp piston to act on the clamp section. The clamp section includes a first clamp portion being non-rotatable relative to the main shaft, and a second clamp portion being rotatable with the main shaft. The pressing mechanism includes first and second pressing portions which respectively press the first and second clamp portions. The second clamp portion or the second pressing portion is elastically displaced when the clamp piston advances by the fluid pressure. Forces in axial and radial directions are respectively applied to the first and second clamp portions, thereby clamping the main shaft. | 2010-01-28 |
20100019428 | Clamping Fixture - The clamping fixture comprises a chuck ( | 2010-01-28 |
20100019429 | CLAMPING DEVICE - Disclosed is a clamping device for securing and clamping work-piece quickly and efficiently. The clamping device includes an elongated slide bar; a first support assembly and a second support assembly. The first support assembly affixed at a proximal end portion of the elongated slide bar includes a first body portion, and a first clamping member. The second support assembly includes a second body portion, a second clamping member configured on the second body portion, and a locking mechanism configured on the second body portion. The second body portion is slidably coupled to the elongated slide bar for assuming a plurality of positions with respect to the first body portion. The first clamping member and the second clamping member are positioned in a spaced apart relationship for abuttingly clamping the work-piece there between to assume a clamped position of the plurality of positions. | 2010-01-28 |
20100019430 | Magnetic cutting board - A cutting board comprising a base and a working board held together by magnets, aligning pins, or fingers on the base gripping the working cutting board. The base has cut-outs so that a plate, tray, or shallow bowl can be slid under the board permitting the cuttings to be slid off the board into the bowl without having to lift the board, likely tilting it and spilling the cuttings and/or juices or dumping separated portions of the cut food. | 2010-01-28 |