04th week of 2016 patent applcation highlights part 60 |
Patent application number | Title | Published |
20160027723 | SEMICONDUCTOR DEVICE - This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a peripheral area of the upper surface of a multilayer wiring substrate are separated into inner and outer ones and a plurality of signal through holes coupled to a plurality of signal wirings drawn inside are located between a plurality of rows of signal bonding electrodes and a central region where a plurality of bonding electrodes for core power supply are located so that the chip pad pitch can be decreased and the cost of the BGA can be reduced without an increase in the number of layers in the multilayer wiring substrate. | 2016-01-28 |
20160027724 | WIRING BOARD - The wiring board of the present invention includes at least one insulating layer and at least one conductor layer being alternately laminated, a semiconductor element connection pad formed on an upper surface of the insulating layer at an uppermost layer of the insulating layers, a cap connection pattern arranged so as to surround a region where the semiconductor element connection pad is formed, and at least one strip-shaped pattern extending from the semiconductor element connection pad to a region outside an end portion on the region side of the cap connection pattern. The cap connection pattern is formed by a plurality of island-shaped patterns spaced apart from one another, and the strip-shaped pattern is formed between the adjacent island-shaped patterns on the upper surface of the insulating layer at the uppermost layer. | 2016-01-28 |
20160027725 | MULTILAYER WIRING BOARD AND METHOD FOR MANUFACTURING SAME - A multilayer wiring board includes a main wiring board which mounts a semiconductor component on a surface of the main wiring board, and a wiring structure body which is mounted to the main wiring board and is formed to be electrically connected to the semiconductor component. The wiring structure body includes conductive pads formed on a first side of the wiring structure body, a heat radiation component formed on a second side of the wiring structure body on the opposite side with respect to the first side, an insulation layer positioned between the conductive pads and the heat radiation component, and via conductors formed in the insulation layer such that each of the via conductors has a diameter which increases from the first side toward the second side of the wiring structure body. | 2016-01-28 |
20160027726 | SEMICONDUCTOR DEVICE HAVING AN AIRGAP DEFINED AT LEAST PARTIALLY BY A PROTECTIVE STRUCTURE - An apparatus includes a first interconnect and a first barrier structure. The first barrier structure is in contact with a dielectric material. The apparatus further includes a first protective structure in contact with the first barrier structure and an etch stop layer. An airgap is defined at least in part by the first protective structure and the etch stop layer. | 2016-01-28 |
20160027727 | SEMICONDUCTOR DEVICE WITH AIR GAPS AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a first plug; a bit line which is in contact with the first plug and over the first plug and extended in one direction; a second plug including a first part adjacent to the bit line and a second part adjacent to the first plug; a double air gap which is disposed between the first part of the second plug and the bit line and includes a first air gap surrounding the first part of the second plug and a second air gap parallel to sidewalls of the bit line; and a capping layer suitable for capping the first and second air gaps. | 2016-01-28 |
20160027728 | NOISE SHIELDING TECHNIQUES FOR ULTRA LOW CURRENT MEASUREMENTS IN BIOCHEMICAL APPLICATIONS - A device having an integrated noise shield is disclosed. The device includes a plurality of vertical shielding structures substantially surrounding a semiconductor device. The device further includes an opening above the semiconductor device substantially filled with a conductive fluid, wherein the plurality of vertical shielding structures and the conductive fluid shield the semiconductor device from ambient radiation. In some embodiments, the device further includes a conductive bottom shield below the semiconductor device shielding the semiconductor device from ambient radiation. In some embodiments, the opening is configured to allow a biological sample to be introduced into the semiconductor device. In some embodiments, the vertical shielding structures comprise a plurality of vias, wherein each of the plurality of vias connects more than one conductive layers together. In some embodiments, the device comprises a nanopore device, and wherein the nanopore device comprises a single cell of a nanopore array. | 2016-01-28 |
20160027729 | INVERTED-T SHAPED VIA FOR REDUCING ADVERSE STRESS-MIGRATION EFFECTS - A semiconductor interconnect structure is formed as a via with an inverted-T shape to increase the reliability of the interface between the interconnect structure and an underlying electrically conductive, e.g., copper (Cu), layer of material. The inverted-T shape effectively increases a bottom critical dimension of the via, thereby reducing and/or eliminating via degradation of the interconnect structure caused by voids in the electrically conductive layer introduced during high-temperature or stress-migration baking. | 2016-01-28 |
20160027730 | INTERCONNECTION STRUCTURE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME - An interconnection structure may include insulating layers stacked stepwise and dielectric layers interposed between the insulating layers. The interconnection structure may include conductive layers interposed between the insulating layers and surrounding sidewalls of the dielectric layers, respectively. The interconnection structure may include contact plugs each coupled to one of the conductive layers. The contact plugs may at least partially pass through the dielectric layers. | 2016-01-28 |
20160027731 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad. | 2016-01-28 |
20160027732 | SEMICONDUCTOR DEVICE - Characteristics of a semiconductor device are improved. A semiconductor device includes a coil CL | 2016-01-28 |
20160027733 | BACK-END ELECTRICALLY PROGRAMMABLE FUSE - A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current. | 2016-01-28 |
20160027734 | E-FUSE STRUCTURE WITH METHODS OF FUSING THE SAME AND MONITORING MATERIAL LEAKAGE - The present disclosure generally provides for an e-fuse structure and corresponding method for fusing the same and monitoring material leakage. The e-fuse structure can include a metal dummy structure and an electrical fuse link substantially aligned with a portion of the metal dummy structure, wherein the metal dummy structure cools at least part of the electrical fuse link in response to an electric current passing through the electrical fuse link. | 2016-01-28 |
20160027735 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as “a”, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as “b”, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET. | 2016-01-28 |
20160027736 | SEMICONDUCTOR DEVICE - A semiconductor device SD includes a substrate SUB, a plurality of gate electrodes GE, a gate pad GEP, and gate interconnects GINC. The plurality of gate electrodes GE are formed in the substrate SUB, and extend electrically in parallel to each other. The gate pad GEP is formed in a region different from that in which the plurality of gate electrodes GE are formed in the substrate SUB. Each of a plurality of gate interconnects GINC connects the plurality of gate electrodes GE to the gate pad GEP. | 2016-01-28 |
20160027737 | Stretchable Form of Single Crystal Silicon for High Performance Electronics on Rubber Substrates - The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices. | 2016-01-28 |
20160027738 | SEMICONDUCTOR DEVICE WITH REDUCED VIA RESISTANCE - A semiconductor interconnect structure having a first electrically conductive structure having a plurality of bottom portions; a dielectric capping layer, at least a portion of the dielectric capping layer being in contact with a first bottom portion of the plurality of bottom portions; and a second electrically conductive structure in electrical contact with a second bottom portion of the plurality of bottom portions. A method of forming the interconnect structure is also provided. | 2016-01-28 |
20160027739 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING ALIGNMENT MARKS TO ALIGN LAYERS - A method of manufacturing a semiconductor device includes forming a first alignment mark trench in a first material layer on a substrate. A first alignment mark via may then be formed by etching a second material layer that is underneath the first material layer, where the first alignment mark via is positioned to communicate with the first alignment mark trench. Then, a trench-via-merged-type first alignment mark may be formed by filling the first alignment mark trench and the first alignment mark via with a light reflection material layer. | 2016-01-28 |
20160027740 | PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME - A package structure includes a carrier, an electronic component disposed on the carrier, an encapsulant formed on the carrier for encapsulating the electronic component, a first shielding layer formed on the encapsulant, and a second shielding layer formed on the first shielding layer. The first and second shielding layers are made of different materials. With the multiple shielding layers formed on the encapsulating layer, the electronic component is protected from electromagnetic interferences. The present invention also provides a method for fabricating the package structure. | 2016-01-28 |
20160027741 | SEMICONDUCTOR PACKAGES HAVING EMI SHIELDING LAYERS, METHODS OF FABRICATING THE SAME, ELECTRONIC SYSTEMS INCLUDING THE SAME, AND MEMORY CARDS INCLUDING THE SAME - Semiconductor packages are provided. In some embodiments, the semiconductor package includes a substrate, a first ground line including a first internal ground line disposed along edges of the substrate and a plurality of first extended ground lines between the first internal ground line and sidewalls of the substrate, a chip on the substrate, a molding member disposed on the substrate to cover the chip, and an electromagnetic interference (EMI) shielding layer covering the molding member, the EMI shielding layer extending along the sidewalls of the substrate and contacting the end portions of the plurality of first extended ground lines. The plurality of first extended ground lines include end portions that are exposed at the sidewalls of the substrate. | 2016-01-28 |
20160027742 | PORTABLE APPARATUS, IC PACKAGING STRUCTURE, IC PACKAGING OBJECT, AND IC PACKAGING METHOD THEREOF - A portable apparatus, an IC packaging structure, an IC packaging object, and an IC packaging method thereof are disclosed. The IC packaging structure includes an IC packaging object and a substrate. The packaging object includes a die and a metallurgy layer. The die has a contact portion, a saw reserved portion, and a seal ring. The seal ring is disposed between the contact portion and the saw reserved portion. The metallurgy layer is disposed on the contact portion. At least a part of the metallurgy layer overlaps the seal ring. The metallurgy layer includes a solderable layer coated by a solder paste. The substrate includes a solder pad. The solder pad is coupled to the solderable layer coated by the solder paste. | 2016-01-28 |
20160027743 | SEMICONDUCTOR DEVICE - One semiconductor device includes, in a memory mat, a plurality of memory cells having a plurality of capacitors including cylindrical lower electrodes. The semiconductor device includes a first support film pattern group having a plurality of polygonal support film patterns as seen in plan view within the memory mat, wherein each supports sidewalls of corresponding lower electrodes, and a second support film pattern group having a plurality of polygonal support film patterns as seen in plan view within the memory mat, wherein each supports sidewalls of corresponding lower electrodes. The second support film pattern group is formed above the first support film pattern group so that periphery vertices of the respective polygons, as seen in plan view, do not overlap with each other. | 2016-01-28 |
20160027744 | METHOD OF FORMING AN INTEGRATED CRACKSTOP - A method including forming a first dielectric layer above a conductive pad and above a metallic structure, the conductive pad and the metallic structure are each located within an interconnect level above a substrate, forming a first opening and a second opening in the first dielectric layer, the first opening is aligned with and exposes the conductive pad and the second opening is aligned with and exposes the metallic structure, and forming a metallic liner on the conductive pad, on the metallic structure, and above the first dielectric layer. The method may further include forming a second dielectric layer above the metallic liner, and forming a third dielectric layer above the second dielectric layer, the third dielectric layer is thicker than either the first dielectric layer or the second dielectric layer. | 2016-01-28 |
20160027745 | LIGHT EMITTING DEVICE - The present disclosure provides a light emitting device including a serially-connected LED array comprising a plurality of LED cells on a substrate. The serially-connected LED array includes a first LED cell, a second LED cell, and a serially-connected LED sub-array comprising at least three LED cells intervening between the first and second LED cell; and a plurality of conducting metals formed on the LED cells to electrically connect the plurality of LED cell in series; wherein among the LED sub-array which are continuously and sequentially connected by the conducting metals, each LED cell connects to a previous LED cell by a first connecting direction and connects to a next LED cell by a second connecting direction, the first connecting direction is not parallel to the second connecting direction. | 2016-01-28 |
20160027746 | Semiconductor Chip and Method for Forming a Chip Pad - A semiconductor chip with different chip pads and a method for forming a semiconductor chip with different chip pads are disclosed. In some embodiments, the method comprises depositing a barrier layer over a chip front side, depositing a copper layer after depositing the barrier layer, and removing a part of the copper layer located outside a first chip pad region, wherein a remaining portion of the copper layer within the first chip pad region forms a surface layer of the chip pad. The method further comprises removing a part of the barrier layer located outside the first chip pad region. | 2016-01-28 |
20160027747 | SEMICONDUCTOR DEVICE WITH FINE PITCH REDISTRIBUTION LAYERS - A semiconductor device with fine pitch redistribution layers is disclosed and may include a semiconductor die with a bond pad and a first passivation layer comprising an opening above the bond pad. A redistribution layer (RDL) may be formed on the passivation layer with one end of the RDL electrically coupled to the bond pad and a second end comprising a connection region. A second passivation layer may be formed on the RDL with an opening for the connection region of the RDL. An under bump metal (UBM) may be formed on the connection region of the RDL and a portion of the second passivation layer. A bump contact may be formed on the UBM, wherein a width of the RDL is less than a width of the opening in the second passivation layer and may be constant from the bond pad through at least a portion of the opening. | 2016-01-28 |
20160027748 | METHOD OF FORMING A MEMORY DEVICE - A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication. | 2016-01-28 |
20160027749 | TEST CIRCUIT UNDER PAD - Aspects of the present invention relate to the arrangement of points of interconnection of integrated circuit die to the package in which they are enclosed. More specifically, aspects of the present invention pertain to an arrangement of bond pads over the active circuitry of an integrated circuit die, in order to permit a reduction in size of the die. An embodiment of the present invention may place a first bond pad over the active area of an integrated circuit, wherein the first bond pad is electrically coupled to a second bond pad outside of the active area of the integrated circuit. Production and delivery of the integrated circuit may proceed using the second bond pad during packaging, in parallel with the testing of packaging using the first bond pad. When processes related to the use of the first bond pad have been proven successful and sustainable, the second bond pad may be eliminated, resulting in a reduction of the size of the integrated circuit device. This approach may be employed to save die area, increasing the number of devices that may be produced on a silicon wafer, resulting in a reduction in device cost. The approach of the present invention works well whether the chip is pad or core limited. Although reference has been made to the used of this technique on a silicon wafer, an embodiment of the present invention may be employed in the fabrication of integrated circuit device using other materials as well, without departing from the spirit and scope of the present invention. | 2016-01-28 |
20160027750 | Methods and Apparatus for Transmission Lines in Packages - Methods and apparatus for forming a semiconductor device package with a transmission line using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, formed between a top device and a bottom device. A signal transmission line may be formed using a micro-bump line above a bottom device. A ground plane may be formed using a redistribution layer (RDL) within the bottom device, or using additional micro-bump lines. The RDL formed ground plane may comprise open slots. There may be RDLs at the bottom device and the top device above and below the micro-bump lines to form parts of the ground planes. | 2016-01-28 |
20160027751 | SEMICONDUCTOR DEVICE HAVING SOLDER JOINT AND METHOD OF FORMING THE SAME - Provided is a semiconductor device having a high-reliability solder joint. The semiconductor device includes a high-temperature solder formed on a conductive pad. A low-temperature solder having a lower melting point than the high-temperature solder is formed on the high-temperature solder. A barrier layer is formed between the high-temperature solder and the low-temperature solder. An Sn content of the high-temperature solder is higher than that of the low-temperature solder. | 2016-01-28 |
20160027752 | Elongated Bump Structures in Package Structure - A package structure includes a chip attached to a substrate. The chip includes a bump structure including a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a pad region and a mask layer overlying the pad region, wherein the mask layer has an opening exposing a portion of the pad region. The chip is attached to the substrate to form an interconnection between the conductive pillar and the pad region. The opening has a first dimension (d | 2016-01-28 |
20160027753 | SEMICONDUCTOR DEVICE HAVING SINGLE LAYER SUBSTRATE AND METHOD - In one embodiment, a semiconductor device includes a single layer substrate having an insulation layer and conductive patterns on a first surface of the insulation layer. A semiconductor die is attached on a first surface of the single layer substrate and electrically connected to the conductive patterns. Conductive bumps are also on the first surface of the single layer substrate and electrically connected to the semiconductor die through the conductive patterns. An encapsulant overlaps at least portions of the first surface of the single layer substrate. The conductive bumps are at least partially exposed in the encapsulant. | 2016-01-28 |
20160027754 | SEMICONDUCTOR DEVICE - To provide a semiconductor device with a wafer level package structure that allows for probing while reducing the area occupied by the pad electrodes. | 2016-01-28 |
20160027755 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE PROVIDED WITH SEMICONDUCTOR CHIP - One semiconductor chip includes a substrate having insulation properties, a plurality of bump electrodes provided on one surface of the substrate, a plurality of recesses provided in the other surface of the substrate, and a solder layer disposed within the recesses. The recesses are formed such that the area of the opening decreases from the other surface side toward the one surface side of the substrate. | 2016-01-28 |
20160027756 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device can be manufactured with a reduced cost. The semiconductor device ( | 2016-01-28 |
20160027757 | BUMPLESS BUILD-UP LAYER PACKAGE INCLUDING AN INTEGRATED HEAT SPREADER - An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a heat spreader having a lower heat spreader surface, an upper heat spreader surface parallel to the lower heat spreader surface, and at least one heat spreader side, the heat spreader disposed on the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the heat spreader side and lower heat spreader surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface. | 2016-01-28 |
20160027758 | SEMICONDUCTOR DEVICE - [Problem] To provide a semiconductor device with a wafer level package structure that allows for probing while reducing the area occupied by the pad electrodes. [Solution] In the present invention, the following are provided: a semiconductor chip (100) that has first and second pad electrodes (120 | 2016-01-28 |
20160027759 | Process for Connecting Joining Parts - A method is provided for connecting parts to be joined. A first layer sequence is applied to a first part to be joined. The first layer sequence contains silver. A second layer sequence is applied to a second part to be joined. The second layer sequence contains indium and bismuth. The first layer sequence and the second layer sequence are pressed together at their end faces respectively remote from the first part to be joined and the second part to be joined through application of a joining pressure at a joining temperature which amounts to at most 120° C. for a predetermined joining time. The first layer sequence and the second layer sequence fuse together to form a bonding layer which directly adjoins the first part to be joined and the second part to be joined and the melting temperature of which amounts to at least 260° C. | 2016-01-28 |
20160027760 | 4D DEVICE, PROCESS AND STRUCTURE - A 4D device comprises a 2D multi-core logic and a 3D memory stack connected through the memory stack sidewall using a fine pitch T&J connection. The 3D memory in the stack is thinned from the original wafer thickness to no remaining Si. A tongue and groove device at the memory wafer top and bottom surfaces allows an accurate stack alignment. The memory stack also has micro-channels on the backside to allow fluid cooling. The memory stack is further diced at the fixed clock-cycle distance and is flipped on its side and re-assembled on to a template into a pseudo-wafer format. The top side wall of the assembly is polished and built with BEOL to fan-out and use the T&J fine pitch connection to join to the 2D logic wafer. The other side of the memory stack is polished, fanned-out, and bumped with C4 solder. The invention also comprises a process for manufacturing the device. In another aspect, the invention comprises a 4D process and device for over 50× greater than 2D memory density per die and an ultra high density memory. | 2016-01-28 |
20160027761 | ELECTRICAL CONNECTOR BETWEEN DIE PAD AND Z-INTERCONNECT FOR STACKED DIE ASSEMBLIES - Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly. | 2016-01-28 |
20160027762 | Power Semiconductor Module - A power semiconductor module includes a first main electrode, a second main electrode and a control terminal. The power semiconductor module includes controllable power semiconductor components arranged between the first main electrode and the second main electrode. At least some of the controllable power semiconductor components are arranged in a ring arrangement, wherein the controllable power semiconductor components of the ring arrangement are arranged at least approximately along a first circular line of the ring arrangement, and a control conductor track of the ring arrangement is arranged on the first main electrode, wherein the control conductor track runs at least approximately along a second circular line of the ring arrangement, and the second circular line runs concentrically relative to the first circular line. | 2016-01-28 |
20160027763 | Flexible Display Apparatus and Methods - A flexible display includes a plurality of pixel chips, chixels, provided on a flexible substrate. The chixels and the light emitters thereon may be shaped, sized and arranged to minimize chixel, pixel, and sub-pixel gaps and to provide a desired bend radius of the display. The flexible substrate may include light manipulators, such as filters, light converters and the like to manipulate the light emitted from light emitters of the chixels. The light manipulators may be arranged to minimize chixel gaps between adjacent chixels. | 2016-01-28 |
20160027764 | SEMICONDUCTOR PACKAGE STACK STRUCTURE HAVING INTERPOSER SUBSTRATE - Provided is a semiconductor package stack structure. The semiconductor package stack structure includes a lower semiconductor package, an interposer substrate disposed on the lower semiconductor package and having a horizontal width greater than a horizontal width of the lower semiconductor package, an upper semiconductor package disposed on the interposer substrate, and underfill portions filling a space between the lower semiconductor package and the interposer substrate and surround side surfaces of the lower semiconductor package. | 2016-01-28 |
20160027765 | Display Device - A display device includes at least one semiconductor body, which has a semiconductor layer sequence, which has an active region provided for producing radiation and forms a plurality of pixels. The device also includes a driver circuit that has a plurality of switches, which are each provided for controlling at least one pixel. A first metallization layer and/or the second metallization layer are electroconductively connected to at least one of the pixels. The first metallization layer and the second metallization layer are arranged overlapping one another in such a manner that, in a plan view onto the display device, the driver circuit is covered with at least one of the metallization layers at every point which overlaps with one of the pixels or is arranged between two adjacent pixels. | 2016-01-28 |
20160027766 | FAN-OUT POP STACKING PROCESS - Package on package structures and manners of formation are described. In an embodiment, an array of trenches is formed partially through a fan-out substrate. In an embodiment, a plurality of laterally separate locations thermal interface material is dispensed onto an array of embedded bottom die. In an embodiment a thermal compression tool including an array of cavities corresponding to an array of top packages is brought into contact with the array of top packages and underlying fan-out substrate during PoP joint formation. The fan-out substrate may be secured to a vacuum chuck during several processing operations. | 2016-01-28 |
20160027767 | METHOD FOR FABRICATING A POWER SEMICONDUCTOR PACKAGE INCLUDING VERTICALLY STACKED DRIVER IC - In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier. | 2016-01-28 |
20160027768 | SYNTHESIS OF COMPLEX CELLS - Hierarchical layout synthesis of complex cells. In some embodiments, a method may include partitioning a cell into a plurality of subcells, where the cell represents a set of electronic components in an integrated circuit; identifying, among the plurality of subcells, a most complex subcell; synthesizing a layout of the most complex subcell for each of one or more side-port configurations; selecting a side-port configuration based upon the layout of the most complex subcell; and synthesizing a layout of one or more of the plurality of subcells neighboring the most complex subcell by propagating one or more constraints associated with the selected side-port configuration. | 2016-01-28 |
20160027769 | INTEGRATED CIRCUIT, SEMICONDUCTOR DEVICE BASED ON INTEGRATED CIRCUIT, AND STANDARD CELL LIBRARY - An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts. | 2016-01-28 |
20160027770 | Methods for Linewidth Modification and Apparatus Implementing the Same - A linear-shaped core structure of a first material is formed on an underlying material. A layer of a second material is conformally deposited over the linear-shaped core structure and exposed portions of the underlying material. The layer of the second material is etched so as to leave a filament of the second material on each sidewall of the linear-shaped core structure, and so as to remove the second material from the underlying material. The linear-shaped core structure of the first material is removed so as to leave each filament of the second material on the underlying material. Each filament of the second material provides a mask for etching the underlying material. Each filament of the second material can be selectively etched further to adjust its size, and to correspondingly adjust a size of a feature to be formed in the underlying material. | 2016-01-28 |
20160027771 | CONFIGURATION OF GATE TO DRAIN (GD) CLAMP AND ESD PROTECTION CIRCUIT FOR POWER DEVICE BREAKDOWN PROTECTION - A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns in the semiconductor substrate wherein the parallel doped columns having a predefined gap. The doped columns further include a U-shaped bend column connect together the ends of parallel doped columns with a deep doped-well that is disposed below and engulfing the U-shaped bend. | 2016-01-28 |
20160027772 | INTEGRATED CAPACITOR IN AN INTEGRATED CIRCUIT - An integrated capacitor includes a semiconductor substrate comprising a trench isolation area; a first interlayer dielectric (ILD) layer covering the trench isolation area; a first electrode plate comprising at least a first contact layer in the first ILD layer, wherein the contact layer is disposed directly on the trench isolation area; a second electrode plate in the first ILD layer; and a capacitor dielectric structure between the first electrode plate and the second electrode plate. | 2016-01-28 |
20160027773 | SEMICONDUCTOR DEVICE - A semiconductor device includes high-voltage (HV) and low-voltage (LV) MOS's formed in a substrate. The HV MOS includes a first semiconductor region having a first-type conductivity and a first doping level, a second semiconductor region having the first-type conductivity and a second doping level lower than the first doping level, a third semiconductor region having a second-type conductivity, and a fourth semiconductor region having the first-type conductivity. The first, second, third, and fourth semiconductor regions are arranged along a first direction, and are drain, drift, channel, and source regions, respectively, of the HV MOS. The LV MOS includes the fourth semiconductor region, a fifth semiconductor region having the second-type conductivity, and a sixth semiconductor region having the first-type conductivity. The fourth, fifth, and sixth semiconductor regions are arranged along a second direction different from the first direction, and are drain, channel, and source regions, respectively, of the LV MOS. | 2016-01-28 |
20160027774 | BIDIRECTIONAL SWITCH - A bidirectional switch formed in a substrate includes first and second main vertical thyristors in antiparallel connection. A third auxiliary vertical thyristor has a rear surface layer in common with the rear surface layer of the first thyristor. A peripheral region surrounds the thyristors and connects the rear surface layer to a layer of the same conductivity type of the third thyristor located on the other side of the substrate. A metallization connects the rear surfaces of the first and second thyristors. An insulating structure is located between the rear surface layer of the third thyristor and the metallization. The insulating structure extends under the periphery of the first thyristor. The insulating structure includes a region made of an insulating material and a complementary region made of a semiconductor material. | 2016-01-28 |
20160027775 | DUAL-WIDTH FIN STRUCTURE FOR FINFETS DEVICES - A method of forming a FinFET device having Si or high Ge concentration SiGe fins with a narrow width under the gate and a wider width under the spacer and the resulting device are provided. Embodiments include forming fins; forming a dummy gate, with a dummy oxide thereunder and a nitride HM on top, on the fins, the dummy gate formed perpendicular to the fins; forming a nitride spacer on each side of the dummy gate; forming an oxide in-between adjacent gates and planarizing; removing the nitride HM and dummy gate, forming a channel between the nitride spacers; oxidizing the fins in the channel; removing the dummy oxide and oxidized portions of the fins; and forming a RMG on the fins between the nitride spacers. | 2016-01-28 |
20160027776 | DENSELY SPACED FINS FOR SEMICONDUCTOR FIN FIELD EFFECT TRANSISTORS - A method of forming a fin-based field-effect transistor device includes forming one or more first fins comprising silicon on a substrate, forming epitaxial layers on sides of the one or more first fins, and removing the one or more first fins to form a plurality of second fins. | 2016-01-28 |
20160027777 | FinFET DEVICE WITH DUAL-STRAINED CHANNELS AND METHOD FOR MANUFACTURING THEREOF - A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed. | 2016-01-28 |
20160027778 | SEMICONDUCTOR DEVICE - One semiconductor device includes a first active region provided on a semiconductor substrate in which a transistor having a high dielectric constant gate insulating film, a gate electrode, and a diffusion layer is disposed, an element separation region that is in contact with and surrounds the first active region, and a dummy active region that is in contact with the element separation region. | 2016-01-28 |
20160027779 | METHOD FOR PROVIDING AN NMOS DEVICE AND A PMOS DEVICE ON A SILICON SUBSTRATE AND SILICON SUBSTRATE COMPRISING AN NMOS DEVICE AND A PMOS DEVICE - The disclosed technology generally relates to complementary metal-oxide-silicon (CMOS) devices, and more particularly to an n-channel metal-oxide-silicon (nMOS) device and a p-channel metal-oxide-silicon (pMOS) device that are under different types of strains. In one aspect, a method comprises providing trenches in a dielectric layer on a semiconductor substrate, where at least a first trench defines an nMOS region and a second trench defines a pMOS region, and where the trenches extend through the dielectric layer and abut a surface of the substrate. The method additionally includes growing a first seed layer in the first trench on the surface and growing a common strain-relaxed buffer layer in the first trench and the second trench, where the common strain-relaxed buffer layer comprises silicon germanium (SiGe). The method further includes growing a common channel layer comprising germanium (Ge) in the first and second trenches and on the common strain-relaxed buffer layer. The properties of the first seed layer and the common strained relaxed buffer layer are predetermined such that the common channel layer is under a tensile strain or is unstrained in the nMOS region and is under a compressive strain in the pMOS region. Aspects also include devices formed using the method. | 2016-01-28 |
20160027780 | METHOD FOR FORMING A GERMANIUM CHANNEL LAYER FOR AN NMOS TRANSISTOR DEVICE, NMOS TRANSISTOR DEVICE AND CMOS DEVICE - The disclosed technology generally relates to complementary metal-oxide-silicon (CMOS) devices, and more particularly to a transistor device comprising a germanium channel layer, such as an n-channel metal-oxide-silicon (NMOS) transistor device. In one aspect, a method of forming a germanium channel layer for an NMOS transistor device comprises providing a trench having sidewalls defined by a dielectric material structure and abutting on a silicon substrate's surface, and growing a seed layer in the trench on the surface, where the seed layer has a front surface comprising facets having a (111) orientation. The method additionally includes growing a strain-relaxed buffer layer in the trench on the seed layer, where the strain-relaxed buffer layer comprises silicon germanium. The method further includes growing a channel layer comprising germanium (Ge) on the strain-relaxed buffer layer. In other aspects, devices, e.g., an NMOS transistor device and a CMOS device, includes features fabricated using the method. | 2016-01-28 |
20160027781 | III-V LAYERS FOR N-TYPE AND P-TYPE MOS SOURCE-DRAIN CONTACTS - Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. In some example embodiments, the techniques can be used to implement the contacts of MOS transistors of a CMOS device, where an intermediate III-V semiconductor material layer is provided between the p-type and n-type source/drain regions and their respective contact metals to significantly reduce contact resistance. The intermediate III-V semiconductor material layer may have a small bandgap (e.g., lower than 0.5 eV) and/or otherwise be doped to provide the desired conductivity. The techniques can be used on numerous transistor architectures (e.g., planar, finned, and nanowire transistors), including strained and unstrained channel structures. | 2016-01-28 |
20160027782 | SEMICONDUCTOR MEMORY DEVICE - To increase a storage capacity of a memory module per unit area, and to provide a memory module with low power consumption, a transistor formed using an oxide semiconductor film, a silicon carbide film, a gallium nitride film, or the like, which is highly purified and has a wide band gap of 2.5 eV or higher is used for a DRAM, so that a retention period of potentials in a capacitor can be extended. Further, a memory cell has n capacitors with different capacitances and the n capacitors are each connected to a corresponding one of n data lines, so that a variety of the storage capacitances can be obtained and multilevel data can be stored. The capacitors may be stacked for reducing the area of the memory cell. | 2016-01-28 |
20160027783 | PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE - One production method for semiconductor devices includes sequentially forming a stopper film and a BPSG film, forming a cylinder etch laminated mask upon the BPSG film, forming openings having a prescribed pattern in the cylinder etch laminated mask, then, using same as a mask, forming a cylinder hole that pierces from the BPSG film to the stopper film in the thickness direction. Next, forming a conductive layer that adjoins the side surfaces of the BPSG film, the stopper film, and a polysilicon film being part of the cylinder etch laminated mask, then removing the polysilicon film and the BPSG film . | 2016-01-28 |
20160027784 | SEMICONDUCTOR DEVICE - The semiconductor device includes a source line, a bit line, a signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line through switching elements, a second driver circuit electrically connected to the source line through a switching element, a third driver circuit electrically connected to the signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material. | 2016-01-28 |
20160027785 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - One semiconductor device includes a semiconductor substrate having a plurality of first trenches formed to extend in the first direction, an embedded gate electrode embedded in a lower part of each of the first trenches with a gate insulating film there between, an embedded insulating film embedded in each of the first trenches, said embedded insulating film being on the embedded gate electrode, an isolating insulating film, which is provided on the embedded insulating film, and which has a width smaller than that of the first trenches, a diffusion region that is provided on the semiconductor substrate by being adjacent to the first trenches, a conductive layer in contact with the diffusion region, and a contact plug in contact with the conductive layer. The conductive layer is disposed also on the embedded insulating film on the embedded gate electrode, and is partitioned by means of the isolating insulating film. | 2016-01-28 |
20160027786 | SEMICONDUCTOR DEVICES HAVING SELF-ALIGNED CONTACT PADS - A semiconductor device includes a substrate having a field area that defines active areas, gate trenches in the substrate and extending in a first direction, a buried gate in a respective gate trench, gate capping fences in a respective gate trench over a respective buried gate, the gate capping fences protruding from top surfaces of the active areas and extending in the first direction, bit line trenches in the gate capping fences, a respective bit line trench crossing the gate capping fences and extending in a second direction perpendicular to the first direction, an insulator structure on inner walls of a respective bit line trench, bit lines and bit line capping patterns stacked on the insulator structures in a respective bit line trench, contact pads self-aligned with the gate capping fences and on the substrate between the adjacent bit lines, and a lower electrode of a capacitor on a respective contact pad. | 2016-01-28 |
20160027787 | PADS INCLUDING CURVED SIDES AND RELATED ELECTRONIC DEVICES, STRUCTURES, AND METHODS - An electronic device may include a substrate, and a plurality of spaced apart pads on the substrate. Each of the pads may includes first, second, third, and fourth sides, the first and third sides may be opposite sides that are substantially straight, and the second and fourth sides may be opposite sides that are curved. Related methods, devices, and structures are also discussed. | 2016-01-28 |
20160027788 | DYNAMIC RANDOM ACCESS MEMORY CELL WITH SELF-ALIGNED STRAP - After formation of trench capacitors and source and drain regions and gate structures for access transistors, a dielectric spacer is formed on a first sidewall of each source region, while a second sidewall of each source region and sidewalls of drain regions are physically exposed. Each dielectric spacer can be employed as an etch mask during removal of trench top dielectric portions to form strap cavities for forming strap structures. Optionally, selective deposition of a semiconductor material can be performed to form raised source and drain regions. In this case, the raised source regions grow only from the first sidewalls and do not grow from the second sidewalls. The raised source regions can be employed as a part of an etch mask during formation of the strap cavities. The strap structures are formed as self-aligned structures that are electrically isolated from adjacent access transistors by the dielectric spacers. | 2016-01-28 |
20160027789 | DUMMY GATE STRUCTURE FOR ELECTRICAL ISOLATION OF A FIN DRAM - Trench capacitors can be formed between lengthwise sidewalls of semiconductor fins, and source and drain regions of access transistors are formed in the semiconductor fins. A dummy gate structure is formed between end walls of a neighboring pair of semiconductor fins, and limits the lateral extent of raised source and drain regions that are formed by selective epitaxy. The dummy gate structure prevents electrical shorts between neighboring semiconductor fins. Gate spacers can be formed around gate structures and the dummy gate structures. The dummy gate structures can be replaced with dummy replacement gate structures or dielectric material portions, or can remain the same without substitution of any material. The dummy gate structures may consist of at least one dielectric material, or may include electrically floating conductive material portions. | 2016-01-28 |
20160027790 | Three-Dimensional Printed Memory - As technology scales, the mask cost rises sharply. The present invention discloses a three-dimensional printed memory (3D-P). It uses shared data-masks to print data. Because a shared data-mask does not contain the mask-patterns for identical mass-contents, the share of the data-mask cost on each mass-content is significantly reduced. For mass publication, the minimum feature size of the 3D-P is preferably less than 45 nm. | 2016-01-28 |
20160027791 | Three-Dimensional Offset-Printed Memory - The present invention discloses a three-dimensional offset-printed memory (3D-oP). Compared with a conventional three-dimensional mask-programmed read-only memory (3D-MPROM), it has a lower data-mask count and thereby a lower data-mask cost. The mask-patterns for different memory levels/bits-in-a-cell are merged onto a multi-region data-mask. At different printing steps, a wafer is offset by different values with respect to said data-mask. Accordingly, data-patterns are printed into different memory levels/bits-in-a-cell from a same data-mask. | 2016-01-28 |
20160027792 | SPLIT GATE MEMORY DEVICE, SEMICONDUCTOR DEVICE AND FORMING METHOD THEREOF - A split gate memory device, a semiconductor device and a manufacturing method thereof are provided. In the split gate memory device, an erasing gate is further disposed, wherein the easing gate and a control gate are respectively disposed on two sides of a floating gate. Thus, an erase operation is implemented by the erasing gate instead of the control gate. Accordingly, electric potential applied to the control gate is reduced. Therefore, hot-electron effect in channel region may be avoided, and performance degradation of the memory caused by the hot-electron effect may be avoided as well. Furthermore, as electric potential applied to the control gate is reduced, a gate oxide layer underneath the control gate may be thinner. Accordingly, manufacturing processes of the control gate and the gate oxide layer and that of the gate and the gate oxide layer of a logic transistor in a periphery circuit may be compatible. | 2016-01-28 |
20160027793 | SEMICONDUCTOR DEVICES INCLUDING STAIR STEP STRUCTURES, AND RELATED METHODS - Semiconductor devices, such as three-dimensional memory devices, include a memory array including a stack of conductive tiers and a stair step structure. The stair step structure is positioned between first and second portions of the memory array and includes contact regions for respective conductive tiers of the stack of conductive tiers. The first portion of the memory array includes a first plurality of select gates extending in a particular direction over the stack. The second portion of the memory array includes a second plurality of select gates also extending in the particular direction over the stack of conductive tiers. Methods of forming and methods of operating such semiconductor devices, including vertical memory devices, are also disclosed. | 2016-01-28 |
20160027794 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - After forming a first film over the main surface of a semiconductor substrate, the first film is patterned, thereby forming a control gate electrode for a non-volatile memory, a dummy gate electrode, and a first film pattern. Subsequently, a memory gate electrode for the non-volatile memory adjacent to the control gate electrode is formed. Then, the first film pattern is patterned thereby forming a gate electrode and a dummy gate electrode. | 2016-01-28 |
20160027795 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate, a stack structure, peripheral gate structures and residual spacers. The substrate includes a cell array region and a peripheral circuit region. The stack structure is disposed on the cell array region, having electrodes and insulating layers alternately stacked. The peripheral gate structures are disposed on the peripheral circuit region, being spaced apart from each other in one direction and having a peripheral gate pattern disposed on the substrate, and a peripheral gate spacer disposed on a sidewall of the peripheral gate pattern. The residual spacers are disposed on sidewalls of the peripheral gate structures, having a sacrificial pattern and an insulating pattern that are stacked. The insulating pattern includes substantially the same material as the insulating layers of the stack structure. | 2016-01-28 |
20160027796 | SEMICONDUCTOR DEVICES - According to example embodiments, a semiconductor device includes a substrate, a plurality of word lines spaced apart from each other in a first direction on the substrate, a channel layer in a channel hole defined by the plurality of word lines, a gate insulating layer in the channel hole along an inner wall of the channel hole; and a self-aligned contact on an upper portion of the channel layer in the channel hole. The gate insulating layer is between the plurality of word lines and the channel layer. The first direction is perpendicular to an upper surface of the substrate. The channel hole exposes the upper surface of the substrate. | 2016-01-28 |
20160027797 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - The present disclosure discloses an array substrate, manufacturing method thereof, and display device. The present disclosure belongs to the technical field of display technology, solves the technical problem of high impedance of the jumper joints of the array substrate in the prior art. The array substrate comprises: a first wiring and a second wiring located in a first metal layer; a first insulating layer covering the first metal layer, wherein the first insulating layer is provided with via holes corresponding to the first wiring and the second wiring respectively; and a jumper located in a second metal layer provided on the first insulating layer, wherein the jumper is connected with the first wiring and the second wiring through the via holes, thereby the first wiring and the second wiring being electrically conducted with each other through the jumper. The array substrate of the present disclosure can be used in liquid crystal television, liquid crystal display, mobile phone, tablet personal computer and other display devices. | 2016-01-28 |
20160027798 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - The embodiments of the invention provide an array substrate, a method for manufacturing the same and a display device, relate to the field of display technology, and can reduce the color cast phenomenon of the display device, and improve the display effect. | 2016-01-28 |
20160027799 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE - An array substrate, a manufacturing method thereof and a display device are disclosed. The manufacturing method of an array substrate including: forming patterns including a thin film transistor, a gate wiring and a data wiring on the base substrate; the gate wiring and the data wiring are located in a PAD area; forming patterns of an insulating spacing layer, a first transparent electrode and a passivation layer, and forming a first via hole and a second via hole in areas corresponding to the gate wiring and the data wiring respectively to expose the gate wiring and the data wiring; a thickness of the insulating spacing layer in the PAD area on the array substrate is less than that of the insulating spacing layer in other areas. Therefore, the connection electrode can make better contact with the corresponding signal lines to avoid abnormal rubbing mura. | 2016-01-28 |
20160027800 | MOTHERBOARD, ARRAY SUBSTRATE AND FABRICATION METHOD THEREOF, AND DISPLAY DEVICE - An array substrate and a fabrication method thereof, a display device including the array substrate and a motherboard including the array substrate are provided. The array substrate includes a pixel region and a peripheral wiring region. The peripheral wiring region includes a transparent conductive contact electrode disposed on a base substrate. The transparent conductive contact electrode is electrically connected with a metal electrode line disposed below the transparent conductive contact electrode through via holes disposed in different insulating layers, and the via holes disposed in different insulating layers do not overlap with each other in a projection direction. | 2016-01-28 |
20160027801 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY PANEL - An array substrate, a manufacturing method thereof and a display panel are disclosed. The array substrate comprises: a base substrate ( | 2016-01-28 |
20160027802 | THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF - A thin film transistor array panel includes: a substrate; a gate line and a common voltage line electrically separated from each other and elongated parallel with each other on the substrate; a gate insulating layer on the gate line and the common voltage line; a first passivation layer on the gate insulating layer; a common electrode on the first passivation layer; a second passivation layer on the common electrode; and a pixel electrode and a connection member on the second passivation layer and electrically separated from each other. The connection member is elongated in a horizontal direction parallel with the gate line and connects the common voltage line and the common electrode to each other. | 2016-01-28 |
20160027803 | FLEXIBLE DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A flexible display device includes: a flexible substrate having a lower substrate including a prominence pattern, a barrier layer pattern on the prominence pattern, and a planarization film; a gate line on the flexible substrate; a data line crossing the gate line with having a gate insulation film therebetween to define a pixel region; a thin film transistor formed at an intersection of the gate line and the data line; and a passivation layer on the flexible substrate including the thin film transistor. With this configuration, the flexible substrate and the flexible display device can be enhanced by preventing property deterioration of the elements due to bending stresses. | 2016-01-28 |
20160027804 | METHOD FOR MANUFACTURING TFT BACKPLANE AND STRUCTURE OF TFT BACKPLANE - The present invention provides method for manufacturing a TFT backplane and a structure of a TFT backplane. The method includes ( | 2016-01-28 |
20160027805 | THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF - A thin film transistor array panel and a manufacturing method thereof according to an exemplary embodiment of the present invention form a contact hole in a second passivation layer formed of an organic insulator, protect a side of the contact hole by covering with a protection member formed of the same layer as the first field generating electrode and formed of a transparent conductive material, and etch the first passivation layer below the second passivation layer using the protection member as a mask. Therefore, it is possible to prevent the second passivation layer formed of an organic insulator from being overetched while etching the insulating layer below the second passivation layer so that the contact hole is prevented from being made excessively wide. | 2016-01-28 |
20160027806 | FinFET DEVICE WITH ABRUPT JUNCTIONS - A plurality of semiconductor fins is formed on a surface of an insulator layer. Gate structures are then formed that are orientated perpendicular and straddle each semiconductor fin. A dielectric spacer is then formed on vertical sidewalls of each gate structure. Next, an etch is performed that removes exposed portions of each semiconductor fin and a portion of the insulator layer not protected by the dielectric spacers and the gate structures. The etch provides semiconductor fin portions that have exposed vertical sidewalls. A doped semiconductor material is then formed from each exposed vertical sidewall of each semiconductor fin portion, followed by an anneal which causes diffusion of dopants from the doped semiconductor material into each semiconductor fin portion and the formation of source/drain regions. The source/drain regions are present along the sidewalls of each semiconductor fin portion and are located beneath the dielectric spacers. | 2016-01-28 |
20160027807 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY DEVICE, THIN-FILM TRANSISTOR (TFT) AND MANUFACTURING METHOD THEREOF - An array substrate and a manufacturing method thereof, a display device, a thin-film transistor (TFT) and a manufacturing method thereof. The array substrate comprises a base substrate and a pixel electrode and a TFT formed on the base substrate. The TFT includes an active layer and a source/drain pattern. The source/drain pattern is connected with the active layer. The pixel electrode is connected with the active layer. The array substrate can improve the aperture ratio of pixels and the chargeability of the TFT. | 2016-01-28 |
20160027808 | DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - An array substrate for a display device includes a first base substrate; a thin film transistor disposed on the first base substrate that includes a semiconductor layer, a gate electrode, a source electrode, and a drain electrode; a first passivation layer that covers the thin film transistor and that includes an inorganic insulating material; a second passivation layer disposed on the first passivation layer that includes an exposure hole that exposes the first passivation layer on the drain electrode; a common electrode disposed on the second passivation layer; a third passivation layer that covers the common electrode and that includes a contact hole inside the exposure hole to expose the drain electrode; a cavity between the first passivation layer and the third passivation layer on the drain electrode; and a pixel electrode disposed on the third passivation layer and connected with the drain electrode. | 2016-01-28 |
20160027809 | SEMICONDUCTOR DEVICE - A semiconductor device capable of retaining data for a long time is provided. The semiconductor device includes first to third transistors, a fourth transistor including first and second gates, first to third nodes, a capacitor, and an input terminal. A source of the first transistor is connected to the input terminal. A drain of the first transistor and a source of the second transistor are connected to the first node. A gate of the second transistor, a drain of the second transistor, and a source of the third transistor are connected to the second node. A gate of the third transistor, a drain of the third transistor, the capacitor, and the second gate of the fourth transistor are connected to the third node. | 2016-01-28 |
20160027810 | Semiconductor Device, Display Module, and Electronic Appliance - The circuit includes a first transistor; a second transistor whose first terminal is connected to a gate of the first transistor for setting the potential of the gate of the first transistor to a level at which the first transistor is turned on; a third transistor for setting the potential of a gate of the second transistor to a level at which the second transistor is turned on and bringing the gate of the second transistor into a floating state; and a fourth transistor for setting the potential of the gate of the second transistor to a level at which the second transistor is turned off. With such a configuration, a potential difference between the gate and a source of the second transistor can be kept at a level higher than the threshold voltage of the second transistor, so that operation speed can be improved. | 2016-01-28 |
20160027811 | THIN FILM TRANSISTOR, ARRAY SUBSTRATE AND DISPLAY DEVICE - Disclosed are a thin film transistor, an array substrate and a display device. The thin film transistor comprises a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode, wherein the active layer comprises at least two layers of semiconductor thin films, and the at least two layers of semiconductor thin films comprise at least one layer of monocrystalline semiconductor thin film. | 2016-01-28 |
20160027812 | ARRAY SUBSTRATE, METHOD FOR FABRICATING THE SAME AND DISPLAY DEVICE - An array substrate, a method for fabricating the same and a display device are disclosed. The array substrate includes: a gate electrode of a TFT and a gate insulation layer sequentially formed on a base substrate; a semiconductor active layer, an etch stop layer and a source electrode and a drain electrode of the TFT sequentially formed on a part of the gate insulation layer that corresponds to the gate electrode of the TFT, the source and drain electrodes of the TFT are respectively in contact with the semiconductor active layer by way of via holes. The array substrate further includes: a first insulation layer formed between the gate electrode of the TFT and the gate insulation layer and the gate electrode is in contact with the gate insulation layer at a channel region of the TFT between the source electrode and the drain electrode of the TFT. | 2016-01-28 |
20160027813 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF AND DISPLAY APPARATUS - An array substrate and a manufacturing method thereof, and a display apparatus comprising the array substrate are provided. The array substrate comprises a base substrate, and a thin film transistor and a storing capacitor provided on the base substrate, the thin film transistor comprises a gate, a source, a drain and a gate insulation layer provided between the source and drain and the gate, the storing capacitor comprises a first plate, a second plate and a dielectric layer provided between the first plate and the second plate, wherein, both of the first plate and the second plate are formed of metal material, and the dielectric layer is formed of the same material as the gate insulation layer. In the array substrate of the present invention, the charging speed of the storing capacitor can be improved and the display quality of the display apparatus comprising the array substrate is further improved. | 2016-01-28 |
20160027814 | BACKPLANE FOR DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE BACKPLANE - A backplane for a display apparatus includes a substrate including a display area and a non-display area; a first transistor formed on the display area; and a second transistor formed on the non-display area, wherein a first active layer includes a first channel area, a first source area disposed on one side of the first channel area, a first drain area disposed on the other side of the first channel area, and a low-density doped area and a halo doped area that are adjacent to both ends of the first gate electrode, and the second active layer includes a second channel area, a second source area disposed on one side of the second channel area, and a second drain area disposed on the other side of the second channel area. | 2016-01-28 |
20160027815 | LIGHT EMITTING DEVICE, DRIVING METHOD OF LIGHT EMITTING DEVICE AND ELECTRONIC DEVICE - By controlling the luminance of light emitting element not by means of a voltage to be impressed to the TFT but by means of controlling a current that flows to the TFT in a signal line drive circuit, the current that flows to the light emitting element is held to a desired value without depending on the characteristics of the TFT. Further, a voltage of inverted bias is impressed to the light emitting element every predetermined period. Since a multiplier effect is given by the two configurations described above, it is possible to prevent the luminance from deteriorating due to a deterioration of the organic luminescent layer, and further, it is possible to maintain the current that flows to the light emitting element to a desired value without depending on the characteristics of the TFT. | 2016-01-28 |
20160027816 | MASK SET, PIXEL UNIT AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE - A mask set, a pixel unit and a manufacturing method thereof, an array substrate and a display device are provided to overcome the problem of low brightness of a display screen of a display device. In the pixel unit, the maximum size value of an overlapped area between an active layer and a drain electrode of a thin-film transistor (TFT) in the direction parallel to data line is less than the size value of one side, overlapped with the data line, in an overlapped area between the active layer and a source electrode; and the source electrode is the portion of the data line disposed in an overlapped area between the active layer and the data line. The pixel unit has the advantages of a larger opening area and higher light transmittance. Thus, the brightness of a display screen of the display device comprising the pixel units can be enhanced. Moreover, the problem of screen flicker can be avoided to some extent, and hence the display quality of images can be improved. | 2016-01-28 |
20160027817 | ARRAY SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE - Disclosed is an array substrate, a method of manufacturing the same, and a display device. The method of manufacturing an array substrate includes: forming a pattern comprising an active layer, a source, a drain, a data line and a pixel electrode on a base substrate through a single patterning process; forming a pattern of an insulating layer; forming a pattern comprising a gate and a gate line through a single patterning process. In the array substrate, the method of manufacturing the same, and the display device of the present invention, only two patterning processes are required to achieve the fabrication of the array substrate, which has less and simple process steps, thereby reduces the manufacturing complexity and manufacturing cost, and increasing the production efficiency and the economic benefit. | 2016-01-28 |
20160027818 | MANUFACTURING METHOD OF THIN FILM TRANSISTOR, MANUFACTURING METHOD OF ARRAY SUBSTRATE AND ARRAY SUBSTRATE - A manufacturing method of a thin film transistor, a manufacturing method of an array substrate and an array substrate are provided. The manufacturing method of the thin film transistor comprises: forming an active layer, a source electrode and a drain electrode on a substrate by one patterning process, the active layer, the source electrode and the drain electrode being located in a same layer. The manufacturing method of the thin film transistor can effectively reduce the number of patterning processes, so as to enhance the capacity in mass production, and reduce the cost. | 2016-01-28 |
20160027819 | ARRAY SUBSTRATE AND METHOD FOR FABRICATING THE SAME - An array substrate and a method for fabricating the same are disclosed. The method includes steps of providing a substrate ( | 2016-01-28 |
20160027820 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY DEVICE - A manufacturing method of an array substrate, including: forming a pattern layer including a pixel electrode, and a pattern layer including a gate electrode and a gate line on a base substrate; on the substrate with the pattern layer including the gate electrode and the gate line formed thereon, forming a gate insulating layer, a pattern layer at least including a metal oxide semiconductor active layer and a pattern layer at least including an etch stop layer; wherein, a first via hole for exposing the pixel electrode is formed over the pixel electrode; on the substrate with the etch stop layer formed thereon, forming a pattern layer including a source electrode, a drain electrode and a data line; wherein, the source electrode and the drain electrode each contact a metal oxide semiconductor active layer, and the drain electrode is electrically connected to the pixel electrode through the first via hole. | 2016-01-28 |
20160027821 | IMAGE SENSORS - An image sensor includes a substrate including a pixel region and a peripheral circuit region, and a first device isolation layer disposed in the substrate to define a plurality of unit pixels that are adjacent to each other in a first direction in the pixel region. Each of the plurality of unit pixels includes at least one light sensing element disposed in the substrate. The image sensor includes an interlayer insulating structure on the substrate, and a first blocking structure disposed on the first device isolation layer and penetrating the interlayer insulating structure. The first blocking structure is disposed between the plurality of unit pixels when viewed from a plan view. The first blocking structure extends in a second direction intersecting the first direction when viewed from a plan view. | 2016-01-28 |
20160027822 | SOLID-STATE IMAGE PICKUP ELEMENT, IMAGE PICKUP APPARATUS, ELECTRONIC APPARATUS, AND PRODUCTION METHOD - Provided is a solid-state image pickup element including: a sensor unit configured to generate an electrical signal in response to incident light; a color filter covering the sensor unit; and a lens configured to concentrate the incident light into the sensor unit via the color filter and formed by a laminated film made of a predetermined lens material. The lens is formed on the color filter without providing a planarization layer for removing a difference in level in the color filter. | 2016-01-28 |