05th week of 2009 patent applcation highlights part 20 |
Patent application number | Title | Published |
20090027013 | Method and Apparatus for Charging Batteries - A battery charging system is disclosed. The battery charging system includes a battery charger, a switching circuit and a control circuit. The battery charger receives electric power from a DC power supply and charges a rechargeable battery based on a setting current. The switching circuit is capable of switching between a first charging mode and a second charging mode. In the first charging mode, the battery charger charges the rechargeable battery while the DC power supply is supplying electric power to the battery charger in a state where the DC power supply is able to supply electric power to a load. In the second charging mode, the DC power supply charges the rechargeable battery in a state where the DC power supply is able to supply electric power to the load. The control circuit controls the switching circuit based on a comparison result of the magnitude of a charging current (or a charging power) in the first charging mode and the magnitude of a charging current (or a charging power) in the second charging mode. | 2009-01-29 |
20090027014 | Capacitor save energy verification - A memory subsystem is configured to obtain power from an external system and from at least one power capacitors. The memory subsystem includes logic to verify the power delivery capability of the power capacitors. | 2009-01-29 |
20090027015 | DC/DC CONVERTER WITH IMPROVED STABILITY - The DC/DC converter according to one embodiment includes a switch, an inductor, a capacitor, a resistor, and a voltage divider. The switch is coupled to the input voltage. The inductor is used for coupling the first switch to an output node of the DC/DC converter so as to generate the output voltage at the output node. The capacitor is coupled to the output voltage. The resistor is coupled to the capacitor in series, and is coupled to ground. The voltage divider is coupled across the capacitor so as to reduce the zero frequency of the DC/DC converter. | 2009-01-29 |
20090027016 | AUXILIARY LIGHTING CIRCUIT FOR A GASEOUS DISCHARGE LAMP - A non-arcing electrical switch comprising means for sensing current, means for impressing a source potential across the electrical switch, means for controlling voltage; and means for controlling phase, wherein the means for sensing current, the means for impressing a source potential across the electrical switch, the means for controlling phase and the means for controlling voltage are operably connected. | 2009-01-29 |
20090027017 | Circuit arrangement for the regulation of a current through a load - A circuit arrangement ( | 2009-01-29 |
20090027018 | INTEGRATED CIRCUIT AND A METHOD FOR SELECTING A VOLTAGE IN AN INTEGRATED CIRCUIT - An integrated circuit comprising an adjustable voltage source to allow a plurality of voltage values to be selected; means for measuring a voltage value derived from the adjustable voltage source; and means for configuring the adjustable voltage source to provide a selected voltage value, wherein the selected voltage value is selected based upon a voltage value measured by the means for measuring and a voltage selected by a controller. | 2009-01-29 |
20090027019 | Control loop for switching power converters - A control loop for a clocked switching power converter where the loop features a comparator ( | 2009-01-29 |
20090027020 | THRESHOLD VOLTAGE MONITORING AND CONTROL IN SYNCHRONOUS POWER CONVERTERS - A method of providing threshold voltage monitoring and control in synchronous power converters is disclosed. The method establishes a threshold voltage level for at least one of an upper gate and a lower gate power switch in a synchronous power converter. The threshold voltage levels indicate switching delay times are present in the upper and lower gate power switches. The method detects body diode conduction levels for both the upper and lower gate power switches. When at least one of the detected body diode conduction levels exceed a prescribed body diode conduction level, the method adjusts the threshold voltage level for at least one of the upper and lower gate power switches to reduce a body diode conduction time for the at least one of the upper and lower gate power switches. | 2009-01-29 |
20090027021 | DEAD-TIME TRANSITION ADJUSTMENTS FOR SYNCHRONOUS POWER CONVERTERS - A method of operating a synchronous power converter detects when at least one of an upper power switch and a lower power switch of the converter transition to an off state during a dead-time transition interval between the upper power switch and the lower power switch. The method generates a first comparison signal, indicative of a voltage level at a phase node of the converter, in a dead-time adjustment circuit coupled to the converter. The method further detects a body diode conduction level of at least one of the upper and lower power switches in the off state using at least a second comparison signal generated in the dead-time adjustment circuit and adjusts the dead-time transition interval between the upper power switch and the lower power switch using at least one current source from the dead-time adjustment circuit to reduce the dead-time transition interval to a desired dead-time interval. | 2009-01-29 |
20090027022 | CHARGE PUMP CIRCUIT, AND CONTROL CIRCUIT AND CONTROL METHOD THEREOF - A first switch group includes switches provided on a path for charging a flying capacitor using an input voltage. A second switch group includes switches provided on a path for charging an output capacitor using charge stored in the flying capacitor. A pulse modulator generates a pulse signal having a duty ratio adjusted so that a feedback voltage corresponding to an output voltage of a charge pump circuit matches a given reference voltage. A driver receives the pulse signal from the pulse modulator, and turns on either one of the first switch group and the second switch group during a period corresponding to a high-time of the pulse signal and turns on the other switch group during a period corresponding to a low-time thereof. | 2009-01-29 |
20090027023 | Switching regulator circuit - Provided is a switching regulator having satisfactory energy conversion efficiency during light load conditions. Such a structure is employed that an oscillating frequency for the switching regulator and a drive capability of a switch element are variable and such a control is taken that during the light load, the oscillating frequency for the switching regulator or the drive capability of the switch element is reduced. | 2009-01-29 |
20090027024 | LOAD CURRENT COMPENSATION IN SYNCHRONOUS POWER CONVERTERS - A method of operating a synchronous power converter generates a control signal in a load current compensation circuit based on a light load condition at the converter, where the control signal controls a gate driver for at least one power switch of the converter. When the gate driver is turned off via the control signal, the method monitors one or more comparison signals in a reference voltage adjustment module of the compensation circuit, a first comparison signal of the one or more comparison signals indicative of a voltage level at a phase node of the converter. Based on a remaining body diode conduction level associated a body diode with the at least one power switch as detected by at least a second comparison signal, the method adjusts a reference voltage for the at least one power switch with the adjustment module until the body diode is no longer conducting. | 2009-01-29 |
20090027025 | NON-LINEAR PWM CONTROLLER - In one embodiment, the controller of these teachings includes a nonlinear controller component capable of providing an amplitude determining input signal to a control signal providing component, the control signal providing component providing output having a predetermined amplitude substantially over one time interval from a number of time intervals or output having a predetermined average amplitude substantially over one time interval from a number of time intervals, the amplitude determining input signal corresponding to at least one predetermined system state variable. The nonlinear controller component is operatively connected to receive as inputs at least one predetermined system state variable. A relationship between the amplitude determining input signal and at least one predetermined system state variable is obtained by a predetermined method. | 2009-01-29 |
20090027026 | WINDOW COMPARATOR WITH ACCURATE LEVELS FOR USE IN DC-DC CONVERTERS - The present invention relates to a improved feedback circuit for generating a quantized control signal representing the relation of a signal to be controlled relative to predetermined limits of at least one error signal window, the circuit comprising signal detecting means, a detected signal connected to error amplifying means for amplifying the error between the detected signal and a first reference signal, the output error signal of the error amplifying means connected to at least a first comparator means and second comparator means each configured to compare the error signal with one of the upper limit and lower limit of the at least one error signal window. The invention provides a circuit and method by which only one accurate comparator is needed and for the error windows only simple, inaccurate comparators can be used. Thus, accuracy of the distance between the defined error window levels is much more fixed because it is primary determined by mismatch of resistors and not by the offset of the used comparators. Further, the capacitive load on the feedback node is smaller, which leads to a better response time. Furthermore, the current consumption is considerably less. Moreover, the circuit will be smaller. Finally, yet importantly, the overall offset of the output voltage is comparable to the offset in the standard solution. | 2009-01-29 |
20090027027 | Anti-ring asynchronous boost converter and anti-ring method for an asynchronous boost converter - The phase node voltage or the PWM signal in an asynchronous boost converter is monitored to detect a phase node voltage ringing. When a phase node voltage ringing is detected, a detection signal is asserted to establish a bypass path to bypass the inductor of the converter. A charge bypass circuit is shunt to the inductor, and controlled by the detection signal to establish the bypass path. Due to the bypass path, the phase node voltage is maintained at a constant, and the phase node voltage radiation and input/output noise are eliminated. | 2009-01-29 |
20090027028 | PULSE WIDTH MODULATED CONTROLLER APPLIED TO SWITCH-TYPE VOLTAGE REGULATOR - A PWM controller applied to switch-type voltage regulator includes an error amplifier, a soft-start control circuit, a compensating load and a comparator. The error amplifier receives a reference voltage signal and a feedback voltage signal and outputs an error current signal according to the received feedback voltage signal and the reference voltage signal. The soft-start control circuit outputs a compensating current signal according to at least one soft-start control signal. The compensating load receives the error current signal and the compensating current signal, and outputs a compensating signal. The comparator receives a ramp signal and the compensating signal, and outputs a pulse width modulated (PWM) signal. When a supply voltage rises, the error amplifier is compensated with a preset soft-start compensating current to a circuit common ground VSS, so that the error signal slowly rises during the soft-start control process. Therefore, the function of soft-starting is effectuated. | 2009-01-29 |
20090027029 | Load control unit - A load control unit for controlling the supply of an electric power to a load from battery in accordance with a pulse-width modulation control includes: a reference voltage generating unit; a first charging/discharging unit; a second charging/discharging unit connected in series to the first charging/discharging unit to charge and discharge in reverse to those of the first charging/discharging unit; a first comparing unit that compares the voltage of the first charging/discharging unit with the reference voltage and switches between the charge and discharge of the first charging/discharging unit to generate a triangle wave; and a second comparing unit that compares a divided voltage by dividing the voltage of the battery with the voltage of the triangle wave generated by the first comparing unit to generate a PWM pulse. The ratio of capacities between the first and second charging/discharging units approximates to the ratio of resistances for obtaining the divided voltage. | 2009-01-29 |
20090027030 | Low noise bandgap voltage reference - A bandgap voltage reference circuit that can be implemented with low noise characteristics is described. To achieve such low noise, a bandgap reference circuit is provided that includes an amplifier coupled at its inputs to first and second transistors respectively, the transistors being arranged to generate a voltage representative of the base emitter voltage differences between each of the first and second transistors across a sensing resistor. The circuit additionally provides an additional current to the sensing resistor to reduce the noise contribution into the amplifier from the first transistor. Such a circuit may be corrected for second order temperature effects by inclusion of a temperature dependent current source. | 2009-01-29 |
20090027031 | Low noise bandgap voltage reference - A bandgap voltage reference circuit that can be implemented with low noise characteristics is described. To achieve such low noise, a bandgap reference circuit is provided that includes an amplifier coupled at its inputs to first and second transistors respectively, the transistors being arranged to generate a voltage representative of the base emitter voltage differences between each of the first and second transistors across a sensing resistor. The circuit additionally provides an additional current to the sensing resistor to reduce the noise contribution into the amplifier from the first transistor. Such a circuit may be corrected for second order temperature effects by inclusion of a temperature dependent current source. | 2009-01-29 |
20090027032 | Circuit arrangment for the temperature-dependent regulation of a load current - The invention concerns a circuit arrangement ( | 2009-01-29 |
20090027033 | SYSTEM AND METHOD FOR INTEGRATED TEMPERATURE MEASUREMENT IN POWER OVER ETHERNET APPLICATIONS - A system and method for integrated thermal monitoring in Power over Ethernet (PoE) applications. Headroom in a particular cable installation is identified using ambient temperature measurement alone or in combination with determined cable characteristics. In calculating an amount of headroom for a particular cable installation, the current capable of being carried over the cable would not be limited by worst-case cable assumptions. | 2009-01-29 |
20090027034 | METHOD AND APPARATUS FOR REGULATING VOLTAGE IN A REMOTE DEVICE - A system and the method are provided for supplying power to a remote device. In one embodiment, the method involves regulating voltage for at least one device remote from a power source. The regulating includes monitoring a current response of the remote device and adjusting a voltage of the power source until the current response reaches an operating range of the remote device. | 2009-01-29 |
20090027035 | Output Regulation Circuit of a Power Converter without Current Sensing Loss and Method Thereof - An output regulation circuit of a power converter without current sensing loss includes a transforming circuit to receive a proportional voltage from the primary winding of the power converter. The first proportional voltage is transformed to a charging current signal. When the power switch during on-time period, the charging current signal charges an energy storage device. Thus, the circuit controls the power switch according to a voltage limited signal of the energy storage device. | 2009-01-29 |
20090027036 | SENSING DEVICES FROM MOLECULAR ELECTRONIC DEVICES UTILIZING HEXABENZOCORONENES - The present invention generally relates to the fabrication of molecular electronics devices from molecular wires and Single Wall Nanotubes (SWNT). In one embodiment, the cutting of a SWNT is achieved by opening a window of small width by lithography patterning of a protective layer on top of the SWNT, followed by applying an oxygen plasma to the exposed SWNT portion. In another embodiment, the gap of a cut SWNT is reconnected by one or more difunctional molecules having appropriate lengths reacting to the functional groups on the cut SWNT ends to form covalent bonds. In another embodiment, the gap of a cut SWNT gap is filled with a self-assembled monolayer from derivatives of novel contorted hexabenzocoranenes. In yet another embodiment, a device based on molecular wire reconnecting a cut SWNT is used as a sensor to detect a biological binding event. | 2009-01-29 |
20090027037 | Method for detecting an isolated network - The subject matter of the invention is a method for detecting an isolated network for an inverter ( | 2009-01-29 |
20090027038 | Systems And Methods That Detect Changes In Incident Optical Radiation - Systems, methods and sensors detect changes in incident optical radiation. Current is driven through one or more active areas of a detector while the incident optical radiation illuminates the active areas. Voltage is sensed across one or more of the active areas, a change in the voltage being indicative of the changes in incident optical radiation. | 2009-01-29 |
20090027039 | POWER SUPPLY - A power supply is for receiving an AC voltage and outputting a DC voltage and an output current to an electronic device. The power supply includes an input module, an output module, a measuring interface, a measuring interface, and a switch module. The input module is for receiving the AC voltage. The output module is for outputting the DC voltage and the output current to the electronic device. The measuring interface is for electrically contacting with a part of the electronic device. The measuring module is for measuring the DC voltage, the output current, and a voltage and a current of the part of the electronic device. The switch module is for choosing one of the output module and the measuring interface to be electrically connected to the measuring module. | 2009-01-29 |
20090027040 | OPEN CIRCUIT DELAY DEVICES, SYSTEMS, AND METHODS FOR ANALYTE MEASUREMENT - System, circuits, and methods to reduce or eliminate uncompensated voltage drop between an electrode of an electrochemical cell usable for analyte measurement. In one example, a system is provided that includes a test strip, a reference voltage circuit, an operational amplifier connected to the reference voltage circuit to provide a predetermined fraction of a reference voltage substantially equal to the test voltage applied to the first line, the operational amplifier having an output configured for one of a connected or disconnected state to the first line, and a processing circuit connected to the output of the operational amplifier and the first line such that, during a disconnected state between the output and the first line, the processing circuit remains in connection with the first line. In another example, a method of measuring an electrochemical reaction of an electrochemical cell is provided that includes applying a test voltage to the first electrode and connecting the second electrode to ground; uncoupling the first electrode from the output of the circuit while allowing electrical communication from the first electrode to the processor; and coupling the first electrode to the output to measure a test current generated in the electrochemical cell without an uncompensated voltage drop. | 2009-01-29 |
20090027041 | BUFFER CIRCUIT, AMPLIFIER CIRCUIT, AND TEST APPARATUS - There is provided a buffer circuit that outputs a signal according to an input signal. The buffer circuit includes a first receiving transistor that receives the input signal through its base terminal, a first clamp transistor having polarity same as that of the first receiving transistor, of which an emitter terminal and a collector terminal are connected to corresponding terminals of the first receiving transistor and which receives a first clamp voltage restricting a signal level output from the buffer circuit through its base terminal, and a first current defining section that is commonly provided for the first receiving transistor and the first clamp transistor and defines a total amount of emitter currents flowing into the first receiving transistor and the first clamp transistor. The buffer circuit outputs an output signal according to an emitter voltage of the first receiving transistor. | 2009-01-29 |
20090027042 | Method and apparatus for amplifying a signal and test device using same - An amplifier circuit is used in a multimeter to amplify signals applied between a pair of test terminals. A voltage applied to one of the test terminals is amplified by a first operational amplifier configured as a voltage follower. An output of the first operational amplifier is applied to an inverting input of a second operational amplifier configured as an integrator. An output of the second operational amplifier is connected to the other of the test terminals. A voltage generated at the output of the second operational amplifier provides an indication of the magnitude and polarity of the voltage applied to the first and second test terminals. | 2009-01-29 |
20090027043 | ROLLER ENCODER - An encoder is provided for a conveyor having a belt, a plurality of rollers supporting the belt and a motor for driving one of the rollers. The encoder includes a hall effect cartridge having at least one hall effect sensor. The hall effect cartridge is adapted to be mounted inside of one of the rollers supporting the conveyor. The encoder also includes a magnetic ring adapted to be mounted inside the roller and rotate with the roller, wherein the ball effect sensor monitors the rotation of the magnetic ring and generates a signal in the form of pulse data based on the rotation of the roller. | 2009-01-29 |
20090027044 | Measuring Arrangement Comprising a Magnet - The invention refers to a measuring arrangement where a magnet moves or is positioned because of the movement or position of an object, and this movement or positioning of the magnet is collected by a sensor, an in particular non-magnetic dividing wall being provided between the magnet and the sensor, and a mechanic converter, in particular a gear being arranged between the object and the magnet. | 2009-01-29 |
20090027045 | Apparatus for sensing position and/or torque - An apparatus for measuring relative displacement between a first shaft and a second shaft includes first and second rotor assemblies. The first rotor assembly is coupled to the first shaft and is centered on an axis. The second rotor assembly is coupled to the second shaft. The second rotor assembly has first and second stator plates. Each of the first and second stator plates includes an upper surface and a lower surface. The first and second stator plates include a plurality of teeth extending in a direction radial of the axis. The apparatus further includes at least one magnet having a magnetic field and disposed on the first rotor assembly. The apparatus includes a flux collector arrangement having first and second collectors positioned adjacent the first and second stator plates, respectively, forming a gap. A sensing device disposed within the gap senses a magnetic flux of the magnetic field. | 2009-01-29 |
20090027046 | MAGNETIC DETECTION DEVICE - A magnetic detection device is provided in which a first signal is outputted in accordance with the mutual phase relationship between the output of a first magnetoelectric conversion output circuit and the output of a second magnetoelectric conversion output circuit that are based on the movement, in forward direction, of a detection subject, thereby generating a pulse of a high level 1 and a low level 1; a second signal is outputted in accordance with the mutual phase relationship between the output of the first magnetoelectric conversion output circuit and the output of the second magnetoelectric conversion output circuit that are based on the movement, in forward direction, of the detection subject; an output signal processing circuit for generating a pulse of a high level 2 and a low level 2 is provided; and not only the pulse of the high level 1 and the low level 1 does not cross the other comparison level, but also the pulse of the high level 2 and the low level 2 does not cross the one comparison level. | 2009-01-29 |
20090027047 | CURRENT SENSOR HAVING SANDWICHED MAGNETIC PERMEABILITY LAYER - A current sensor includes a support structure ( | 2009-01-29 |
20090027048 | Three-Axis Magnetic Sensor and Method for Manufacturing the Same - In the three-axis magnetic sensor of the present invention, a plurality of magnetoresistive effect element bars are connected in series by means of bias magnets to constitute magnetoresistive effect elements, and magnetoresistive effect elements of the X-axis sensor and those of the Y-axis sensor are formed on a flat surface parallel to the flat surface of the substrate. The sensitivity direction of magnetization is a direction vertical to the longitudinal direction of each of the magnetoresistive effect element bars, and magnetoresistive effect elements of the X-axis sensor and those of the Y-axis sensor are formed in such a way that the magnetization directions are orthogonal to each other. Further, magnetoresistive effect elements of the Z-axis sensor are formed on a tilted surface of the projection projected from the flat surface of the substrate in such a way that the magnetization direction is inside the tilted surface. The Z-axis sensor is provided in such a way that the sensitivity direction is vertical to the longitudinal direction of the magnetoresistive effect element bar. | 2009-01-29 |
20090027049 | Cancellation of ringing artifacts and far field interference in nuclear quadrupole resonance - A device for detecting a class of target species containing quadrupolar nuclei in a specimen by nuclear quadrupole resonance, comprising pulse generating means for generating a three-pulse-composite-pulse to refocus signals that were excited by another pulse, irradiating means for irradiating a specimen with the three-pulse-composite-pulse, detecting means for detecting an NQR signal in response to irradiating the specimen, coupling means for transmitting the three-pulse-composite-pulse to the irradiating means, coupling means for receiving the NQR signal from the detecting means and transform means for converting the free induction decay signal into a frequency domain signal. A method for detecting a class of target species containing quadrupolar nuclei in a specimen by nuclear quadrupole resonance, comprising generating a three-pulse-composite-pulse, irradiating said specimen with said three-pulse-composite-pulse, detecting an NQR signal in response to irradiating said specimen and converting said free induction decay signal into a frequency domain signal. | 2009-01-29 |
20090027050 | FREQUENCY SWEPT EXCITATION FOR MAGNETIC RESONANCE - A method of magnetic resonance is provided that uses a frequency swept excitation wherein the acquired signal is a time domain signal is provided. In one embodiment, the method comprises, applying a sweeping frequency excitation and acquiring a time domain signal. The sweeping frequency excitation has a duration and is configured to sequentially excite isochromats having different resonant frequencies. Acquisition of the time domain signal is done during the duration of the sweeping frequency excitation. The time domain signal is based on evolution of the isochromats. | 2009-01-29 |
20090027051 | Method for magnetic resonance imaging using inversion recovery with on-resonant water suppression including mri systems and software embodying same - Featured are methods for magnetic resonance imaging of a volume, such a volume having susceptibility-generating objects or interfaces having susceptibility mismatches therein. Such a method includes selectively visualizing one of susceptibility-generating objects or interfaces having susceptibility mismatches as hyperintense signals, where such visualizing includes controlling variable imaging parameters so as to control a geometric extent of a signal enhancing effect, m more particular aspects of the present invention, such selectively visualizing includes attenuating or essentially suppressing signals from fat and/or water, namely on-resonant water protons, so as to thereby enhance a signal(s) associated with magnetic susceptibility gradient(s). Also featured are MRI systems, apparatuses and/or applications programs for execution on a computer system controlling the MRI data acquisition process embodying such methods. | 2009-01-29 |
20090027052 | Method for acquiring measured data - A PET examination which acquires a data record of the body of a patient is carried out during at least one embodiment of a method for acquiring measured data. On the basis of the measured values of the data record, at least one region of interest in the body of the patient is determined, in which at least one examination of at least one embodiment of a method is carried out. | 2009-01-29 |
20090027053 | MAGNETIC RESONANCE EXAMINATION PLATFORM WITH INDEPENDENTLY MOVEABLE BED AND ANTENNA DEVICE - An examination platform for a magnetic resonance apparatus has a patient bed for supporting a patient, a local antenna device for acquisition of magnetic resonance signals, and a drive device arranged at the patient bed. The drive device is coupled with the local antenna device. The local antenna device thus can be moved parallel to the longitudinal axis of the patient bed independently of a movement of the patient bed. A magnetic resonance apparatus and a method for acquisition of image data of a patient employ such an examination platform. | 2009-01-29 |
20090027054 | RADIO-FREQUENCY ACQUISITION DEVICE FOR A MAGNETIC RESONANCE TOMOGRAPHY APPARATUS - A radio-frequency acquisition device for a magnetic resonance tomography apparatus has at least one reception antenna for acquisition of magnetic resonance signals and with an amplifier device to amplify acquired magnetic resonance signals. The amplifier device has an input transistor and a transformation device to transform the source impedance of the acquisition antenna into a source impedance adapted to the input transistor, and wherein the transformation device can be switched between at least two transformation ratios. | 2009-01-29 |
20090027055 | Locating Technique and Apparatus Using an Approximated Dipole Signal - Location determination is performed using a transmitter including an elongated generally planar loop antenna defining an elongation axis. The elongation axis is positioned along at least a portion of a path. A magnetic field is then generated which approximates a dipole field. Certain characteristics of the magnetic field are then determined at a receiving position radially displaced from the antenna elongation axis. Using the determined certain characteristics, at least one orientation parameter is established which characterizes a positional relationship between the receiving position and the antenna on the path. The magnetic field may be transmitted as a monotone single phase signal. The orientation parameter may be a radial offset and/or an angular orientation between the receiving position and the antenna on the path. The antenna of the transmitter may be inserted into a first borehole to transmit the magnetic field to a receiver inserted into a second borehole. | 2009-01-29 |
20090027056 | Battery performance monitor - Improvements both in the methods whereby existing techniques for determining the condition of a battery are communicated to a user (for example, to the owner of a private vehicle, or to the service manager of a fleet of vehicles), or the vehicle's operating system, and in the methods for evaluating the condition of the battery are disclosed. It has been discovered by the inventors that the difference in internal resistance of a fully charged battery as measured during charging and as measured after charging is greater for a battery in poor condition than for a new battery. The invention relates in part to instruments and corresponding methods for evaluating the condition of a battery utilizing this discovery. | 2009-01-29 |
20090027057 | Ethernet Electrometer - An electrometer includes an input terminal adapted to receive an input signal an ethernet terminal, a web server, and a microcontroller. The ethernet terminal is adapted to receive an ethernet cable such that electrical power is provided to the ethernet terminal. The web server is in electrical communication with the ethernet terminal, and is adapted to receive a command. The microcontroller is in electrical communication with at least one of the ethernet terminal and the web server, and is adapted to execute the received command. | 2009-01-29 |
20090027058 | Integrated circuit and integrated circuit package - An integrated circuit includes a monitoring-target circuit portion | 2009-01-29 |
20090027059 | Techniques for Detecting Open Integrated Circuit Pins - A technique of detecting an open integrated circuit (IC) pin includes selectably coupling a first open detect circuit, which includes a first inverter having a first threshold, to the IC pin. Next, a first logic state at an output of the first inverter is determined. Then, based upon the first logic state, it is determined whether the IC pin is open or whether it is indeterminate as to whether the IC pin is open. When it is indeterminate as to whether the IC pin is open, based on the first logic state, a second open detect circuit is selectably coupled to the IC pin. The second open detect circuit includes a second inverter having a second threshold (the first threshold is greater than the second threshold). A second logic state at an output of the second inverter is then determined. Finally, based upon the first and second logic states, it is determined whether the IC pin is open. | 2009-01-29 |
20090027060 | ADAPTER AND INTERFACE AND ELECTRONIC DEVICE TEST APPARATUS PROVIDED WITH ADAPTER - An adapter able to reduce the costs of an electronic device test apparatus, the adapter having a frame member interposed, between an opening formed at a handler and a HIFIX attached to a test head and inserted in the opening for adapting the shape of the HIFIX to the shape of the opening. | 2009-01-29 |
20090027061 | METHOD AND APPARATUS FOR AN ELECTRICAL CONDUCTOR MONITORING SYSTEM - A system and method for determining the status of each monitored conductor, and optionally indicating peak current or other parameters are provided. Wireless self-powered sensor elements can eliminate much of the wiring required in traditional systems, and greatly ease the installation in difficult underground locations. | 2009-01-29 |
20090027062 | PARTIAL DISCHARGE DETECTION DEVICE - The present invention provides a high-performance partial discharge detection device which is user-friendly and compact and which allows detection of the electromagnetic waves caused by partial discharge, over a wide bandwidth with a simple constitution and a favorable S/N ratio. The waveguide antenna which receives electromagnetic waves that leak from the insulating spacer is attached to the outer circumferential face of the insulating spacer. The waveguide antenna is constituted by a waveguide portion and a coaxial cable connector which is installed on the waveguide portion. The waveguide portion has a metal short-circuit plate provided at one end thereof, and an opening formed at the other end thereof, which covers part of the outer circumferential face of the insulating spacer. | 2009-01-29 |
20090027063 | Method for Calibrating an Electrostatic Discharge Tester - The present disclosure relates to a method for calibrating transient behaviour of an electrostatic discharge (ESD) test system. The system includes an ESD pulse generator and probe needles for applying a predetermined pulse on a device under test. The probe needles are connected to the ESD pulse generator via conductors. The test system includes measurement equipment for detecting transient behaviour of the device under test by simultaneously capturing voltage and current waveforms the device as a result of the pulse. The method comprises the steps of: (a) applying the ESD test system on a first known system with a first known impedance, (b) applying the ESD test system on a second known system with a known second impedance, and (c) determining calibration data for the transient behaviour the ESD test system on the basis of captured voltage and current waveforms, taking into account said known first and second impedances. In preferred embodiments the waveforms are transferred to the frequency domain for correlation. | 2009-01-29 |
20090027064 | METHOD AND SYSTEM FOR ERROR CHECKING AN ELECTROCHEMICAL SENSOR - A method and a corresponding system for error checking an electrochemical sensor having at least two electrodes and a liquid measuring medium applied thereto are disclosed. The method comprises determining a first admittance between a first set of electrodes of the sensor; determining a second admittance between a second set of electrodes of the sensor; determining a value using the first admittance and the second admittance; and displaying an error message if the value is out of a predetermined tolerance. | 2009-01-29 |
20090027065 | Wordline-To-Bitline Output Timing Ring Oscillator Circuit for Evaluating Storage Array Performance - A wordline-to-bitline timing ring oscillator circuit for evaluating storage cell access time provides data on internal bitline access timing, and in particular the total wordline select-to-bitline read output timing. Columns of a storage array are connected in a ring, forming a ring oscillator. The bitline read circuit output of each column is connected to a wordline select input of a next column, with a net inversion around the ring, so that a ring oscillator is formed. The period of oscillation of the ring oscillator is determined by the total wordline select-to-bitline read circuit output timing for a first phase and the pre-charge interval time for the other phase, with the bitline read timing dominating. The circuit may be applied both to small-signal storage arrays, with the sense amplifier timing included within the ring oscillator period, or to large-signal storage arrays, with the read evaluate circuit timing included. | 2009-01-29 |
20090027066 | Method and system of real-time estimation of transmission line parameters in on-line power flow calculations - A system and method for estimating parameters of transmission lines employing phasor measurement units is provided, wherein measurements are provided from the phasor measurement units relating to a transmission line. These measurements are filtered to remove invalid measurements. Using the remaining valid measurements, resistance, reactance and grounding admittance are calculated and estimated and checked for errors. | 2009-01-29 |
20090027067 | Method and system for real time identification of voltage stability via identification of weakest lines and buses contributing to power system collapse - A method of identifying voltage instability in a power system via identification of a weakest line and bus that contribute to the collapse of the system is provided. The method includes periodically calculating an extended line stability index for the transmission lines monitored in the power system; and using the extended line stability index to determine the distance of an operation state in the power system from a collapse point of the system caused by voltage instability. | 2009-01-29 |
20090027068 | Proximity Sensor - A capacitive touch sensor providing an automatic switch-off function for an apparatus in which the sensor is incorporated is provided. The sensor comprises a sensing element coupled to a capacitance measurement circuit for measuring the capacitance of the sensing element. A control circuit is operable to determine from the capacitance measurement whether an object is in proximity with the sensor. The determined presence of an object may be used to toggle a function of the apparatus. Furthermore, when it is determined that an object has not been in proximity with the sensor for a predetermined time duration, an output signal for switching off the apparatus is provided. The predetermined time duration may be selected from a number of predefined time durations, or may be programmed using an resistor-capacitor network. Pulses may be applied to the control circuit to override features of the automatic switch-off functionality. | 2009-01-29 |
20090027069 | FUNCTIONALIZED CARBON NANOTUBE-POLYMER COMPOSITES AND INTERACTIONS WITH RADIATION - The present invention involves the interaction of radiation with functionalized carbon nanotubes that have been incorporated into various host materials, particularly polymeric ones. The present invention is directed to chemistries, methods, and apparatuses which exploit this type of radiation interaction, and to the materials which result from such interactions. The present invention is also directed toward the time dependent behavior of functionalized carbon nanotubes in such composite systems. | 2009-01-29 |
20090027070 | ELECTROCHEMICAL IMPEDANCE SPECTROSCOPY METHOD AND SYSTEM - A dual cell Electrochemical Impedance System (EIS) testing apparatus and method for measuring coating integrity on various substrates. The counter reference electrode is in a first cell in electrical contact with the coating. The working electrode is in a second cell in electrical contact with the coating instead of the substrate material acting as the working electrode. Voltage is applied at the working electrode at varying frequencies and current is measured at the combined reference/counter electrode. From the known voltage and the measured current, the impedance of the coating is calculated. Coatings on non-metallic substrates can be measured with this apparatus. In one embodiment, the EIS cells are in the form of vacuum cups containing an electrolyte gel for testing non-horizontal coatings in the field. Also, known current can be applied to the working electrode and voltage measured at the counter reference electrode can be used to calculate coating impedance. | 2009-01-29 |
20090027071 | PROBE TAP - A probe tap that monitors data or signals occurring within a device is disclosed. The probe tap can be used to monitor signals, data, or other communications between components of the device. The probe tap can be connected to traces, pins, or other aspects or components of a device and collects data that can be analyzed. The probe tap can include one or more leads that can be removably connected with or between components of a device. The collected data can be provided to an analyzer for analysis. A pod can be included in the probe tap that is used to prepare the data for analysis by the analyzer. Alternately or additionally, the pod can be included in the analyzer. | 2009-01-29 |
20090027072 | APPARATUS FOR TESTING CHIPS WITH BALL GRID ARRAY - An exemplary an apparatus for testing chips with ball grid array comprised of a number of solder balls is provided. The apparatus includes a main printed circuit board, a supporting board and a testing device. The main printed circuit board has a edge connector. The supporting board defines a number of electrically conductive through holes arranged in an array corresponding to the ball grid array. One end of each of the electrically conductive through holes is configured for electrically connection to the main printed circuit board, the other end of the electrically through holes is configured for receiving and electrically connecting the corresponding solder ball of the ball grid array. The testing device has a socket connector for insertion of the edge connector therein. The testing device is configured for testing the chip. | 2009-01-29 |
20090027073 | DEVICE MOUNTED APPARATUS, TEST HEAD, AND ELECTRONIC DEVICE TEST SYSTEM - A device mounted apparatus includes a board on which a plurality of devices are mounted and a device cooling cover covering the plurality of devices, and formed inside it with a channel through which a refrigerant can flow. The device cooling cover includes a first cover covering only the measurement device among the plurality of devices, and a second cover covering only the power device among the plurality of devices. The first cover and the second cover are electrically insulated from each other. | 2009-01-29 |
20090027074 | Test structure and test method - The present invention discloses a wafer level test structure and a test method; in which, a heating plate is formed on the wafer for heating a structure to be tested positioned above or adjacent to the heating plate. The heating plate produces heat by electrically connecting to a current. Thus, the heat provided by the heating plate and the electric input/output into/from the structure to be tested are controlled separately and not influenced each other. | 2009-01-29 |
20090027075 | System And Method of Digitally Testing An Analog Driver Circuit - A circuit and method of testing an analog driver circuit using digital scan-based test methodologies. The circuit of the present invention comprises a control circuit for generating signals in response to a test enable signal, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal in response to the differential input signal and the signals generated by the control circuit, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit in response the signals generated by the control circuit, and a differential receiver circuit for receiving the differential output from the differential driver circuit, convert the differential output signal to a single ended signal and transmitting the single ended signal, all in response to the test enable signal. The method of the present invention comprises digitally testing the differential driver circuit by activating a test enable signal, skewing the differential output termination impedance in response to the test enable signal, adjusting a voltage offset of the differential receiver circuit in response to the test enable signal, selecting a power level for the differential driver circuit in response to the test enable signal, enabling a decoder in response to the test enable signal, wherein the decoder activates only one segment of the differential driver circuit during any one test sequence, activating one of the segments for testing, stimulating the differential driver circuit with digital test patterns, receiving an output of the differential driver circuit by the differential receiver circuit, converting the received differential driver output to a single-ended signal, observing the single-ended signal; and deactivating the test enable signal. | 2009-01-29 |
20090027076 | DEVICE AND METHOD FOR TESTING INTEGRATED CIRCUIT DICE IN AN INTEGRATED CIRCUIT MODULE - An IC module, such as a Multi-Chip Module (MCM), includes multiple IC dice, each having a test mode enable bond pad, such as an output enable pad. A fuse incorporated into the MCM's substrate connects each die's test mode enable bond pad to one of the MCM's no-connection (N/C) pins, and a resistor incorporated into the substrate connects the test mode enable bond pads to one of the MCM's ground pins. By applying a supply voltage to the test mode enable bond pads through the N/C pin, a test mode is initiated in the dice. Once testing is complete, the fuse may be blown, and a ground voltage applied to the test mode enable bond pads through the ground pins so the resistor disables the test mode in the dice and initiates an operational mode. As a result, dice packaged in IC modules may be tested after packaging. | 2009-01-29 |
20090027077 | METHOD AND APPARATUS FOR IDENTIFYING OUTLIERS FOLLOWING BURN-IN TESTING - A method includes performing burn-in testing of a device in a tester to generate post burn-in data. Pre-burn-in data associated with the device is compared to the post burn-in data. The device is identified as an outlier device based on the comparison. | 2009-01-29 |
20090027078 | FAULT TOLERANT ASYNCHRONOUS CIRCUITS - New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits. | 2009-01-29 |
20090027079 | Method and Apparatus for Implementing Complex Logic Within a Memory Array - A logic gate is described that implements complex logic within a memory array. The logic gate receives at least three of a first storage cell signal, a second storage cell signal, a first external signal, or a second external signal at a first input circuitry and second input circuitry. The logic gate then performs one of a set of logic functions using the first storage cell signal, the second storage cell signal, the first external signal, or the second external signal. The set of logic functions includes at least one of a matching function, an OR-AND function, or an AND function. | 2009-01-29 |
20090027080 | Low leakage and data retention circuitry - An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry. | 2009-01-29 |
20090027081 | Eight Transistor Tri-State Driver Implementing Cascade Structures To Reduce Peak Current Consumption, Layout Area and Slew Rate - An eight-transistor tri-state driver. The tri-state driver implements multiple cascade structures where each cascade structure may refer to a pair of complementary transistors serially connected. Each cascade structure may include a p-conductivity type transistor serially connected to a n-conductivity type transistor. By implementing cascade structures in a tri-state driver, there is a lower peak current consumption, a reduced slew rate as well as a reduction in the amount of layout area used in comparison to the classic tri-state drivers. | 2009-01-29 |
20090027082 | Level shifter - A level shifter is operated at high speed. An input unit | 2009-01-29 |
20090027083 | SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS HAVING THE SAME - With an offset circuit including transistors of the same conductivity type, offset of an input signal is performed. Then, the input signal after the offset is supplied to a logic circuit including transistors of the same conductivity type as that of the offset circuit, thereby H and L levels of the input signal can be shifted at the same time. Further, since the offset circuit and the logic circuit are formed using the transistors of the same conductivity type, a display device can be manufactured at a low cost. | 2009-01-29 |
20090027084 | RAPID RESPONSE PUSH-UP PULL-DOWN BUFFER CIRCUIT - A rapid response push-up pull-down buffer circuit configuration is used as an output buffer of a semiconductor memory device. The buffer circuit includes a pre-driver outputting a driving signal in response to an input data. The buffer circuit also includes an output driver driving an output signal in response to the driving signal which also has a driving strength adjusted in response to a level of the output signal. Accordingly, the driving strength can be automatically controlled in response to a level of the output signal which also results in enhancing the response speed of the buffer circuit. | 2009-01-29 |
20090027085 | RESONANT CLOCK AND INTERCONNECT ARCHITECTURE FOR DIGITAL DEVICES WITH MULTIPLE CLOCK NETWORKS - A clock and data distribution network is proposed that distributes clock and data signals without buffers, thus achieving very low jitter, skew, loose timing requirements, and energy consumption. Such network uses resonant drivers and is generally applicable to architectures for programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs), as well as other semiconductor devices with multiple clock networks operating at various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, applications specific integrated circuits (ASICs), and Systems-on-a-Chip (SOCs). | 2009-01-29 |
20090027086 | Comparator and method with controllable threshold and hysteresis - A comparator ( | 2009-01-29 |
20090027087 | LOW POWER VOLTAGE DETECTION CIRCUIT AND METHOD THEREFOR - In one embodiment, a low power voltage detection circuit includes a first voltage detection device that receives power from an input voltage and a second voltage detection device receives power from an output of the low power voltage detection circuit. | 2009-01-29 |
20090027088 | HIGH RESOLUTION TIME DETECTING APPARATUS USING INTERPOLATION AND TIME DETECTING METHOD USING THE SAME - A high resolution time detecting apparatus using interpolation and a time detecting method using the same are provided. The time detecting apparatus includes a delayer which generates delayed signals by sequentially delaying a reference signal using a plurality of delay elements, a latch unit which outputs latch signals using the delayed signals, and an interpolation unit which outputs interpolated signals using input and output signals of the delay elements. As a result, a high resolution TDC using an interpolation and a time detecting method using the same provide improved performance of digital PLL, high resolution digital signal output at a low power consumption, and controlled circuit size. | 2009-01-29 |
20090027089 | Driver Circuit; Electronic Circuit Having Driver Circuit and Corresponding Method - A driver circuit includes an output, at least one transistor including a load section coupled between the output and a supply voltage, and a circuit coupled to a control terminal of the at least one transistor to apply a control voltage to the control terminal in at least one operation mode of the driver circuit. The control voltage is within a predetermined voltage range de-pending on a first predetermined voltage below a nominal voltage range of the output. | 2009-01-29 |
20090027090 | CURRENT MODE MEMORY APPARATUS, SYSTEMS, AND METHODS - Some embodiments include a first circuit to receive input signals and to drive signals at first circuit output nodes, and a second circuit to receive at least a portion of current passing through the first circuit output nodes and to generate output signals at second circuit output nodes, the second circuit including a pair of transistors coupled to the second circuit output nodes with gates of the pair of transistors to receive different signals to affect a value of a voltage difference between the output signals, the different signals being different from the output signals. Other embodiments including additional apparatus, systems, and methods are disclosed. | 2009-01-29 |
20090027091 | CLOCK FREQUENCY DIVIDING CIRCUIT - A first frequency dividing circuit and a second frequency dividing circuit are provided, and these circuits frequency-divide two-phase external clocks injected from an external part, to output four-phase clocks with phase guarantee. Each of the frequency dividing circuits includes a mixer, an adding circuit, and a phase circuit. The first frequency dividing circuit and the second frequency dividing circuit are coupled in loop shape via a first coupling circuit and a second coupling circuit. The first coupling circuit receives a first output signal of the first frequency dividing circuit to output a second external input signal to the second frequency dividing circuit, and the second coupling circuit receives a second output signal of the second frequency dividing circuit to output a first external input signal to the first frequency dividing circuit, and a clock frequency dividing circuit with a high loop gain and a wide lock range can be realized. | 2009-01-29 |
20090027092 | METHOD AND APPARATUS FOR PRODUCING CLEAN, UNDISTORTED VARIABLE VOLTAGE 50 - 60 HZ SINE WAVE - The invention is directed to a solid-state replacement for a variable transformer. The circuit arrangement presented is not placed in series with the load. It can change output voltage quickly, and is able to deliver more current to the load than is drawn from the source while stepping down because the circuit is not placed in series with a load. The output voltage from the driver circuit is a low-frequency sine wave that is “chopped” by a high frequency carrier, yet the end result after the transformer or LC filter is a very clean sine wave. The circuit arrangement is lightweight and inexpensive to fabricate. | 2009-01-29 |
20090027093 | SAMPLING CIRCUIT AND METHOD - A sampling circuit for sampling an input data to obtain an output data includes a delay control unit, a first sampling unit, a second sampling unit, and a processing unit. The delay control unit delays a sampling signal for a first delay time to generate a first delayed signal, and delays the sampling signal for a second delay time to generate a second delayed signal; the first sampling unit samples the input data to obtain a first sampled value according to the first delayed signal, wherein the first sampling unit is utilized to generate the output data; the second sampling unit samples the input data to obtain a second sampled value according to the second delayed signal; and the processing unit controls the delay control unit to adjust at least the first delay time according to the first and second sampled values to calibrate the first delayed signal. | 2009-01-29 |
20090027094 | TRIMMABLE DELAY LOCKED LOOP CIRCUITRY WITH IMPROVED INITIALIZATION CHARACTERISTICS - Disclosed herein is improved delay locked loop (DLL) initialization circuitry that alters the measurement used to initialize the variable delay line's delay (e.g., entry point or exit point) by using three clock phases: the DLL reference clock (input to the delay line), the reference clock as trimmed by a delay Tref, and the feedback clock as trimmed by a delay Tfb. By using these three phases at the appropriate time, the measurement is aware of the Tac trim for both positive (Tref) and negative (Tfb) trims. Specifically, measurement ‘start’ and ‘stop’ signals each pass through only one of delays Tref and Tfb, such that error in the measurement is a function of both Tref and Tfb. This improves the accuracy of the measurement such that additional shifting of the DLL is not necessary after initialization, and allows a wide trim range even for high clock frequencies. | 2009-01-29 |
20090027095 | THRESHOLD CORRECTION CIRCUIT, INTEGRATED CIRCUIT WITH THRESHOLD CORRECTION FUNCTION, AND CIRCUIT BOARD WITH THRESHOLD CORRECTION FUNCTION - In order to monitor various types of noises which are to be introduced on signals through signal lines on a circuit board and automatically adjust the thresholds for signal state discriminations to make it possible to surely make a signal state discrimination without being affected by these noises even if the amplitude of a signal is reduced for higher-speed transmission and lowered electric power, there is provided a configuration comprising a signal generation unit generating a noise monitor signal; a noise monitor signal line receiving and propagating the noise monitor signal; a noise detection unit detecting a noise which has been introduced into that noise monitor signal propagated through the noise monitor signal line and which affects a state discrimination using a threshold; and a threshold adjustment unit, if the noise detection unit detects the noise, adjusting the threshold such that the state discrimination is not affected by the noise. | 2009-01-29 |
20090027096 | DC BRUSHED MOTOR DRIVE WITH CIRCUIT TO REDUCE DI/DT AND EMI, FOR MOSFET VTH DETECTION, VOLTAGE SOURCE DETECTION, AND OVERPOWER PROTECTION - A gate driver for performing gate shaping on a first transistor of having gate, source, and drain terminals, the first transistor being selected from a switching stage of a power switching circuit having high- and low-side transistors series connected at a switching node for driving a load. The gate driver includes the following steps: upon receipt of an ON pulse pre-charging the gate terminal until gate to source terminal voltage equals Vth, controlling the di/dt(ON) flowing in the first transistor while free wheeling current is flowing in a second transistor of the switching stage, and controlling the dv/dt(ON) of the first transistor while a charge on the gate terminal is present; and upon receipt of an OFF pulse controlling the dv/dt(OFF) of the first transistor until free wheeling current is flowing in the second transistor, and controlling the di/dt(OFF) flowing in the first transistor while the gate to source terminal voltage equals Vth. | 2009-01-29 |
20090027097 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefore for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool. | 2009-01-29 |
20090027098 | Phase shift circuit with lower intrinsic delay - A phase shift circuit that includes two, rather than four, delay chains and corresponding selectors is described. This provides a significant area savings and reduces the intrinsic delay of the phase shift circuit, which is particularly beneficial for embodiments in which there is no intrinsic delay matching. In one specific implementation, the phase shift circuit includes a first delay circuit and a matching delay circuit. The first delay circuit provides a first delay that includes a first intrinsic delay and a first intentional delay. The delay matching circuit provides a matching delay that matches the first intrinsic delay. In one specific implementation, the phase shift circuit also includes a second delay circuit to provide a second delay that includes a second intrinsic delay and second intentional delay, where the second intrinsic delay matches the first intrinsic delay and the second intentional delay is half as long as the first intentional delay. Matching the intrinsic delay of the first delay circuit allows for comparing its output against a delayed version of the input signal, rather than the input signal. As a result, Fmax, the maximum frequency of the input signal at which the phase shift circuit may operate, is not limited by the intrinsic delay or by Fmin, the minimum frequency of the input signal at which the phase shift circuit may operate. | 2009-01-29 |
20090027099 | Output driver circuit having a clamped mode and an operating mode - An output driver circuit | 2009-01-29 |
20090027100 | LEVEL SHIFTER AND FLAT PANEL DISPLAY USING THE SAME - A level shifter for a flat panel display device includes: first and second transistors that are different type transistors and serially coupled between first and second power supplies, the second power supply for supplying a lower voltage power than the first power supply; a first capacitor between gate electrodes of the first and second transistors; an input line for a first input signal coupled to the gate electrode of the first or second transistor; a third transistor between a second electrode of the first capacitor and a third power supply, the third transistor having a gate electrode coupled to an input line of a second input signal; and a fourth transistor between the second electrode of the first capacitor and the third transistor, the fourth transistor having first and gate electrodes that are coupled to the second electrode of the first capacitor, such that the fourth transistor is diode-connected. | 2009-01-29 |
20090027101 | LEVEL SHIFT CIRCUIT - The present invention provides a level shift circuit that can reliably cut off the path of a through current regardless of the state of supply of power to plural circuit sections that operate by different power supplies. The level shift circuit is provided with an input circuit section that operates by a power supply voltage VDD | 2009-01-29 |
20090027102 | Low-Leakage Level-Shifters with Supply Detection - Low-leakage level-shifters with reduced leakage are disclosed. In one example, a level-shifter circuit to reduce leakage when there is an invalid supply voltage is described, including a level-shifter configured to shift a voltage of an digital input signal based on a first supply voltage to a digital output signal based on a second supply voltage, comprising a first transistor and a second transistor configured to set the digital output signal based on the digital input signal, a supply detector configured to generate a detection signal based on the first supply voltage, a disabler configured to, based on the detection signal, set the digital output signal of the level-shifter to a predetermined state, and a leakage reducer configured to, based on the detection signal, electrically disconnect the first and second transistors from the level-shifter. | 2009-01-29 |
20090027103 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit capable of maintaining characteristics of transistors in a circuit including a plurality of cascade connected transistors. The circuit includes an inverter which has a series connection of P-MOS transistors and a pair of N-MOS transistors. The P-MOS transistor is connected to a high potential source V | 2009-01-29 |
20090027104 | Methods and apparatus for predictable level shifter power-up state - In one aspect, a level shifter for shifting a voltage level from a first voltage level to a second voltage level and having a predictable power-up state is provided. The level shifter comprises a first input and a second input forming a differential input to receive signals at the first voltage level, a first output and a second output forming a differential output to provide output signals at the second voltage level, and at least one circuit element coupled between the differential input and the differential output to pull the first output to a lower voltage level than the second output during power-up so that the level shifter powers-up in a desired state | 2009-01-29 |
20090027105 | Voltage divider and internal supply voltage generation circuit including the same - In a voltage divider and an internal supply voltage generation circuit, the voltage divider includes a first transistor having a resistance value that varies in proportion to a change in temperature; and a second transistor having a resistance value that varies in inverse proportion to the change in temperature. | 2009-01-29 |
20090027106 | Substantially Zero Temperature Coefficient Bias Generator - In an embodiment, a bias generator circuit comprises a first circuit and a second circuit. The first circuit includes a first input coupled to a voltage source and a first output that provides a first output current having a substantially non-zero temperature coefficient. The first circuit comprises a first transistor and a second transistor. The second circuit includes a second input that receives the first output current from the first circuit and a second output that provides a second output current. The second circuit comprises a third transistor and a fourth transistor. The second output current has a substantially zero temperature coefficient dependent on (i) a difference between an effective channel size of the first transistor and an effective channel size of the second transistor, and (ii) a difference between an effective channel size of the third transistor and an effective channel size of the fourth transistor. | 2009-01-29 |
20090027107 | SEMICONDUCTOR DEVICE AND OFFSET VOLTAGE ADJUSTING METHOD - A semiconductor device includes a fuse section having a plurality of fuse circuits configured to generate switch control signals; and an offset adjusting section configured to adjust an offset voltage of a differential amplifier based on the switch control signals supplied from output nodes of the plurality of fuse circuits. Each of the plurality of fuse circuits includes a fuse connected between a first power supply voltage and a cut node; a current source connected between a second power supply voltage and the output node; and a first transistor connected between the output node and the cut node and having a gate connected to the second power supply voltage. | 2009-01-29 |
20090027108 | Multiple-stage charge pump circuit with charge recycle circuit - A multiple-stage charge pump circuit includes first and second pump capacitors, a charge recycle circuit, and first and second transfer circuits. The charge recycle circuit includes first and second driving circuits and a switch circuit turning off to make a node floating and to couple first terminals of the first and second pump capacitors to the node in a first time period. The switch circuit and first and second driving circuits provide a specific voltage to the node and control voltages at the first terminals of the first and second pump capacitors in second and third time periods, respectively. The first and second transfer circuits provide a high voltage to a second terminal of the first pump capacitor in the second time period, and provide the voltage of the second terminal of the first pump capacitor to a second terminal of the second pump capacitor in the third time period. | 2009-01-29 |
20090027109 | CHARGE PUMP CIRCUIT WITH BIPOLAR OUTPUT - A charge pump circuit with bipolar output comprises a first set of switch device capable of selectively connecting two terminals of a first transfer capacitor to a voltage source and a ground terminal, respectively, a second set of switch device capable of selectively connecting the two terminals of the first transfer capacitor to a grounded first storage capacitor and the voltage source, respectively, a third set of switch device capable of selectively connecting two terminals of a second transfer capacitor to the first transfer capacitor connected to the voltage source and the ground terminal, respectively, and a fourth set of switch device capable of selectively connecting the two terminals of the second transfer capacitor to a grounded second storage capacitor and the ground terminal, respectively. These four sets of switch devices totally have nine switches, and are collocated with clock signals to be selectively driven by a four-phase signal or a two-phase signal so as to produce bipolar voltages with magnitudes higher than the input voltage and also accomplish the highest conversion efficiency. | 2009-01-29 |
20090027110 | HIGH VOLTAGE GENERATOR - A high voltage generator includes a charge pump configured to output a pumping voltage in accordance with a first clock signal and a second clock signal having a level opposed to a level of the first clock signal; a first regulator configured to stabilize the pumping voltage to a voltage having constant level, thereby outputting a first regulation voltage; and a second regulator configured to convert the first regulation voltage into a voltage having constant level, thereby outputting a second regulation voltage. Here, the first regulator increases the pumping voltage by n number so that the first regulation voltage reaches a first level, and the second regulator increases the first regulation voltage by m number so the second regulation voltage reaches a second level smaller than the first level. | 2009-01-29 |
20090027111 | ALTERNATING CURRENT LEVEL DETECTION CIRCUIT - A detection circuit includes a current source with no temperature coefficient; a current generation circuit that generates a VBE proportional reference current from the current source with no temperature coefficient; a current mirror circuit that returns an output current of the current generation circuit; a reference voltage generation circuit that generates a VBE proportional voltage with a negative temperature coefficient on the basis of the current returned by the current mirror circuit so that the VBE proportional voltage is used as a reference voltage of a comparator; and a full-wave rectifying means, having a differential pair and a rectifier circuit, using the current source with no temperature coefficient, having an alternating current signal supplied as an input signal, for generating a direct current voltage with a negative coefficient on the basis of a voltage obtained by full-wave rectifying the alternating current signal, and for using the generated voltage as a comparative voltage of the comparator. | 2009-01-29 |
20090027112 | CONTROLLABLE PRECISION TRANSCONDUCTANCE - Techniques for providing precise transconductance values are disclosed. For instance, an apparatus includes a slave transconductance cell and a control loop. The control loop provides a tuning voltage to the slave transconductance cell. Moreover, the control loop includes a master transconductance cell that generates a master output current, and a current amplifier that generates the tuning voltage based on an error signal. The error signal reflects a difference between a reference current and the master output current. Further, the current amplifier provides the tuning voltage to the master transconductance cell. | 2009-01-29 |