05th week of 2009 patent applcation highlights part 29 |
Patent application number | Title | Published |
20090027913 | Lighting Arrangement for an Automotive Vehicle - A lighting array comprising a plurality of lighting modules, each lighting module comprising a substrate having at least one light emitting diode mounted thereon is disclosed. The modules are arranged to radiate light in a substantially parallel manner. At least some of the modules in the array are arranged in a stepwise manner to adapt to the curvature of an automotive glazing. The modules are preferably arranged to form a centre high mount stop lamp. | 2009-01-29 |
20090027914 | Structure for a center high mounted stop lamp - The present invention discloses a structure for a center high mounted stop lamp, which comprises: a light pipe, a housing and LEDs. The light pipe has an inorganic light guide coating on a lateral side thereof and has LEDs at both ends thereof. The housing covers the light pipe and has a light reflection layer. The light reflection layer is arranged around the light pipe and behind the inorganic light guide coating. The light emitted by LEDs is scattered by the light pipe and reflected by the inorganic light guide coating. Thus, the light pipe can uniformly emit light. Further, the light emitted by the light pipe is concentrated and reflected out by the light reflection layer. Thereby, the present invention can decrease the number of required LEDs, save power, prolong the service life of LEDs and promote economic efficiency. | 2009-01-29 |
20090027915 | LIGHT SOURCE UNIT AND OBJECT READER - A light source unit and reader can include a line light source that is attached to a radiator and a rod lens that is attached above the line light source. The radiator with the line light source and the rod lens attached thereto, and a linear strip-shaped reflector arranged in front of the rod lens, are housed in a carriage. The carriage is supported beneath contact glass and movable in a direction normal to a longitudinal axis of the line light source. The lens has a section in a plane normal to a longitudinal axis of the lens, in which a surface of the lens facing the light source has a curved line that expands or is convexly facing toward the light source. The opposite surface of the lens from the light source has composite curves including a plurality of continuous curves with different radii of curvature. The composite curves are located on both sides of a plane containing the optical axis of the LED and expand or are convex in an opposite direction from the light source. | 2009-01-29 |
20090027916 | LED lamp tube - An LED lamp tube is disclosed to include a tube that admits light, circuit boards respectively mounted inside the tube, each circuit board carrying an array of LEDs, two end caps respectively capped on the ends of the tube to hold the circuit boards inside the tube and connectable to connectors of a conventional fluorescent bulb holder to secure the tube to the conventional fluorescent bulb holder, and a power cord extending from the circuit boards out of the tube for connection to power supply to obtain the necessary working voltage for the LEDs. | 2009-01-29 |
20090027917 | OPTICAL FIBER INDICATOR LIGHT - The optical fiber indicator light includes a lighting device, an optical fiber and an optical guiding structure. The optical fiber has a first optical fiber point a second optical fiber point. The first optical fiber point is abutted on the lighting device and the second optical fiber point is opposed against the first optical fiber point. The optical guiding structure has a lens, a passage, and an air chamber connected with the passage. The air chamber is located behind the lens. A portion of the optical fiber is contained in the passage, and the second optical fiber point is placed in the air chamber. Light emitted from the optical fiber may be diffused by the air chamber to enlarge visible area of the optical fiber. | 2009-01-29 |
20090027918 | TRANSREFLECTORS, TRANSREFLECTOR SYSTEMS AND DISPLAYS AND METHODS OF MAKING TRANSREFLECTORS - Light emitting assembly includes at least one film, sheet, plate or substrate positioned between a light source and a display for redirecting at least some of the light emitted by the light source. One side of the film, sheet, plate or substrate may have a pattern of reflective or refractive surfaces or deformities and the other side may have corresponding or aligned optical deformities of well defined shape. Light emitted from the light source that strikes a reflective or refractive surface or deformity on the one side of the film, sheet, plate or substrate passes through the film, sheet, plate or substrate and is redirected by at least one corresponding optical deformity on the other side of the film, sheet, plate or substrate. | 2009-01-29 |
20090027919 | BACKLIGHT MODULE - A backlight module including a back plate, a reflection sheet, a light guiding plate, a reflector, and a first light source and a second light source is provided. The reflection sheet is disposed on the back plate, and one end of the reflection sheet is bent to form a lamp reflector. The light guiding plate is disposed on the reflection sheet, and has a first side and a corresponding second side. A first containing space is formed between the first side of the light guiding plate and the lamp reflector. The reflector is disposed at the second side of the light guide plate, and a second containing space is formed between the second side of the light guiding plate and the reflector. The first light source and the second light source are disposed within the first and the second containing space, respectively. | 2009-01-29 |
20090027920 | LIGHT EMITTING PANEL ASSEMBLIES - Backlight assembly includes a waveguide having a greater width than height and at least one light emitting area for illuminating a display. A light source assembly optically coupled to the panel includes a light emitting source and at least a reflective or refractive surface to disperse light emitted from the light emitting source more along the width than height of the panel. | 2009-01-29 |
20090027921 | ELECTRONIC DEVICE - An electronic device includes a case, a display panel and a backlight module. The case has at least a hole. The display panel is disposed in the case to display information. The backlight module is disposed in the case as a light source of the display panel. The backlight module has at least a light emitting element, a light-guide plate and at least a light-guide tube. The light-guide plate guides the light emitted by the light emitting element to the display panel. The light-guide tube has a light input end and a light output end. The light input end is disposed at the hole of the case and is exposed outside, and the light output end is located at one side of the light-guide plate. Therefore, the light-guide tube can guide external environment light to the light-guide plate. | 2009-01-29 |
20090027922 | Power adapter - A power adapter comprises a converter module having circuitry for converting an alternating current (AC) power supply to a direct current (DC) power supply, a connector couplable to an electronic device for supplying the DC power supply to the electronic device, and a switch manually actuatable to control power consumption by the power adapter. | 2009-01-29 |
20090027923 | POWER SUPPLY DEVICE AND POWER SUPPLY CONTROL METHOD - A power supply device includes input terminals, output terminals, a main transformer having a primary winding and secondary windings, a primary circuit connected between the input terminals and the primary winding of the main transformer, a secondary circuit connected between the secondary windings of the main transformer | 2009-01-29 |
20090027924 | Feedback Control Device - A feedback control device is provided. The feedback control device includes a controlled-system which outputs and output in correspondence with a control signal; a feedback signal generating member which generates a feedback signal as the output of the controlled-system; a reference signal unit which outputs a reference control signal to the controlled-system; and a determination unit which determines a version of the controlled-system on the basis of the feedback signal generated by the feedback signal generating member when the reference signal unit outputs the reference control signal to the controlled-system. | 2009-01-29 |
20090027925 | SWITCHING POWER SUPPLY - A buck-boost converter of an H bridge type having a function for initially charging a smoothing output capacitor without a relay and a rush current preventing resistance. A compact and flat power supply is attained by employing a current critical mode H bridge system for a PFC converter and providing a function of initially charging a smoothing output capacitor to a converter circuit. | 2009-01-29 |
20090027926 | METHOD AND APPARATUS TO PROVIDE SYNCHRONOUS RECTIFYING CIRCUIT FOR FLYBACK POWER CONVERTERS - A synchronous rectifying circuit is provided for flyback power converter. A pulse generator is utilized to generate a pulse signal in response to a leading edge and a trailing edge of a switching signal. The switching signal is used for switching the transformer of the power converter. An isolation device such as pulse transformer or small capacitors is coupled to the pulse generator for transferring the pulse signal through an isolation barrier of a transformer. A synchronous rectifier includes a power switch and a control circuit. The power switch is connected in between the secondary side of the transformer and the output of the power converter for the rectifying operation. The control circuit having a latch is operated to receive the pulse signal for controlling the power switch. | 2009-01-29 |
20090027927 | Switch mode power supply - A switch mode power supply according to the invention that can improve the reliability thereof includes a series circuit connected between the positive and negative electrodes of a DC power supply | 2009-01-29 |
20090027928 | STEP UP CONVERTER WITH OVERCURRENT PROTECTION - A step up converter with overcurrent protection is disclosed. The step up converter can precisely limit the output current of the upstream device. Current from the input terminal of the converter is detected and compared with a predetermined maximum current to get a comparison value which is delivered to a close-loop regulator. The overcurrent protection is achieved by the regulator outputting a control signal to fulfill the conduction or resistance increase of a resistive element of the protection circuit. Furthermore, detection of the temperature or the output voltage may trigger shut off of the protection circuit to implement a protection function. | 2009-01-29 |
20090027929 | POWER SUPPLY CIRCUIT OF IMAGE DISPLAY APPARATUS - A power supply circuit of an image display apparatus is provided. The power supply circuit uses a single DC-DC converter, and is capable of supplying low voltage when the image display apparatus is in standby mode, and supplying high voltage as required when the image display apparatus is in operating mode. As a result, power consumption and manufacturing costs are reduced. | 2009-01-29 |
20090027930 | AC-DC CONVERTER - An AC-DC converter includes a rectifier DB for rectifying an alternating current supplied from an alternating power source AC, a power factor controller | 2009-01-29 |
20090027931 | AC-DC CONVERTER - An AC-DC converter includes a rectifier DB for rectifying an alternating current supplied from an alternating power source AC, a power factor controller | 2009-01-29 |
20090027932 | ALTERNATIVE-SOURCE ENERGY MANAGEMENT - A power converter system includes a power converter system including: a DC-to-AC power converter; a first output configured to be coupled to a power grid; a first input configured to be coupled to the power grid; second outputs each configured to be coupled to a corresponding AC load; a power-grid switch coupled to the converter and to the first output; load switches coupled to the converter, the second outputs, and the first input; and a controller coupled to the load switches and to the first output and configured to determine whether energy from the power grid satisfies at least one criterion, the controller being further configured to control the power-grid switch and the load switches to couple the converter to the first output and to couple the first input to the second outputs if the at least one criterion is satisfied and otherwise to control the power-grid switch and the load switches to isolate the converter from the first output and to couple the converter to at least one of the second outputs. | 2009-01-29 |
20090027933 | VOLTAGE LINK CONTROL OF A DC-AC BOOST CONVERTER SYSTEM - Systems and methods are disclosed for a DC boost converter. The systems and methods combine operation of an inductor with the input capacitor of a DC/AC inverter via a switch configuration to power the DC/AC inverter. The switch configuration is controlled by a plurality of control signals generated by a controller based on a variety of control modes, and feedback signals. | 2009-01-29 |
20090027934 | Electric Transformer-Rectifier - An electric transformer-rectifier is provided such that electrical current is supplied from a three phase alternating current supply. The device includes a tri-phase transformer, where each secondary winding has its terminals available to connect to their respective secondary windings. Power is supplied to a set of three boost converters, which in turn supply power to a set of three banks. In embodiments of the invention a set of three full wave mono-phase rectifiers, connected to the respective secondary wirings, supply power to respective capacitors banks and a three buck converter. Further the device produces continuous current to the load and sinusoidal input current in each winding of the transformer. By this invention it is possible to build a power converter in which incoming voltages and currents are approximately sinusoidal and the outgoing voltages are approximately constant. | 2009-01-29 |
20090027935 | Polyphase Inverter, Control Method Thereof, Air Sending Device and Polyphase Current Output System - Capacitors act as bootstrap capacitors of a high side control circuits. The capacitors are charged in a period in which all of high arm switching devices are non-conductive, so-called in a precharge period. When any of U-phase current, V-phase current and W-phase current is smaller than a negative predetermined value (when an absolute value is larger), it is judged which is the largest value. The low arm switching device is turned on only for a phase corresponding to the current of the largest value and the low arm switching devices of other phases are turned off. | 2009-01-29 |
20090027936 | RF POWER SUPPLY - An RF power supply, in particular a plasma supply device, for generating an output power greater than 500 W at an output frequency of at least 3 MHz includes at least one inverter connectable to a DC power supply, which inverter comprises at least one switching element and an output network. An accompanying line connects an electrical component to the inverter by a lead-in of the output network. | 2009-01-29 |
20090027937 | High frequency power supply - A high frequency power supply, in particular a plasma supply device, for generating an output power greater than 1 kW at a basic frequency of at least 3 MHz with at least one switch bridge, which has two series connected switching elements, wherein one of the switching elements is connected to a reference potential varying in operation, and is activated by a driver, and wherein the driver has a differential input with two signal inputs and is connected to the reference potential varying in operation. | 2009-01-29 |
20090027938 | METHOD AND APPARATUS PROVIDING MULTI-PLANED ARRAY MEMORY DEVICE - A three dimensional variable resistance memory array and method of forming the same. The memory array has memory cells in multiple planes in three dimensions. The planes of the memory cells include shared interconnect lines, dually connected to driving and sensing circuits, that are used for addressing the cells for programming and reading. The memory array is formed using only a single patterned mask per central array plane to form the memory cells of such planes. | 2009-01-29 |
20090027939 | MULTI-CHIP PACKAGE REDUCING POWER-UP PEAK CURRENT - Disclosed is a multi-chip package having a plurality of memory chips. Each memory chip includes a memory cell array storing e-fuse data, a read-out control circuit reading e-fuse data in response to a read signal, a first internal pad receiving a first control signal, a read-out controller generating the read signal to define a read period, and to generate a second control signal following the read period, and a second internal pad receiving the second control signal, wherein the plurality of memory chips is connected series and each respective read-out control circuit and read-out controller in each one of the plurality of memory chips cooperate to implement a sequential read of e-fuse data across the plurality of memory chips. | 2009-01-29 |
20090027940 | Memory Module - A memory module with a module board is disclosed, on the front side of which a plurality of first memory devices are arranged in rows. A plurality of second memory devices are arranged in rows on the back side. The first and second memory devices have a single chip each. Further, a first register device for providing first control signals to first rows of first memory devices and to first rows of second memory devices is provided. A second register device serves to provide first control signals to second rows of first memory devices and to second rows of second memory devices. | 2009-01-29 |
20090027941 | SEMICONDUCTOR MEMORY DEVICE WITH POWER SUPPLY WIRING ON THE MOST UPPER LAYER - A memory cell array in a semiconductor substrate has a plurality of memory cells arranged in rows and columns. A first circuit is located at one end of the memory cell array in a column direction. A second circuit is located at the other end of the memory cell array in the column direction. A first wire is located above the memory cell array between the first circuit and the second circuit. The first wire is located in a most upper layer in the semiconductor substrate to supply power to the second circuit. | 2009-01-29 |
20090027942 | SEMICONDUCTOR MEMORY UNIT AND ARRAY - A memory unit comprising a gate electrode, a gate dielectric under said gate electrode, an active area and a metal-semiconductor compound layer is provided. The active area comprises a first source/drain region, a second source/drain region, a normal field channel region formed under said gate electrode, a fringing field channel region formed between said first source/drain region and said normal field channel region, a pocket implantation region formed under the fringing or normal field channel regions and an extension doping region formed between said second source/drain region and said normal field channel region. The metal-semiconductor compound layer is formed over said gate electrode, first source/drain region and second source/drain region. | 2009-01-29 |
20090027943 | RESISTIVE MEMORY INCLUDING BIDIRECTIONAL WRITE OPERATION - A memory includes a first electrode, a second electrode, and a resistive memory element coupled between the first electrode and the second electrode. The memory includes a circuit configured to write a data value to the resistive memory element by sequentially applying a first signal from the first electrode to the second electrode and a second signal from the second electrode to the first electrode. | 2009-01-29 |
20090027944 | Increased Switching Cycle Resistive Memory Element - An integrated circuit including a resistive memory element and a method of manufacturing the integrated circuit are described. The method of manufacturing the integrated circuit includes depositing a switching layer material and intentionally forming inhomogeneously distributed defects within the switching layer material to increase a number of switching cycles of the resistive memory element. The resistive memory element includes a switching layer that selectively switches between a low resistance state and a high resistance state. The switching layer contains intentionally formed defects that increase the number of switching cycles of the switching layer. | 2009-01-29 |
20090027945 | Method and Apparatus for Implementing Enhanced SRAM Read Performance Sort Ring Oscillator (PSRO) - A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO), and a design structure on which the subject circuit resides is provided. A pair of parallel reverse polarity connected inverters defines a static latch or cross-coupled memory cell. The SRAM cell includes independent left and right wordlines providing a respective gate input to a pair of access transistors used to access to the memory cell. The SRAM cell includes a voltage supply connection to one side of the static latch. For example, a complement side of the static latch is connected to the voltage supply. A plurality of the SRAM cells is assembled together to form a SRAM base block. A plurality of the SRAM base blocks is connected together to form the SRAM read PSRO. | 2009-01-29 |
20090027946 | METHOD AND APPARATUS FOR IMPLEMENTING ENHANCED SRAM READ PERFORMANCE SORT RING OSCILLATOR (PSRO) - A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO). A pair of parallel reverse polarity connected inverters defines a static latch or cross-coupled memory cell. The SRAM cell includes independent left and right wordlines providing a respective gate input to a pair of access transistors used to access to the memory cell. The SRAM cell includes a voltage supply connection to one side of the static latch. For example, a complement side of the static latch is connected to the voltage supply. A plurality of the SRAM cells is assembled together to form a SRAM base block. A plurality of the SRAM base blocks is connected together to form the SRAM read PSRO. | 2009-01-29 |
20090027947 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - In a reading operation, an off time and a reading time of a holding control transistor is controlled by a replica circuit, so that a read margin is enlarged. Furthermore, a high power source potential and a low power source potential of an SRAM memory cell are switched in reading and writing operations of the memory cell and in a data holding state by a power source potential switching portion. As a result, a write margin is enlarged, and a leakage current is reduced. | 2009-01-29 |
20090027948 | Integrated Circuits, Method of Programming a Cell, Thermal Select Magnetoresistive Element, Memory Module - An embodiment of the invention includes an integrated circuit that has a cell. The cell includes a first magnetic layer arrangement having a magnetization which corresponds to a predefined ground state magnetization, a non-magnetic spacer layer coupled to the first layer arrangement, a second magnetic layer arrangement disposed on the opposite side of the non-magnetic spacer layer with regard to the first magnetic layer arrangement, the second magnetic layer arrangement having a magnetization fixation temperature that is lower than the magnetization fixation temperature of the first magnetic layer arrangement, and at least a portion of the second magnetic layer arrangement having a closed magnetic flux structure in its demagnetized state. | 2009-01-29 |
20090027949 | Magnetic storage device - A magnetic storage device is provided which has significantly reduced power consumption. In the magnetic storage device, a yoke is arranged so as to circumferentially surround part of a line extending in an arbitrary direction, and a magneto-resistive element to which information can be written by utilizing a magnetic field generated by the line is arranged in the vicinity of the line. In this case, the length of the magnetic path of the yoke is set to 6 μm or less. | 2009-01-29 |
20090027950 | Block Erase for Phase Change Memory - An embodiment of our invention includes a method of programming at least one phase change memory block, the at least one block comprising at least one phase change memory cell, the at least one cell comprising at least one phase change material. The method includes the steps of transitioning all cells within the at least one block to a first state and, after all cells within the at least one block have been transitioned to the first state, transitioning at least one cell within the at least one block to at least a second state. Transitioning a cell to the at least second state is faster than transitioning a cell to the first state. At least the step of transitioning all cells within the at least one block to a first state may include transitioning all cells within the at least one block in a substantially simultaneous manner. | 2009-01-29 |
20090027951 | Reading phase change memories with select devices - A phase change memory including a threshold device, such as an ovonic threshold switch, and a storage device may be read. Reading the cell may involve applying a first voltage to a selected cell and then a second voltage, lower than the first voltage. The first voltage may be sufficient to threshold the ovonic threshold switch if the storage device is in the set state. | 2009-01-29 |
20090027952 | PHASE CHANGE MEMORY DEVICE WITH REFERENCE CELL ARRAY - A phase change memory device includes a plurality of bit lines and a reference bit line intersecting a plurality of word lines. A cell array block has a phase change resistance cell arranged where a word line and a bit line intersect. A reference cell array block is configured to output a reference current and is formed where the word line and a reference bit line intersect. A column selecting unit is configured to select a corresponding bit line connected to the cell array block. A reference column selecting unit is connected to the reference cell array block and is configured to select the reference bit line. A sense amplifier is connected to the column selecting unit and the reference column selecting unit and is configured to receive the reference current and a cell data current of the bit line. | 2009-01-29 |
20090027953 | PHASE CHANGE MEMORY DEVICE - A phase change memory device includes a plurality of word lines arranged in a row direction and a plurality of bit lines arranged in a column direction. A plurality of reference bit line and a plurality of clamp bit lines are arranged in the column direction. A cell array block including a phase change resistance cell is arranged where a word line and a bit line intersect. A reference cell array block is formed where a word line and the reference bit line intersect. The reference cell array block is configured to output a reference current. A clamp cell array block is formed where a word line and a clamp bit line intersect. The clamp cell array block is configured to output a clamp current. A sense amplifier is connected to each of the bit lines and is configured to receive a clamp voltage and a reference voltage. | 2009-01-29 |
20090027954 | PHASE CHANGE MEMORY DEVICE WITH BIT LINE DISCHARGE PATH - A phase change memory device includes a cell array. The cell array includes a phase change resistance cell formed at an intersection of a word line and a bit line and a dummy cell configured to discharge the bit line in response to a bit line discharge signal in a precharge mode. A column switching unit is configured to selectively control a connection between the bit line and a global bit line in response to a column selecting signal. | 2009-01-29 |
20090027955 | NON-VOLATILE MEMORY DEVICES INCLUDING STACKED NAND-TYPE RESISTIVE MEMORY CELL STRINGS AND METHODS OF FABRICATING THE SAME - A non-volatile memory device includes a substrate, an insulating layer on the substrate, and a plurality of serially connected resistive memory cells stacked in the insulating layer such that a first one of the plurality of resistive memory cells is on the substrate and a next one of the plurality of resistive memory cells is on the first one of the plurality of resistive memory cells to define a NAND-type resistive memory cell string. A bit line on the insulating layer is electrically connected to a last one of the plurality of resistive memory cells. At least one of the plurality of resistive memory cells may include a switching device and a data storage element including a variable resistor connected in parallel with the switching device. Related devices and fabrication methods are also discussed. | 2009-01-29 |
20090027956 | RESISTANCE VARIABLE MEMORY DEVICE REDUCING WORD LINE VOLTAGE - A resistance variable memory device includes a memory cell array, a sense amplifier circuit, and a column selection circuit. The memory cell array includes a plurality of block units and a plurality of word line drivers, where each of the block units is connected between adjacent word line drivers and includes a plurality of memory blocks. The sense amplifier circuit includes a plurality of sense amplifier units, where each of the sense amplifier units provides a read current to a corresponding block unit and includes a plurality of sense amplifiers. The column selection circuit is connected between the memory cell array and the sense amplifier circuit and selects at least one of the plurality of memory blocks in response to a column selection signal to apply the read current from the sense amplifier circuit to the selected memory block. | 2009-01-29 |
20090027957 | VOLTAGE SUPPLY CIRCUIT AND FLASH MEMORY DEVICE INCLUDING THE SAME, AND METHOD OF SUPPLYING OPERATING VOLTAGE - A voltage supply circuit includes a voltage generator and a controller. The voltage generator is configured to pump an externally input voltage and store the pumped external voltage as a first voltage having a set voltage level, before power-up begins, or pump the external voltage, add the pumped voltage to the stored voltage, and output the added voltage as an operating voltage. The controller is configured to output a first control signal to drive the voltage generator or stop operation of the voltage generator, according to an operating state. | 2009-01-29 |
20090027958 | VOLTAGE CONVERTER CIRCUIT AND FLASH MEMORY DEVICE HAVING THE SAME - A voltage conversion circuit includes a reference voltage generation unit for generating a reference voltage having a uniform level regardless of a level of an input voltage varying according to an operation mode; and a driver unit for generating and outputting an active voltage or a standby voltage using the reference voltage output by the reference voltage generation unit according to a control signal. | 2009-01-29 |
20090027959 | PROGRAMMING MULTILEVEL CELL MEMORY ARRAYS - Methods and apparatus, such as those for programming of multilevel cell NAND memory arrays to facilitate a reduction of program disturb, are disclosed. In one such method, memory cells are shifted from a first Vt distribution to a second Vt distribution higher than the first Vt distribution during a first portion of a programming operation if a second or a fourth data state is desired, while memory cells remain in the first Vt distribution if the first or a third data state is desired. During a second portion of the programming operating, if the third data state is desired, those memory cells are shifted from the first Vt distribution to a third Vt distribution higher than the second Vt distribution and, if the fourth data state is desired, those memory cells are shifted from the second Vt distribution to a fourth Vt distribution higher than the third Vt distribution. | 2009-01-29 |
20090027960 | Cell deterioration warning apparatus and method - Memory devices and methods adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a target threshold voltage range representative of the desired bit pattern. Reading such memory devices includes generating an analog data signal indicative of a threshold voltage of a target memory cell. Warning of cell deterioration can be performed using reference cells programmed in accordance with a known pattern such as to approximate deterioration of non-volatile memory cells of the device. | 2009-01-29 |
20090027961 | Non-volatile memory cell programming method - A non-volatile memory cell programming method is provided. A memory cell programming method of programming 2-bit data in a memory cell having 4 threshold voltage distributions may comprise: a first program operation of programming a first bit of the 2-bit data in the memory cell by applying a first programming voltage to the memory cell; a second program operation of programming a second bit of the 2-bit data in the memory cell by applying a second programming voltage to the memory cell; and a stabilization operation of applying a stabilization voltage having an electric field opposite in polarity to an electric field formed by the first and second programming voltages to the memory cell after one of the first and second program operations that corresponds to a higher one of the first and second programming voltages is performed. | 2009-01-29 |
20090027962 | MULTIPLE LEVEL CELL MEMORY DEVICE WITH SINGLE BIT PER CELL, RE-MAPPABLE MEMORY BLOCK - A non-volatile memory device has a plurality of memory cells that are organized into memory blocks. Each block can operate in either a multiple level cell mode or a single bit per cell mode. One dedicated memory block is capable of operating only in the single bit per cell mode. If the dedicated memory block is found to be defective, a defect-free block can be remapped to that dedicated memory block location to act only in the single bit per cell mode. | 2009-01-29 |
20090027963 | HIGH PERFORMANCE MULTI-LEVEL NON-VOLATILE MEMORY DEVICE - Non-volatile memory devices and arrays are described that utilize band engineered gate-stacks and multiple charge trapping layers allowing a multiple trapping site gate-insulator stack memory cell that utilizes a band engineered direct tunneling or crested barrier tunnel layer and charge blocking layer for high speed programming/erasure. Charge retention is enhanced by utilization of nano-crystals and/or bulk trapping materials in a composite non-conductive trapping layer and a high K dielectric insulating layers. The band-gap engineered gate-stack with asymmetric direct tunneling or crested barrier tunnel layers of the non-volatile memory cells of embodiments of the present invention allow for low voltage high speed tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. Memory cell embodiments of the present invention allow multiple levels of bit storage in a memory cell through multiple charge centroids and/or multiple threshold voltage levels. | 2009-01-29 |
20090027964 | SEMICONDUCTOR MEMORY DEVICE HAVING PLURAL WORD LINES ARRANGED AT NARROW PITCH AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes a memory cell array which includes at least one memory unit having a preset number of memory cell transistors and a selection gate transistor on a source side, a preset number of word lines respectively connected to control gates of the preset number of memory cell transistors, and a selection gate line on a source side connected to a gate electrode of the selection gate transistor on the source side. In the semiconductor memory device, a distance C between the selection gate line at least on the source side and one of the word lines adjacent thereto is set to n*A+(n−1)B, where n is an integer greater than or equal to 2, A indicates the pitch between adjacent ones of the preset number of word lines, and B indicates the width of each of the preset number of word lines. | 2009-01-29 |
20090027965 | ROW SELECTOR CIRCUIT FOR ELECTRICALLY PROGRAMMABLE AND ERASABLE NON VOLATILE MEMORIES - The invention relates to a row decoder circuit for non volatile memory devices of the electrically programmable and erasable type, for example of the Flash EEPROM type having a NOR architecture. The proposed row decoder circuit allows to carry out the erasing step very quickly, for example with a granularity emulating at least 16 kB and even overcoming by at least 2 kB Flash memories of the NAND type. The memory can thus maintain high performances in terms of random access speed but shows a high erasing speed typical of memory architectures of the NAND type. | 2009-01-29 |
20090027966 | FLASH MEMORY DEVICE - A bad block address of a flash memory device is stored through a fuse circuit and then compared with an input address in order to disable bad blocks. The flash memory device includes a bad block information unit for storing an address of a bad block, a comparator for comparing an input address including a memory block address and the address of the bad block stored in the bad block information unit, and for outputting a first control signal according to the comparison result, and an address counter for outputting a second control signal to enable or disable a memory block corresponding to the memory block address in response to the first control signal. | 2009-01-29 |
20090027967 | NON-VOLATILE MEMORY DEVICE PROGRAMMING SELECTION TRANSISTOR AND METHOD OF PROGRAMMING THE SAME - A memory system includes a flash memory device and a memory controller for controlling the flash memory device. The flash memory device includes a cell string and a selection transistor connected in series to the cell string. The cell string includes multiple series-connected memory cells. The selection transistor has the same structure as a memory cell of the series-connected memory cells, and is programmed through channel hot electron injection. | 2009-01-29 |
20090027968 | NAND FLASH MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A NAND flash memory device having memory cells for storing data includes a fuse circuit configured to store option information for operation of the NAND flash memory device as logic codes. A register circuit includes registers for temporarily storing the logic codes stored in the fuse circuit. A test circuit is configured to change the logic code stored in the register circuit and store the changed logic code irrespective of the logic code of the fuse circuit for test operation of the NAND flash memory device. A processor is configured to control operation of the NAND flash memory device. | 2009-01-29 |
20090027969 | METHOD OF USING HOT-CARRIER-INJECTION DEGRADATION AS A PROGRAMMABLE FUSE/SWITCH - Method and apparatus for providing nonvolatile storage with a programmable transistor. The method includes receiving a data value to be stored in the programmable transistor and programming the programmable transistor to store the received data value. Programming includes applying a selected voltage to the programmable transistor. The selected voltage is selected to inject carriers into a gate oxide layer of the programmable transistor. The carriers are maintained in the gate oxide layer of the programmable transistor in the absence of the selected voltage, thereby programming the programmable transistor with the received data value. | 2009-01-29 |
20090027970 | Programming based on controller performance requirements - Methods and solid state drives are disclosed, for example a solid state drive that is adapted to receive and transmit analog data signals representative of bit patterns of three or more levels (such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits). Programming of the solid state drive, comprising an array of non-volatile memory cells, might include adjusting the level of each memory cell being programmed in response to a desired performance level of a controller circuit. | 2009-01-29 |
20090027971 | Apparatuses, computer program products and methods for reading data from memory cells - In reading data from a memory cell, a determining circuit determines whether a received voltage value is within at least one first voltage range through a one-time read operation using a semiconductor device that senses an output current corresponding to the received voltage value. The at least one first voltage range includes a first upper limit voltage value and a first lower limit voltage value. A data value of the memory cell is set as a first data value when the received voltage value is within the specific voltage range. | 2009-01-29 |
20090027972 | WORDLINE DRIVER FOR A NON-VOLATILE MEMORY DEVICE, A NON-VOLATILE MEMORY DEVICE AND METHOD - A wordline driver, for a non-volatile memory device, comprises a wordline driver output, a first power source, adapted to provide an erase level voltage for erasing portions of the non-volatile memory device, a second power source, adapted to provide read and program level voltages for reading and programming portions of the non-volatile memory device and first switching means, including an isolation transistor, adapted to connect the wordline driver output to a one of the first and second power sources dependent upon an operating mode of the wordline driver. The wordline driver further comprises a programmable switch controller for providing a variable control signal to a control electrode of the isolation transistor. The programmable switch controller is arranged to set the variable control signal to a value dependent upon the operating parameters of the non-volatile memory device and such that the endurance of the isolation transistor is maximised. | 2009-01-29 |
20090027973 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A non-volatile semiconductor storage device includes: one or more memory cells including anti-fuse elements capable of writing data by breaking down a gate insulation film of a MOS transistor with a high voltage; a sense node having its one end connected to each of the anti-fuse elements; a sense amplifier comparing the potential of the sense node with the reference potential and amplifying the difference therebetween, the sense amplifier being activated according to a sense-amplifier activation signal; an initialization circuit initializing the potential of the sense node according to an initialization signal; a control circuit outputting the initialization signal at a predetermined timing after input of an external signal input from the outside and outputting a first activation signal to activate the sense amplifier at a predetermined timing after input of the external signal; and a switching circuit outputting the first activation signal as the sense-amplifier activation signal when a normal data read operation is performed, and outputting an inverted version of the external signal as the sense-amplifier activation signal when a test execution is instructed for the one or more memory cells before the gate insulation film is broken down. | 2009-01-29 |
20090027974 | MEMORY CONTROL METHOD AND MEMORY CONTROL CIRCUIT - A memory control method includes: latching a clock signal to selectively generate a phase lead detection result and a phase lag detection result in response to a data strobe signal; delaying the data strobe signal to generate a plurality of delayed data strobe signals; latching the clock signal to generate a plurality of phase detection results in response to the delayed data strobe signals so as to correspond to the delayed data strobe signals; latching write data carried by a data signal according to rising/falling edges of the data strobe signal; performing odd/even data separation on the write data to generate a data separation signal carrying odd/even data corresponding to the write data; and in a situation where the data strobe signal leads the clock signal, delaying or bypassing the odd/even data carried by the data separation signal according to the phase detection results. A memory control circuit is provided. | 2009-01-29 |
20090027975 | METHOD FOR DRIVING PHASE CHANGE MEMORY DEVICE - A method is disclosed for driving a phase change memory device including a phase change resistor. The method includes applying a trigger voltage to the phase change resistor for a first write time to preheat the phase change resistor, applying a first write voltage to the phase change resistor for a second write time to control a first state of the phase change resistor, and applying a second voltage to the phase change resistor for a third write time to control a second state of the phase change resistor. | 2009-01-29 |
20090027976 | Threshold device for a memory array - A threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different dielectric materials is disclosed. A memory plug having first and second terminals includes, electrically in series with the first and second terminals, the threshold device and a memory element that stores data as a plurality of conductivity profiles. The threshold device is operative to impart a characteristic I-V curve that defines current flow through the memory element as a function of applied voltage across the terminals during data operations. The threshold device substantially reduces or eliminates current flow through half-selected or un-selected memory plugs and allows a sufficient magnitude of current to flow through memory plugs that are selected for read and write operations. The threshold device reduces or eliminates data disturb in half-selected memory plugs and increases S/N ratio during read operations. | 2009-01-29 |
20090027977 | Low read current architecture for memory - A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured. | 2009-01-29 |
20090027978 | Semiconductor device and semiconductor signal processing apparatus - A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width. | 2009-01-29 |
20090027979 | Semiconductor memory device and data sensing method thereof - A semiconductor memory device includes first and second edge drivers configured to generate sensing control signals, a memory cell array between first and second edge drivers, and pluralities of unit sense amplifiers detecting data from the memory cell array in response to the sensing control signals. | 2009-01-29 |
20090027980 | SEMICONDUCTOR MEMORY - Address comparison circuits each compare the defect addresses programmed in the redundancy fuse circuits with an access address and output a redundancy signal when a comparison result is a match. A switch circuit is controlled to switch according to a redundancy selection signal output from a selection fuse circuit, and validates in response to the redundancy signal either a corresponding regular redundancy line or the reservation redundancy line. By dividing the redundancy lines into the regular redundancy lines and the reservation redundancy line, each of the redundancy fuse circuits can be made to correspond to one of the plurality of redundancy lines with the simple switch circuit. Therefore, a difference in propagation delay time of a signal can be made small and a difference in access time can be made small between when relieving a defect and when there is no defect. | 2009-01-29 |
20090027981 | METHOD OF TESTING DATA PATHS IN AN ELECTRONIC CIRCUIT - A method of testing a complex electronic circuit, comprising a plurality of transfer operators DMA | 2009-01-29 |
20090027982 | SEMICONDUCTOR MEMORY AND TEST SYSTEM - A cell array has a word line and a bit line coupled to memory cells, and a redundancy word line and a redundancy bit line coupled to redundancy memory cells. A read unit reads data held in the memory cell. A defect detection input unit receives a defect detection signal from a test apparatus. A dummy defect output unit outputs a dummy defect signal during a predetermined period of time after the defect detection input unit receives the defect detection signal. A data output unit inverts a logic of the read data output from the read unit during an activation of the dummy defect signal. Accordingly, an artificial defect can be generated by the semiconductor memory without changing the test apparatus or a test program. As a result of this, a relief efficiency can be enhanced and a test cost can be reduced. | 2009-01-29 |
20090027983 | HALF-SELECT COMPLIANT MEMORY CELL PRECHARGE CIRCUIT - A programmable precharge circuit includes a plurality of transistors. Each transistor has a different threshold voltage from other transistors of the plurality of transistors. Each transistor is configured to connect a supply voltage to a node, and the node is selectively coupled to bitlines in accordance with a memory operation. Control logic is configured to enable at least one of the plurality of transistors to provide a programmable precharge voltage to the node in accordance with a respective threshold voltage drop from the supply voltage of one of the plurality of transistors. | 2009-01-29 |
20090027984 | SEMICONDUCTOR DEVICE - The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to bit line LBL. | 2009-01-29 |
20090027985 | SEMICONDUCTOR STORAGE DEVICE - The semiconductor storage device according to the present invention comprises a switch provided to a bit line between a memory cells and a sense amplifier and capable of continuously varying a degree of conduction; and a switch control circuit for varying the degree of conduction of the switch in accordance with an access request signal. The semiconductor storage device of the present invention enables operation in which the degree of conduction between the sense amplifier and a memory cell is increased, and an ON state is achieved during a time in which the sense amplifier amplifies the holding voltage of the memory cell and feeds the amplified holding voltage to the bit line. The access time can thereby be reduced. | 2009-01-29 |
20090027986 | Semiconductor memory device - The present invention provides a semiconductor memory device in which the number of write amplifiers is decreased by increasing the number of bit line pairs connected to one pair of common write data lines. Further, by decreasing the number of bit line pairs connected to one pair of common read data lines, parasitic capacitance connected to the pair of common read data lines is reduced and, accordingly, time in which the potential difference between the pair of common read data lines increases is shortened. Thus, while preventing enlargement of the chip layout area, read time can be shortened. | 2009-01-29 |
20090027987 | Memory Device and Testing - An apparatus including a memory cell, a reference cell, a control unit, coupled to the memory cell and the reference cell, and configured to initiate write processes of the memory cell and the reference cell, and a detection unit, coupled to the reference cell, and configured to detect a write completion of the reference cell. Related methods are also disclosed. | 2009-01-29 |
20090027988 | Memory device, memory controller and memory system - An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals. | 2009-01-29 |
20090027989 | System and Method to Reduce Dynamic Ram Power Consumption via the use of Valid Data Indicators - A DRAM or SDRAM component maintains an indicator that indicates whether or not an independently refreshable memory unit of a DRAM array, such as a row, contains valid data. When a refresh operation is directed to the associated memory, the refresh operation is suppressed if the memory does not contain valid data. Significant power savings may be realized by suppressing refresh operations directed to invalid data. | 2009-01-29 |
20090027990 | ADAPTIVE VOLTAGE CONTROL FOR SRAM - The present invention pertains to semiconductor memory devices, and particularly to a system and method for adaptively setting the operating voltages for SRAM for both Vtrip and SNM to reduce power while maintaining functionality and performance, based on modeling and characterizing a test structure. One embodiment comprises an SRAM array, a test structure that characterizes one or more parameters that are predictive of the SRAM functionality and outputs data of the parameters, a test controller that reads the parameters and identifies an operating voltage that satisfies predetermined yield criteria, and a voltage controller to set an operating voltage for the SRAM array based on the identified operating voltage. One method sets an operating voltage for an SRAM by reading test structure data of the parameters, analyzing the data to identify an operating voltage that satisfies predetermined yield criteria, and setting the operating voltage for the SRAM based on the identified operating voltage. | 2009-01-29 |
20090027991 | Information processing apparatus, memory unit erroneous write preventing method, and information processing system - To make it possible to reliably halt writing processing while restraining erroneous writing to the memory unit, present apparatus has a memory unit to which data is written for each write request; a voltage converting unit which converts a first power source voltage into a first operable voltage with which a write request issuing unit is operable, and supplies the first operable voltage to the write request issuing unit; a voltage monitoring unit, which outputs an issuance restraining signal which restrains issuance of the write request, when the first power source voltage becomes lower than a reference voltage; and an issuance restrain controlling unit which receives the issuance restrain signal, and then after completion of writing for each of the write request to write memory unit, which restrains the issuance of the write request by the write request issuance unit. | 2009-01-29 |
20090027992 | PSRAM AND METHOD FOR OPERATING THEREOF - Disclosed is a pseudo static random access memory (PSRAM) and a method for operating the same. The PSRAM includes a multi-bit control register and a multiplexer circuit operatively coupled to the multi-bit control register. The multi-bit control register has a first set of bits reserved for a page control mode of the PSRAM and a second set of bits reserved for a bus control mode of the PSRAM. The multiplexer circuit activates one of the page control mode and the bus control mode of the PSRAM based on a logic level of an address bit inputted to the multiplexer circuit. | 2009-01-29 |
20090027993 | Semiconductor memory device and data storage method - According to an aspect of the present invention, there is provided a semiconductor memory device for storing data defining a multidimensional space based on coordinate information of the data, including: a cell array having memory cells arranged in a lattice pattern, for storing the data; a word line selector selecting and driving any one of a plurality of word lines which activate memory cells arranged in a row direction; write amplifiers/sense amplifiers writing/reading data to/from the memory cells arranged in a column direction; an amplifier selector inputting/outputting the data to/from the selected one of the write amplifiers/sense amplifiers; and an address conversion circuit generating a row address to be supplied to the word line selector based on the coordinate information of the data, and to generate a column address to be supplied to the amplifier selector by converting the coordinate information of the data into one-dimensional information. | 2009-01-29 |
20090027994 | Mixing and kneading machine and method of implementing continual compounding - A mixing and kneading machine ( | 2009-01-29 |
20090027995 | APPARATUS AND METHOD TO FEED LIVESTOCK - A portable feed apparatus comprising a feed container, a mixing assembly that receives a feed from said feed container, at least one feed additive assembly in flowable connection with said mixing assembly, and a controller in communication with said mixing assembly. | 2009-01-29 |
20090027996 | Method and Apparatus for Mixing Fluids - Described is a mixing device and method for mixing fluids. Fluids to be mixed are introduced into a near-critical or a supercritical fluid carrier fluid. A density gradient is generated in the carrier fluid upon introduction of a fluid to be mixed that induces a convective velocity that provides for rapid mixing. The invention has application in such commercial applications as semiconductor and wafer fabrication where rapid cycle times or rapid mixing of fluids is required and where low tolerances for residues are permitted. | 2009-01-29 |
20090027997 | Single-Use Container With Stirring Device - The invention is directed to a container fabricated out of plastic material for sterile liquids for the chemical, biotechnological, pharmaceutical and food industry, that includes a unit for mixing liquids whereby a flexible container wall is penetrated by a supporting shaft and is integrally connected with the container wall and an area of the inner space of the container supports at least one stirring device plate connectable with a drive outside of the inner space. | 2009-01-29 |
20090027998 | Magnetic mixer - A device facilitating mixing of a fluid containing magnetic or magnetizable particles, including a support for a container for the fluid and particles, a first magnet adjacent one side of the support, a second magnet adjacent the other side, and a drive for moving the second magnet between a first position near the container top and a second position near the container bottom. The first magnet is supported in a third position on the one side near the container bottom. A related tray and method for mixing magnetic particles are also disclosed. | 2009-01-29 |
20090027999 | Method and apparatus for continuous land based seismic data monitoring and acquisition - A seismic exploration method and unit comprised of continuous recording, self-contained wireless seismometer units or pods. The self-contained unit may include a tilt meter, a compass and a mechanically gimbaled clock platform. Upon retrieval, seismic data recorded by the unit can be extracted and the unit can be charged, tested, re-synchronized, and operation can be re-initiated without the need to open the unit's case. The unit may include an additional geophone to mechanically vibrate the unit to gauge the degree of coupling between the unit and the earth. The unit may correct seismic data for the effects of crystal aging arising from the clock. Deployment location of the unit may be determined tracking linear and angular acceleration from an initial position. The unit may utilize multiple geophones angularly oriented to one another in order to redundantly measure seismic activity in a particular plane. | 2009-01-29 |
20090028000 | METHOD AND PROCESS FOR THE SYSTEMATIC EXPLORATION OF URANIUM IN THE ATHABASCA BASIN - A method for the identification of metallic deposits in a rock formation is provided. The method for the identification includes the steps of providing an acoustic source for generating frequencies to produce acoustic waves, arranging at least one geophone optimized to detect the frequencies and oriented to enhance reflection planes from faults and fractures associated with an ore body in a rock formation and locating the acoustic source and at least one geophone in at least one shallow bore hole beneath unconsolidated surface material of the rock formation. The method further includes the steps of directing the acoustic waves to an underlying rock formation to generate seismic reflection data and processing the seismic reflection data by altering the frequency and the amplitude to identify unique seismic attributes that allow detection of at least one metallic deposit or ore body in the rock formation. | 2009-01-29 |
20090028001 | REFLECTIVE AND SLANTED ARRAY CHANNELIZED SENSOR ARRAYS - Reflective and slanted array channelized sensor arrays having a broadband source providing acoustic energy to a reflective or slanted array that reflects a portion of the incident signal to one or more sensing films wherein the response is measured. | 2009-01-29 |
20090028002 | Ultrasonic sensor - An ultrasonic sensor includes a sending device and a receiving device. The sending device has a sending surface for sending an ultrasonic wave into a sending area. The receiving device has a receiving surface for receiving the ultrasonic wave reflected by an external object from a receiving area. The sending area has an overlapping area with the receiving area. The overlapping area is offset to one of the sending area and the receiving area. | 2009-01-29 |
20090028003 | APPARATUS AND METHOD FOR SENSING OF THREE-DIMENSIONAL ENVIRONMENTAL INFORMATION - An apparatus for providing information about a three-dimensional environment to a user includes; a handle, at least one sensor operatively coupled to the handle, a tactile pad disposed on the handle, a plurality of tactile buttons arrayed on the tactile pad, a plurality of actuators, wherein each actuator is operatively coupled to one of the plurality of tactile buttons to control a height thereof in relation to the tactile pad, and a processor which receives signals from the at least one sensor and controls positioning of the plurality of actuators to represent a physical environment sensed by the at least one sensor. | 2009-01-29 |
20090028004 | SYSTEM FOR MONITORING A PERSON | 2009-01-29 |
20090028005 | WRISTWATCH-TYPE MOBILE DEVICE - Provided is a wristwatch-type mobile device. The wristwatch-type mobile device includes a wristwatch device, a mobile device, and an I/O device. The I/O device is selectively used as one of an output device of the wristwatch device and an I/O device of the mobile device. | 2009-01-29 |
20090028006 | Clock Setup Over a Network - The present invention provides apparatuses and methods for updating a target device from a clock device through a network. The clock device obtains a time value from a clock source and sends the time value to a target device. A node within the network determines a time delay, adjusts the time value in accordance with the time delay, and sends the adjusted time value to the target device. The node may determine a time delay from an internal timer or from a measurement message when adjusting the time value. The clock device may send a subsequent time update message to the target device if the target device does not acknowledge reception of a time update. The clock device may also send a time update message to a target device when a status change of daylight savings time occurs and obtain a subsequent time value from a clock source. | 2009-01-29 |
20090028007 | Near-Field Optical Head and Information Recording Apparatus - The invention is a near-field optical head that generates near-field light to heat a predetermined area of a medium and applies a magnetic field to the predetermined area to record information, the head including an optical waveguide | 2009-01-29 |
20090028008 | HIGH PERFORMANCE DVD WRITING CURRENT CIRCUIT - A writing current circuit ( | 2009-01-29 |
20090028009 | Dynamic Mobile CD Music Attributes Database - Technology related to CD (compact disc) players are described. In one instance, a handheld CD player includes a CD drive to receive a CD and to determine a CD identification from the CD and a media slot to receive a portable memory card having a database. The handheld CD player also includes an attributes access module configured to retrieve music attributes from the database associated with the CD identification and to store the CD identification in the database if the CD identification is not already in the database. | 2009-01-29 |
20090028010 | Media Processor and Control Method of Media Processor - A media processor such as a CD publisher functions as a media library. The CD publisher takes out media from a media storage unit, sets the media in a media drive, performs writing of data, and stores the media in a writing-completed media storage unit if there is a data writing request and/or an additional data writing request. The publisher takes out the target media from the media storage unit on the basis of details stored in the storage unit and sets the media in the media drive if there is a data reference request and a data output request. Data of the media can be referenced from the outside, and media in which data writing has been completed can be used as a media library. When final additional writing is completed or there is a discharge command of the media, printing of a label related to data written on a label surface of the media is collectively performed, and then the media is discharged. | 2009-01-29 |
20090028011 | Optical disk device - An optical disk as disclosed herein includes, among other things, a summing module that sums a compensation signal to a predetermined signal in a servo loop. The compensation signal compensates for a periodical disturbance input into a servo system of the optical disk device in units of a rotation angle of the disk rotating module. A phase lead imparting module imparts a predetermined amount of phase lead to an output signal from an optical detector module and outputs the predetermined amount of phase lead as the compensation signal. The predetermined amount of phase lead is determined in accordance with the rotation period information. The optical disk device performs an accurate iterative learning control to provide stable servo performance. The iterative learning control is performed such that the signal having imparted an optimal amount of phase lead in accordance with the rotation period information is added to the servo loop. | 2009-01-29 |
20090028012 | REMOVABLE MEDIUM RECORDING/REPRODUCING DEVICE RECORDING/REPRODUCING OPERATION INHIBITING METHOD, RECORDING OPERATION INHIBITING METHOD, FIRMWARE UPDATE METHOD, AND FILE CONTAINING THE FIRMWARE - Immediately after firmware is installed in a flash ROM (R | 2009-01-29 |