05th week of 2015 patent applcation highlights part 62 |
Patent application number | Title | Published |
20150032977 | MEMORY MANAGEMENT SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT - According to one aspect of the present disclosure a method and technique for managing memory access is disclosed. The method includes setting a memory databus utilization threshold for each of a plurality of processors of a data processing system to maintain memory databus utilization of the data processing system at or below a system threshold. The method also includes monitoring memory databus utilization for the plurality of processors and, in response to determining that memory databus utilization for at least one of the processors is below its threshold, reallocating at least a portion of unused databus utilization from the at least one processor to at least one of the other processors. | 2015-01-29 |
20150032978 | TRANSFERRING DIFFERENCES BETWEEN CHUNKS DURING REPLICATION - Techniques and mechanisms described herein facilitate the replication of data between storage nodes. According to various embodiments, a request to provide a data chunk to a target storage node may be received at a source data storage node. A reference data chunk may be identified based on fingerprint information associated with the requested data chunk. The reference data chunk may be stored on the target storage node. The reference data chunk and the requested data chunk may each include a first data portion. Data chunk reconstruction information may be transmitted from the source data storage node to the target data storage node. The data chunk reconstruction information may identify the reference data chunk. The data chunk reconstruction information may include data difference information for constructing the requested data chunk at the target data storage node based on the reference data chunk. | 2015-01-29 |
20150032979 | SELF-ADJUSTING PHASE CHANGE MEMORY STORAGE MODULE - A dynamic self-adjusting memory storage device and method of operating. The device includes a plurality of adjustable-size phase change memory (PCM) storage sub-modules connected to and communicating over a bus with a control device. One of the plurality of adjustable-size memory storage sub-modules is in a stand-by mode of operation. The control device implements steps to: determine, based on a switching criteria, when the memory storage device needs to be switched to a different operation mode; select one or more adjustable-sized memory storage sub-modules for switching to said different operation mode; copy stored data from a selected actively operating adjustable-size memory storage sub-module to said adjustable-size memory storage sub-module in said stand-by mode; and change the capacity of the selected actively operating adjustable-size memory storage sub-module after the copying. The dynamic self-adjusting memory capacity method is performed without powering down the memory storage device or paying any timing penalty. | 2015-01-29 |
20150032980 | Storage System and Method for Accessing Logical Volumes - A method and a storage system are provided for accessing volumes. The storage system provisions to a host, a place holder handle configured for allowing access to any volume selected by the host and allowed to be accessed by the host. The volume forms part of accessible volumes included in the storage system. The storage system receives from the host a first request for associating the place holder handle with a first selected volume from among the accessible volumes and enables the host to access the first selected volume in response to receiving an access request indicative of the place holder handle. | 2015-01-29 |
20150032981 | STORAGE SYSTEM, STORAGE CONTROL DEVICE AND DATA TRANSFER METHOD - When a redundancy failures occurs in sequentiality-guaranteed data transfer, data transfer in a short period of time is resumed such that wherein when a factor by which the second storage device stops processing of the storage system is multiple failures of the two or more redundant control devices during a process of developing data to a storage medium in the second storage device, a session managing unit sets inconsistency as the copy session state, and a buffer managing unit sets the buffer data lost state, and when a data transfer process is resumed between the first storage device and the second storage device, the session managing unit sets consistency as the copy session state when the buffer data lost state is set by the buffer managing unit. | 2015-01-29 |
20150032982 | SYSTEMS AND METHODS FOR STORAGE CONSISTENCY - A storage layer is configured to implement efficient open-close consistency operations. Open close consistency may comprise preserving the original state of a file until the file is closed. The storage layer may be configured to clone a file in response to a file open request. Cloning the file may comprise referencing file data by two separate sets of identifiers. One set may be configured to reflect file modifications, and the other set may be configured to preserve the original state of the file. Subsequent operations configured to modify the file may be performed in reference to one of the sets of identifiers, while the storage layer provides access to the unmodified file through the other set of identifiers. Closing the file may comprise merging the sets of identifiers according to a merge policy. | 2015-01-29 |
20150032983 | STORAGE MANAGEMENT SYSTEM AND STORAGE MANAGEMENT METHOD - An embodiment of this invention is a storage management system including a processor and a storage device to manage a storage system having one or more copy functions. The processor locates data designated to determine a backup method. The storage device stores copy function management information on the one or more copy functions of the storage system. The processor refers to the copy function management information to ascertain the unit of copy operation of each of the one or more copy functions. The processor determines a candidate for a copy function of the storage system to be used to back up the designated data depending on the data configuration in a volume holding the designated data and the unit of copy operation of the candidate for the copy function. | 2015-01-29 |
20150032984 | METHOD AND SYSTEM FOR RESPONDING TO CLIENT REQUESTS FOR INFORMATION MAINTAINED BY STORAGE SYSTEMS - Method and system for providing information regarding a plurality of storage devices managed by a plurality of storage servers are provided. The storage space at the storage devices is presented to a plurality of computing systems as logical storage space. A plurality of searchable data structures having a plurality of data object types are stored at a temporary memory storage device of a management console that interfaces with the plurality of computing systems and the storage servers. Each data object type stores information regarding the storage device. The searchable data structure includes information regarding the storage devices and the logical storage space presented to the computing systems. A lock data structure for tracking locks that are assigned for accessing information pertaining to a storage server and a data object type is maintained to prevent unauthorized access to at least one of the searchable data structures. | 2015-01-29 |
20150032985 | MEMORY ALLOCATION ANALYSIS - The subject disclosure relates to analyzing memory allocations for one or more computer-implemented processes. In particular, in conjunction with employing tags for tracking memory allocation commands, currently allocated memory can be examined for various characteristics of inefficient memory use. For example, as memory is initially allocated, a predetermined bit pattern can be written to the newly allocated memory. Thus, detection of the predetermined bit pattern can be indicative of wasted memory use. Moreover, additional features can be provided to both analyze data and present views associated with that analysis relating to identification of memory fragmentation, over-allocation, sparse memory use, duplication of allocations, multiple module loads, and so forth. | 2015-01-29 |
20150032986 | MEMORY BLOCK MANAGEMENT SYSTEMS AND METHODS - A system for real-time operating system memory block and message management is disclosed. The real-time operating system enables different processes to migrate an allocated memory block from one type of memory block to another type of memory block, and to reliably release the block back to its correct pool of origin. According to one aspect of the inventive subject matter, a memory management engine allocates memory in a basic type to a first process, and upon a migration request from a second process, convert the allocated memory from the basic type to a message type for the second process. Allocating memory in the basic type can be fast but does not ensure proper release of the memory block to its pool of origin. Converting the basic type to the message type enables the operating system to reliably release the block back to its correct pool of origin from any process. | 2015-01-29 |
20150032987 | COMPUTER PROGRAM INSTALLATION ACROSS MULTIPLE MEMORIES - Embodiments herein are directed to a method for installing a program across multiple memories. The method includes calculating a memory space requirement of the program. It may be determined that a first available memory space in a first memory of the first computer system is smaller than the memory space requirement. The first memory is a default memory for installing the program. Upon determining that the first available memory space in the first memory is smaller than the memory space requirement, the method may perform the step of identifying a second memory in communication with the first computer system that has a second available memory space. The first and second available memory spaces, when combined, are sufficient for the memory space requirement to install files of the program. The files of the program may be installed in the first and second memories. | 2015-01-29 |
20150032988 | REGULAR EXPRESSION MEMORY REGION WITH INTEGRATED REGULAR EXPRESSION ENGINE - A method and circuit arrangement selectively perform regular expression matching in connection with accessing data with a processing unit based upon one or more regular expression matching-related attributes stored in a memory address translation data structure such as an Effective To Real Translation (ERAT) or Translation Lookaside Buffer (TLB). A regular expression matching-related attribute in such a data structure may be used to control whether data being communicated between the processing unit and a communications bus is routed through an expression engine integrated with the processing unit such that regular expression matching may be performed in association with the data communication. | 2015-01-29 |
20150032989 | Methods, Systems, and Products for Hashing Using Twisted Tabulation - Methods, systems, and products describe a robust solution for the dictionary problem of data structures. A hash function based on tabulation is twisted to utilize an additional xoring operation and a shift. This twisted tabulation offers strong robustness guarantees over a set of queries in both linear probing and chaining. | 2015-01-29 |
20150032990 | Scalable and Parameterized VLSI Architecture for Compressive Sensing Sparse Approximation - Systems and methods for implementing a scalable very-large-scale integration (VLSI) architecture to perform compressive sensing (CS) hardware reconstruction for data signals in accordance with embodiments of the invention are disclosed. The VLSI architecture is optimized for CS signal reconstruction by implementing a reformulation of the orthogonal matching pursuit (OMP) process and utilizing architecture resource sharing techniques. Typically, the VLSI architecture is a CS reconstruction engine that includes a vector and scalar computation cores where the cores can be time-multiplexed (via dynamic configuration) to perform each task associated with OMP. The vector core includes configurable processing elements (PEs) connected in parallel. Further, the cores can be linked by data-path memories, where complex data flow of OMP can be customized utilizing local memory controllers synchronized by a top-level finite-state machine. The computing resources (cores and data-paths) can be reused across the entire OMP process resulting in optimal utilization of the PEs. | 2015-01-29 |
20150032991 | SYSTEMS AND METHODS FOR INCREASING THE ENERGY SCALE OF A QUANTUM PROCESSOR - Increasing the energy scale of a quantum processor improves its performance. Energy scale of a quantum processor may be increased by increasing the coupling strength of communicatively coupled superconducting devices comprised in the quantum processor. Configuring the physical dimensions of communicatively coupled superconducting devices such that an intentional direct coupling is induced between a pair of superconducting devices communicatively coupled by a coupling device may controllably add an additional mutual inductance to the mutual inductance of the pair of superconducting devices. Furthermore, reducing the beta parameter of a coupling device may improve the tunability of the coupling device. The combined effects of improved tunability of the coupling devices and the increased coupling strength between superconducting devices communicatively coupled by respective coupling devices comprised in the quantum processor may thus improve the performance of the quantum processor. | 2015-01-29 |
20150032992 | DATA PROCESSING ARRANGEMENT AND METHOD FOR DATA PROCESSING - A processing arrangement having a first processing component and a second processing component is provided. The first component has a first output memory and a second output memory and a control device using the first memory storing a value to be output and the second memory stores a value that is based according to a prescribed function on the value. The control device stores a new value in the first memory whenever the second component has read a value stored in the first memory. The second component has a reading device reading the values stored in the first and second memories, and a processing device that checks whether the value read from the second memory is based according to the prescribed function on the value read from the first memory and, depending on the result, to process the value read from the first memory. | 2015-01-29 |
20150032993 | SYSTEMS AND METHODS FOR ACHIEVING ORTHOGONAL CONTROL OF NON-ORTHOGONAL QUBIT PARAMETERS - Achieving orthogonal control of non-orthogonal qubit parameters of a logical qubit allows for increasing the length of a qubit chain thereby increasing the effective connectivity of the qubit chain. A hybrid qubit is formed by communicatively coupling a dedicated second qubit to a first qubit. By tuning a programmable parameter of the second qubit of a hybrid qubit, an effective programmable parameter of the hybrid qubit is adjusted without affecting another effective programmable parameter of the hybrid qubit thereby achieving orthogonal control of otherwise non-orthogonal qubit parameters. The length of the logical qubit may thus be increased by communicatively coupling a plurality of such hybrid qubits together. | 2015-01-29 |
20150032994 | SYSTEMS AND METHODS FOR IMPROVING THE PERFORMANCE OF A QUANTUM PROCESSOR BY REDUCING ERRORS - Techniques for improving the performance of a quantum processor are described. Some techniques employ improving the processor topology through design and fabrication, reducing intrinsic/control errors, reducing thermally-assisted errors and methods of encoding problems in the quantum processor for error correction. | 2015-01-29 |
20150032995 | PROCESSORS OPERABLE TO ALLOW FLEXIBLE INSTRUCTION ALIGNMENT - Methods and apparatus are provided for optimizing a processor core. Common processor subcircuitry is used to perform calculations for various types of instructions, including branch and non-branch instructions. Increasing the commonality of calculations across different instruction types allows branch instructions to jump to byte aligned memory address even if supported instructions are multi-byte or word aligned. | 2015-01-29 |
20150032996 | EXECUTION-AWARE MEMORY PROTECTION - Execution-Aware Memory protection technologies are described. A processor includes an instruction fetch unit to fetch instructions of applications executing in a multitasking environment and an execution unit to execute the instructions. A memory protection unit (MPU) enforces memory access control of the applications by defining an instruction region (I-space) and a data region (D-space and linking the I-space to the D-space. When the MPU determining whether an instruction address is within the I-space and whether a data address of a data access operation is within the D-space. The MPU issues a memory protection fault for the data access operation when either the instruction address is not within the I-space or the data address is not within the D-space. | 2015-01-29 |
20150032997 | TRACKING LONG GHV IN HIGH PERFORMANCE OUT-OF-ORDER SUPERSCALAR PROCESSORS - Tracking global history vector in high performance out of order superscalar processors, in one aspect, may comprise providing a shift register storing global history vector that stores branch predictions and outcomes. A counter is maintained to determine a number of bits to shift the shift register to recover branch history. In another aspect, the global history vector may be implemented with a circular buffer structure. Youngest and oldest pointers to the circular buffer are maintained and used in recovery. | 2015-01-29 |
20150032998 | METHOD, APPARATUS, AND SYSTEM FOR TRANSACTIONAL SPECULATION CONTROL INSTRUCTIONS - An apparatus and method is described herein for providing speculation control instructions. An xAcquire and xRelease instruction are provided to define a critical section. In one embodiment, the xAcquire instruction includes a lock instruction with an elision prefix and the xRelease instruction includes a lock release instruction with an elision prefix. As a result, a processor is able to elide locks and transactionally execute a critical section defined in software by xAcquire and xRelease. But by adding only prefix hints, legacy processor are able to execute the same code by just ignoring the hints and executing the critical section traditionally with locks to guarantee mutual exclusion. Moreover, xBegin and xEnd are similarly provided for in an Instruction Set Architecture (ISA) to define a transactional code region. In addition, other control speculation instructions, such as xAbort to enable explicit abort of a critical or transactional code section and xTest to test a state of speculative execution is also provided in the ISA. | 2015-01-29 |
20150032999 | INSTRUCTION SET ARCHITECTURE WITH OPCODE LOOKUP USING MEMORY ATTRIBUTE - A method and circuit arrangement decode instructions based in part on one or more decode-related attributes stored in a memory address translation data structure such as an Effective To Real Translation (ERAT) or Translation Lookaside Buffer (TLB). A memory address translation data structure may be accessed, for example, in connection with a decode of an instruction stored in a page of memory, such that one or more attributes associated with the page in the data structure may be used to control how that instruction is decoded. | 2015-01-29 |
20150033000 | Parallel Processing Array of Arithmetic Unit having a Barrier Instruction - A parallel processing array processor has a plurality of arithmetic units and a unit that manages barrier instructions whereby processing of program sequences may be coordinated. The array processor further comprises a hierarchy of assigned units whereby multiple program sequences may be processed in parallel. | 2015-01-29 |
20150033001 | METHOD, DEVICE AND SYSTEM FOR CONTROL SIGNALLING IN A DATA PATH MODULE OF A DATA STREAM PROCESSING ENGINE - Techniques and mechanisms for exchanging control signals in a data path module of a data stream processing engine. In an embodiment, the data path module may be configured to form a set of one or more data paths corresponding to an instruction which is to be executed. In another embodiment, data processing units of the data path module may be configured to exchange one or more control signals for elastic execution of the instruction. | 2015-01-29 |
20150033002 | REQUESTING MEMORY SPACES AND RESOURCES USING A MEMORY CONTROLLER - Methods of requesting memory spaces and resources using a memory controller are provided. A particular method may include communicating, by a memory controller, a request to a computer program for a resource, and using the resource in response to an indication from the computer program that the resource is available. Another particular method may include communicating a request to a memory controller for at least one of a memory space of a memory or a second resource. The memory controller may be configured to communicate the request from the first resource to a computer program. Another particular method may also include using, by the first resource, at least one of the memory space or the second resource in response to an indication that the memory space or the second resource is available. | 2015-01-29 |
20150033003 | HOST AND METHOD OF UPGRADING CONNECTION MANAGER OF DONGLES - A host device with a function dongle includes a first connection manager and a first version file. The host upgrades the first connection manager and the first version file. The host gets a second version file which is saved in the dongle. The dongle includes a second connection manager corresponding to the second version file. The host determines whether the upgraded first connection manager is newer than the second connection manager according to the upgraded first version file and the second version file. The host upgrades the second connection manager if the upgraded first connection manager is newer than the second connection manager. | 2015-01-29 |
20150033004 | Processing Device - Disclosed herein is a processing device comprising a secured execution environment comprising means for bringing the processing device into a predetermined operational state; and a timer; a communication interface for data communication between the processing device and a remote device management system external to the processing device; wherein the secured execution environment is configured, responsive to an expiry of the timer, to bring the processing device into said predetermined operational state; and responsive to a receipt, from the remote device management system via said communications interface, of a predetermined signal, to restart the timer. | 2015-01-29 |
20150033005 | SYSTEM AND METHOD FOR BOOT ACCELERATION OF A DATA PROCESSING SYSTEM - A system and method to reduce the boot time of a data processing system by informing a memory device to send data prior to the boot time. The data processing system includes: a host system having a host processor and host memory; and (2) the memory device. The memory device is preconfigured in advance prior to the boot time with one or more Read commands with one or more corresponding physical addresses of host memory. This preconfiguration can be done at the time of system integration or before every boot operation. Once the system power-on occurs, the memory device sends the data in packets to the host memory. Whenever the host processor needs data it will be available in host memory which significantly reduces the boot time. | 2015-01-29 |
20150033006 | HIDING LOGICAL PROCESSORS FROM AN OPERATING SYSTEM ON A COMPUTER - Hiding logical processors from an operating system (OS) of a computer is described. In an example, a method of hiding at least one logical processor in a computer having a plurality of logical processors includes: initializing the plurality of logical processors by executing a pre-boot routine in system firmware; identifying at least one logical processor of the plurality of logical processors to be hidden from an operating system (OS) of the computer to provide at least one hidden logical processor and at least one visible logical processor; placing each of the at least one hidden logical processor into a system management mode (SMM) by executing a park routine in the system firmware; and booting the OS of the computer to use the at least one visible logical processor. | 2015-01-29 |
20150033007 | Method and System for Sharing a Hotkey Between Application Instances - Examples of the present disclosure provide a method and a system for sharing a hotkey between application instances. The method includes receiving a hotkey release message from an application instance that registers a first hotkey, wherein the hotkey release message is to release the first hotkey and includes identification information about the first hotkey; and according to the identification information about the first hotkey, initiating a register request for registering the first hotkey. Employing the examples of the present disclosure, between application instances, when an application instance that currently registers a hotkey exits, the application instance that currently registers the hotkey may notify a next application instance to register the hotkey, so that the transitivity of the hotkey may be ensured, the hotkey may be shared, and the accuracy of hotkey response may be improved. | 2015-01-29 |
20150033008 | EFFICIENT COMMON STORAGE OF PARTIALLY ENCRYPTED CONTENT - Techniques and mechanisms described herein facilitate the efficient common storage of partially encrypted content. According to various embodiments, a client device to transmit a designated representation of a media content item via a communications interface may be received. The media content item may be associated with a plurality of representations including the designated representation. The media content item may be associated with first media content data and second media content data. The first media content data may be shared among the plurality of representations. The second media content data may be specific to the designated representation. The first media content data may be combined with the second media content data to create a designated partially encrypted media content portion associated with the designated representation via a processor. The designated partially encrypted media content portion may be transmitted to the client device via the communications interface. | 2015-01-29 |
20150033009 | Method and System for Authenticating a User by an Application - The invention relates to a method for authenticating a user by an application by means of a challenge-response method. In this case, the challenge ( | 2015-01-29 |
20150033010 | METHOD FOR THE SECURE EXCHANGE OF DATA OVER AN AD-HOC NETWORK IMPLEMENTING AN XCAST BROADCASTING SERVICE AND ASSOCIATED NODE - A method for the secure exchange of data over an ad-hoc network implementing an Xcast broadcasting service and an associated node are disclosed. The method includes providing a security graph for the network and a communication graph for the network, routing a data item between the sender node sending the data and each receiver node receiving the data along a secure route on the security graph. The method also includes generating, between one relay node and a subsequent relay node of the secure route, an appropriate message, containing the data protected in accordance with a security association shared between the relay node and the subsequent relay node. The method further includes routing the message from the relay node to the subsequent relay node along a communication route on the communication graph. | 2015-01-29 |
20150033011 | METHOD FOR INITIALIZING A MEMORY AREA THAT IS ASSOCIATED WITH A SMART METER - A method for initializing a memory area associated with a smart meter,: establishing a first communication channel between a first computer system and a security module, the security module being associated with a memory area, and the first computer system being associated with a set of computer systems interconnected via a network; authenticating the first computer system with respect to the security module; once the first computer system has been successfully authenticated, the security module receiving data from the first computer system by secure transmission and storage of the data in the memory area in order to initialize the memory area, communication between a second computer system of a utility company and/or operator of the measuring system and the security module being only possible while bypassing the first computer system, owing to the stored data, the second computer system being a computer system of the set of computer systems. | 2015-01-29 |
20150033012 | SECURE PROCESSING ENVIRONMENT MEASUREMENT AND ATTESTATION - Embodiments of an invention for secure processing environment measurement and attestation are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first instruction associated with a build or a rebuild of a secure enclave. The execution unit is to execute the first instruction. Execution of the first instruction, when associated with the build, includes calculation of a first measurement and a second measurement of the secure enclave. Execution of the first instruction, when associated with the rebuild, includes calculation of the second measurement without calculation of the first measurement. | 2015-01-29 |
20150033013 | Network-based Service Content Protection - Network-based service content protection techniques are described. In one or more implementations, content is edited locally by a computing device. The edited content is automatically encrypted without any user intervention by the computing device using an encryption credential, e.g., encryption key or other secret. The automatic encryption is performed responsive to a request to store the content at a network-based service provider such that the encrypted content can only be decrypted and accessed with the encryption credential and the encrypted content is uploaded to the network-based service provider. | 2015-01-29 |
20150033014 | Compact and Efficient Communication Security through Combining Anti-Replay with Encryption - A method of providing anti-replay protection, authentication, and encryption with minimal data overhead is provided. A sender uses an arbitrary-length pseudorandom permutation to encrypt messages that include plaintext and successively increasing sequence numbers, to produce ciphertext messages. The sender transmits the ciphertext messages. A receiver receives the ciphertext messages and, for each received ciphertext message, performs the following operations. The receiver decrypts the given ciphertext message to recover plaintext and a candidate sequence number from the message. The receiver determines if the candidate sequence number is in any one of multiple acceptable sequence number windows having respective sequence number ranges that are based on at least one of a highest sequence number previously accepted and a last sequence number that was previously rejected, as established based on processing of previously received ciphertext messages. | 2015-01-29 |
20150033015 | METHODS AND SYSTEMS FOR SECURELY UPLOADING FILES ONTO AIRCRAFT - Embodiments described herein provide for a system for verifying integrity of files uplinked to a remote vehicle. The system is configured to receive a first message authentication code (MAC) for the uplinked file, a first acknowledgement MAC for the MAC, and a first cyclic redundancy check (CRC) for the first MAC and the acknowledgement MAC. The system is also configured to compute a second MAC from the uplinked file, a second acknowledgement MAC from the second MAC and a second CRC from the second MAC and second acknowledgement MAC. Integrity of the uplinked file is verified by comparing the first CRC with the second CRC. If integrity of the uplinked file is confirmed, the uplinked file is accepted. If integrity of the uplinked file is not confirmed, the uplinked file is rejected. | 2015-01-29 |
20150033016 | SYSTEMS AND METHODS FOR SECURING REAL-TIME MESSAGES - A first aspect of the invention includes a method of securing messages using multiple cryptographic algorithms that distributes the burden of computing a session key using a strong cryptographic algorithm while using the session key with a faster cryptographic algorithm to protect messages long enough to compute a new session key. Some embodiments can be improved by use of a non-repeating seed, slotted storage of session keys, or both. A second aspect of the invention is generally directed to an augmented multi-stage hash function, which can be used as the faster cryptographic algorithm. | 2015-01-29 |
20150033017 | Methods and Apparatuses for Electronic Message Authentication - Various methods are provided for facilitating the message recipient authentication using facial detection. One example method may include receiving a message. The message may include a plurality of encoded facial features that identify a message recipient. The method may further include causing an image to be captured of the message recipient in an instance in which the message is accessed. The method may also include authenticating the message recipient based on the captured image and the received plurality of encoded features provided with the received message. Similar and related example apparatuses and example computer program products are also provided. | 2015-01-29 |
20150033018 | SYSTEM FOR DETERMINING WHETHER CHARACTER STRING HAS BEEN ACCEPTED BY AUTOMATON - Provided is a server connectable to a client for input of a string and that has an automaton defining a subsequent state for transition for each state and each character. This server has a key chain generating unit for generating a key chain for each combination of index, character and state expressing the position of each character in a string, the key chain having encrypted keys for the next index corresponding to the subsequent state of transition from the current state in accordance with the character on the basis of the key corresponding to the current state, and a providing unit for communicating with a client and providing to the client a key chain corresponding to each inputted key among a set of key chains for each index in a state concealing the inputted characters from the client. | 2015-01-29 |
20150033019 | CRYPTOGRAPHIC COMMUNICATION SYSTEM, COMMUNICATION DEVICE, KEY DISTRIBUTION DEVICE, AND CRYPTOGRAPHIC COMMUNICATION METHOD - A cryptographic communication system constituted by a first communication device, and a second communication device that stores a master key serving as an encryption key, the cryptographic communication system being characterized in that said first communication device has a common key storing unit configured to store a key pair constituted by a first key serving as a common key used to communicate with said second communication device and a second key obtained by encrypting said first key by using said master key held by said second communication device, and also has a common key transmitting unit configured to transmit said second key to said second communication device, and said second communication device has common key obtaining unit configured to receive said second key and obtaining said first key by decrypting said received second key by using said master key. | 2015-01-29 |
20150033020 | Protocol for Controlling Access to Encryption Keys - A secure remote-data-storage system stores encrypted data and both plaintext and encrypted keys at a server, where data at the server is inadequate to recover the plaintext of the encrypted data; and stores at least one encrypted key at a client system. To decrypt the data, the client must obtain a copy of the encrypted data from the server, and a key to decrypt its locally-stored encrypted key. Once decrypted, the locally-stored key can be used to decrypt the encrypted data, or to decrypt an encrypted key from the server, which may then be used decrypt the encrypted data. | 2015-01-29 |
20150033021 | REMOTE ACCESS TO LOCAL NETWORK VIA SECURITY GATEWAY - Multiple protocol tunnels (e.g., IPsec tunnels) are deployed to enable an access terminal that is connected to a network to access a local network associated with a femto access point. A first protocol tunnel is established between a security gateway and the femto access point. A second protocol tunnel is then established in either of two ways. In some implementations the second protocol tunnel is established between the access terminal and the security gateway. In other implementations the second protocol tunnel is established between the access terminal and the femto access point, whereby a portion of the tunnel is routed through the first tunnel. | 2015-01-29 |
20150033022 | CONFIGURING A VALID DURATION PERIOD FOR A DIGITAL CERTIFICATE - A valid duration period for a digital certificate is established by a process that includes assigning numeric values to certificate term. The numeric value assigned to each certificate term is representative of the valid duration period. The method continues by identifying one certificate term, which may include requesting a user to select a certificate term. The method may include transmitting the requested certificate term to a server. The certificate term requested is sent via a certificate request. The server is configured to convert the numeric value associated with the requested certificate term into a duration counter value. The method may also include a certificate server receiving from the server, the certificate request including the duration counter value. The method may conclude with transmitting the signed certificate request to a client device capable of generating the digital certificate with the requested certificate term. | 2015-01-29 |
20150033023 | PREVENTING PLAYBACK OF STREAMING VIDEO IF ADS ARE REMOVED - A digitally signed manifest file includes metadata that specifies whether a policy regarding the digital signature should be enforced. The policy is then used to generate additional metadata associated with the program and ad content of the video stream. The metadata is tamper resistant so that any modification or removal of the metadata will prevent the video stream from playing. If the metadata indicates that the policy should be enforced, the digital signature of the manifest is verified by the client, and an invalid or missing signature prevents the video stream from being played back. The metadata defines which media players are allowed and/or not allowed to play back a video stream, including media players that are configured to skip or remove ads, and/or includes an encryption key identifier for verifying the digital signature. The ad content is digitally signed to prevent modification or replacement of the ad content. | 2015-01-29 |
20150033024 | DATA DISTRIBUTION PATH VERIFICATION - A method may include receiving data and first path-metadata. The first path-metadata may include a first entity identifier. The first entity identifier may be associated with a first receiving entity that receives the data and the first path-metadata from an originating entity. The first path-metadata may also include a first digital signature associated with the originating entity. The method may further include receiving second path-metadata that may include the first path-metadata and a second entity identifier associated with a second receiving entity. The second path-metadata may also include a second digital signature associated with the first receiving entity. The method may additionally include verifying that the data was communicated by the originating entity to the first receiving entity and from the first receiving entity to the second receiving entity based on the first path-metadata, the second path-metadata, the first digital signature, and the second digital signature. | 2015-01-29 |
20150033025 | Digital Signature Technique - A method for signing a digital message, including the following steps: selecting parameters that include first and second primes, a ring of polynomials related to the primes, and at least one range-defining integer; deriving private and public keys respectively related to a random polynomial private key of the ring of polynomials, and to evaluations of roots of unity of the random polynomial to obtain a public key set of integers; storing the private key and publishing the public key; signing the digital message by: (A) generating a noise polynomial, (B) deriving a candidate signature by obtaining a hash of the digital message and the public key evaluated at the noise polynomial, and determining the candidate signature using the private key, a polynomial derived from the hash, and the noise polynomial, (C) determining whether the coefficients of the candidate signature are in a predetermined range dependent on the at least one range-defining integer, and (D) repeating steps (A) through (C) until the criterion of step (C) is satisfied, and outputting the resultant candidate signature as an encoded signed message. | 2015-01-29 |
20150033026 | DYNAMIC TARDOS TRAITOR TRACING SCHEMES - A fingerprinting method. For each round in a series of rounds: providing to each receiver in a set of receivers a version of a source item of content, the source item of content corresponding to the round. For the round there is a corresponding part of a fingerprint-code for the receiver, the part includes one or more symbols. The version provided to the receiver represents those one or more symbols. One or more corresponding symbols are obtained from a suspect item as a corresponding part of a suspect-code. For each receiver in the set of receivers, a corresponding score that indicates a likelihood that the receiver is a colluding-receiver is updated. | 2015-01-29 |
20150033027 | CRYPTOGRAPHIC SECURITY FUNCTIONS BASED ON ANTICIPATED CHANGES IN DYNAMIC MINUTIAE - Dynamic key cryptography validates mobile device users to cloud services by uniquely identifying the user's electronic device using a very wide range of hardware, firmware, and software minutiae, user secrets, and user biometric values found in or collected by the device. Processes for uniquely identifying and validating the device include: selecting a subset of minutia from a plurality of minutia types; computing a challenge from which the user device can form a response based on the selected combination of minutia; computing a set of pre-processed responses that covers a range of all actual responses possible to be received from the device if the combination of the particular device with the device's collected actual values of minutia is valid; receiving an actual response to the challenge from the device; determining whether the actual response matches any of the pre-processed responses; and providing validation, enabling authentication, data protection, and digital signatures. | 2015-01-29 |
20150033028 | METHOD FOR READING ATTRIBUTES FROM AN ID TOKEN - A method for reading at least one attribute stored in an ID token assigned to a user involving: authenticating the user to the ID token, authenticating a first computer system to the ID token, and, assuming successful authentication of the user and the first computer system to the ID token, read access by the first computer system to the at least one attribute stored in the ID token for transmission of the at least one attribute to a second computer system, and generating of a time indication for the at least one attribute by the first computer system. | 2015-01-29 |
20150033029 | APPARATUS, METHOD AND COMPUTER-READABLE MEDIUM - An apparatus includes a memory; and a processor coupled to the memory and configured to: authenticate an identification for accessing a first service by comparing a password associating with the identification with an first encrypted password that is generated by encrypting the password on the basis of a first encryption policy to authenticate an access to the first service; and provide a second service with the identification and the password to cause to generate information when an authentication of the identification is successful, the information being accessed to authenticate the identification when the second service is accessed based on the identification and the password. | 2015-01-29 |
20150033030 | SECURELY RECOVERING A COMPUTING DEVICE - A method and an apparatus for establishing an operating environment by certifying a code image received from a host over a communication link are described. The code image may be digitally signed through a central authority server. Certification of the code image may be determined by a fingerprint embedded within a secure storage area such as a read only memory (ROM) of the portable device based on a public key certification process. A certified code image may be assigned a hash signature to be stored in a storage of the portable device. An operating environment of the portable device may be established after executing the certified code. | 2015-01-29 |
20150033031 | System and Method for Detecting a Security Compromise on a Device - Embodiments of a system and method for detecting a security compromise on a device are described. Embodiments may be implemented by a content consumption application configured to protect content decryption keys on a device, such as a computer system (e.g., a desktop or notebook computer) or a mobile device (e.g., a smartphone or tablet). For instance, the content consumption application may be configured to provide decryption keys for respective content to a media component (or another component of the operating system) if multiple conditions have been met. For instance, in various embodiments, the content consumption application may pass the key to the media component after ensuring that i) one or more security mechanisms of the device operating system have not been compromised and ii) one or more executable instructions of the content consumption application have not been tampered (e.g., instructions corresponding to a function that handles the decryption key(s)). | 2015-01-29 |
20150033032 | ENCRYPTED DATABASE SYSTEM, CLIENT TERMINAL, DATABASE SERVER, DATA LINKING METHOD AND PROGRAM - An encrypted database system or the like, which make it possible to perform linking between a plurality of tables without decrypting them and further to reduce a risk of the data correlation leaking out, is provided. A client terminal ( | 2015-01-29 |
20150033033 | Efficient Homomorphic Encryption Scheme for Bilinear Forms - In one exemplary embodiment, a computer readable storage medium tangibly embodying a program of instructions executable by a machine for performing operations including: receiving information B to be encrypted as a ciphertext C in accordance with an encryption scheme having an encrypt function; and encrypting B in accordance with the encrypt function to obtain C, the scheme utilizes at least one public key A, where B, C, and A are matrices, the encrypt function receives as inputs A and B and outputs C as C←AS+pX+B(mod q), S is a random matrix, X is an error matrix, p is in integer, q is an odd prime number. In other exemplary embodiments, the encryption scheme includes a decrypt function that receives as inputs at least one private key T (a matrix) and C and outputs B as B=T | 2015-01-29 |
20150033034 | MEASURING A SECURE ENCLAVE - Embodiments of an invention for measuring a secure enclave are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first, a second, and a third instruction. The execution unit is to execute the first, the second, and the third instruction. Execution of the first instruction includes initializing a measurement field in a control structure of a secure enclave with an initial value. Execution of the second instruction includes adding a region to the secure enclave. Execution of the third instruction includes measuring a subregion of the region. | 2015-01-29 |
20150033035 | Apparatus and Method for Accessing an Encrypted Memory Portion - An apparatus for accessing an encrypted memory portion of a memory is provided. The apparatus includes a plurality of signature generators, wherein each signature generator of the plurality of signature generators is configured to generate a signature of a plurality of signatures depending on an instruction of a plurality of instructions, wherein each of the plurality of instructions is a processor instruction for controlling a processor. Moreover, the apparatus includes a key modifier for generating a processed key depending on a standard key and on the plurality of signatures. Furthermore, the apparatus includes a controller for accessing the encrypted memory portion of the memory, wherein the memory access controller is configured to employ the processed key to access the encrypted memory portion of the memory. | 2015-01-29 |
20150033036 | SECURING BACKING STORAGE DATA PASSED THROUGH A NETWORK - Techniques described herein generally relate to methods, data processing devices and computer readable media to ensure that data stored in a remote backing storage device are in encrypted form before that data is transferred to another device or over a network. In some examples, the methods, data processing devices and computer readable media may be arranged to encrypt the data passed to the network when the data stored in the backing storage device is in unencrypted form. Also disclosed are methods, data processing devices and computer readable media that identify when the data stored in the backing storage device is in unencrypted form, including methods that may detect that the data may appear to be in encrypted form as a result of the data being compressed. | 2015-01-29 |
20150033037 | KEY ROTATION FOR A MEMORY CONTROLLER - Systems, methods, and other embodiments associated with rotating keys for a memory are described. According to one embodiment, a memory system comprises a memory controller configured to control access to a memory and to process memory access requests. Rrekeying logic is configured to rotate a first key that was used to scramble data in the memory and re-scramble the data with a second key by: determining when the memory controller is in an idle cycle and performing a rekeying operation on a portion of the memory during the idle cycle, and pausing the rekeying operation when the memory controller is not in an idle cycle to allow memory access requests to be performed and resuming the rekeying operation during a next idle cycle. | 2015-01-29 |
20150033038 | METHODS, APPARATUS, AND SYSTEMS FOR SECURE DEMAND PAGING AND OTHER PAGING OPERATIONS FOR PROCESSOR DEVICES - A secure demand paging system ( | 2015-01-29 |
20150033039 | SECTOR MAP-BASED RAPID DATA ENCRYPTION POLICY COMPLIANCE - To comply with a policy for a computing device indicating that data written by the computing device to the storage volume after activation of the policy be encrypted, a sector map is accessed. The sector map identifies one or more sectors of a storage volume and also identifies, for each of the one or more sectors of the storage volume, a signature of the content of the sector. In response to a request to read the content of a sector, the content of the sector is returned without decrypting the content if the sector is one of the one or more sectors and the signature of the content of the sector matches the signature of the sector identified in the sector map. Otherwise, the content of the sector is decrypted and the decrypted content is returned. | 2015-01-29 |
20150033040 | POWER SUPPLY CIRCUIT FOR CENTRAL PROCESSING UNIT - A power supply circuit for supplying power to a central processing unit (CPU) of a computer includes a pulse width modulation (PWM) controller, a control circuit, a switch circuit, a first current protection circuit, a second current protection circuit, a first power circuit, and a second power circuit. When the computer is turned on, a first current protection threshold is set by the PWM controller through the first current protection circuit. When the computer is in a standby mode, a second current protection threshold is set by the PWM controller through the second current protection circuit. | 2015-01-29 |
20150033041 | POWER SUPPLY CIRCUIT FOR CENTRAL PROCESSING UNIT - A power supply circuit applied to a central processing unit (CPU) of a computer includes a pulse width modulation (PWM) controller, a control circuit, a first switch circuit, a second switch circuit, a first compensation circuit, a second compensation circuit, a first power circuit, and a second power circuit. When the computer is turned on, the PWM controller regulates duty cycles of pulse signals and outputs the regulated pulse signals to the first and second power circuits according to a first compensation signal, to provide a stable voltage to the CPU. When the computer is in a standby mode, the PWM controller regulates duty cycles of pulse signals and outputs the regulated pulse signals to the first power circuit according to a second compensation signal, to provide a stable voltage to the CPU. | 2015-01-29 |
20150033042 | POWER SUPPLY SYSTEM, ELECTRONIC DEVICE, CABLE, AND PROGRAM - A power supply system includes an electronic device configured to output from an external audio output terminal a power-supply signal according to a target value for supply voltage when power is supplied to an external device and a cable with a rectifier circuit that rectifies the power-supply signal and generates the supply voltage. | 2015-01-29 |
20150033043 | ELECTRONIC DEVICE, CONTROL METHOD, AND SYSTEM - An electronic device is connected to a server device. The electronic device includes: a detection unit that detects a state of the electronic device; a generation unit that generates third information in which first information that is information indicating the state of the electronic device and second information that is information indicating time of detection by the detection unit are associated with each other; a registration unit that registers the third information in a memory unit in order of generation; and a control unit that performs, when power supply to the electronic device is started, control to transmit latest third information among one or more pieces of the third information stored in the memory unit, to the server device, as stop information related to time at which the electronic device was stopped. | 2015-01-29 |
20150033044 | Methods and Circuits for Dynamically Scaling DRAM Power and Performance - A memory system supports high-performance and low-power modes. The memory system includes a memory core and a core interface. The memory core employs core supply voltages that remain the same in both modes. Supply voltages and signaling rates for the core interface may be scaled down to save power. Level shifters between the memory core and core interface level shift signals as needed to accommodate the signaling voltages used by the core interface in the different modes. | 2015-01-29 |
20150033045 | Power Supply Droop Reduction Using Feed Forward Current Control - An apparatus for performing instruction throttling for a computing system is disclosed. The apparatus may include a first counter, a second counter, and a control circuit. The second counter may be configured to increment in response to a determination that a processing cycle of a processor has completed. The control circuit may be configured to initialize the first and second counters, detect the processor has issued and instruction, decrement the first counter in response to the detection of the issued instruction, block the processor from issuing instructions dependent upon the a value of the first counter, reset the first counter dependent upon a value of the second counter, and reset the second counter in response to a determination that the value of the second counter is greater than a pre-determined value. | 2015-01-29 |
20150033046 | METHOD OF POWER MANAGEMENT, PORTABLE SYSTEM AND PORTABLE POWER BANK - A method of power management is to be implemented by a portable electronic device coupled to a portable power bank. The portable power bank is further coupled to an electrical appliance. In the method, the portable electronic device receives power information from the portable power bank, and controls the portable power bank to operate in one of a first mode, in which electrical power is provided to the electrical appliance, and a second mode, in which electrical power is not provided to the electrical appliance, based on whether or not the portable power bank has sufficient amount of power. | 2015-01-29 |
20150033047 | Application Processors, Mobile Devices Including The Same And Methods Of Managing Power Of Application Processors - An application processor includes a memory controller, a display block and a power management unit. The memory controller controls an external memory that stores an image signal to be displayed on a display unit. The display block includes an internal frame buffer and a display controller and the display controller controls the image signal to be displayed on the display unit. The power management unit adaptively controls a power mode of the application processor based on a characteristic of the image signal to be displayed and a power control overhead index. | 2015-01-29 |
20150033048 | MULTIPLE VOLTAGE GENERATOR AND VOLTAGE REGULATION METHODOLOGY FOR POWER DENSE INTEGRATED POWER SYSTEMS - An integrated power system suitable for simultaneously powering marine propulsion and service loads. The system includes: (a) at least one generator configured with at least first and second armature windings configured to output respective first and second alternating current power signals of different voltages, the at least two armature windings positioned within the same stator slots so that they magnetically couple; (b) at least first and second rectifier circuits coupled to said generator to convert said first and second alternating current power signals into first and second direct current power signals; (c) a first load to which said first direct current power signal is coupled and a second load to which said second direct current power signal is coupled. | 2015-01-29 |
20150033049 | METHOD, DEVICE AND MOBILE TERMINAL FOR INFORMATION BACKUP - Disclosed is a method for information backup, comprising: an information backup device detects a battery volume of a mobile terminal and determines whether or not the battery volume reaches a preset low-battery alarming threshold; and the information backup device stores contact information stored in the mobile terminal into a backup memory card when the battery volume reduces the low-battery alarming threshold. The present disclosure also discloses a device and a mobile terminal for information backup. The present disclosure enables the user of a mobile terminal to timely view contact information when the mobile terminal runs out of power. | 2015-01-29 |
20150033050 | SEMICONDUCTOR INTEGRATED CIRCUIT AND COMPUTING DEVICE INCLUDING THE SAME - A semiconductor integrated circuit and a computing system including the same are provided. The semiconductor integrated circuit includes: an integrated clock gating cell including a clock output node; and clock-based cells each including a clock input node. The clock output node of the integrated clock gating cell and the clock input nodes of the clock-based cells are aligned on a straight line and commonly connected to a clock gating path. | 2015-01-29 |
20150033051 | Restricting Clock Signal Delivery Based On Activity In A Processor - In an embodiment, a processor has a core to execute instructions which includes a first cache memory, a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, and a core activity monitor logic to monitor activity of the core and, responsive to a miss in the first cache memory, to send a first restriction command to cause the clock generation logic to reduce delivery of the first clock signal to at least one of the units to a first frequency less than a frequency of the first clock signal. Other embodiments are described and claimed. | 2015-01-29 |
20150033052 | Wakeup Receiver Circuit, Electronic System and Method to Wake up a Device - A device is operated in a low power mode of operation. The device receives a differential signal that includes a first polarity signal and a second polarity signal. A slope of a first direction is detected in the differential signal and a slope of a second direction is detected in the differential signal. A wakeup of the device is caused in response to the detection of the first slope of the differential signal and the second slope of the differential signal. | 2015-01-29 |
20150033053 | METHOD AND APPARATUS FOR CONTROLLING POWER CONSUMPTION OF A PORTABLE TERMINAL - A method for controlling a power consumption in a portable terminal and a portable terminal supporting the method are provided. The method includes receiving first data from at least one device, by a main processor; transmitting second data based on the received first data to a sub processor, by the main processor; receiving the second data from the main processor, and determining whether the main processor is in a sleep state, by the sub processor; and when it is determined that the main processor is in a sleep state, maintaining the sleep state of the main processor, receiving the first data from the at least one device, and controlling the at least one device based on the received first data and second data, by the sub processor. | 2015-01-29 |
20150033054 | METHOD FOR OPERATING AT LEAST TWO DATA PROCESSING UNITS WITH HIGH AVAILABILITY, IN PARTICULAR IN A VEHICLE, AND DEVICE FOR OPERATING A MACHINE - A method for operating at least two data processing units with high availability, in particular in a vehicle, is provided. A first data processing unit and a second data processing unit can each provide the same function to an extent of at least 60 percent or at least 90 percent. The second data processing unit removes automatically at least one entry for a process to be executed from a memory unit or automatically places itself into a standby mode. | 2015-01-29 |
20150033055 | Techniques for Managing Power and Performance of Multi-Socket Processors - Examples are disclosed for managing power and performance of multi-socket processors. In some examples, a utilization rate of a first processor circuitry in a first processor socket may be determined. An active memory ratio of a cache for the first processor circuitry may be compared to a threshold ratio or a data traffic rate between the first processor circuitry and a second processor circuitry in a second processor socket may be compared to a threshold rate. According to some examples, a first power state of the first processor circuitry may be changed based on the determined utilization rate. The first power state may also be changed based on the comparison of the active memory ratio to the threshold ratio or the comparison of the data traffic rate to the threshold rate. | 2015-01-29 |
20150033056 | Reducing power consumption of sensor by overriding instructions to measure - Systems and methods for reducing power consumption of a device utilized to measure affective response to content by overriding selections of a mode-selector. The mode-selector receives tags corresponding to segments of content. The mode-selector selects, based on the tags, modes for operating the device to measure affective response to the segments. A threshold module receives measurements of the user's state, taken by a sensor, and indicates whether a predefined threshold is reached by the measurements. If reached, the device is operated according to a first mode to measure the affective response. Otherwise, the device is operated according to a second mode to measure the affective response. The power consumption of the device when operating in the second mode is significantly lower than the power consumption of the device when operating in the first mode. | 2015-01-29 |
20150033057 | POWER CONSERVATION BASED ON CACHING - The present invention relates to a method and device that conserves power. In some embodiments, the device is a battery powered storage device. The invention employs a large cache and aggressive caching algorithm to serve data from the storage media (hard disk or SSD) or write data to the storage media. The cache provides an efficient location from which to serve data, especially multi-media. In one embodiment, the algorithm determines when to place the drive into a lower power state, such as idle, or standby, based on the amount of anticipated idle time provided by the large cache. | 2015-01-29 |
20150033058 | SERVER CLUSTER AND CONTROL MECHANISM THEREOF - A server cluster including a network switch and multiple server nodes is provided. The network switch is connected to an external network. Each server node includes a network port, a network chip and a control unit. The network port is connected to the network switch via a cable. The network chip detects the cable to obtain a connection state with the external network at the server node after the network switch is started, and accordingly outputs a connection state signal. The control unit turns on or shuts down the server node according to the connection state signal and an on/off state of the server node. | 2015-01-29 |
20150033059 | STATUS-SENSITIVE POWER OBSERVING SYSTEM - The present invention relates to a status-sensitive power observing system ( | 2015-01-29 |
20150033060 | CLOCK DATA RECOVERY CIRCUIT, TIMING CONTROLLER INCLUDING THE SAME, AND METHOD OF DRIVING THE TIMING CONTROLLER - Provided is a clock data recovery circuit including a phase-frequency detector configured to detect a frequency and phase of a reference clock signal and control a frequency and phase of an internal clock signal based on the detected frequency, a frequency detector configured to detect a frequency of a data signal and, based on the detected frequency of the data signal, adjust the frequency of the internal clock signal; and a phase detector configured to detect a phase of the data signal based on the detected frequency of the data signal and adjust the phase of the internal clock signal. Accordingly, a timing controller that includes the clock data recovery circuit is capable of establishing data communication at high speeds when the system is powered on/off to reduce power consumption. Also, the timing controller does not need to include an additional external clock generation device, and is capable of achieving frequency synchronization using a non-precision clock signal generated in the timing controller. | 2015-01-29 |
20150033061 | Harmonic Detector of Critical Path Monitors - A system for monitoring a clock input signal including a reference clock to be monitored, a flip-flop, a plurality of delay logic blocks, a sampling unit, and a comparison unit. The reference clock may have an expected maximum frequency. The flip-flop may be configured to generate a corresponding clock signal at a reduced frequency compared to the reference clock. The plurality of delay logic blocks may be configured to receive the reduced frequency clock signal and delay the signal for various amounts of time, each less than an expected period of the reference clock. The sampling unit may be configured to sample the signals output from the plurality of delay logic blocks. The comparison unit may be configured to receive the outputs of the flip-flop and the sampling unit and use these outputs to determine if the reference clock is running at an acceptable frequency compared to the expected frequency. | 2015-01-29 |
20150033062 | APPARATUS AND METHOD FOR CONTROLLING CONTROLLABLE CLOCK SOURCE TO GENERATE CLOCK SIGNAL WITH FREQUENCY TRANSITION - A clock generator includes a controllable clock source and a frequency hopping controller. The controllable clock source generates a clock signal to a clock-driven device. The frequency hopping controller controls the controllable clock source to make the clock signal have at least one frequency transition from one clock frequency to another clock frequency, wherein the controllable clock source stays in a frequency-locked state during a time period of the at least one frequency transition. | 2015-01-29 |
20150033063 | STORAGE FAILURE PROCESSING IN A SHARED STORAGE ARCHITECTURE - The disclosed embodiments relate to systems and methods for coordinating management of a shared disk storage between nodes. Particularly, a messaging protocol may be used to communicate notifications regarding each node's perception of the shared storage's state. The nodes may use the messaging protocol to achieve consensus when recovering from a storage device failure. Some embodiments provide for recovery when localized failures, such as failures at an adapter on a node, occur. | 2015-01-29 |
20150033064 | SELF-IDENTIFYING MEMORY ERRORS - A memory region can durably self-identify as being faulty when read. Information that would have been assigned to the faulty memory region can be assigned to another of that sized region in memory using a replacement encoding technique. For phase change memory, at least two fault states can be provided for durably self-identifying a faulty memory region; one state at a highest resistance range and the other state at a lowest resistance range. Replacement cells can be used to shift or assign data when a self-identifying memory fault is present. A memory controller and memory module, alone or in combination may manage replacement cell use and facilitate driving a newly discovered faulty cell to a fault state if the faulty cell is not already at the fault state. | 2015-01-29 |
20150033065 | SOLID STATE DRIVE EMERGENCY PRE-BOOT APPLICATION PROVIDING EXPANDED DATA RECOVERY FUNCTION - An apparatus includes a non-volatile memory and a controller. The non-volatile memory includes a user area and a non-user area. The user area is generally enabled to store and retrieve data in a logical block address space of a host. The non-user area stores a failure-specific recovery routine. The controller may be communicatively coupled to the non-volatile memory. The controller is generally enabled, when operationally coupled to the host, (i) to respond to host commands to read and to write data into the user area of the non-volatile memory and (ii) upon detection of a predefined failure of a controller boot process, to respond to host read requests by returning the failure-specific recovery routine stored in the non-user area of the non-volatile memory. | 2015-01-29 |
20150033066 | PARTIAL WRITE ERROR RECOVERY - A data storage device may have at least a qualifier circuit that is configured to recognize a write error during a write operation for a single user data sector on a data storage medium and resume the write operation from the location of the write error by skipping at least one user data sub-sector to provide multiple separate original user data sub-sectors that collectively form the single user data sector. | 2015-01-29 |
20150033067 | AUTOMATIC RAID MIRRORING WHEN ADDING A SECOND BOOT DRIVE - A storage system including a first boot drive configured to store an operating system, one or more data drives configured to store user data, the one or more data drives distinct from the first boot drive, and a controller configured to detect when a second boot drive is added to the storage system, and automatically configure the first boot drive and the second boot drive in a redundant array of independent disks (“RAID”) configuration when the controller detects that the second boot drive is added to the storage system. | 2015-01-29 |
20150033068 | FAILOVER TO BACKUP SITE IN CONNECTION WITH TRIANGULAR ASYNCHRONOUS REPLICATION - Handling failure of a primary group at a first data center that is part of plurality of data centers providing triangular asynchronous replication, includes creating a data mirroring relationship between at least one storage volume at a second data center having a synchronous backup group that is part of the plurality of data centers and at least one storage volume at a third data center having an asynchronous backup group that is part of the plurality of data centers and resuming work at the second data center. Handling failure of a primary group at a first data center may also include synchronizing the at least one storage volume at the second data center with the at least one storage volume at the third data center prior to resuming work at the second data center. | 2015-01-29 |
20150033069 | PERFORMING A DATA WRITE ON A STORAGE DEVICE - A method of performing a data write on a storage device comprises instructing a device driver for the device to perform a write to the storage device, registering the device driver as a transaction participant with a transaction co-ordinator, executing a flashcopy of the storage device, performing the write on the storage device, and performing a two-phase commit between device driver and transaction co-ordinator. Preferably, the method comprises receiving an instruction to perform a rollback, and reversing the data write according to the flashcopy. In a further refinement, a method of scheduling a flashcopy of a storage device comprises receiving an instruction to perform a flashcopy, ascertaining the current transaction in relation to the device, registering the device driver for the device as a transaction participant in the current transaction with a transaction co-ordinator, receiving a transaction complete indication from the co-ordinator, and executing the flashcopy for the device. | 2015-01-29 |
20150033070 | DATA RECOVERY METHOD, DATA RECOVERY DEVICE AND DISTRIBUTED STORAGE SYSTEM - A data recovery method, a data recovery device and a distributed storage system are provided, where the method includes: in a case that a distributed storage system loses data of three nodes, recovering data on a target data storage node of the data on the three nodes according to data of a parity node and a data storage node without data loss; and performing degraded recovery on the remaining lost data according to the recovered data of the target data storage node. According to the embodiments of the present invention, a target data storage node first recovered is determined according to the symmetry of lost data, and the lost data of three nodes is recovered according to parity data and data that is not lost, which can improve the data recovery performance of the distributed storage system in a case that the data of three nodes is lost. | 2015-01-29 |
20150033071 | ROBUST HARDWARE/SOFTWARE ERROR RECOVERY SYSTEM - A method for error detection and recovery is provided in which a host controller and host software collaborate together. The host controller may: detect an error condition, set an error interrupt or register, and/or halt task execution or processing at the host controller. The host software may: detect an error condition as a result of the host controller having set the error interrupt or register; performs error handling, and clears the error condition. The host controller then resumes execution or processing of tasks upon detecting that error condition has been cleared by the host software. | 2015-01-29 |
20150033072 | MONITORING HIERARCHICAL CONTAINER-BASED SOFTWARE SYSTEMS - A computer receives a heartbeat message that includes both program reset information and at least one segment, of the heartbeat message, that is configured to indicate whether or not a first program is functioning correctly. The computer determines if the heartbeat message includes the indication that the first program is functioning correctly. If the computer determines that the heartbeat message indicates that the first program is functioning correctly, then the computer sends a data stream to the first program. | 2015-01-29 |
20150033073 | METHOD AND APPARATUS FOR PROCESSING ERROR EVENT OF MEDICAL DIAGNOSIS DEVICE, AND FOR PROVIDING MEDICAL INFORMATION - A method and an apparatus for processing an error event of a medical diagnosis device is provided that includes detecting an error event at a medical diagnosis system, determining an error correcting mode from among a first mode for restarting a diagnosis process at which the error event occurred, a second mode for informing the error event to components of the medical diagnosis system at which the error event did not occur, and a third mode for stopping operation of the medical diagnosis system, based on information regarding the error event, and processing the error event based on the determined error correcting mode. There is also provided a method for providing medical information that includes receiving medical data, providing a diagnosis process a first region, providing log data at a second region, and providing video data at a third region of the screen image. | 2015-01-29 |
20150033074 | DEADLOCK DETECTION AND RECOVERY IN SAS - Systems and methods herein provide for managing devices through a Serial Attached Small Computer System Interface (SAS) expander. The SAS expander includes a processor adapted to detect deadlock conditions in a SAS environment. In one embodiment, the SAS expander is operable to detect an Open Address Frame associated with a connection request from a source device to a destination device. The Open Address Frame includes a source address and a destination address associated with the source device and the destination device, respectively. The expander receives an arbitration in progress status on a partial pathway that is associated with the connection request. The expander is further operable to modify the Open Address Frame to include a deadlock indicator and forward the modified Open Address Frame on the partial pathway. When the modified Open Address Frame is received, the expander initiates pathway recovery upon determination that the deadlock indicator is valid. | 2015-01-29 |
20150033075 | CACHE DEBUG SYSTEM FOR PROGRAMMABLE CIRCUITS - An integrated circuit may be provided with system-on-chip circuitry including system-on-chip interconnects and a microprocessor unit subsystem. The subsystem may include microprocessor cores that execute instructions stored in memory. Cache may be used to cache data for the microprocessor cores. A memory coherency control unit may be used to maintain memory coherency during operation of the microprocessor unit subsystem. The memory coherency control unit may be coupled to the system-on-chip interconnects by a bus. A command translator may be interposed in the bus. The command translator may have a slave interface that communicates with the interconnects and a master interface that communicates with the memory coherency control unit. The integrated circuit may have programmable circuitry that is programmed to implement a debug master coupled to the interconnects. During debug operations, the command translator may translate commands from the debug master. | 2015-01-29 |
20150033076 | ANOMALY DETECTION SYSTEM, ANOMALY DETECTION METHOD, AND PROGRAM FOR THE SAME - A method is for handling an anomaly in an industrial control system (ICS) connected to a network with a plurality of other ICSs and an anomaly analyzer. An ICS receives status data from its own industrial process, and stores this status data as normal pattern data. The ICS transmits its own status data to one or more other ICSs. The ICS receives an indication from the anomaly analyzer that the ICS is suspected of having an anomaly. The ICS transmits alternate status data based on the normal pattern data stored during non-suspect operation, and stores the status data received from its own industrial process as real status data. In response to receiving from the anomaly analyzer an indication that the ICS is not operating anomalously, the ICS transmits the stored real data, and switches back to transmitting its own status data to one or more other ICSs. | 2015-01-29 |