05th week of 2012 patent applcation highlights part 32 |
Patent application number | Title | Published |
20120026738 | LIGHT-EMITTING APPARATUS AND ILLUMINATION APPARATUS - According to one embodiment, a light-emitting apparatus includes a substrate, an attachment member, and a mechanical fixing component. The substrate has light-emitting elements mounted on one surface side thereof. The attachment member includes a concave portion in which the substrate is arranged with a gap between the substrate and a side circumference of the concave portion. The mechanical fixing component includes a pressure portion that is in contact with the one surface side of the substrate, the mechanical fixing component being configured to hold the substrate in the concave portion of the attachment member by elastic pressing force of the pressure portion acting in a direction from the one surface side toward the other surface side of the substrate. | 2012-02-02 |
20120026739 | ELECTRONIC APPARATUS AND METHOD FOR MANUFACTURING THE SAME - An electronic apparatus includes a cover unit, a touchpad unit and a contact member. The cover unit has a window through which an operation section is exposed and the window has an inwardly inclined peripheral surface as an inclined portion. The touchpad unit is arranged substantially in the window. The contact member is secured on the touchpad unit and is exposed through the window. The contact member has a joining part for the cover unit. The joining part of the contact member forms a contiguous inclined surface together with the inclined portion of the cover unit. | 2012-02-02 |
20120026740 | LIGHTING APPARATUS - A lighting apparatus is broadly disclosed and embodied herein. The lighting apparatus may include a heat sink, a first reflector provided over the heat sink, a light emitting module provided at the first reflector, an enclosure provided over the heat sink to surround the light emitting module, and a second reflector provided over the light emitting module. At least a portion of the light emitted from the light emitting module may be reflected at least in a direction a prescribed angle below a horizontal plane of the light emitting module. | 2012-02-02 |
20120026741 | LIQUID CRYSTAL POLYESTER COMPOSITION, REFLECTIVE PLATE AND LIGHT-EMITTING DEVICE - The present invention provides a composition comprising a liquid crystal polyester, a white pigment and a glass fiber bundle obtained by bundling glass fibers using a sizing agent comprising a polyurethane having a polyester polyol unit and at least one of an aliphatic diisocyanate unit or an alicyclic diisocyanate unit, wherein the polyester polyol unit is a polyol unit having an aliphatic polyhydric alcohol unit and at least one of an aliphatic polybasic acid unit or an alicyclic polybasic acid unit. The liquid crystal polyester composition can provide a reflective plate having a high reflectivity. | 2012-02-02 |
20120026742 | Light Guide Plate and Manufacturing Method Thereof - The present invention provides a light guide plate and a manufacturing method thereof. The manufacturing method firstly forms a plurality of spherical recesses arranged at intervals on a light-emitting surface of a light guide plate body when the light guide plate body is formed by pressing, and then applies a diffuser particle with corresponding shape on a surface of each of the spherical recesses, so as to complete the manufacture of the light guide plate. When being mounted in a backlight module, the light guide plate benefits the backlight module of reducing the use of diffuser films, so as to reduce the thickness and weight of the backlight module. | 2012-02-02 |
20120026743 | LIGHTING APPARATUS - A lighting apparatus includes a metal mounting fixed to a needed place such as a ceiling or a wall, rod-shaped holding metal fixtures, and a lighting apparatus body constituted by a chassis to which one end portion of each holding metal fixture is loosely fitted, a board which is fixed to the chassis and on which light emitting diodes are mounted as luminous elements, a reflecting panel, a cover (diffusing panel) that covers the light emitting diodes, and so on. By inserting the lock section of the other end portion of each holding metal fixture into an insertion hole and then locking each holding metal fixture on the metal mounting, the lighting apparatus body is held in a state of being separated from the metal mounting. | 2012-02-02 |
20120026744 | MOUNTING ASSEMBLY - A luminaire mounting assembly comprises a mounting bracket having at least one keyed aperture, the mounting bracket having one of a slider assembly and at least one tab, a fixture housing having the other of a slider assembly and the at least one tab, the slider assembly movable between a first fixture position and a second fixture position, the slider assembly having a fixed element, a plunger movable relative to the fixed element, the plunger biased toward a first plunger position and engaging the at least one tab, the plunger movable to a second plunger position to pass the at least one tab. | 2012-02-02 |
20120026745 | LAMP DEVICE, COOLING SYSTEM AND COOLING MODULE - A lamp device includes a lamp housing, a light emitting component serving as a heat source and a cooling system. The cooling system includes a liquid coolant, a cooling module, a vapor conduit, a coolant conduit, and a condenser. The cooling module includes a casing and a converting component. The casing has a thermal-transmittance wall having an interior surface and an exterior surface, a coolant inlet and a vapor outlet. The converting component divides an interior of the casing into a coolant chamber and a vaporization chamber. The converting component is formed with a plurality of orifices for permitting the liquid coolant in the coolant chamber to be ejected therethrough to form plumes of the liquid coolant that travel toward the interior surface of the thermal-transmittance wall and that exchange heat with the thermal-transmittance wall to result in coolant vapor flowing out of the vaporization chamber via the vapor outlet. | 2012-02-02 |
20120026746 | LIGHTING ASSEMBLY AND AUTOMOTIVE HEADLAMP ARRANGEMENT - The invention describes a lighting assembly ( | 2012-02-02 |
20120026747 | LIGHT SOURCE UNIT OF SEMICONDUCTOR-TYPE LIGHT SOURCE OF VEHICLE LIGHTING DEVICE AND VEHICLE LIGHTING DEVICE - A capacity of a sealing member is reduced to its required minimum. The present invention provides: a board | 2012-02-02 |
20120026748 | LIGHT EMITTING DEVICE AND LUMINAIRE - The present invention relates to a light emitting device | 2012-02-02 |
20120026749 | LOW STRAY LIGHT BEAM DUMP WITH FIBER DELIVERY - The present invention is directed to a beam dump which is configured for not increasing a temperature of a laser with which it may be implemented. The beam dump may include an opaque enclosure which is configured for receiving light (ex.—initial light) from a light source (ex.—a frequency-converted laser), said light being delivered through an aperture of the enclosure via one or more connected optical fibers. The received light may be scattered within the enclosure. However, the beam dump is configured for minimizing the amount of light which is back scattered light into the fiber(s). For instance, the amount of back scattered light may be less than 1/1000 of the initial light. Further, the beam dump may be configured for minimizing photocontamination which may be caused when the light contacts interior surfaces of the enclosure. Still further, the beam dump may be a small size, low cost structure. | 2012-02-02 |
20120026750 | CONTROLLED FLARING LIGHT TRANSMISSION DEVICE - Various exemplary embodiments relate to a light transmission device for transmitting light from at least one light source to an illuminated surface. The device may include at least one light entrance surface that allows entrance of light from the at least one light source; a light emitting surface with an area greater than the total area of the at least one light entrance surface; at least one light pipe portion extending from the at least one light entrance surface toward the illuminated surface wherein the light pipe portion internally reflects the light toward the illuminated surface; and a flared diffusion portion between the at least one light pipe portion and the light emitting surface wherein the diffusion portion internally reflects the light towards the light emitting surface. The device may be a solid piece of plastic. The light pipe portions may be curved to bend light toward the illuminated surface. | 2012-02-02 |
20120026751 | LIGHT GUIDE UNIT AND LIGHT SOURCE MODULE - A light guide unit including a light guide plate and a scattering reflective unit is provided. The light guide plate has a first surface, a second surface opposite to the first surface, and a light incident surface connecting the first surface and the second surface. The light incident surface includes a first recess and a second recess arranged in a sequence from the first surface to the second surface. An average radius of curvature of the first recess is less than an average radius of curvature of the second recess. The scattering reflective unit is disposed on the second surface. A light source module is also provided. | 2012-02-02 |
20120026752 | BACKLIGHT MODULE AND ELECTRONIC DEVICE USING THE SAME - A backlight module includes a support frame, two light sources, and a light guide film. The support frame includes a support portion and a fixing portion connected to an edge of the support portion, and the support frame defines at least one receiving groove. Each light source includes a light output surface and is received in the support frame. The light guide film includes two light input surfaces at the opposite ends thereof and two light guide portions connected with the light input surfaces. The light input surfaces of the light guide film face the light output surfaces of the light sources. | 2012-02-02 |
20120026753 | ILLUMINATION DEVICE AND DISPLAY APPARATUS USING THE SAME - An illumination device for guiding light rays from a light-emitting diode (LED) module toward a light guide plate to thereby perform planar illumination is disclosed. The illumination device includes a printed circuit board with a plurality of LED elements attached thereto. The circuit board has two or more positioning bosses which are attached in the same process as that of the LEDs. While letting the positioning bosses be tightly coupled with corresponding holes provided in the light guide plate, the circuit board and the light guide plate are adhered and fixed together, thereby accurately retaining the positional relationship between the LEDs and the light guide plate. | 2012-02-02 |
20120026754 | DOUBLE PHASE-SHIFTING FULL-BRIDGE DC-TO-DC CONVERTER - A DC-to-DC converter has a leading full-bridge inverter and a lagging full-bridge inverter for receiving a DC input and producing respective AC output voltages. A full-wave rectifier circuit rectifies the AC output voltages to produce a rectified output voltage, which is filtered by a current doubling output filter circuit to produce a DC output voltage. A master phase-shift controller and a slave phase-shift controller respectively provide first and second control signals to the leading full-bridge inverter and third and fourth control signals to the lagging full-bridge inverter to regulate the DC output voltage by changing a phase of the second and fourth control signals with respect to the first and third control signals below a predetermined DC output voltage, and by changing a phase of the third and fourth control signals with respect to the first and second control signals above the predetermined threshold. | 2012-02-02 |
20120026755 | RESONANT CONVERTER SYSTEM HAVING SYNCHRONOUS CONTROL CIRCUIT AND CONTROLLING METHOD THEREOF - The configurations of a resonant converter system and a controlling method thereof are provided. The proposed resonant converter system includes a resonant converter receiving an input voltage for outputting an output voltage, a rectifying device having a first rectifying switch and a synchronous rectification control circuit coupled to the resonant converter and including a signal generation apparatus generating a weighted turn-off signal to turn off the first rectifying switch at a zero crossing point of a first current flowing through the first rectifying switch. | 2012-02-02 |
20120026756 | CONTROL CIRCUIT, CONTROL METHOD, AND POWER SUPPLY DEVICE - A control circuit, a control method, and a power supply device are provided. The control circuit includes an obtaining sub-circuit, adapted to obtain a voltage signal from a reverse surge current when the reverse surge current appears on a primary side of a switch power circuit of a synchronous rectification circuit; a maintaining sub-circuit, adapted to continuously output a first control signal in a preset first time period when the voltage signal is greater than a preset first voltage threshold; and a control sub-circuit, adapted to control and switch off switch tubes of the secondary side of the switch power circuit of the synchronous rectification circuit according to the first control signal. Thus, a reverse current surge of the switch power circuit of the synchronous rectification circuit can be effectively suppressed, and the safety of a switch power supply of the synchronous rectification circuit can be effectively protected. | 2012-02-02 |
20120026757 | CONVERTER CONTROLLER - Provided is a converter controller capable of preventing destruction of an element such as an auxiliary switch by preventing operation interference between auxiliary circuits of respective phases in a multiphase soft switching converter. A duty threshold input unit receives, as an input, an obtained acceptable duty deviation value. A duty deviation computation unit judges whether or not the duty deviation between the phases does not exceed an acceptable duty deviation value. When the duty deviation between the phases exceeds the acceptable duty deviation value, the duty deviation computation unit corrects an adjusted U-phase duty ratio, adjusted V-phase duty ratio and adjusted W-phase duty ratio under the PID control rule, and outputs the resultant duty ratios to an FC converter control circuit. On the other hand, when the duty deviation between the phases does not exceed the acceptable duty deviation value, the duty deviation computation unit does not correct the adjusted U-phase duty ratio, adjusted V-phase duty ratio and adjusted W-phase duty ratio and outputs them to the FC converter control circuit. | 2012-02-02 |
20120026758 | APPARATUS AND METHOD FOR CONTROLLING SWITCH OF FLYBACK CONVERTER FOR SOLAR GENERATING SYSTEM - There is provided an apparatus and method for controlling a switch of a flyback converter for a solar generating system. The apparatus for controlling a switch of a flyback converter for a solar generating system includes: an MPPT controller generating a current command value for a maximum power point tracker of a solar cell module, based on input voltage, input current, and output voltage of the flyback converter; a current controller generating a current control signal for tracking the current command value; an output current command value generator generating the phase and magnitude command value of the output current, based on the phase of the output voltage and the current control signal; and a switch controller controlling the main switch of the flyback converter, based on the phase and magnitude command value of the output current, thereby simplifying a circuit while solving disadvantages of a discontinuous conduction mode and a boundary conduction mode. | 2012-02-02 |
20120026759 | ULTRA LOW STANDBY CONSUMPTION IN A HIGH POWER POWER CONVERTER - A power converter with low power consumption during a standby operating condition. An example power controller includes a main converter coupled to a dc input of the power converter to control a transfer of energy from the dc input of the power converter to a main output of the power converter. A standby converter is also included and is coupled to the dc input of the power converter to control a transfer of energy from the dc input of the power converter to a standby output of the power converter during a standby operating condition of the power converter. A standby circuit is also included and is coupled to the dc input of the power converter and coupled to the main converter. The standby circuit decouples the main converter from the dc input of the power converter during the standby operating condition of the power converter. | 2012-02-02 |
20120026760 | DC VOLTAGE COMPENSATION IN A MULTI-TERMINAL HVDC POWER TRANSMISSION NETWORK - In a multi-terminal HVDC power transmission network comprising at least three HVDC converter stations interconnected by at least two transmission lines, where at least one of the transmission lines is a long line, an active voltage source device is series connected to one of the transmission lines, which maintains the DC voltage of the transmission lines of the network to be within a predefined voltage range by injecting an additional DC voltage in series with the one transmission line. | 2012-02-02 |
20120026761 | ADAPTIVE CURRENT LIMITER AND DIMMER SYSTEM INCLUDING THE SAME - In an embodiment, an adaptive current limiter includes a sense element, a current pass element, and a controller. The sense element includes a first sense terminal coupled to a power supply terminal and a second sense terminal. The sense element generates a sense voltage in response to a feedback current. The current pass element includes a first terminal for receiving the feedback current, a second terminal coupled to the second sense terminal, and a control terminal. The controller is coupled to the sense element and to the control terminal for adjusting the feedback current conducted by the current pass element based on the sense voltage and a time-varying voltage signal. | 2012-02-02 |
20120026762 | Pre-Bias Control for Switched Mode Power Supplies - An embodiment of the invention provides a method of reducing a drop in voltage on a pre-biased output of a DC-DC step-down switching converter. A high side switch is activated to conduct a first current to the pre-biased output. After the high side switch is activated, a low side switch is activated to draw a second current from the pre-biased output such that the magnitude of the first current is greater than the magnitude of the second current for at least a portion of a time period T | 2012-02-02 |
20120026763 | Energy-Efficient Standby Mode In A Switching Power Supply - A switching power supply includes power factor correction circuitry and a standby output converter. One or more loads may be coupled to one or more outputs of the switching power supply. The switching power supply is configured to disable the power factor correction circuitry under some load conditions and to enable the power factor correction circuitry under other load conditions. As a consequence, power that would have been drawn by the power factor correction circuitry is conserved when the power factor correction circuitry is disabled. | 2012-02-02 |
20120026764 | CONTROL SYSTEM FOR HIGH-EFFICIENCY OPERATION IN PARALLEL INVERTER INSTALLATIONS - A control system for parallel connected inverter legs energized by a power source and configured for servicing a load is disclosed. The invention facilitates the number of running inverter legs to adaptively react to changes in the load by dynamically switching various inverter legs “on” or “off” in response to variations in load demand, while continuing magnetization of an output transformer connected with an “off” inverter leg via a back-feed from another output transformer of an “on” inverter leg, greatly improving the dynamic response to load changes. This design enables a fast reaction to load changes with “off” inverter legs transitioning to on-line operation instantaneously. | 2012-02-02 |
20120026765 | CONTROL DEVICE OF A SWITCHING POWER SUPPLY - A control device controls a switching converter having an input alternating supply voltage and a regulated direct voltage at the output terminal. The converter comprises a switch and the control device is adapted to control the on time period and the off time period of said switch for each cycle. The control device has a first input signal representative of the current flowing through at least one element of the converter and comprises a zero crossing detector adapted to detect at least one pair of first and second zero crossings of said first signal for each switching cycle, said second zero crossing immediately following the first zero crossing and occurring in opposite direction with respect to the first zero crossing. The control device comprises a synchronizer adapted to synchronize the start of the on period with each second zero crossing of said first signal. | 2012-02-02 |
20120026766 | CONTROL DEVICE OF A SWITCHING POWER SUPPLY - A control device controls a switching converter that converts an alternating supply voltage to a regulated voltage and comprises a switch connected to an inductor. The control device is adapted to control the on period and the off period of said switch for each cycle. The control device comprises a ramp generator adapted to generate a ramp voltage, a comparator adapted to determine the final instant of the on period of the switch by crossing the ramp voltage with a first voltage. The control device has a first signal representing a current through the inductor and a second signal representative of the current flowing through at least one element of the converter. The control device is adapted to control the closing of said switch according to said first signal and comprises a synchronizer adapted to synchronize the start of the ramp voltage with the zero crossing of said second signal. | 2012-02-02 |
20120026767 | POWER CONVERSION DEVICE - A power conversion device connected with a three-phase power system through a transformer, including unit converters cascade-connected so that reactors are unnecessary, and volume and weight are reduced. The secondary winding of the transformer is an open winding having six terminals. A first converter group, includes a circuit which has three converter arms, which are star-connected, connected to three of the terminals of the secondary winding. A second converter group, having three different converter arms which are star-connected, is connected to three other terminals of the secondary winding. A neutral point (the point where the star connection is made) of the first converter group, and a neutral point of the second converter group are made to be the output terminals of the power conversion device. | 2012-02-02 |
20120026768 | FACILITY POWER SUPPLY WITH POWER-FACTOR CORRECTION - An embodiment of a power supply includes an input node, a converter stage, and an outlet. The input node is operable to receive an input AC signal having peak portions and non-peak portions. The converter stage is operable to generate a DC power signal from the input AC signal and to cause a first current to be drawn from the input node during at least the non-peak portions of the input AC signal. And the outlet is operable to carry the DC power signal. For example, such a power supply may be installed in a facility such as a residence, office building, or manufacturing plant, or the facility's existing power supply may be retrofitted, to provide one or more power outlets that each carry a respective power-factor-corrected (PFC) DC voltage. Because the outlet voltages are PFC voltages, the amount of wasted power dissipated in the facility power lines/wiring and in the main power lines from the power company may be significantly reduced, without requiring each piece of equipment (e.g., an appliance, machinery) that is wired/plugged into the outlets to have an onboard PFC. This savings in wasted power may provide a significant cost savings to both the facility owner (e.g., lower electric bill) and the power company (e.g., lower power-generation and grid costs), and the ability to use equipment lacking onboard PFCs may reduce the purchase price of the equipment. | 2012-02-02 |
20120026769 | PHOTOVOLTAIC INVERTER SYSTEM AND METHOD OF STARTING SAME AT HIGH OPEN-CIRCUIT VOLTAGE - A power inverter system includes a DC to AC inverter configured to convert DC voltage from a DC power source to AC voltage. A DC link couples the DC power source and the inverter. An inverter pre-charger operates to pre-charge the inverter to achieve a desired DC link voltage prior to connecting the power inverter system to an AC power grid. A phased lock loop synchronizes the pre-charged inverter to the AC power grid prior to connecting the power inverter system to the AC power grid. The pre-charged inverter regulates the DC link voltage to about the minimum voltage level that allows control of AC grid currents via the inverter subsequent to connecting the power inverter system to the AC grid. The inverter operates in a maximum power point tracking control mode only subsequent to a first voltage transient caused by connecting the DC power source to energize the power inverter system. | 2012-02-02 |
20120026770 | POWER CONVERTER WITH LINEAR DISTRIBUTION OF HEAT SOURCES - A power converter design is disclosed with a novel approach to thermal management which enhances the performance and significantly reduces the cost of the converter compared to prior art power converters. The invention minimizes the heating of one power component by another within the power converter and therefore enables the power converter to work at higher power levels. Essentially, the power converter uses a heatsink having a high length to width ratio, a linear array of power components thermally coupled to the heatsink parallel to the long axis of the heatsink and a heat removal system which produces the highest cross sectional thermal flux perpendicular to said long axis. In addition, a number of ancillary thermal management techniques are used to significantly enhance the value of this basic approach. A specific circuit design for the power converter is not disclosed or discussed as the invention can be applied to any number of power converter electrical topologies. What is addressed is the specific thermal management of the three primary component groups found in any power converter; semiconductor devices, magnetic components and capacitors. The invention uses specific geometries and power component arrangements as well as strategic use of advanced thermal materials. | 2012-02-02 |
20120026771 | VEHICLE-USE POWER SUPPLY CONTROL APPARATUS AND CONTROL APPARATUS FOR CONTROLLING ELECTRIC ROTATING MACHINE MOUNTED ON VEHICLE AS MAIN ENGINE - The vehicle-use power supply control apparatus is for controlling transmission of electric power between a vehicle-mounted power supply apparatus including switching elements turned on and off in accordance with manipulation signals and an external power supply located outside the vehicle. The vehicle-use power supply control apparatus includes a control section to output an electric power transmission command signal depending on an electric power transmission request signal received from an external device, and a manipulation signal generating section to generate the manipulation signals based on the electric power transmission command signal received from the control section. The control section is configured to operate in order that noise sound generated due to switching operation of the vehicle-mounted power supply apparatus is within an audio frequency range. | 2012-02-02 |
20120026772 | MEMORY MODULE AND LAYOUT METHOD THEREFOR - The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector. | 2012-02-02 |
20120026773 | SEMICONDUCTOR MEMORY APPARATUS HAVING SENSE AMPLIFIER - Disclosed is a semiconductor memory apparatus comprising an upper mat and a lower mat with a sense amplifier array region in between, where the sense amplifier array region includes a plurality of sense amplifiers. There is also a plurality of bit lines configured to extend toward the sense amplifier array region from the upper mat, and a plurality of complementary bit lines configured to extend toward the sense amplifier array region from the lower mat. Bit lines of the upper mat and complementary bit lines of the lower mat are configured to be alternately disposed at a predetermined interval in the sense amplifier array region, and the sense amplifier is configured to be formed between a bit line and a corresponding complementary bit line. | 2012-02-02 |
20120026774 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME - An object is to provide a semiconductor device in which lower power consumption is realized by lowering voltage for data writing without increase in types of power supply potentials. Another object is to provide a semiconductor device in which threshold voltage drop of a selection transistor is suppressed without increase in types of power supply potentials for data writing. A diode-connected transistor is electrically connected in series with a word line electrically connected to a gate of an n-channel selection transistor. A capacitor is provided between the word line and a bit line electrically connected to one of a source and a drain of the selection transistor; alternatively, the capacitance between the bit line and the word line is used. In data writing, the timing of selecting the word line is earlier than the timing of selecting the bit line. | 2012-02-02 |
20120026775 | METHOD OF OPERATING SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a method of operating a semiconductor memory device is disclosed. The method can include storing read-only data in at least one selected from a memory cell of an uppermost layer and a memory cell of a lowermost layer of a plurality of memory cells connected in series via a channel body. The channel body extends upward from a substrate to intersect a plurality of electrode layers stacked on the substrate. The method can include prohibiting a data erase operation of the read-only memory cell having the read-only data stored in the read-only memory cell. | 2012-02-02 |
20120026776 | MEMORY RESISTOR HAVING PLURAL DIFFERENT ACTIVE MATERIALS - Methods and means related to memory resistors are provided. A memristor includes at least two different active materials disposed between a pair of electrodes. The active materials are selected to exhibit respective and opposite changes in electrical resistance in response to changes in oxygen ion content. The active materials are subject to oxygen ion reconfiguration under the influence of an applied electric field. An electrical resistance of the memristor is thus adjustable by way of applied programming voltages and is non-volatile between programming events. | 2012-02-02 |
20120026777 | Variable-resistance memory device - Disclosed herein is a variable-resistance memory device including: a memory-cell array employing a plurality of memory cells each including a storage element having a resistance varying in accordance with the direction of a voltage applied to the storage element and including an access transistor connected in series to the storage element between a bit line and a source line; and a voltage supplying circuit for setting a read voltage used for reading out the resistance of the storage element on a selected bit line connected to the memory cell serving as a read object in an operation to supply the read voltage to the selected bit line. | 2012-02-02 |
20120026778 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor memory device includes: a memory cell array including multiple first lines, multiple second lines crossing the first lines, and memory cells arranged at intersections between the first lines and the second lines and including variable resistive elements; and a control circuit which controls resistance values of the variable resistive elements in a way that a cell voltage is applied to the memory cell arranged at an intersection between a selected first line and a selected second line by applying first and second voltages to the selected first and second lines, respectively. The control circuit applies a voltage gradually raised or lowered from a first initial voltage as the first voltage to the selected first line, and a pulsing voltage as the second voltage to the selected second line. The second voltage includes a voltage pulse which is raised from a second initial voltage to turn the memory cell into a non-selected state to a voltage to turn the memory cell into a selected state, is kept at the raised voltage to thereby cause a cell current to flow into the memory cell, and is lowered to the second initial voltage when the cell current that increases while the voltage of the memory cell is rising with a change in the first voltage reaches a predetermined compliance current. | 2012-02-02 |
20120026779 | NONVOLATILE MEMORIES AND RECONFIGURABLE CIRCUITS - A nonvolatile memory according to an embodiment includes at least one memory cell including: a variable resistance memory comprising one end connected to a first terminal, and the other end connected to a second terminal, a drive voltage being applied to the first terminal; and a diode comprising a cathode connected to the second terminal, and an anode connected to a third terminal, a ground potential being applied to the third terminal. An output of the memory cell is output from the second terminal, the output of the memory cell depends on a resistance state of the variable resistance memory. | 2012-02-02 |
20120026780 | Conductive Metal Oxide Structures In Non Volatile Re Writable Memory Devices - A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s). | 2012-02-02 |
20120026781 | RESISTIVE MEMORY AND METHOD - A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area. | 2012-02-02 |
20120026782 | SEMICONDUCTOR MEMORY DEVICE - In two inverters included in a latch in a memory cell, the source or drain of a PMOS load transistor connected to a memory node is cut off, and the source or drain of an NMOS drive transistor connected to another memory node is cut off, whereby internal data is fixed or permanently stored in the memory cell while ensuring a resistance to damage to the gate of the transistor and without impairing the regularity of the layout. | 2012-02-02 |
20120026783 | Latching Circuit - A non-volatile latch circuit includes a pair of cross-coupled inverters, a pair of resistance-based memory elements, and write circuitry configured to write data to the pair of resistance-based memory elements. The pair of resistance-based memory elements is isolated from the pair of cross-coupled inverters during a latching operation. A sensing circuit includes a first current path that includes a first resistance-based memory element and an output of the sensing circuit. The sensing circuit includes a second current path to reduce current flow through the first resistance-based memory element at a first operating point of the sensing circuit. The sensing circuit may also include an n-type metal-oxide-semiconductor (NMOS) transistor to provide a step down supply voltage to the first current path. | 2012-02-02 |
20120026784 | RANDOM NUMBER GENERATOR - According to an aspect of embodiments, there is provided a random number generating circuit including at least one magnetic tunnel junction (MTJ) element and a control circuit. The MTJ element comes into a high resistance state corresponding to a first logical value and also comes into a low resistance state corresponding to a second logical value different from the first logical value. The control circuit supplies the MTJ element with a first current for stochastically reversing the MTJ element from the high resistance state to the low resistance state when the MTJ element is in the high resistance state, and supplies the MTJ element with a second current for stochastically reversing the MTJ element from the low resistance state to the high resistance state when the MTJ element is in the low resistance state. | 2012-02-02 |
20120026785 | Non-Volatile Magnetic Memory Element with Graded Layer - A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound. | 2012-02-02 |
20120026786 | WRITE OPERATION FOR PHASE CHANGE MEMORY - Embodiments disclosed herein may relate to controlling a discharge of a capacitive element coupled to a phase change memory cell to produce a specified state in the phase change memory cell. | 2012-02-02 |
20120026787 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME - A transistor includes first and second control gates, and a storage gate. The storage gate is made to be a conductor, supplied with a specific potential, and then made to be an insulator, thereby holding the potential. Data is written by making the storage gate a conductor, supplying a potential of data to be stored, and making the storage gate an insulator. Data is read by making the storage gate an insulator, supplying a potential to a read signal line connected to one of a source and a drain of the transistor, supplying a potential for reading data to the first control gate, and then detecting a potential of a bit line connected to the other of the source and the drain. | 2012-02-02 |
20120026788 | DISTORTION ESTIMATION AND CANCELLATION IN MEMORY DEVICES - A method for operating a memory ( | 2012-02-02 |
20120026789 | DISTORTION ESTIMATION AND CANCELLATION IN MEMORY DEVICES - A method for operating a memory ( | 2012-02-02 |
20120026790 | Non-volatile memory device including block state confirmation cell and method of operating the same - Provided are a semiconductor device having a block state confirmation cell that may store information indicating the number of data bits written to a plurality of memory cells, a method of reading memory data based on the number of the data bits written, and/or a memory programming method of storing the information indicating the number of the data bits written. The semiconductor device may include one or more memory blocks and a controller. Each of the memory blocks may include a plurality of memory cells each storing data, and a block state confirmation cell storing information indicating the number of data bits written to the memory cells. The controller may read the data bits from the memory blocks based on the number of data bits, which is indicated in the information in the block state confirmation cell. | 2012-02-02 |
20120026791 | Method for Non-Volatile Memory With Background Data Latch Caching During Read Operations - Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with a read operation. A read caching scheme is implemented for memory cells where more than one bit is sensed together, such as sensing all of the n bits of each memory cell of a physical page together. The n-bit physical page of memory cells sensed correspond to n logical binary pages, one for each of the n-bits. Each of the binary logical pages is being output in each cycle, while the multi-bit sensing of the physical page is performed every nth cycles. | 2012-02-02 |
20120026792 | ERASE CYCLE COUNTER USAGE IN A MEMORY DEVICE - Memory devices to facilitate adjustment of program voltages applied during a program operation based upon erase operation cycle counter values stored in the memory device. In one such embodiment, an erase cycle counter is maintained for each block of a memory device and is stored in the associated block of memory. Programming voltage levels utilized during program operations of memory cells are determined, at least in part, based upon the value of the erase cycle counter stored in a memory block undergoing a programming operation, for example. | 2012-02-02 |
20120026793 | Nonvolatile Memory Cell With Extended Well - One embodiment relates to a memory device. The memory device includes a capacitor having a first capacitor plate and a second capacitor plate, wherein the first and second capacitor plates are separated by an insulating layer and are formed over a first portion of a semiconductor substrate. The memory device also includes a transistor having a source region, a drain region, and a gate region, where the gate region is coupled to the second capacitor plate. The transistor is formed over a second portion of the semiconductor substrate. A well region is disposed in the first and second portions of the semiconductor substrate and has a doping-type that is opposite a doping-type of the semiconductor substrate. Other embodiments are also disclosed. | 2012-02-02 |
20120026794 | Method and apparatus of operating a non-volatile DRAM - A non-volatile DRAM cell includes a pass-gate transistor and a cell capacitor. A read operation of the non-volatile cell begins by negatively charging the cell capacitor. A cell capacitor of an associated dummy non-volatile DRAM cell is fully discharged. The pass-gate transistor is activated and if the pass-gate transistor is programmed it does not turn on and if it is erased, it turns on. Charge is shared on the complementary pair of precharged bit lines connected to the non-volatile DRAM cell and its associated Dummy non-volatile DRAM cell. A sense amplifier detects the difference in the data state stored in the pass-gate to transistor. The program and erase of the non-volatile DRAM cell is accomplished by charge injection from the associated bit line of the non-volatile DRAM cell. | 2012-02-02 |
20120026795 | Electronic Apparatus and Data Reading Method - In one embodiment, there is provided an electronic apparatus. The apparatus includes: a storage device including a plurality of blocks that are units of data erasure. Each of the blocks includes a plurality of pages that are units of data reading or writing. Each of the pages includes: a data area storing a data; and a redundant area storing order information indicating an order of the data stored in the data area. The apparatus further includes: a reading module configured to read the data stored in the data area of each of the pages, in order from a last page to a head page, wherein, in reading each of the pages, the reading module is configured to read the order information stored in the redundant area prior to reading the data stored in the data area; a determining module configured to determine whether currently-read order information coincides with already-read order information; and a reading controller configured to control the reading module such that a data is not read from a data area of a page storing the currently-read order information, when the determining module determines that the currently-read order information coincides with the already-read order information. | 2012-02-02 |
20120026796 | STORAGE DEVICE AND METHOD FOR OPERATING THE SAME - A storage device includes a control unit, a first voltage supply unit for supplying a first working voltage to the control unit, N memory units, a second voltage supply unit for supplying a second working voltage to each memory unit, a logic gate, a first voltage detecting unit and a second voltage detecting unit. Once the first voltage detecting unit detects that the first working voltage of the control unit is abnormal, the logic gate outputs a first write protect signal to notify the control unit and control the memory units to enter a write protect mode. Once the second voltage detecting unit detects that the second working voltage of one or more memory units is abnormal, the logic gate outputs a second write protect signal to notify the control unit and control the one or more memory units to enter the write protect mode. | 2012-02-02 |
20120026797 | NonVolatile Memory Devices, Methods Of Programming The Same, And Memory Systems Including The Same - A nonvolatile memory device including a bit line connected to a cell string, a page buffer connected to the bit line, the page buffer is configured to output a target bit line forcing voltage level to the bit line during a programming operation, and a bit line forcing voltage clamp circuit connected between the bit line and the page buffer, and the bit line forcing voltage clamp circuit is configured to adjust the target bit line forcing voltage level to the bit line. | 2012-02-02 |
20120026798 | SEMICONDUCTOR NONVOLATILE MEMORY DEVICE - An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. | 2012-02-02 |
20120026799 | NON-VOLATILE MEMORY DEVICE HAVING REFERENCE CELLS, AND RELATED METHOD OF SETTING REFERENCE CURRENT - A method of setting a reference current of a nonvolatile memory device comprises measuring a noise characteristic of each of multiple reference cells, and selecting at least one of the reference cells as a reference cell for generating a reference current according to the measured noise characteristics. | 2012-02-02 |
20120026800 | SEMICONDUCTOR APPARATUS AND METHOD FOR TRANSFERRING CONTROL VOLTAGE - A semiconductor apparatus includes a control voltage transfer unit configured to transfer a control voltage transmitted through first transmission lines, to second transmission lines in response to a select signal transmitted through a select signal transmission line; a select signal driving unit configured to drive the select signal to the select signal transmission line; and a voltage boosting control unit configured to float the select signal transmission line when a voltage level of the select signal transmission line increase to or above a target level. | 2012-02-02 |
20120026801 | SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR DISCHARGING WORDLINE THEREOF - Various embodiments of a semiconductor apparatus having a discharge technology are disclosed. In one exemplary embodiment, the semiconductor apparatus may include a plurality of lines in which a selected line is driven by a first control voltage and an unselected line is driven by a second control voltage with a level lower than the first control voltage. The apparatus may also include a discharge control unit configured to form a discharge current path between a discharge node of the selected line and a common discharge node of the unselected line and induce a predetermined voltage difference between the discharge node and the common discharge node; and a common discharge unit configured to discharge current flowing through the discharge current path. | 2012-02-02 |
20120026802 | MANAGED HYBRID MEMORY WITH ADAPTIVE POWER SUPPLY - Subject matter disclosed herein relates to a memory device, and more particularly to a managed hybrid memory that includes a power supply. | 2012-02-02 |
20120026803 | DATA OUTPUT CIRCUIT AND METHOD - A data output circuit includes a strobe signal controlling block configured to generate a first delayed strobe signal by delaying a first strobe signal by a certain delay amount, an input/output sense amplifying block configured to amplify first parallel data signals to generate second parallel data signals having the same number of bits as that of the first parallel data signals in response to the first strobe signal and the first delayed strobe signal, a storing block configured to latch the second parallel data signals in response to a second strobe signal and a second delayed strobe signal, and a parallel-to-serial converting block configured to sequentially output the second parallel data signals latched in the storing block, wherein the first strobe signal is used to generate a data signal that is outputted first among the second parallel data signals. | 2012-02-02 |
20120026804 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of memory layers arranged in multilayer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections of the first lines and the second lines; a pulse generator operative to generate pulses required for data access to the memory cell; and a control means operative to control the pulse generator such that the pulse output from the pulse generator has energy in accordance with the memory layer to which the access target memory cell belongs. | 2012-02-02 |
20120026805 | SRAM BITCELL DATA RETENTION CONTROL FOR LEAKAGE OPTIMIZATION - An integrated circuit includes a static random access memory (SRAM) array coupled to a first voltage supply node and a second voltage supply node. The first and second voltage supply nodes provide a retention voltage across the SRAM array. A current limiter is disposed between the SRAM array and the first voltage supply node, and a voltage regulator is coupled in parallel with the current limiter between the SRAM array and the first voltage supply node. The voltage regulator is configured to maintain the retention voltage across the SRAM array above a predetermined level. | 2012-02-02 |
20120026806 | DATA INPUT CIRCUIT - A data input circuit includes a valid strobe signal generation circuit and a data strobe signal counter. The valid strobe signal generation circuit is configured to remove a pulse of an internal strobe signal generated and generate a valid strobe signal. The pulse may have been generated during a preamble period. The data strobe signal counter is configured to count the valid strobe signal according to burst length information and generate a write latch signal for aligning data at a time of a write operation. | 2012-02-02 |
20120026807 | SEMICONDUCTOR MEMORY CHIP AND INTEGRATED CIRCUIT - A semiconductor memory chip includes: a driving voltage reception unit configured to receive a power supply voltage and a ground voltage; a first data driving unit configured to be supplied with the power supply voltage and the ground voltage, and drive first data to output the driven first data through a first data line; a second data driving unit configured to be supplied with the power supply voltage and the ground voltage, and drive second data to output the driven second data through a second data line; and a MOS transistor coupled between the first data line and the second data line. | 2012-02-02 |
20120026808 | Integrated Circuit With Low Power SRAM - An integrated circuit containing a SRAM memory with SRAM bits optimized to have a lower minimum read voltage than the minimum write voltage. A method for reading a SRAM memory bit using a read voltage that is lower than the write voltage. | 2012-02-02 |
20120026809 | MULTI-BIT TEST CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A multi-bit test circuit for a semiconductor memory is configured to cause an active command to activate active signals. At least two active signals are respectively inputted to a plurality of banks at different timings in a multi-bit test mode. | 2012-02-02 |
20120026810 | SEMICONDUCTOR MEMORY DEVICE AND ANTIFUSE PROGRAMMING METHOD - An antifuse comprised of an NMOS transistor or an NMOS capacitor includes a first terminal coupled to a gate electrode, a second terminal coupled to a diffusion layer, and a gate insulating film interposed between the gate electrode and the diffusion layer. A programming circuit includes a first programming circuit which has first current drive capability and which performs first programming operation and a second programming circuit which has second current drive capability larger than the first current drive capability and which performs second programming operation to follow the first programming operation. In the first programming operation, the first programming circuit breaks down the gate insulating film by applying a first programming voltage between the first terminal and the second terminal. In the second programming operation, the second programming circuit applies a second programming voltage lower than the first programming voltage between the first terminal and the second terminal. | 2012-02-02 |
20120026811 | Integrated semiconductor device - Disclosed herein is an integrated semiconductor device including: a first semiconductor device having a clock generation section, first data storage sections storing input data as transfer data, data output terminals provided, one for each of the first data storage sections, and a clock output terminal adapted to output a transfer clock; and a second semiconductor device having data input terminals which receive the transfer data, a clock input terminal adapted to receive the transfer clock, second data storage sections associated with the data input terminals respectively to store input data, and selection sections associated with the second data storage sections respectively to select either the transfer data or data shifted and output to the associated second data storage section in a first series circuit which is formed by connecting the second data storage sections in series, the selection sections supplying the selected data to the associated second data storage section. | 2012-02-02 |
20120026812 | MEMORY WITH TERMINATION CIRCUIT - Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a first termination circuit that includes a first resistor and a first switch, the first resistor being provided between a first power supply terminal and the signal line, the first switch controlling a current flowing through the first resistor to be turned on and off, and a control circuit that outputs a first control signal to the first termination circuit so that the first switch is turned on when the first transmitter-receiver receives data, the first switch is turned off when the first transmitter-receiver transmits the data, and the first switch is continuously on during a first predetermined period after receiving the data when the first transmitter-receiver further receives another data after receiving the data. | 2012-02-02 |
20120026813 | Semiconductor device changing an active time-out time interval - A device includes a plurality of memory areas each including a plurality of memory cells required to perform refresh of information stored therein by a plurality of sense amplifiers, a first control circuit determining, in connection with one refresh requirement signal at a time, a number of refresh-target memory areas to produce a determined number, a second control circuit controlling, in accordance with the one refresh requirement signal at a time, refresh operation with respect to the refresh-target memory areas, and a third control circuit adjusting, in connection with the refresh operation, an active time-out time interval according to the determined number. The active time-out time interval indicates a time interval from a first time instant when the sense amplifiers are activated to a second time instant when word lines related to the refresh-target memory areas are inactivated. | 2012-02-02 |
20120026814 | CIRCUIT FOR TRANSMITTING AND RECEIVING DATA AND CONTROL METHOD THEREOF - A data receiving circuit includes a delay unit for outputting a delayed control signal by delaying a control signal based on a CAS latency, an output driver for time-dividing parallel data based on the control signal and the delayed control signal to generate divided parallel data, and for writing and transmitting the divided parallel data, and a latch for receiving the parallel data from the output driver and sorting, by combining or dividing, the received parallel data in response to the control signal and the delayed control signal. | 2012-02-02 |
20120026815 | Semiconductor device and method of testing the same - A semiconductor device may include, but is not limited to, first and second memory regions, and first to fifth control circuits. The first and second memory regions are mutually exclusive at the same time. The first control circuit performs a first access to the first memory region. The second control circuit performs a second access to the second memory region. The third control circuit controls activation and deactivation of the first and second control circuits based on a first logic received from a plurality of first external terminals. The fourth control circuit switches between the first and second accesses based on at least a second logic received from a second external terminal. The fifth control circuit controls validation and invalidation of the fourth control circuit. | 2012-02-02 |
20120026816 | DEFECTIVE MEMORY BLOCK IDENTIFICATION IN A MEMORY DEVICE - During manufacture and testing of a memory device, a memory test is performed to determine which, if any, memory blocks are defective. A memory map of the defective blocks is stored in one of the defect-free memory blocks so that it can be read later by a controller during normal operation of the memory device. In one embodiment, the memory test is for a programmability test to determine if the memory block can be programmed. An indication of programmability is stored in each block in a predetermined location. | 2012-02-02 |
20120026817 | Low Cost Testing and Sorting of Integrated Circuits - Methods of testing and sorting integrated circuits in clusters are disclosed. Each cluster has power and data terminals connected to common power and data busses providing a common power supply. Each integrated circuit has a first non-volatile memory storing an activation code and a second programmable non-volatile memory that is capable of storing the activation code. If an integrated circuit passes testing, the activation code stored in the first non-volatile memory is written into the second non-volatile memory. An integrated circuit is independently functional upon separation from the cluster if the codes in the first and second non-volatile memories match. Upon separation, integrated circuits are queried to determine which respond. Each integrated circuit includes logic adapted to determine whether the codes in the first and second non-volatile memories match. If the codes do not match, the logic permanently disables the integrated circuit upon separation from the cluster. | 2012-02-02 |
20120026818 | Split Bit Line Architecture Circuits and Methods for Memory Devices - Apparatus and methods for providing a high density memory array with reduced read access time are disclosed. Multiple split bit lines are arranged along columns of adjacent memory bit cells. A multiple input sense amplifier is coupled to the multiple split bit lines. The loading on the multiple split bit line is reduced, and the corresponding read speed of the memory array is enhanced over the prior art. The sense amplifier and the memory bit cells have a common cell pitch layout height so that no silicon area penalty arises due to the use of the multiple split bit lines and sense amplifiers. Increased memory array efficiency is achieved. | 2012-02-02 |
20120026819 | Fast Cyclic Decoder Circuit for FIFO/LIFO Data Buffer - Embodiments of systems and methods for improved first-in-first-out (FIFO), last-in-last out (LIFO) and full-cycle decoders are described herein. In the various embodiments of the system, a clock generator is operable to generate a clock signal having an active phase and an inactive phase. A set of monotonic flip-flops are operable to capture a set of incoming data addresses during the active cycle of the clock and to generate therefrom data corresponding to single bits in the addresses that have changed compared to the data addresses received by the set of monotonic flip-flops during an immediately preceding data capture cycle. A set of static flip-flops are operable to capture a set of incoming data addresses during the inactive phase of the clock cycle and to generate set output data therefrom. A decoder operable to process the set output data from the set of static flip-flops and to generate a set of old wordlines corresponding to a set of data addresses in the immediately preceding data capture cycle. Combinational is logic operable to receive the set of single changed bits and the set of old wordlines and to generate therefrom a set of new wordlines. Methods are also described herein for using the aforementioned system. | 2012-02-02 |
20120026820 | INTEGRATED CIRCUITS FOR PROVIDING CLOCK PERIODS AND OPERATING METHODS THEREOF - An integrated circuit includes a capacitor. A switch is electrically coupled with the capacitor in a parallel fashion. A comparator includes a first input node, a second input node, and an output node. The second input node is electrically coupled with a first plate of the capacitor. The output node is electrically coupled with the switch. A transistor is electrically coupled with a second plate of the capacitor. A circuit is electrically coupled with a gate of the transistor. The circuit is configured to provide a bias voltage to the gate of the transistor so as to control a current that is supplied to charge the capacitor. | 2012-02-02 |
20120026821 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of bank groups including at least two banks, respectively, and a plurality of address counters corresponding to the plurality of bank groups in a one-to-one manner. A refresh operation of a selected bank group is performed in response to a bank group refresh command. | 2012-02-02 |
20120026822 | SEMICONDUCTOR DEVICE AND METHOD OF DRIVING THE SAME - A semiconductor device has an electrical fuse element including: a first filament; a second filament connected to the first filament; and a series readout section connected to an end of the first filament opposite to another end of the first filament connected to the second filament, the series readout section reading series resistance of the first filament and the second filament. | 2012-02-02 |
20120026823 | APPARATUS FOR MIXING AND DISCHARGING A FLUID PRODUCT AND RELATED SYSTEM - A discharge apparatus for discharging a fluid product comprises a housing ( | 2012-02-02 |
20120026824 | BLENDING SCALE - A blending scale for dosing and blending two products. The blending scale includes an auxiliary product dosing device, and an auxiliary product dispenser receiving the auxiliary product from the auxiliary product dosing device and releasing the auxiliary product within a dynamic unconstrained stream of the main product to produce and maximise a blend of the auxiliary and main products. A blend collector measures a quantity of the blend of the auxiliary and main products. A controller controls release of the auxiliary product in a synchronized manner with the dynamic unconstrained stream of the main product, based on the defined quantity of the auxiliary product measured by the auxiliary product dosing device. The dynamic stream of the main product is terminated once a targeted quantity of the blend measured by the blend collector is obtained. A method for accurately dosing and homogeneously blending two products is also disclosed. | 2012-02-02 |
20120026825 | BONE CEMENT SYSTEM - A bone cement system ( | 2012-02-02 |
20120026826 | BLENDING ASSEMBLY WITH AUTOMATED DISPENSING VALVE - A blending assembly that comprises a blender base that has an actuating member and a control mechanism, and a container that is removably mountable on the blender base. The container has an integral dispensing spout and dispensing valve. The dispensing valve opens and closes the dispensing spout. The container is adapted to receive ingredients. The control mechanism operates an impeller of the container to blend the ingredients and operates the actuating member to engage the dispensing valve to move the dispensing valve between open and closed positions with respect to the container, thereby opening and closing the dispensing spout for dispensing the blended ingredients. | 2012-02-02 |
20120026827 | FOOD PROCESSOR WITH ATTACHMENT - A blending apparatus is provided which includes a container defining a cavity having a center axis and a substantially rectangular cross section through the center axis. The blending apparatus further includes a lid to cover the cavity defined by the container, and an attachment to fit within the cavity and rotate about the center axis of the cavity. In some arrangements, a set of sides of the container defines (i) a substantially octagonal interior cross section through the center axis at a location adjacent a bottom of the container to prevent lodging of food products at the bottom of the container when the attachment rotates within the cavity; and (ii) a substantially square interior cross section through the center axis at a location further from the bottom of the container. | 2012-02-02 |
20120026828 | CONTROL DEVICE FOR POSITIONING AN INSTRUMENTED CABLE TOWED IN WATER - Control device ( | 2012-02-02 |
20120026829 | Method for wave decomposition using multi-component motion sensors - Three-axis velocity data, obtained along with pressure data in a marine seismic survey, are rotated to a ray direction. Plane wave decomposition is applied in the ray direction to the rotated velocity data. The pressure data and the velocity data are combined to generate at least one of up-going and down-going wave fields. The at least one of up-going and down-going wave fields are used in a time-space domain to image the earth's subsurface. | 2012-02-02 |
20120026830 | METHODS AND SYSTEMS TO ELIMINATE UNDESIRABLE VARIATIONS IN TIME-LAPSE SEISMIC SURVEYS - Device and method for processing 4-dimensional (4-D) seismic traces. The method includes receiving at least two vintages of seismic traces recorded by seismic receivers for a same subsurface area, wherein said seismic receivers are located at the ocean floor; applying up-down deconvolution to each of said vintages of seismic traces to obtain a representation of a reflectivity of said subsurface area from each vintage of seismic traces; and redatuming the up-down deconvolution result of each vintage from the ocean floor to a desired water depth of the ocean to reduce one or more changes in said seismic traces associated with water layer variations between recordings of said series of seismic traces. The redatumed seismic data is used to generate one or more images representing characteristics of said subsurface area. | 2012-02-02 |
20120026831 | METHOD AND APPARATUS FOR MEASURING FORMATION ANISOTROPY WHILE DRILLING - A logging system for measuring anisotrophic properties of the materials penetrated by a borehole. A downhole or “logging tool” element of the system comprises a source section that comprises either a unipole or a dipole acoustic source. The receiver section comprises a plurality of receiver stations disposed at different axial spacings from the acoustic source. Each receiver station comprises one or more acoustic receivers. The system requires that the source and receiver sections rotate synchronously as the logging tool is conveyed along the borehole. Receiver responses are measured in a plurality of azimuthal angle segments and processed as a function of rotation angle of the tool. The logging system can be embodied as a logging-while-drilling system, a measurement-while-drilling system, and a wireline system that synchronously rotates source and receiver sections. All embodiments require that the acoustic source operate at a relatively high frequency. | 2012-02-02 |
20120026832 | JOINT STRUCTURAL DIP REMOVAL - A method for structural dip removal. The method includes converting a seismic volume to a depth domain, extracting seismic dips from the seismic volume in the depth domain along a borehole trajectory, analyzing a borehole using the seismic dips to obtain structural dip data, and in response to determining that the seismic dips and borehole dips obtained from borehole imagery are consistent, generating a three dimensional (“3D”) structural model using the structural dip data. The method further includes performing a structural restoration using the 3D structural model to obtain depositional geometry data, removing structural dip from the borehole imagery using the 3D structural model to obtain sedimentary dip data, and performing a stratigraphic interpretation using the depositional geometry data and the sedimentary dip data. | 2012-02-02 |
20120026833 | 3-D HARMONIC-SOURCE REVERSE TIME MIGRATION SYSTEMS AND METHODS FOR SEISMIC DATA ANALYSIS - Computing device and method for processing seismic traces to produce an image of a subsurface area. The method includes receiving a series of seismic traces related to the subsurface area and recorded by one or more seismic receivers, wherein the one or more seismic sources are originally generated by a source; applying a phase encoding function to the series of seismic traces, at least a portion of said seismic traces comprise signals reflected by geological interfaces of the subsurface area; applying a 3 dimensional (3D) harmonic-source reverse time migration of the series of seismic traces encoded with the phase encoding function; computing a forward wavefield by solving a first wave equation; computing a backward wavefield by solving a second wave equation; and cross-correlating the forward wavefield with the backward wavefield to generate an image of the subsurface. | 2012-02-02 |
20120026834 | OBTAINING A RESPONSE BASED ON DIFFERENCING OF OUTPUTS OF SENSORS - A sensor assembly has first sensors spaced apart along a first direction, and second sensors oriented in a second direction generally orthogonal to the first direction. Differencing of outputs of the first sensors is performed, and differencing of outputs of the second sensors is performed. A signal output is produced by combining the differenced outputs of the first sensors and the differenced outputs of the second sensors, where the signal output represents a seismic response of a subterranean structure. | 2012-02-02 |
20120026835 | SUBSURFACE IMAGING METHOD USING VIRTUAL SOURCES DISTRIBUTED UNIFORMLY OVER THE SUBSURFACE - There are provided a subsurface imaging apparatus and method for modeling a subsurface structure by solving a wavefield equation by waveform inversion. A virtual source that generates an observed wavefield and is distributed over grid points of the subsurface is obtained by applying a least-square method to an equation including a Green's function of the subsurface medium. Then, a subsurface model generating the observed wavefield when applying the virtual source is obtained. | 2012-02-02 |
20120026836 | Proximity timer switch - A timer switch which is activated by the proximity of an object situated in a given distance range and is present there for a given time period. | 2012-02-02 |
20120026837 | SOUND DIRECTION DETECTION - In accordance with some embodiments of the present disclosure, a process for determining a direction vector of a sound source is described. The process may be implemented to detect, by a first sound sensor, a first sound pressure of a sound wave propagated from the sound source, and detect, by a second sound sensor, a second sound pressure of the sound wave. The process may further be implemented to determine, by a processor, the direction vector of the sound source relative to the first sound sensor and second sound sensor, wherein the direction vector is based on the first sound pressure, the second sound pressure, and a first distance between a first physical location of the first sound sensor and a second physical location of the second sound sensor. | 2012-02-02 |