05th week of 2011 patent applcation highlights part 28 |
Patent application number | Title | Published |
20110026312 | Semiconductor device including memory having nodes connected with continuous diffusion layer but isolated from each other by transistor - A semiconductor device includes a memory cell which includes a first inverter and a second inverter, the first inverter includes a first drive transistor and a first load transistor, the second inverter includes a second drive transistor and a second load transistor, and an input terminal and an output terminal thereof, respectively, connected to an input terminal and an output terminal of the first inverter, a first transmission transistor provided between the output terminal of the first inverter and a line of a first bit line pair, a second transmission transistor provided between the output terminal of the second inverter and another line of the first bit line pair, a third transmission transistor provided between the output terminal of the first inverter and a line of a second bit line pair, a fourth transmission transistor provided between the output terminal of the second inverter and another line of the second bit line pair, and a first isolation transistor which isolates the second drive transistor and the first transmission transistor. A first active region in which the first transmission transistor, the second transmission transistor, the second drive transistor, and the first isolation transistor are formed, is formed in a continuous region. The first isolation transistor is provided between the second drive transistor and the first transmission transistor. | 2011-02-03 |
20110026313 | TRANSISTOR-BASED MEMORY CELL AND RELATED OPERATING METHODS - A loadless static random access memory cell is provided. The memory cell includes four transistors. The first transistor has a gate terminal corresponding to a word line of the memory cell, a source/drain terminal corresponding to a first bit line of the memory cell, and a drain/source terminal corresponding to a first storage node of the memory cell. The second transistor has a gate terminal corresponding to the word line, a source/drain terminal corresponding to a second bit line of the memory cell, and a drain/source terminal corresponding to a second storage node of the memory cell. The third transistor has a gate terminal coupled to the second storage node, a drain terminal coupled to the first storage node, a source terminal corresponding to a reference voltage, and a body terminal directly connected to the third gate terminal. The fourth transistor has a gate terminal coupled to the first storage node, a drain terminal coupled to the second storage node, a source terminal corresponding to the reference voltage, and a body terminal directly connected to the fourth gate terminal. | 2011-02-03 |
20110026314 | Static Memory Device with Five Transistors and Operating Method - At the bottom of a column (COLi) of memory cells (CEL) of the SRAM type with five portless transistors, there is placed an additional cell (CLS), with a structure identical to the cells (CEL), which makes it possible to write and read a datum in a memory cell (CEL) of the column without using a read amplifier. | 2011-02-03 |
20110026315 | Single-Event Upset Immune Static Random Access Memory Cell Circuit, System, And Method - A circuit and method are provided in which a six-transistor (6-T) SRAM memory cell is hardened to single-event upsets by adding isolation-field effect transistors (“iso-fets”) connected between the reference voltage Vdd and the field-effect transistors (“fets”) respectively corresponding to first and second inverters of the memory cell. According to certain embodiments, the control gates of first and second P-iso-fets are respectively tied to the control gates of first and second pull-up P-fets. According to certain embodiments, first and second N-iso-fets are connected between the output nodes of the memory cell and the pull-down N-fets respectively corresponding to the first and second inverters. The control gates of the first and second N-iso-fets are respectively tied to the control gates of the first and second pull-down N-fets. Again according to certain embodiments, one or more of the iso-fets are physically removed from the proximity of other transistors which comprise the memory cell. | 2011-02-03 |
20110026316 | MAGNETORESISTIVE MEMORY ELEMENTS WITH SEPARATE READ AND WRITE CURRENT PATHS - A magnetoresistive memory element has a free layer, and a write current path aligned with a free layer plane. The memory element has a pinned layer with a magnetization direction aligned with that of the free layer. A barrier layer is disposed between the free layer and the pinned layer. The free, barrier and pinned layers together form a layer stack that has a read current path that extends through the layer stack and that is not aligned with the write current path in the free layer. | 2011-02-03 |
20110026317 | SPIN-TRANSFER TORQUE MEMORY SELF-REFERENCE READ AND WRITE ASSIST METHODS - A spin-transfer torque memory apparatus and self-reference read and write assist schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage. A magnetic field is applied through the free magnetic layer the forming a magnetic field modified magnetic tunnel junction data cell. Then a second read current is applied thorough the magnetic field modified magnetic tunnel junction data cell forming a second bit line read voltage and compared with the first bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state. Methods of applying a destabilizing magnetic field to the MTJ and then writing the desired resistance state are also disclosed. | 2011-02-03 |
20110026318 | ITERATIVE WRITE PAUSING TECHNIQUES TO IMPROVE READ LATENCY OF MEMORY SYSTEMS - Iterative write pausing techniques to improve read latency of memory systems including memory systems with phase change memory (PCM) devices. A PCM device includes a plurality of memory locations and a mechanism for executing an iterative write to one or more of the memory locations in response to receiving a write command that includes data to be written. The executing includes initiating the iterative write, updating a state of the iterative write, pausing the iterative write including saving the state in response to receiving a pause command, and resuming the iterative write in response to receiving a resume command. The resuming is responsive to the saved state and to the data to be written. | 2011-02-03 |
20110026319 | NON-VOLATILE SEMICONDUCTOR MEMORY CIRCUIT AND METHOD OF CONTROLLING THE SAME - A non-volatile semiconductor memory circuit for use in compensating for time dependent resistive changes in phase change memory cells is presented. The non-volatile semiconductor memory circuit includes a control signal generation unit and a sensing block. The control signal generation unit is configured to provide a control signal having a voltage level corresponding to a read command or a write command. The sensing block is configured to selectively provide a first sensing reference voltage substantially equal to a reference voltage. The sensing block is also configured to selectively provide a second sensing reference voltage which is lower than the reference voltage. The first and second sensing reference voltages are selectively provided as a function of the voltage level of the control signal in which the first and second sensing reference voltages are used to read data of the memory cell array. | 2011-02-03 |
20110026320 | STAGGERED MAGNETIC TUNNEL JUNCTION - A staggered magnetic tunnel junction includes a free magnetic layer extending in a lateral direction between a first end portion and an opposing second end portion and a tunneling barrier disposed between a reference magnetic layer and the first end portion and forming a magnetic tunnel junction. Current flows through the free magnetic layer in the lateral direction to switch the magnetic tunnel junction between a high resistance state and a low resistance state. | 2011-02-03 |
20110026321 | MAGNETIC MEMORY WITH POROUS NON-CONDUCTIVE CURRENT CONFINEMENT LAYER - A magnetic element having a ferromagnetic pinned layer, a ferromagnetic free layer, a non-magnetic spacer layer therebetween, and a porous non-electrically conducting current confinement layer between the free layer and the pinned layer. The current confinement layer forms an interface either between the free layer and the non-magnetic spacer layer or the pinned layer and the non-magnetic spacer layer. | 2011-02-03 |
20110026322 | RECORDING METHOD FOR MAGNETIC MEMORY DEVICE - [Object] To provide a recording method for a magnetic memory device including a recording layer that is capable of changing a magnetization direction and holds information as a magnetization direction of a magnetic body and a magnetization reference layer that is provided with respect to the recording layer with an insulation layer interposed therebetween and becomes a reference of the magnetization direction, the magnetic memory device being recorded with information by a current flowing between the recording layer and the magnetization reference layer via the insulation layer, the recording method being capable of maintaining, even when a write pulse considerably higher than an inversion threshold value is applied, a write error rate of 10 | 2011-02-03 |
20110026323 | Gated Diode Memory Cells - A gated diode memory cell is provided, including one or more transistors, such as field effect transistors (“FETs”), and a gated diode in signal communication with the FETs such that the gate of the gated diode is in signal communication with the source of a first FET, wherein the gate of the gated diode forms one terminal of the storage cell and the source of the gated diode forms another terminal of the storage cell, the drain of the first FET being in signal communication with a bitline (“BL”) and the gate of the first FET being in signal communication with a write wordline (“WLw”), and the source of the gated diode being in signal communication with a read wordline (“WLr”). | 2011-02-03 |
20110026324 | Method for Programming a Floating Gate - The invention provides methods for programming a floating gate. A floating gate tunneling device is used with an analog comparing device in a circuit having a floating reference node and an offset-mitigating feedback loop for iteratively programming a floating gate, or multiple floating gates. | 2011-02-03 |
20110026325 | METHOD OF PROGRAMMING A MULTI LEVEL CELL - A method of programming a multi level cell in a non-volatile memory device includes: performing a program operation on main cells and indicator cells; performing a first verifying operation on the main cells and the indicator cells based on a first verifying voltage; performing repeatedly the program operation and the first verifying operation until a threshold voltage of a first cell of the indicator cells is higher than the first verifying voltage; and performing a second verifying operation on the main cells and the indicator cells based on a second verifying voltage when the threshold voltage of the first cell is higher than the first verifying voltage. | 2011-02-03 |
20110026326 | MEMORY SYSTEM INCLUDING FLASH MEMORY AND METHOD OF OPERATING THE SAME - A method for operating a memory system including a flash memory device having a plurality of memory blocks includes determining whether a read error generated during a read operation of the flash memory device is caused by read disturbance and replacing a memory block which includes the read error, with a spare memory block if the read error is caused by read disturbance. | 2011-02-03 |
20110026327 | BIT-LINE CONNECTIONS FOR NON-VOLATILE STORAGE - Bit line connections for non-volatile storage devices and methods for fabricating the same are disclosed. At least two different types of bit line connections may be used between memory cells and bit lines. The different types of bit line connections may be structurally different from each other as follows. One type of bit line connection may include a metal pad between an upper via and lower via. Another type of bit line connection may include an upper via and lower via, but does not include the metal pad. Three rows of bit line connections may be used to relax the pitch. For example, two rows of bit line connections on the outside may have the metal pad, whereas bit line connections in the middle row do not have the metal pad. | 2011-02-03 |
20110026328 | SYSTEM AND METHOD OF MAINTAINING DATA INTEGRITY IN A FLASH STORAGE DEVICE - A flash storage device includes a power hold circuit including a double layer capacitor. A power source supplies power to the flash storage device and charges the double layer capacitor. The double layer capacitor supplies power for maintaining integrity of data during a data transfer occurring in the flash storage device when the power supplied by the power source is disrupted. Additionally, the flash storage device can inhibit subsequent data transfers until the power supplied by the power source is restored. | 2011-02-03 |
20110026329 | SEMICONDUCTOR DEVICE USING CHARGE PUMP CIRCUIT - A semiconductor device including a plurality of capacitance units connected in parallel between a first voltage and a second voltage. Each of the plurality of capacitance units includes: a capacitance element connected with the first voltage; and a capacitance disconnecting circuit connected between the second voltage and the capacitance element. The capacitance disconnecting circuit includes a non-volatile memory cell with a threshold voltage changed based on a change of a leakage current which flows from the capacitance element, and blocks off the leakage current based on a rise of the threshold voltage of the non-volatile memory cell when the leakage current exceeds a predetermined value. | 2011-02-03 |
20110026330 | PROGRAM METHOD OF FLASH MEMORY DEVICE - In a program method of a flash memory device where memory cells within a string are turned on to electrically connect channel regions, all of the channel regions within a second string are precharged uniformly by applying a ground voltage to a first bit line connected to a first string including to-be-programmed cells and a program-inhibited voltage to a second bit line connected to the second string including program-inhibited cells. If a program operation is executed, channel boosting occurs in the channel regions within the second string including the program-inhibited cells. Accordingly, a channel boosting potential can be increased and a program disturbance phenomenon, in which the threshold voltage of program-inhibited cells is changed, can be prevented. | 2011-02-03 |
20110026331 | PROGRAM VOLTAGE COMPENSATION WITH WORD LINE BIAS CHANGE TO SUPPRESS CHARGE TRAPPING IN MEMORY - Program disturb is reduced in a non-volatile storage system during a program operation for a selected word line by initially using a pass voltage with a lower amplitude on word lines which are adjacent to the selected word line. This helps reduce charge trapping at floating gate edges, which can widen threshold voltage distributions with increasing program-erase cycles. When program pulses of higher amplitude are applied to the selected word line, the pass voltage switches to a higher level to provide a sufficient amount of channel boosting. The switch to a higher pass voltage can be triggered by a specified program pulse being applied or by tracking lower state storage elements until they reach a target verify level. The amplitude of the program voltage steps down when the pass voltage steps up, to cancel out capacitive coupling to the selected storage elements from the change in the pass voltage. | 2011-02-03 |
20110026332 | Semiconductor memory device and its operation method - Disclosed herein is a semiconductor memory device including: a bit line and a sense line; a data storage element having a data storage state changing in accordance with a voltage applied to the bit line; a first switch for controlling connection of the sense line to the bit line; a data latch circuit having a second data holding node and a first data holding node connected to the sense line; and a second switch for controlling connection of the second data holding node of the data latch circuit to the bit line. | 2011-02-03 |
20110026333 | BULK BIAS VOLTAGE GENERATING DEVICE AND SEMICONDUCTOR MEMORY APPARATUS INCLUDING THE SAME - A bulk bias voltage generating device is configured to generate a first bulk bias voltage in a deep power down mode and a second bulk bias voltage in a normal mode. The first bulk bias voltage comprises an internal voltage level, and the second bulk bias voltage comprises an external voltage level. | 2011-02-03 |
20110026334 | BIDIRECTIONAL EQUALIZER WITH CMOS INDUCTIVE BIAS CIRCUIT - An integrated circuit (IC) device, system and related method of communicating data are described. The IC device includes; a data port configured to provide output data to a channel and receive input data from the channel, an impedance matching circuit connected to the data port and configured to operate as an output driver circuit when the output data is being transmitted and as an on die termination circuit when the input data is being received, and an active inductive bias circuit connected to the data port in parallel with the impedance matching circuit, and configured to adjust the impedance of the data port to the channel during transmission of the output data as a function of output data frequency and adjust the impedance of the data port to the channel during receipt of the input data as a function of input data frequency. | 2011-02-03 |
20110026335 | POWER-UP SIGNAL GENERATION CIRCUIT - A power-up signal generation circuit includes a fixed level transition voltage generation unit, a variable level transition voltage generation unit, a comparison unit, and a selective output unit. The fixed level transition voltage generation unit is configured to generate a fixed level transition voltage changing at a constant level of an external voltage. The variable level transition voltage generation unit is configured to generate a variable level transition voltage changing at a level of an external voltage which varies depending on temperature. The comparison unit is configured to compare the level of the fixed level transition voltage with the level of the variable level transition voltage, and generate a selection signal. The selective output unit is configured to output the fixed level transition voltage or the variable level transition voltage as a power-up signal in response to the selection signal. | 2011-02-03 |
20110026336 | Data Storage Using Read-Mask-Write Operation - Method and apparatus for writing data to a storage array, such as but not limited to an STRAM or RRAM memory array, using a read-mask-write operation. In accordance with various embodiments, a first bit pattern stored in a plurality of memory cells is read. A second bit pattern is stored to the plurality of memory cells by applying a mask to selectively write only those cells of said plurality corresponding to different bit values between the first and second bit patterns. | 2011-02-03 |
20110026337 | DATA INPUT/OUTPUT CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS INCLUDING THE SAME - A circuit includes a data input/output unit configured to connect to a first memory bank and a second memory bank. The data input/output unit includes a data switching unit configured to be selectively coupled with the first or second memory bank in response to a bank selection signal, and an input/output driver configured to amplify an output of the data switching unit and transfer the amplified output to a global data line during the read operation, and configured to amplify data from the global data line and transfer the amplified data to the data switching unit during the write operation. | 2011-02-03 |
20110026338 | REDUNDANCY CIRCUIT OF SEMICONDUCTOR MEMORY - A redundancy circuit of a semiconductor memory apparatus includes an enable signal generation unit configured to have a plurality of enable fuses corresponding to a first mat grouping information signal and a second mat grouping information signal and enable an enable signal when at least one of the plurality of enable fuses is cut and a mat grouping information signal corresponding to the cut fuse is inputted; a fail address setting control block configured to select the first mat grouping information signal or the second mat grouping information signal depending upon whether an enable fuse corresponding to the first mat grouping information signal is cut or not, and generate fail setting addresses; and a comparison section configured to compare the fail setting addresses with real addresses and generate a redundancy address. | 2011-02-03 |
20110026339 | Semiconductor memory device performing refresh operation and method of testing the same - A semiconductor memory device includes a mask information storage circuit that stores therein mask information indicating an area for which the self refresh operation is not performed among a plurality of areas in a memory cell array, a mask determining circuit that is activated by a self refresh command and generates a match signal in response to a detection of a match between a refresh address and the mask information, and a refresh operation control circuit that disables the self refresh operation in response to an activation of the match signal. When a test mode signal is activated, the mask determining circuit is also activated by the auto refresh command. With this configuration, it is possible to perform a test of a partial array self refresh function without actually entering a self refresh mode. | 2011-02-03 |
20110026340 | MEMORY TEST CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT AND MEMORY TEST METHOD - A memory test circuit tests a memory including an actual array portion and a redundancy portion. The memory test circuit includes: an input data selector outputting first test data excluding data for the redundancy portion in test data representing data for the actual array portion and the redundancy portion as input selecting data in a redundancy BIST mode (RBM); an input data switching circuit outputting the test data as output test data to the memory in a direct BIST mode (DBM), and outputting data obtained by adding redundancy bits to the input selecting data as the output test data to the memory based on the input selecting data and output redundancy codes representing redundancy codes in the RBM; an output data switching circuit outputting data obtained by removing the redundancy bits from read data as output selecting data based on the read data from the memory and the output redundancy codes in the RBM; and a memory BIST comparator checking a value of the read data with a checking expectation value to output a checking result as a test result in the DBM, and checking a value of the output selecting data with an expectation value for the actual array portion in the checking expectation value to output a checking result as the test result in the RBM. | 2011-02-03 |
20110026341 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes memory banks, each having sub banks. The semiconductor memory apparatus is configured to allocate same test input/output line to a certain sub bank of one memory bank and a certain sub bank of another memory bank during a multi-bit test. | 2011-02-03 |
20110026342 | MULTI-PORT MEMORY DEVICE - A multi-port memory device includes: a bank having a plurality of matrices; a plurality of test data input/output units where data is input/output using a test mode for detecting a defective memory cell; a plurality of ports converted into a decoding device for decoding a command/address at the test mode; a plurality of data transfer lines for transferring data between the matrices and the test data I/O units, wherein the data transfer lines is grouped into the number of matrices; and a plurality of temporary storing units included between the data transfer lines and the matrices for temporarily storing data. | 2011-02-03 |
20110026343 | BIST DDR MEMORY INTERFACE CIRCUIT AND METHOD FOR TESTING THE SAME - An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit includes a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a phase shifted data strobe output signal in response to receiving an internal data strobe input signal. A second multiplexer selects one of the internal data strobe input signals and a third multiplexer selects the phase shifted data strobe output signal that corresponds to the selected internal data strobe input signal. A phase detector determines a phase difference between the selected internal data strobe input signal and the selected phase shifted data strobe output signal and outputs a phase difference value. | 2011-02-03 |
20110026344 | DATA CONTROL CIRCUIT - The data control circuit includes an input/output line and a driver. The input/output line precharging circuit precharges a global input/output line to a predetermined voltage when either a reading operation or a writing operation is inoperative. The driver includes a number of MOS transistors and drives the global input/output line in response to receiving data from a local input/output line and a complementary local input/output line during the reading operation. | 2011-02-03 |
20110026345 | PRECHARGE CONTROL CIRCUITS AND METHODS FOR MEMORY HAVING BUFFERED WRITE COMMANDS - Memories, precharge control circuits, methods of controlling, and methods of utilizing are disclosed, including precharge control circuits for a memory having at least one bank of memory. One such control circuit includes at least one precharge preprocessor circuit. The precharge preprocessor circuit is coupled to a respective bank of memory and is configured to prevent precharge of the respective bank of memory until after execution of buffered write commands issued to the respective bank of memory is completed. | 2011-02-03 |
20110026346 | SELF-TIMED LOW POWER SENSE AMPLIFIER - A sense amplifier is disclosed comprising a first sense input, a second sense input, a latch, a first p-channel control transistor arranged to electrically power a first section of the latch and having a gate terminal linked to the first sense input, and a second p-channel control transistor arranged to electrically power a second section of the latch and having a gate terminal linked to the second sense input. Application may be in particular to low power embedded memories. | 2011-02-03 |
20110026347 | Differential Sense Amplifier - A differential sense amplifier can perform data sensing using a very low supply voltage. | 2011-02-03 |
20110026348 | Semiconductor device having hierarchically structured bit lines and system including the same - A semiconductor device includes a global bit line, a dummy global bit line that is shorter than the global bit line, a sense amplifier that amplifies a potential difference between the global bit line and the dummy global bit line, a plurality of memory blocks each including a hierarchy switch and a local bit line that is connected to the global bit line via the hierarchy switch, a dummy memory block that includes a dummy hierarchy switch and a dummy local bit line that is connected to the dummy global bit line via the dummy hierarchy switch, and a control circuit that activates any one of hierarchy switches and the dummy hierarchy switch. With this configuration, it is possible to obtain the same memory capacity between a memory mat located at an edge and the other memory mat. | 2011-02-03 |
20110026349 | CIRCUIT FOR COMPENSATING TEMPERATURE DETECTION RANGE OF SEMICONDUCTOR MEMORY APPARATUS - A circuit for compensating a temperature measurement range of a semiconductor memory apparatus is presented. The circuit includes an oscillator, a temperature variable pulse generating unit, a counter, and an output controlling unit. The counter enable signal generating unit inputs a temperature pulse and outputs a counter enable signal corresponding to the temperature pulse in response to receiving a control signal. The counter inputs and counts an oscillator signal in response to receiving the counter enable signal and outputs a counting signal. The output controlling unit outputs a temperature information code signal proportional to the counting signal or to output the temperature information code signal at a fixed level corresponding to a maximum value of the counting signal. | 2011-02-03 |
20110026350 | Resettable Memory Apparatuses and Design - In one aspect of the present invention, a memory apparatus comprises a plurality of resettable memory cells, a plurality of memory units, and a reset information propagation logic coupled to the resettable memory cells and the memory units. The reset information propagation logic designed to write reset information into a portion of the memory units in response to one of the resettable memory cells having a reset value when one of the memory units is written into. | 2011-02-03 |
20110026351 | METHOD OF REDUCING CURRENT OF MEMORY IN SELF-REFRESHING MODE AND RELATED MEMORY - The present invention provides a method of reducing current of a memory in a self-refreshing mode and a related memory. The memory includes a word line driver and a controller, and the word line driver includes a transistor. The transistor has a control terminal, a first terminal coupled to a word line, and a second terminal. The method includes: after the memory enters the self-refreshing mode: controlling a voltage difference between the control terminal and the second terminal to correspond to a first value during a self-refreshing operation period; and controlling a voltage difference between the control terminal and the second terminal to correspond to a second value smaller than the first value during a non self-refreshing operation period. | 2011-02-03 |
20110026352 | METHOD OF REDUCING CURRENT OF MEMORY IN SELF-REFRESHING MODE AND RELATED MEMORY - The present invention provides a method of reducing current of a memory in a self-refreshing mode and a related memory. The memory includes a word line driver and a controller, and the word line driver includes a transistor. The transistor has a control terminal, a first terminal coupled to a word line, and a second terminal. The method includes: after the memory enters the self-refreshing mode: controlling a voltage difference between the control terminal and the second terminal to correspond to a first value during a self-refreshing operation period; and controlling a voltage difference between the control terminal and the second terminal to correspond to a second value smaller than the first value during a non self-refreshing operation period. | 2011-02-03 |
20110026353 | DATA REFRESH FOR NON-VOLATILE STORAGE - Techniques are disclosed to refresh data in a non-volatile storage device often enough to combat erroneous or corrupted data bits, but not so often as to interfere with memory access or to cause excessive stress on the memory cells. One embodiment includes determining to perform a refresh of data stored in a first group of non-volatile storage elements in a device based on a condition of data in the first group, determining that a second group of non-volatile storage elements in the device should undergo a refresh procedure based on when the second group of non-volatile storage elements were last programmed relative to when the first group of non-volatile storage elements were last programmed, and performing the refresh procedure on the second group of non-volatile storage element. | 2011-02-03 |
20110026354 | CURRENT LEAKAGE REDUCTION - An OTP memory array includes a bit line coupled to a plurality of memory banks. Each memory bank includes a plurality of memory cells, a footer, and a bias device, and is associated with a current mirror. When a memory cell is activated (e.g., for reading) the memory bank including the activated memory cell is referred to as an activated memory bank and other banks are referred to as deactivated memory banks. A current tracking device serves to compensate for bit line leakage current in deactivated memory cells in the activated memory bank. Further, footers and bias devices in deactivated memory banks and associated current mirrors are configured to reduce/eliminate bit line current leakage through deactivated memory cells in deactivated memory banks. | 2011-02-03 |
20110026355 | INTERFACE CIRCUIT AND SEMICONDUCTOR DEVICE INCORPORATING SAME - An interface circuit includes an input/output terminal, a clock generator, a set of multiple data ports, and a data port selector. The input/output terminal is connected to the external circuit to receive a data signal. The clock generator generates a series of multiple phase-shifted clock signals based on a basic clock signal. Each of the multiple data ports is connected to the input/output terminal and the clock generator to receive the data signal in synchronization with an associated one of the multiple phase-shifted clock signals to output a latched data signal. The data port selector is connected to the multiple data ports to check the multiple latched data signals to select one of the multiple data ports. The interface circuit loads the data signal through the selected data port in synchronization with the associated one of the multiple phase-shifted clock signals. | 2011-02-03 |
20110026356 | APPARATUS AND METHODF FOR THE UNIFORM DISTRIBUTION OF MICROPARTICLES IN A LIQUID - The invention relates to an apparatus for the uniform distribution of microparticles in a liquid, said apparatus comprising a storage chamber | 2011-02-03 |
20110026357 | AGITATION MIXING APPARATUS - In an agitation mixing apparatus | 2011-02-03 |
20110026358 | BLENDER ASSEMBLY AND METHOD FOR PRODUCING A PREPARATION USING SAID ASSEMBLY - The invention relates to a blender device comprising: a rotor ( | 2011-02-03 |
20110026359 | Mixing system for two-component cartridge - In a mixing system for two-component cartridges having a neck section structure with an inner discharge channel and an outer tubular discharge channel for discharging first and second material components from first and second chambers of the cartridge, the inner discharge channel is provided with pockets extending into the outer discharge channel for dividing the second material flow into second material flow strands and a baffle plate is arranged centrally in front of the inner discharge channel for directing the inner material flow outwardly through the pockets in strands of the inner material component between strands of the outer material component, so that a pre-mixing of the material components occurs already directly at the openings of the discharge channels. | 2011-02-03 |
20110026360 | FLEXIBLE POUCH WITH A MIXING APPARATUS - A flexible pouch has a mixing apparatus, the mixer shaft of which is adjustable in length for use as a bioreactor for culturing microorganisms and cells. | 2011-02-03 |
20110026361 | STIRRING BLADE AND SEALED STIRRING APPARATUS - An up/down movable diaphragm is disposed to an upper surface portion of a stirring vessel so as to airtightly cover the upper surface portion, a drive shaft passing through the diaphragm is fixed and vertically disposed to the diaphragm, and a stirring blade coupled with and fixed to a lower end portion of the drive shaft so as to be orthogonal thereto is composed of a laterally long and oval sheet-shaped member having a major axis and a minor axis passing through a center thereof, and a stirring is performed by moving the stirring blade up and down. With this arrangement, there are provided a stirring blade and a stirring apparatus which do not apply a strong shearing force to a stirring liquid, do not have an anxiety of polluting the stirring liquid, and can sufficiently fluidize, mix, disperse, and homogenize the stirring liquid in a stirring blade and a stirring apparatus for performing a stirring in fields of medicine and food. | 2011-02-03 |
20110026362 | Telemetry Coding and Surface Detection for a Mud Pulser - A method for encoding a non-negative integer, for example, representative of MWD/LWD data, includes encoding at least a portion of the integer using at least a first order Fibonacci derived sequence. The remainder of the integer may be encoded using conventional Fibonacci encoding. The invention tends to improve coding efficiency, downhole and surface synchronization, and surface detection. | 2011-02-03 |
20110026363 | WIRELESS POSITION SENSING IN THREE DIMENSIONS USING ULTRASOUND - The present invention provides a method of position sensing between a wireless mobile component carrying a mobile ultrasonic transducer and a fixed component carrying a plurality of fixed ultrasonic transducers in a predetermined spaced-apart relationship, the method comprising turning off all the transducers to establish a period of silence, activating one or more of the fixed transducers to transmit an ultrasonic signal, starting a plurality of timers corresponding to the respective plurality of fixed transducers generally simultaneously with transmitting the signal, receiving the signal at the mobile transducer, transmitting a signal from the mobile transducer responsive to the received signal, receiving the signal transmitted by the mobile transducer at each fixed transducer and stopping the respective timer generally at the time of reception of an edge of the received signal found within the first twenty received edges and preferably within the first ten received edges and more preferably at the first received rising edge, calculating the distance between the mobile transducer and each fixed transducer based on a predetermined constant representative of the speed of sound and the time taken for transit of the signal to each fixed transducer as measured by the respective timers, and performing trigonometric calculations using the calculated distances in order to determine the 3-dimensional position of the mobile component relative to the fixed component. | 2011-02-03 |
20110026364 | Apparatus and method for estimating position using ultrasonic signals - A three-dimensional (3D) position estimation apparatus and method using ultrasonic signals may estimate a 3D position based on distances between two ultrasonic signal transmitters and an ultrasonic signal receiver, and direction angles where the ultrasonic signal receiver receives the ultrasonic signals. When the ultrasonic signal receiver moves on a fixed distance, the 3D position estimation apparatus and method may estimate the 3D position of the ultrasonic signal receiver based on the fixed distance and the direction angles where the ultrasonic signal receiver receives the ultrasonic signals. | 2011-02-03 |
20110026365 | ULTRASONIC TRANSDUCER AND SIGNAL DECAY TIME ADJUSTING METHOD APPLIED THERETO - A signal decay time adjusting method is used in an ultrasonic transducer. Firstly, a first driving signal is generated by a pre-processing module. When the first driving signal is received, an ultrasonic transmitting/receiving module generates vibration and transmits a sensing wave according to the first driving signal. Then, the pre-processing module stops generating the first driving signal so that the vibration generated within the ultrasonic transmitting/receiving module is decayed as a decay signal. Then, a second driving signal is generated by the pre-processing module according to the first driving signal, and the second driving signal is transmitted to the ultrasonic transmitting/receiving module. When the second driving signal is received, the decay signal is offset according to the second driving signal, so that a decay time of the decay signal is shortened. When the sensing wave is reflected by an object, a reflective wave is received by the ultrasonic transmitting/receiving module. | 2011-02-03 |
20110026366 | Water Inflatable Volumetric Hydrophone Array - A hydrophone array includes an inflatable shaped housing enclosing an interior space and formable between a collapsed configuration and an expanded configuration, a framework of compliant material disposed within the interior of the inflatable housing, and a plurality of hydrophones attached to the compliant material at respective positions, wherein said hydrophones are arranged in a predetermined geometric array when the shaped housing is in the expanded configuration. Also provided herein is a system and method for deploying the hydrophone array. | 2011-02-03 |
20110026367 | Acoustic Transducer - The acoustic transducer includes one or more membranes which cover cavities on a substrate by means of a uniformly thick polymer layer produced by vapor deposition. In the region of the cavities vapor deposition is performed on the surface of a liquid, which subsequently may be removed from the cavities via channels. | 2011-02-03 |
20110026368 | GRAPHIC DISPLAY PROGRAMMABLE WRISTWATCH - The present application relates to the preferred and alternate embodiment of the graphic display programmable wristwatch and that will display an array of downloadable static and animated Images on an LCD or LED screen to be used to tell time More particularly, the present application relates to a programmable wristwatch that will serve as a platform for downloadable computer generated graphic images by the means of being placed on a docking station cradle at night to charge the battery along with being able to be connected to a computer The preferred and alternate embodiments of the graphic display programmable wristwatch and would have several distinct and innovative elements an LCD or LED screen, a USB port and a wireless sensor port, a time-keeping unit and a central processing unit. | 2011-02-03 |
20110026369 | Timepiece with Wireless Transmission Arrangement - A timepiece includes a time displaying device, and a wireless transmission arrangement, which includes a first Main Control Unit (MCU), a wireless dongle and a primary transceiver device. The first MCU includes a first Central Processing Unit (CPU) core and a first memory unit arranged to implement a File Allocation Table (FAT) for managing memory data stored in the first memory unit. The wireless dongle is electrically connected to a computer. The primary transceiver device is electrically connected with the first MCU and wirelessly communicated with the wireless dongle, wherein the memory data is allowed to be wirelessly transmitted to the wireless dongle through the primary transceiver device so that the memory data originally stored within the first memory unit is capable of being processed in the computer, and addition data originally stored within the computer can be wirelessly transferred and stored in the first memory unit. | 2011-02-03 |
20110026370 | Chronograph timepiece - Disclosed is a chronograph timepiece in which it is possible to prevent the battery reliability service life time from being exceeded even when the period of time that the chronograph function is used is short, making it possible to prevent failure generation in the chronograph timepiece due to liquid leakage. A 24-hour counter down-counts a period of time that has elapsed starting from 24 hours, and a chronograph counter down-counts the period of time that chronograph measurement operation is performed from a predetermined time; when the count values of the 24-hour counter and the chronograph counter become equal to each other, a processing unit consumes a battery for the residual period of time of the two counters by a battery power consuming unit. | 2011-02-03 |
20110026371 | Chronograph timepiece - Disclosed is a chronograph timepiece in which it is possible to prevent the chronograph drive timing and the magnetic field detection timing from overlapping each other to unnecessarily effect driving with correction drive pulses. A processing unit controls drive circuits so as to drive a time indication motor and a chronograph indication motor with a predetermined timing based respectively on timekeeping information obtained and chronograph measurement information obtained, and effects control such that a magnetic field detecting unit detects a magnetic field with a predetermined timing; when the drive timing for the chronograph indication motor and the magnetic field detection timing for the magnetic field detecting unit overlap each other, the processing unit changes the magnetic field detection timing for the magnetic field detecting unit so that the drive timing for the chronograph indication motor and the magnetic field detection timing for the magnetic field detecting unit may not overlap each other. | 2011-02-03 |
20110026372 | Chronograph timepiece - Disclosed is a chronograph timepiece in which it is possible to prevent a non-rotation state at the time of first driving when chronograph measuring operation is reset during motor drive and restarting is effected. When a resetting operation is performed on a reset button during the driving of a motor and a rotation detection circuit detects non-rotation, a drive control unit controls a drive pulse generation circuit such that the control is completed without reversing the polarity of a motor drive pulse output from the drive pulse generation circuit, and that the motor is driven by a drive pulse of the same polarity as that at the time of the previous resetting in response to a starting operation performed on a start/stop button, driving the motor by the drive pulse of the same polarity at the time of restarting after the resetting. | 2011-02-03 |
20110026373 | MECHANISM TO AVOID RATE VARIATIONS DUE TO GRAVITATION IN A SPRUNG BALANCE REGULATING ORGAN, AND TIMEPIECE PROVIDED WITH SUCH A MECHANISM - The mechanism avoids the rate variations due to the effect of gravitation on a regulating organ of a timepiece whose regulating organ includes a sprung balance and an escape wheel mounted onto a platform. The platform includes a counterweight and is mounted so as to freely rotate about at least a first axis relative to a plate of the movement so that this platform will rotate about the first axis under the effect of terrestrial gravitation. This mechanism includes a wheelwork with a driving kinematical chain linking the escape wheel to a barrel system of the timepiece, and a corrective kinematical chain compensating the movements and speed of the platform relative to the plate, so that these movements of the platform will not perturb the chronometry of the timepiece. | 2011-02-03 |
20110026374 | Programmable watch winding apparatus - A programmable watch winding apparatus includes a user interface for users to input a winding number and rotational direction of turns the programmable watch winding apparatus performs to wind a mechanical watch, and a control unit controlling a transmission device to rotate a rotatory base according to the users' input. Thereby, the programmable watch winding apparatus is fully controlled to automatically wind the mechanical watch carried thereon. | 2011-02-03 |
20110026375 | Stepping motor control circuit and analogue electronic timepiece - When a stepping motor is driven to rotate by a main driving pulse, if an induced signal exceeding a reference threshold voltage is detected only in a third segment, a pulse down operation is performed, and the main driving pulse is not changed when the same is detected in at least a first and the third segments. When it is detected only in a second and the third segments, a rank-up is performed without performing the driving by a correction drive pulse and, when it is not detected in at least the third segment, the rank up operation is performed after the driving by the correction driving pulse. | 2011-02-03 |
20110026376 | SPECTRUM SENSING NETWORK FOR COGNITIVE RADIOS - Cognitive radio devices, methods and systems are generally described. In some examples a communication system includes a cognitive device and a communications device. The cognitive device may include a cognitive receiver for processing a cognitive task, an antenna for receiving radio frequencies in communication with the receiver, and a communications port. The communications device may include a cognitive radio having a processor in communication with a cognitive receiver and a cognitive transmitter. The communications device may also include a portable power source in communication with the cognitive radio and an antenna for sending and receiving signals. A communications port can be arranged in communication with the communications device, where cognitive information can be communicated with the communications device. | 2011-02-03 |
20110026377 | Thermally-Assisted Magnetic Recording Head Comprising Light Source with Photonic-Band Layer - A thermally-assisted magnetic recording head is provided, in which a light source having sufficiently high output power for performing thermal-assist is disposed in the element-integration surface of the substrate to achieve improved mass-productivity. The head includes: a light source having a multilayered structure including a photonic-band layer and having a light-emitting surface opposed to the element-integration surface; a diffraction optical element that converges the emitted light; a light-path changer that changes the direction of the converged light; a waveguide that propagates the direction-changed light toward the opposed-to-medium surface; and a magnetic pole that generates write field. The surface-emitting type light source includes a photonic-band layer having a periodic structure in which a light from an active region resonates, and thus emits laser light on a quite different principle from a VCSEL. Therefore, the light source can be disposed in the element-integration surface, even though having sufficiently high output power. | 2011-02-03 |
20110026378 | Heat-assisted magnetic recording head with laser diode - A heat-assisted magnetic recording head includes a slider, and an edge-emitting laser diode fixed to the slider. The slider includes: a substrate; and an MR element, two reproduction wiring layers, a coil, two recording wiring layers, a magnetic pole, a near-field light generating element, and a waveguide that are stacked above the top surface of the substrate. The two reproduction wiring layers supply a sense current to the MR element. The two recording wiring layers supply a coil current to the coil. The laser diode has an emitting end face including an emission part for emitting laser light, and a bottom surface. The laser diode is arranged so that the bottom surface faces the top surface of the slider. As viewed from above, the laser diode does not overlap the two reproduction wiring layers but overlaps at least one of the two recording wiring layers. | 2011-02-03 |
20110026379 | Heat-assisted magnetic recording head with laser diode - A heat-assisted magnetic recording head includes a slider, and an edge-emitting laser diode fixed to the slider. The slider has a waveguide and an overcoat layer that covers the waveguide. The laser diode has an emitting end face including an emission part for emitting laser light, and a bottom surface. The laser diode is arranged so that the bottom surface faces the top surface of the slider. The waveguide has an incident end face opposed to the emission part of the laser diode. The overcoat layer has an end face that faces the emitting end face of the laser diode. As viewed from above, the end face of the overcoat layer has a convex shape protruding toward the emitting end face of the laser diode so that a part of the end face of the overcoat layer lying over the incident end face of the waveguide comes closest to the emitting end face of the laser diode. | 2011-02-03 |
20110026380 | REPRODUCING DEVICE AND REPRODUCING METHOD - A reproduction device, contains a rotatable operation disk part for performing an input related to reading of data stored in a memory and a capacitance sensor section for outputting a sensor value expressing a change of a capacitance according to depression of the rotatable operation disk part. The device also contains a storage part for storing a reference value corresponding to the sensor value obtained while the rotatable operation disk part is not depressed, and a control part for judging presence/absence of pressing on the rotatable operation disk part based on a vector quantity being a relative value obtained from a difference between the sensor value output from the capacitance sensor section and the reference value stored in the storage part. | 2011-02-03 |
20110026381 | OPTICAL DISK APPARATUS AND ITS REPRODUCING METHOD - Amplitude and frequency of a high-frequency signal superposed on a reproduction laser beam are changed in accordance with a reproduction spot diameter on the surface of the recording layer upon discrimination of an optical disk in initial adjustment after insertion of the optical disk and change of a layer of a multi-layer optical disk. Further, the high-frequency signal is not superposed on the reproduction laser beam until end of the discrimination and change to a target layer upon discrimination of the optical disk and change of a layer of a multi-layer optical disk. | 2011-02-03 |
20110026382 | OPTICAL PICKUP DEVICE, OPTICAL DISC DEVICE AND FOCUS ADJUSTING METHOD - An optical pickup device includes an astigmatism element which imparts astigmatism to laser light reflected on a disc, a spectral element which changes propagating directions of four light fluxes obtained by dividing a light flux of the laser light reflected on the disc to disperse the four light fluxes from each other, and a photodetector having a sensor group which receives the four light fluxes. The optical pickup device is further provided with a memory which holds a correction value for suppressing a DC component in a tracking error signal resulting from a positional displacement of the spectral element. The tracking error signal is corrected by the correction value to thereby suppress the DC component. | 2011-02-03 |
20110026383 | REPRODUCED SIGNAL EVALUATION METHOD AND WRITE ADJUSTMENT METHOD - The present invention aims to provide a reproduced signal evaluation method and a write adjustment method for offering a Blu-ray disc having a large storage capacity with excellent media compatibility. An evaluation index L-SEAT is calculated through signed addition using a Euclidean distance difference calculated from at least one of target signals in which a focused edge is shifted to the right and left, and the quality of the reproduced signal is evaluated based on the evaluation index. Write condition adjustment using the index enables write adjustment not depending on SNR and achieving high adjustment accuracy. | 2011-02-03 |
20110026384 | INFORMATION RECORDING APPARATUS AND INFORMATION RECORDING METHOD - An information recording apparatus for recording additional content on a medium on which a title including one or more files is already recorded, includes means for designating a title to be added on the medium; means for transmitting disc package information, the disc package information and unique IDs; means for receiving and additionally recording on the medium the title to be added generated in the content server, file names of files so as not to be the same as the file names of the files constituting the titles already recorded on the medium; means for receiving and additionally recording a new title for display of a menu screen on the medium, which is generated in the content server, so that the title to be added can be selected, on the basis of the disc package information; and means for receiving and additionally recording new disc package information on the medium. | 2011-02-03 |
20110026385 | SEMICONDUCTOR STORAGE DEVICE, SEMICONDUCTOR DEVICE AND OPTICAL DISC REPRODUCING DEVICE - A semiconductor storage device including a memory cell and having a function of refreshing the memory cell, includes a clock generation circuit configured to receive a first clock, generate a second clock based on an inversion of the first clock, and output the second clock. The semiconductor storage device performs operation of the refresh function in synchronization with at least one of the first and second clocks. | 2011-02-03 |
20110026386 | OPTICAL DISC RECORDING APPARATUS, COMPUTER-READABLE RECORDING MEDIUM RECORDING A FILE MANAGEMENT PROGRAM, AND OPTICAL DISC - An optical disc recording apparatus for recording a video object onto an optical disc. A recording area of the optical disc is divided into a plurality of zones which each include a plurality of adjacent tracks. The optical disc recording apparatus includes: a reading unit for reading from the optical disc the sector information showing data assignment for sectors on the optical disc; a recording unit for recording the video object onto the optical disc; and a control unit for controlling the reading unit and the recording unit. The control unit detects at least one series of consecutive unassigned sectors on the optical disc by referring to the read sector information. Each series has a total size greater than a minimum size and is located within a single zone. The minimum size corresponds to a data amount that ensures uninterrupted reproduction of the video object. The control unit also controls the recording unit to record the video object into the detected series. | 2011-02-03 |
20110026387 | RECORDING DEVICE AND METHOD OF ADJUSTING LASER POWER - A recording device including: an optical head section for irradiating a recording medium with laser to record and reproduce information; a laser driving section for driving the optical head section to output laser; and a control section for, in a process of adjusting recording laser power output from the optical head section, obtaining an evaluation value of a recorded area after a predetermined period of time elapsed since data was recorded as an evaluation value about a reproduction signal during reproduction of the recorded data, and adjusting recording laser power on the basis of the evaluation value after the predetermined period of time elapsed since data was recorded. | 2011-02-03 |
20110026388 | METHOD FOR CALIBRATION FOCUSING ERROR SIGNAL OF LIGHTSCRIBE DISC - A method for calibrating a focusing error signal of a lightscribe disc includes the following steps. An optical pickup head is moved to a focusing reference surface by utilizing radial voltages to some predetermined measuring positions to find and record the best gain value used to calibrate the asymmetry of the focusing error signal. The best gain fitting curve is formed by curve-fitting, based on the recorded radial voltages and the best gain values. The best gain value is obtained by an interpolation or extrapolation method, and used to calibrate the asymmetry of the focusing error signal of a lightscribe disc. | 2011-02-03 |
20110026389 | OPTICAL PICKUP DEVICE AND OPTICAL DISC DEVICE - An optical pickup device includes an astigmatism element which sets focal line positions to be defined by convergence of laser light away from each other, a diffraction element which diffracts four light fluxes obtained by a light flux of the laser light to disperse the four light fluxes from each other, and a photodetector having a first sensing section and a second sensing section which respectively receive m-th order diffraction light and n-th order diffraction light of the four light fluxes. In this arrangement, the first sensing section receives eight light fluxes obtained by dividing the four light fluxes of the m-th order diffraction light by two straight lines to output detection signals of the number less than eight. | 2011-02-03 |
20110026390 | OPTICAL INFORMATION RECORDING/REPRODUCING DEVICE, OPTICAL UNIT, AND OPTICAL INFORMATION RECORDING METHOD - An optical unit is provided with a light source; a light dividing means for dividing light emerging from the light source into a first light and a second light; a light converging means for converging the first and second lights at the same position in the recording layer in the manner that they face each other; a polarization state switching means for switching the polarization states of the first and second lights at the convergence point in the recording layer; and a light irradiation state switching means for switching between the state in which the optical cording medium is irradiated with both the first light and the second light and the state in which the optical recording medium is irradiated with only one of the first and second lights. | 2011-02-03 |
20110026391 | WRITE-ONCE INFORMATION RECORDING MEDIUM, INFORMATION RECORDING APPARATUS, INFORMATION RECORDING METHOD, INFORMATION REPRODUCING APPARATUS AND INFORMATION REPRODUCING METHOD - According to the present invention, multiple space bitmaps (SBMs #0 and #1 | 2011-02-03 |
20110026392 | Method and Apparatus of Subcarrier Grouping for a Wireless Communication System - A method sub-carrier grouping for a wireless communication system including a plurality of sub-carriers is disclosed. The method includes determining a coherent bandwidth of the plurality of sub-carriers, and dividing the plurality of sub-carriers into a plurality of sub-carrier groups according to the coherent bandwidth, wherein the size of each sub-carrier group is smaller than or equal to the coherent bandwidth. | 2011-02-03 |
20110026393 | RF SITE RESILIENCE USING MULTIPLE VISITOR LOCATION REGISTERS SIMULTANEOUSLY - A method and system are presented in which communication redundancy is provided. Multicast packets having the same audio and/or control data are simultaneously transmitted between an RF site and different switches through different communication links. The packets from the RF site have different origination addresses and a unique ID, which permits duplicate packets having different origination addresses but the same unique ID and data to be eliminated and only one set of packets to be transmitted over the air to a receiving end device for which the packets are intended. A switch communication link between the switches permits the primary switch to establish operating characteristics for the alternate switch. | 2011-02-03 |
20110026394 | DISTRIBUTED ETHERNET SYSTEM AND METHOD FOR DETECTING FAULT BASED THEREON - A distributed ethernet system including a plurality of switches, which switches are connected in sequence to form a ring, where after being synchronized in clock, each of the switches sequentially performs loop detection and protocol machine detection periodically according to a predetermined configuration, and sends a fault alarming message when a loop fault or a protocol machine fault occurs. A fault detecting method based on the system is further provided | 2011-02-03 |
20110026395 | Preserving Stable Calls During Failover - According to one method for preserving stable calls during failover, during a dialog between two user endpoints, a determination is made whether a standby call processor has become operational, such as when a corresponding primary call processor is in fault. Responsive to determining that the standby call processor has become operational, a signaling protocol message is received from a requester. A determination is made whether the message includes an in-dialog signaling protocol request. Responsive to determining that the message includes the in-dialog request, a determination is made whether a call state associated with the dialog is found in memory. Responsive to determining that the call state associated with the dialog is not found in memory, a non-call terminating error response is made responding to the in-dialog request. The non-call terminating error response may cause the requester to terminate the in-dialog request but not terminate the dialog. | 2011-02-03 |
20110026396 | DATA PROCESSING DEVICE - This invention provides a data processing device capable of operating a plurality of processing modules in parallel. Processes following a processing flow are assigned to the plural processing modules, respectively, and at least two of the processing modules are capable of running a same process. A network includes an arbitration circuit that, upon receiving a packet from a processing module, according to a process number attached to the packet, selects a processing module out of the processing modules capable of running the process, and outputs the packet to the selected processing module. This thus allows for autonomous transfer of a packet between each processing module and makes it possible to operate the processing modules in parallel. | 2011-02-03 |
20110026397 | CONNECTIVITY FAULT MANAGEMENT TRAFFIC INDICATION EXTENSION - A method in a Maintenance Association Endpoint, MEP, for controlling traffic between a first network element and a second network element connected by a working Traffic Engineering Service Instance, TESI, and a protection TESI. The first network element sets a Traffic field in a Connectivity Check Message, CCM, sent to the second network element. The Traffic field may be set by utilizing a reserved bit within a Flags field of the CCM. The Traffic field indicates which TESI is being utilized to transport the traffic. The second network element takes action to control the traffic based upon a value of the Traffic field in the received CCM. When the Traffic field value in the received CCM does not match the Traffic field value in CCMs sent from the second network element for a predefined period of time, the second network element moves the traffic from its current TESI to the other TESI. | 2011-02-03 |
20110026398 | Dynamic Traffic Rearrangement to Enforce Policy Change in MPLS Networks - A system and method of rearranging Label Switched Paths (LSPs) and rerouting traffic in a DiffServ-enabled Multi-Protocol Label Switched (MPLS) network is disclosed. The system periodically monitors network performance, and rearranges LSPs and reroutes traffic through existing or new Label Switched Paths (LSPs) based on network performance and network bandwidth utilized by various DiffServ classes. | 2011-02-03 |
20110026399 | ADMISSION CONTROL AND ROUTING IN A PACKET NETWORK - Embodiments of the invention provide a network management sub-system which is preferably logically separate from the routing nodes (including gateway nodes) of a network. The network management sub-system receives load information relating to present packet flows on existing predetermined paths in the network, and when a request for admittance of a new packet flow is received, is able to make a decision as to whether the new flow should be both: i) admitted to the network; and ii) on to which path; in substantially the same process step. This is possible because the admission control and routing algorithms are integrated into a single process, the result of which provides both an admission control decision as well as a routing decision at the same time. By performing such an operation in a management sub-system which is separate from the routing nodes, there is no need for such functionality to be duplicated in nodes across the network, and instead the routing nodes are relieved of the burden of having to make such decision themselves. As a consequence, the network nodes can be kept simpler, and network control can be retained by the network operator in the management sub-system. | 2011-02-03 |
20110026400 | NETWORK ON CHIP WITH QUALITY OF SERVICE - The present invention relates to a method for limiting the throughput of a communication in a meshed network, comprising the following steps: allocating fixed paths to communications likely to be established on the network; identifying the communications likely to take a mesh segment; allocating respective throughput quotas to the identified communications such that the sum of these quotas is less than or equal to a nominal throughput of said segment; and measuring the throughput of each communication at the input of the network and suspending the communication when its quota is reached. | 2011-02-03 |
20110026401 | TRANSMISSION RATE CONTROL METHOD AND COMMUNICATION DEVICE - There is provided a transmission rate control method. In this method, data is transmitted to a receiver at the most recent transmission rate R | 2011-02-03 |
20110026402 | TCP ACKNOWLEDGE FOR AGGREGATED PACKET - A method and apparatus according to one embodiment of the invention are operable to detect the accumulation of redundant ACKs (acknowledgment signals) in a queue for streaming data packet units, and to delete a portion of the redundant ACKs to improve transmission efficiencies. In one embodiment, only the most relevant ACK is kept before the ACKs are processed for transmission. In an alternate embodiment, a ratio of defined that limits the maximum number of redundant ACKs that may be deleted. This ratio is based upon a transmission window size. The teachings of the present disclosure may also be applied to flow control in a more general sense in which a plurality of redundant signals responses are being transmitted after being aggregated. | 2011-02-03 |
20110026403 | TRAFFIC MANAGEMENT OF CLIENT TRAFFIC AT INGRESS LOCATION OF A DATA CENTER - A switch device includes a packet-forwarding table for providing traffic management across servers in a server group. Each table entry maps a hash value to a server in the server group. A hash value is computed from data in one or more fields in the header of a received packet. The computed hash value is used as an index into the packet-forwarding table to access a table entry and to identify from the table entry the server in the server group to which the table entry maps the computed hash value. The switch device forwards the packet to the identified server. Implementing traffic management decisions in hardware enables packet switching at the line rate of the switch ports. In addition, the hardware-based traffic management performed by the switch device eliminates session tables and the memory to store them, enabling the switch device to handle an unlimited number of client connections. | 2011-02-03 |
20110026404 | SYSTEMS AND METHODS FOR FACILITATING COMMUNICATIONS OVER A SHARED CHANNEL - A node may include a receiver configured to receive signals transmitted from a gateway and a logic device coupled to the receiver. The node may also include a memory configured to store label information identifying a data packet stored in the node. The logic device may be configured to receive a message from the gateway, where the message includes label information, and access the memory to identify a data packet based on the label information included in the message. The node may also include a transmitter configured to transmit the data packet to the gateway over a channel shared with a number of other nodes. | 2011-02-03 |
20110026405 | ROUTER, INFORMATION PROCESSING DEVICE HAVING SAID ROUTER, AND PACKET ROUTING METHOD - A router includes: a flit arrival time management section that records flit arrival time which is the time at which the packet is received for the first time, transmission interval of the packet which are acquired from a control packet transmitted prior to the first transmission of a packet and input and output channels of the control packet and requires a crossbar section for an output channel from which the packet is supposed to be output before the flit arrival time; a switch assignment section that performs arbitration on the output channel request and performs input/output connection relationship setting processing; and a switch assignment verification section that verifies whether a result of the input/output connection relationship setting processing coincides with the actual routing of the packet. The cross bar section performs switching of the arriving packet using a result of the input/output connection relationship processing. | 2011-02-03 |
20110026406 | APPARATUS AND METHODS FOR CAPTURING DATA PACKETS FROM A NETWORK - In one embodiment, data packets are captured from a network using a physical, network-connectable data capture probe. As the data packets are captured, the data packets are time-stamped with time-of-capture time-stamps. The time-stamped data packets are then stored; and in parallel, the time-stamped data packets are forwarded to at least one consumer in real-time. | 2011-02-03 |
20110026407 | CONTROLLER - This invention enables an abnormality analysis to be easily and reliably performed in the FA system of the EtherCAT (registered trademark). A controller has a protocol monitor function of operating in a monitor system program, and constantly monitors data communicated with a remote device. The controller has an abnormality diagnosis function of detecting abnormality, and thus holds the data monitored immediately before when abnormality is detected. As the protocol monitor function is incorporated, a protocol monitor does not need to be newly plugged into the network as an external device after the occurrence of abnormality, and the data that becomes the cause can be held from the abnormality that occurred first by monitoring from the beginning of the operation of the system and can be used for analysis. | 2011-02-03 |
20110026408 | ERROR RATE MANAGEMENT - The invention deals with the adjustment of the nominal target error rate for transmission of data from a priority queue to a new predetermined target error rate depending on the state of the priority queue. Usually, the adjustment to the new predetermined target error rate will be to a predefined lower target error rate based on states of the priority queue, such as amount of data in the priority queue, time passed since the latest transmission of data from the priority queue, whether the amount of data in the priority queue will fit into one transport block, whether the data unit to be transmitted for the priority queue is the first or last data unit in the priority queue and may also be based on the type of data stored in the priority queue. There may be more than one such priority queue. | 2011-02-03 |
20110026409 | Method, Devices and System for Local Collision Avoidance for Random Access in Relay Networks - An apparatus such as a user equipment is in an embodiment of the invention configured to broadcast an access request to at least one neighboring node, the access request containing signature information indicating a user identifier, to check whether a collision indicator is received from a relay node, and to send another access request depending on a received collision indicator. The collision indicator may e.g. be a signature collision indicator, received from the node in case of colliding users, or a collision indicator of transmission received when transmissions of access requests are colliding at the node. A relay node may be configured to receive an access request from a user equipment, to detect a collision, and to inform the user equipment on a detected collision, indicating a type of collision. | 2011-02-03 |
20110026410 | System and Method for Comparing Packet Traces for Failed and Successful Communications - The system and method get a packet trace for a failed communication and a packet trace for a successful communication. The two packet traces are generated with packets from a common protocol(s) shared by the two communications. The failed and successful communications have at least some network elements in common. A field(s) in the common protocol(s) is identified. The field(s) is updated to be the same in both packet traces. The two packet traces are then compared to produce a list of remaining differences that can be used to diagnose problems in the failed communication. The list can also be compared to bills of materials for the failed and successful communications to further enhance diagnosis of the failed communication. | 2011-02-03 |
20110026411 | METHODS AND SYSTEMS FOR FAIL-SAFE COMMUNICATION - A communication network is described. The network includes communication media and a plurality of network nodes coupled by the communication media. Each of the plurality of network nodes includes a first communication channel and a second communication channel. The first communication channel includes a first physical layer transceiver (PHY device) and the second communication channel includes a second PHY device. The plurality of network nodes are coupled in a dual ring-type topology. | 2011-02-03 |