05th week of 2016 patent applcation highlights part 59 |
Patent application number | Title | Published |
20160035356 | EDITING OF HIGHER-ORDER AMBISONIC AUDIO DATA - In general, techniques are described for editing of higher-order ambisonic audio data. A device comprising a memory and one or more processors may be configured to perform the techniques. The memory may be configured to store spherical harmonic (SH) basis functions. The one or more processors may be configured to manipulate the SH basis functions associated with higher order ambisonics coefficients to alter a direction of an audio object represented by the higher order ambisonics coefficients. | 2016-02-04 |
20160035357 | AUDIO SIGNAL ENCODER COMPRISING A MULTI-CHANNEL PARAMETER SELECTOR - An apparatus comprising: a channel analyser configured to determine for a first frame of at least one audio signal a set of first frame audio signal multi-channel parameters; a multichannel parameter selector configured to select for the first frame a sub-set of the set of first frame audio signal multi-channel parameters based on a value associated with the first frame; and a multichannel parameter encoder configured to generate an encoded first frame audio signal multi-channel parameter based on the selected sub-set of the set of first frame audio signal multi-channel parameters. | 2016-02-04 |
20160035358 | SYSTEMS, METHODS, APPARATUS, AND COMPUTER-READABLE MEDIA FOR THREE-DIMENSIONAL AUDIO CODING USING BASIS FUNCTION COEFFICIENTS - Systems, methods, and apparatus for a unified approach to encoding different types of audio inputs are described. | 2016-02-04 |
20160035359 | SYSTEM AND METHOD TO REDUCE TRANSMISSION BANDWIDTH VIA IMPROVED DISCONTINUOUS TRANSMISSION - The present disclosure is directed towards a method for discontinuous transmission (“DTX”) bandwidth reduction. The method may include receiving, at a processor, a frame identified as speech and determining that the frame was mistakenly identified as speech based upon, at least in part, a voice activity detection algorithm. The method may further include labeling the frame as a silence indicator frame. | 2016-02-04 |
20160035360 | Method and Means of Encoding Background Noise Information - The invention relates to a method and means for encoding background noise information during voice signal encoding methods. A basic idea of the invention is to provide the scalability known for transmitting voice information in a similar manner when forming an SID frame. The invention provides encoding of a narrowband first component and of a broadband second component of a piece of background noise information and formation of an SID frame which describes the background noise with separate areas for the first and second components. | 2016-02-04 |
20160035361 | Harmonic Transposition in an Audio Coding Method and System - The present invention relates to transposing signals in time and/or frequency and in particular to coding of audio signals. More particular, the present invention relates to high frequency reconstruction (HFR) methods including a frequency domain harmonic transposer. A method and system for generating a transposed output signal from an input signal using a transposition factor T is described. The system comprises an analysis window of length L | 2016-02-04 |
20160035362 | METHOD AND APPARATUS FOR ENCODING AND DECODING NOISE SIGNAL - Provided is a method and apparatus for encoding/decoding an audio signal. Sections which are not used to output noise components near important spectral components and sub-bands which are not used to output noise components, are determined to be encoded or decoded, so that the efficiency of encoding and decoding an audio signal increases, and sound quality can be improved using less bits. | 2016-02-04 |
20160035363 | METHOD AND APPARATUS FOR ENCODING AND DECODING NOISE SIGNAL - Provided is a method and apparatus for encoding/decoding an audio signal. Sections which are not used to output noise components near important spectral components and sub-bands which are not used to output noise components, are determined to be encoded or decoded, so that the efficiency of encoding and decoding an audio signal increases, and sound quality can be improved using less bits. | 2016-02-04 |
20160035364 | METHOD AND DEVICE FOR ENCODING A HIGH FREQUENCY SIGNAL, AND METHOD AND DEVICE FOR DECODING A HIGH FREQUENCY SIGNAL - A method and a device for encoding a high frequency signal, and a method and a device for decoding a high frequency signal are provided, which relate to encoding and decoding technology. The method for encoding a high frequency signal includes: determining a signal type of a high frequency signal of a current frame; smoothing and scaling time envelopes of the high frequency signal of the current frame and obtaining time envelopes of the high frequency signal of the current frame that require to be encoded, if the high frequency signal of the current frame is a non-transient signal and a high frequency signal of the previous frame is a transient signal; and quantizing and encoding the time envelopes of the high frequency signal of the current frame that require to be encoded, and frequency information and signal type information of the high frequency signal of the current frame. | 2016-02-04 |
20160035365 | SOUND ENCODING DEVICE, SOUND ENCODING METHOD, SOUND DECODING DEVICE AND SOUND DECODING METHOD - A sound encoding device includes: a processor; and a memory which stores a plurality of instructions, which when executed by the processor, cause the processor to execute: converting a sound signal into a frequency signal by time-frequency converting the sound signal in a unit of a frame having a given time length; detecting a first frequency band in which a phase component of the frequency signal is random for each frame; determining outline information representative of an outline of an amplitude component of the frequency signal included in the first frequency band for each frame; encoding the frequency signal included in a frequency band other than the first frequency band for each frame; and producing a data stream including the encoded frequency signal and the outline information. | 2016-02-04 |
20160035366 | ECHO SUPPRESSION DEVICE AND ECHO SUPPRESSION METHOD - An echo suppression device includes a processor; and a memory which stores a plurality of instructions, which when executed by the processor, cause the processor to execute: generating a corrected sound signal by suppressing an echo signal representing an echo generated by collecting, by a sound input unit, a sound arising from a reproduction sound signal reproduced by a sound output unit; obtaining a gain to attenuate the corrected sound signal according to a degree of distortion of the echo signal with which intensity of the echo signal non-linearly changes with respect to an intensity change of the reproduction sound signal; and suppressing the corrected sound signal according to the gain. | 2016-02-04 |
20160035367 | SPEECH DEREVERBERATION METHODS, DEVICES AND SYSTEMS - Improved audio data processing method and systems are provided. Some implementations involve dividing frequency domain audio data into a plurality of subbands and determining amplitude modulation signal values for each of the plurality of subbands. A band-pass filter may be applied to the amplitude modulation signal values in each subband, to produce band-pass filtered amplitude modulation signal values for each subband. The band-pass filter may have a central frequency that exceeds an average cadence of human speech. A gain may be determined for each subband based, at least in part, on a function of the amplitude modulation signal values and the band-pass filtered amplitude modulation signal values. The determined gain may be applied to each subband. | 2016-02-04 |
20160035368 | APPARATUS, MEDIUM AND METHOD TO ENCODE AND DECODE HIGH FREQUENCY SIGNAL - A method and apparatus to encoding or decoding an audio signal is provided. In the method and apparatus, a noise-floor level to use in encoding or decoding a high frequency signal is updated according to the degree of a voiced or unvoiced sound included in the signal. | 2016-02-04 |
20160035369 | METHOD AND APPARATUS FOR ADAPTIVELY ENCODING AND DECODING HIGH FREQUENCY BAND - Provided are a method and apparatus for encoding and decoding an audio signal. According to the present application, a signal of a high frequency band above a preset frequency band is adaptively encoded or decoded in the time domain or in the frequency domain by using a signal of a low frequency band below the preset frequency band. As such, the sound quality of a high frequency signal is not deteriorate even when an audio signal is encoded or decoded by using a small number of bits and thus coding efficiency may be maximized. | 2016-02-04 |
20160035370 | Formant Dependent Speech Signal Enhancement - An arrangement is described for speech signal processing. An input microphone signal is received that includes a speech signal component and a noise component. The microphone signal is transformed into a frequency domain set of short-term spectra signals. Then speech formant components within the spectra signals are estimated based on detecting regions of high energy density in the spectra signals. One or more dynamically adjusted gain factors are applied to the spectra signals to enhance the speech formant components. | 2016-02-04 |
20160035371 | Method and Apparatus to Determine and Use Audience Affinity and Aptitude - One embodiment is a method of presenting an audio or audio-visual work which includes: (a) detecting media work content properties in an audio portion of the audio or audio-visual work using a media work content properties detection apparatus; (b) associating a presentation rate of the audio of the audio portion of the audio or audio-visual work with the detected media work content properties; and (c) presenting the portion of the audio or audio-visual work using the media work content properties detection apparatus so that the audio is presented at the presentation rate; wherein the media work content properties comprise one or more indicia of words of interest; and wherein the audio or audio-visual work includes conversations. | 2016-02-04 |
20160035372 | READING NARROW DATA TRACKS WITH MULTIPLE WIDE READERS - Technologies are described herein for utilizing multiple, wide readers to read narrow data tracks on a magnetic recording media in a storage device. A system for reading a data track on a magnetic recording media comprises a plurality of reader elements, the width of each reader element being an integer greater than 1 multiple of a width of the data tracks on the recording media. The system further comprises a multi-reader decoder module operably connected to the plurality of reader elements. Each of the reader elements is configured to read a magnetic signal from the magnetic recording media. The multi-reader decoder module is configured to receive a read signal from each of the reader elements, and decode the data on the data track based on the read signals from the reader elements. | 2016-02-04 |
20160035373 | MAGNETIC RECORDING HEAD AND MAGNETIC RECORDING AND REPRODUCING DEVICE - According to one embodiment, a magnetic recording head records information in a magnetic recording medium by shingled magnetic recording. The magnetic recording head includes a magnetic pole and a shield opposing the magnetic pole. The magnetic pole has a shield-opposing surface opposing the shield. The shield-opposing surface includes a first portion and a second portion. A position of the second portion in a track width direction is different from a position of the first portion in the track width direction, the track width direction intersecting a first direction from the magnetic pole toward the shield. The first portion records the information in the magnetic recording medium after the second portion in the shingled magnetic recording. A first distance between the first portion and the shield is shorter than a second distance between the second portion and the shield. The shield-opposing surface is tilted with respect to the first direction. | 2016-02-04 |
20160035374 | MAGNETIC RECORDING HEAD AND MAGNETIC RECORDING AND REPRODUCING DEVICE - According to one embodiment, a magnetic recording head includes a magnetic pole and a shield. The shield has a first opposing surface opposing the magnetic pole. The first opposing surface includes a first opposing portion. The magnetic pole and the first opposing portion overlap in a first direction from the magnetic pole toward the shield. The first opposing portion includes a first protrusion. | 2016-02-04 |
20160035375 | Data Storage Device with Phase Lock Spin-Torque Oscillation Stabilization - A data storage device can be configured at least with a first spin-torque oscillator disposed between and contacting a write pole and a shield on an air bearing surface. A second spin-torque oscillator can be disposed between and contact the write pole and shield with the second spin-torque oscillator separated from the air bearing surface by a first stabilization distance and from the first spin-torque oscillator by a second stabilization distance. The first and second spin-torque oscillators can be configured to magnetostatically couple and phase lock to produce a single microwave frequency in response to a bias field. | 2016-02-04 |
20160035376 | Data Reader with Tuned Microstructure - A data reader may be configured with a tuned microstructure by initially cooling a substrate to a temperature of 100K or lower and subsequently depositing at least one layer of a data reader on the substrate while the substrate is maintained at the temperature. The tuned microstructure may consist of at least a grain size, grain size distribution, interface quality between multiple layers of the data reader, resistance-area product, and magnetoresistance. | 2016-02-04 |
20160035377 | SPIN-VALVE ELEMENT, HARD DISK HEAD, AND HARD DISK HEAD ASSEMBLY - According to one embodiment, a spin-valve element includes a nonmagnetic unit, a first magnetic unit, a second magnetic unit, a third magnetic unit, a current source, and a voltage sensor. The current source is connected to the second magnetic unit and the third magnetic unit. The current source causes a current to flow between the second magnetic unit and the third magnetic unit via the nonmagnetic unit. The voltage sensor is connected to the second magnetic unit and the third magnetic unit. A maximum length of a contact surface between the first magnetic unit and the nonmagnetic unit is not more than a spin diffusion length of the nonmagnetic unit. A length of the first magnetic unit in a direction orthogonal to the contact surface is not more than 3 times a spin diffusion length of the first magnetic unit. The first magnetic unit does not contact an external electrode. | 2016-02-04 |
20160035378 | Reader Designs of Shield to Shield Spacing Improvement - A MR sensor is disclosed with an antiferromagnetic (AFM) layer recessed behind a first stack of layers including a free layer and non-magnetic spacer to reduce reader shield spacing and enable increased areal density. The AFM layer may be formed on a first pinned layer in the first stack that is partially embedded in a second pinned layer having a front portion at an air bearing surface (ABS) to improve pinning strength and avoid a morphology effect. In another embodiment, the AFM layer is embedded in a bottom shield and surrounds the sidewalls and back side of an overlying free layer in the sensor stack to reduce reader shield spacing. Pinning strength is improved because of increased contact between the AFM layer and a pinned layer. The free layer is aligned above a bottom shield center section. | 2016-02-04 |
20160035379 | DEVICES INCLUDING A GAS BARRIER LAYER - Devices that include a near field transducer (NFT); a gas barrier layer positioned on at least a portion of the NFT; and a wear resistance layer positioned on at least a portion of the gas barrier layer wherein the gas barrier layer includes tantalum oxide (TaO), titanium oxide (TiO), chromium oxide (CrO), silicon oxide (SiO), aluminum oxide (AlO), titanium oxide (TiO), zirconium oxide (ZrO), yttrium oxide (YO), magnesium oxide (MgO), beryllium oxide (BeO), niobium oxide (NbO), hafnium oxide (HfO), vanadium oxide (VO), strontium oxide (SrO), or combinations thereof; silicon nitride (SiN), aluminum nitride (Al), boron nitride (BN), titanium nitride (TiN), zirconium nitride (ZrN), niobioum nitride (NbN), hafnium nitride (HfN), chromium nitride (CrN), or combinations thereof silicon carbide (SiC), titanium carbide (TiC), zirconium carbide (ZrC), niobioum carbide (NbC), chromium carbide (CrC), vanadium carbide (VC), boron carbide (BC), or combinations thereof or combinations thereof. | 2016-02-04 |
20160035380 | SOFT MAGNETIC UNDERLAYER HAVING HIGH TEMPERATURE ROBUSTNESS FOR HIGH AREAL DENSITY PERPENDICULAR RECORDING MEDIA - In one embodiment, a perpendicular magnetic recording medium includes: a substrate; and a soft magnetic underlayer structure positioned above the substrate, where the soft magnetic underlayer includes: a coupling layer; a first soft underlayer positioned above the coupling layer; and a second soft underlayer positioned below the coupling layer, where a difference between a magnetic flux density of the soft magnetic underlayer structure at 25° C. and a magnetic flux density of the soft underlayer structure at 85° C. is less than or equal to about 10% of the magnetic flux density of the soft magnetic underlayer structure at 25° C. | 2016-02-04 |
20160035381 | PERPENDICULAR RECORDING MEDIA HAVING HIGH-TEMPERATURE ROBUSTNESS - A perpendicular magnetic recording medium with an grain isolation layer is disclosed. In one embodiment, a perpendicular magnetic recording medium comprises a substrate, a soft non-magnetic under layer formed over the substrate, a granular layer comprising an exchange control layer and a recording layer formed over the soft non-magnetic under layer, wherein a difference between a level at 25 deg C. and a level at 85 deg C. of a slope at a coercivity of a magnetization process curve having saturation magnetization normalized at 1 is obtained when a magnetic field is applied perpendicular to said medium, is 10% or less. | 2016-02-04 |
20160035382 | MAGNETIC RECORDING MEDIUM AND MAGNETIC RECORDING AND REPRODUCING APPARATUS - According to one embodiment, a magnetic recording medium includes an orientation control layer formed on a non-magnetic substrate, the orientation control layer made of a Ni alloy or Ag alloy having fcc structure, a non-magnetic seed layer made of Ag, Ge, and a metal X selected from the group consisting of Al, Mg, Au, and Ti, a non-magnetic intermediate layer made of Ru or Ru alloy, and a magnetic recording layer. The orientation control layer is in contact with the non-magnetic seed layer. | 2016-02-04 |
20160035383 | THERMAL-ASSISTED MAGNETIC RECORDING DEVICE CAPABLE OF WRITING MAGNETIC PATTERNS ON LOWER MULTI-STEP DRIVING SIGNALS - According to one embodiment, there is provided a magnetic disk device including a light irradiation element and a control unit. The light irradiation element is configured to irradiate a magnetic disk with light according to a driving signal. The control unit is configured to lower, in multistep manner, active level of the driving signal contributing intensity of the light when a low frequency pattern of write data is recorded into the magnetic disk. | 2016-02-04 |
20160035384 | SKEW-TOLERANT MULTIPLE-READER ARRAY IN ARRAY-READER BASED MAGNETIC RECORDING - A method for enhancing read performance in an ARMR system includes: obtaining CTS information for a plurality of readers in a multi-reader head of the ARMR system, the CTS information defining a relationship between skew angle and CTS between respective combinations of subsets of the readers; determining, as a function of the CTS information, a subset of the readers which provides enhanced read performance among the readers for each of a plurality of skew angles; assigning a weight value to each of a plurality of read signals generated by a corresponding one of the readers for each of the skew angles, the weight value being indicative of a performance of the corresponding one of the readers relative to one another; and decoding information read from at least one target track of a magnetic storage medium being read as a function of the read signals and corresponding weight values. | 2016-02-04 |
20160035385 | CONTAMINATION REDUCTION HEAD FOR MEDIA - A cleaning head and methods for removing contaminants from a data storage media, the cleaning head having a cleaning surface comprising a self-assembled monolayer, with the cleaning surface leading a read/write transducer. The self-assembled monolayer is selected to have a terminal functional group that has a high affinity to the contaminant(s) desired to be attracted and/or removed. | 2016-02-04 |
20160035386 | EDITING OF HIGHER-ORDER AMBISONIC AUDIO DATA - In general, techniques are described for audio editing of higher-order ambisonic audio data. A device comprising a memory and one or more processors may be configured to perform the techniques. The memory may be configured to store a higher order ambisonic (HOA) representation of the audio object. The one or more processors may be configured to add a source tail to the HOA representation of the audio object by storing one or more spherical harmonic (SH) basis functions associated with the audio object to a buffer. | 2016-02-04 |
20160035387 | AUTOMATED STORY GENERATION - Automatic story production is implemented by the utilization of theme scripts with user assets to generate a quality finished product with minimum user input or direction. A user chooses a predesigned theme script to be applied to the user's assets to automatically create a story with a particular look and feel. Metadata and feature information, when available, is automatically gathered from the user assets to personalize the generated story. A user can include additional information and/or alter any aspect of the generated story to further personalize the resultant finished product. | 2016-02-04 |
20160035388 | VIDEO CHUNKING FOR ROBUST, PROGRESSIVE UPLOADING - Devices and methods are provided herein relating to video chunking for robust, progressive upload. Video can be parsed to determined byte offsets associated with prospective chunk boundaries. Chunks can be generated based on the prospective chunk boundaries and a preferred chunk size. Sample tables can be generated for each chunk. The chunks can be fully self contained, in that they can be received and transcoded independently of other chunks. Thus, if one chunk fails, only that chunk needs to be retransmitted versus the entire video. | 2016-02-04 |
20160035389 | VIDEO-SEGMENT IDENTIFICATION SYSTEMS AND METHODS - Summarization segments of an encoded video can be efficiently identified, without the need to decode the encoded video to obtain image data, by analyzing encoded-buffer-size deltas, each indicating an encoded-buffer-size difference between a pair of intra-coded frames of an encoded video. | 2016-02-04 |
20160035390 | INFORMATION PROCESSING APPARATUS DISPLAYING INDICES OF VIDEO CONTENTS, INFORMATION PROCESSING METHOD AND INFORMATION PROCESSING PROGRAM - An information processing apparatus that includes: a storing portion to store video data: and a display portion to display a first thumbnail generated by decoding the video data, wherein if a scroll instruction is received prior to completion of generation of the first thumbnail, the display portion displays a second thumbnail corresponding to the video data. | 2016-02-04 |
20160035391 | FORENSIC VIDEO RECORDING WITH PRESENCE DETECTION - At a high level, embodiments of the invention relate to augmenting video data with presence data derived from one or more proximity tags. More specifically, embodiments of the invention generate forensically authenticated recordings linking video imagery to the presence of specific objects in or near the recording. One embodiment of the invention includes video recording system comprising a camera, a wireless proximity tag reader, a storage memory and control circuitry operable to receive image data from the camera receive a proximity tag identifier identifying a proximity tag from the proximity tag reader, and store an encoded frame containing the image data and the proximity tag identity in the storage memory. | 2016-02-04 |
20160035392 | SYSTEMS AND METHODS FOR CLIPPING VIDEO SEGMENTS - Systems and methods for streaming video, interacting with video content, and sharing video content are disclosed herein. Other embodiments are also disclosed herein. | 2016-02-04 |
20160035393 | STORAGE CASE - The invention relates to a storage case comprising two parts, each with an outer side and an inner side, where a side area on each part may comprise a connecting element for hinged connection with the other part, where at least one of the two parts on the outer side comprises a circumferential frame connectable with the part and with a central aperture and where further a display element is positioned on the outer side of the at least one part and interlocked between the outer side and the frame connectable to the part. | 2016-02-04 |
20160035394 | Discrete Three-Dimensional Memory - The present invention discloses a discrete three-dimensional memory (3D-M). It comprises at least a 3D-array die and at least a peripheral-circuit die. At least an off-die peripheral-circuit component of the 3D-M arrays is located on the peripheral-circuit die instead of the 3D-array die. The 3D-array die and the peripheral-circuit die have substantially different back-end-of-line (BEOL) structures. | 2016-02-04 |
20160035395 | Discrete Three-Dimensional Vertical Memory - The present invention discloses a discrete three-dimensional vertical memory (3D-M | 2016-02-04 |
20160035396 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes a plurality of wiring patterns of wiring lines disposed in parallel in a line-and-space pattern in a predetermined pitch and extend in a first direction in a first region, first bending patterns that extend pairs of the wiring lines in a second in a second region adjacent to the first region, second bending patterns extend the pairs of wiring lines in opposite directions along the orientation of the first direction in the second region, and dummy patterns separated from the two second bending patterns at a predetermined distance. | 2016-02-04 |
20160035397 | OVERVOLTAGE PROTECTION FOR A FINE GRAINED NEGATIVE WORDLINE SCHEME - A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage. | 2016-02-04 |
20160035398 | MEMORY DEVICES - A method and a system for memory cell programming and erasing with refreshing operation are disclosed. The system includes a selecting module, a processing module and a refresh module. In the method, at first, a target memory cell from a plurality of memory cells in a memory device is selected. Thereafter, the target memory cell belonging to a line of the matrix is programmed or erased by applying a selecting voltage on the target memory cell and a location-related memory cell belonging to the line of the matrix. Then, a refreshing operation to refresh the location-related cell is performed | 2016-02-04 |
20160035399 | METHOD AND APPARATUS FOR ASYNCHRONOUS FIFO CIRCUIT - The disclosure provides an asynchronous FIFO circuit that includes a data memory which is coupled to a write data path and a read data path. The data memory receives a write clock and a read clock. A FIFO write pointer counter receives a write enable signal and the write clock. The FIFO write pointer counter provides a FIFO write pointer signal to the data memory. A FIFO read pointer counter receives a read enable signal and the read clock. The FIFO read pointer counter provides a FIFO read pointer signal to the data memory. A control circuit receives the write enable signal, the read enable signal, the FIFO write pointer signal, the FIFO read pointer signal, the write clock and the read clock. The control circuit generates a memory full signal when the data memory is full and a memory empty signal when the data memory is empty. | 2016-02-04 |
20160035400 | BANK CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A bank control circuit includes an implicit signal generation unit suitable for activating an implicit signal when a first active signal corresponding to a bank which is in an activated state bank, among a plurality of banks; and a delay unit suitable for delaying the implicit signal by a predetermined time, wherein the bank corresponding to the first active signal is precharged based on the implicit signal and activated again based on the delayed implicit signal. | 2016-02-04 |
20160035401 | PRECESSIONAL MAGNETIZATION REVERSAL IN A MAGNETIC TUNNEL JUNCTION WITH A PERPENDICULAR POLARIZER - A magnetic device that includes a perpendicular magnetized polarizing layer configured to provide a first spin-torque and an in-plane magnetized free layer having a magnetization vector having at least a first stable state and a second stable state. The magnetic device also includes a reference layer configured to provide a second spin-torque. The first spin-torque and the second spin-torque can combine. The in-plane magnetized free layer and the reference layer form a magnetic tunnel junction and the combined first spin-torque and second spin-torque influences the magnetic state of the in-plane magnetized free layer. An application of a voltage pulse, having either positive or negative polarity and a selected amplitude and duration, through the magnetic device causes the magnetization vector to oscillate between the first stable state and the second stable state for a portion of the duration regardless of an initial state of the magnetization vector. | 2016-02-04 |
20160035402 | UNIT ARRAY OF A MEMORY DEVICE, MEMORY DEVICE, AND MEMORY SYSTEM INCLUDING THE SAME - A memory device includes a memory array including a plurality of sections, each including a plurality of memory cells and at least one reference cell. The memory device may also include a plurality of sense amplifier circuits respectively corresponding to the plurality of sections, and a plurality of switch circuits, each switch circuit connected between a respective section and sense amplifier circuit. Each switch circuit may be configured to select between communicatively connecting a first column of memory cells or a reference cell to a corresponding sense amplifier. | 2016-02-04 |
20160035403 | VOLTAGE GENERATOR AND MEMORY DEVICE INCLUDING THE SAME - A voltage generator comprises a reference voltage providing unit, a comparison voltage providing unit and a comparison unit. The reference voltage providing unit comprises a reference element and a current source series-connected between a power supply voltage and a ground voltage, and outputs a reference voltage through a reference voltage node, which couples the reference element to the current source. The comparison voltage providing unit comprises a magnetic tunnel junction unit coupled between the power supply voltage and a comparison voltage node, and a transistor switch unit coupled between the ground voltage and the comparison voltage node. The comparison unit provides a write voltage to the transistor switch unit by comparing the reference voltage and the comparison voltage. The voltage generator according to example embodiments may increase the performance of the memory device by performing the write operation using stable multi voltages that are applied to a word line. | 2016-02-04 |
20160035404 | MAGNETIC RAM ARRAY ARCHITECTURE - A magnetic random access memory (MRAM) array including: a plurality of MRAM cells arranged in an array configuration, each comprising a first type nTron and a magnetic memory element; a wordline select circuit comprising of a second type nTron to drive a plurality of parallel wordlines; and a plurality of bitline select circuits, each comprising of said second type nTron for writing to and reading from a column of memory cells in the array and each capable of selecting a single MRAM cell for a memory read or write operation, wherein the second nTron has a higher current drive than the first nTron. | 2016-02-04 |
20160035405 | SEMICONDUCTOR DEVICE CAPABLE OF REDUCING POWER CONSUMPTION - According to one embodiment, a semiconductor device includes a first transistor of a first conductivity type, and a first logical circuit. The first transistor of the first conductivity type is connected between a first node to which a power supply voltage is applied and a second node. The first transistor is turned on in the initial stage of an active cycle, and is turned off by applying the power supply voltage to the second node. The first logical circuit is driven by the power supply voltage applied to the second node. The first logical circuit outputs a voltage which is lower than the power supply voltage in the active cycle based on an input signal supplied thereto. | 2016-02-04 |
20160035406 | FIXED VOLTAGE SENSING IN A MEMORY DEVICE - Methods for sensing ferroelectric memory devices and apparatuses using the same have been disclosed. One such apparatus includes a ferroelectric memory cell coupled to a data line, a reference capacitance, and a common node coupled between the data line and the reference capacitance. A current mirror circuit is coupled to the data line and the reference capacitance. During a sense operation, the common node is configured to be at a fixed voltage and the current mirror circuit is configured to mirror displacement current from the reference capacitance to the ferroelectric memory cell. | 2016-02-04 |
20160035407 | DYNAMIC RANDOM ACCESS MEMORY AND BOOSTED VOLTAGE PRODUCER THEREFOR - A dynamic random access memory (DRAM) is selectively operable in a sleep mode and another mode. The DRAM has data storage cells that are refreshed in the refresh mode. A boosted voltage is provided for the operation of the DRAM. A boosted voltage provider includes a group of charge pump circuits that are selectively activated by a pump control circuit based on a refresh time for refreshing data in the DRAM cells in the sleep mode. | 2016-02-04 |
20160035408 | MEMORY CONTROL DEVICE AND A DELAY CONTROLLER - A memory control device includes a plurality of delay circuits to set a delay value for each terminal of a memory, each of the plurality of delay circuits being connected to a terminal of the memory. Further, the memory control device includes a first register to store a first DLL value output by a delay locked loop circuit, a plurality of second registers to store a first setting value to set the delay value for the each terminal of the memory, each of the plurality of second registers being connected to a delay circuit of the plurality of delay circuits, and a delay controller to calculate a second setting value based on the first DLL value, a second DLL value output by the delay locked loop circuit after the first DLL value, and the first setting value, and to update the first setting value to the second setting value. | 2016-02-04 |
20160035409 | Multiple Gating Modes and Half-Frequency Dynamic Calibration for DDR Memory Controllers - Circuits and methods are described for a DDR memory controller where two different DQS gating modes are utilized. These gating modes together ensure that the DQS signal, driven by a DDR memory to the memory controller, is only available when read data is valid. Two types of gating logic are used: Initial DQS gating logic, and Functional DQS gating logic. The Initial gating logic has additional timing margin in the Initial DQS gating value to allow for the unknown round trip timing during initial bit levelling calibration. DQS functional gating is then optimized during further calibration to gate DQS precisely as latency and phase calibration are performed, resulting in a precise gating value for Functional DQS gating. Providing dual gating modes is especially useful when data capture is performed at half the DQS frequency in view of rising clock rates for DDR memories. | 2016-02-04 |
20160035410 | MEMORY AND MEMORY SYSTEM INCLUDING THE SAME - A memory includes a first cell array including a plurality of first memory cells connected to a plurality of word lines, a bit line selection unit configured to select one or more bit lines among a plurality of bit lines based on repair information, a second cell array including a plurality of second memory cells connected to the plurality of word lines and the plurality of bit lines, wherein a group of the plurality of second memory cells connected to a corresponding word line stores the number of activations of the corresponding word line when the one or more connected bit lines are selected and an activation number update unit configured to update a value stored in the second memory cells, which are connected to the one or more selected bit lines and the activated word line among the plurality of word lines. | 2016-02-04 |
20160035411 | MEMORY CONTROL CIRCUIT AND ASSOCIATED MEMORY CONTROL METHOD - a memory control circuit includes a comparator, an eye width measuring circuit and a calibration circuit, wherein the comparator is arranged to compare a data signal with a reference voltage to generate a compared data signal; the eye width measuring circuit is coupled to the comparator, and is arranged to measure an eye width of the compared data signal to generate a measuring result; and the calibration circuit is coupled to the comparator and the eye width measuring circuit, and is arranged to adjust a level of the reference voltage according to the measuring result. | 2016-02-04 |
20160035412 | FAIL-SAFE I/O TO ACHIEVE ULTRA LOW SYSTEM POWER - The disclosure provides an input/output (IO) circuit powered by an input/output (IO) supply voltage. The IO circuit includes a cutoff circuit that receives a first invert signal, the IO supply voltage, a bias voltage and a pad voltage. An output stage is coupled to the cutoff circuit. The output stage receives a first signal, a second signal and the bias voltage. A pad is coupled to the output stage, and a voltage generated at the pad is the pad voltage. The cutoff circuit and the output stage maintain the pad voltage at logic high when the IO supply voltage transition below a defined threshold. | 2016-02-04 |
20160035413 | NON-VOLATILE STATIC RANDOM ACCESS MEMORY CIRCUITS - A non-volatile static random access memory (nvSRAM) circuit is provided. The nvSRAM circuit includes first and second switches and a latch circuit. The first switch has a first terminal coupled to a first bit line. The second switch has a first terminal coupled to a second bit line. The latch circuit is coupled to second terminals of the first and second switches. The latch circuit has a first non-volatile memory element. When the nvSRAM circuit is at a writing mode, first input data on the first bit line is written into in the latch circuit, and the first non-volatile memory element has a first state corresponding to the first data. When the nvSRAM circuit is at a reading mode, first readout data is generated according to the first state of the first non-volatile memory element is generated and provided to the first bit line. | 2016-02-04 |
20160035414 | SRAM BIT-LINE AND WRITE ASSIST APPARATUS AND METHOD FOR LOWERING DYNAMIC POWER AND PEAK CURRENT, AND A DUAL INPUT LEVEL-SHIFTER - Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in a group such that area occupied by the local write assist logic units and the read/write local column multiplexers in the group is smaller than it would be when global write assist logic units and the read/write global column multiplexers are used. Described is a dual input level-shifter with integrated latch. Described is an apparatus which comprises: a write assist pulse generator operating on a first power supply; one or more pull-up devices coupled to the write assist pulse generator, the one or more pull-up devices operating on a second power supply different from the first power supply; and an output node to provide power supply to a memory cell. | 2016-02-04 |
20160035415 | NON-VOLATILE MEMORY USING BI-DIRECTIONAL RESISTIVE ELEMENTS - A memory cell includes a single bi-directional resistive memory element (BRME) having a first terminal directly connected to a first power rail and a second terminal coupled to an internal node; and a first transistor having a control electrode coupled to the internal node, and a first current electrode coupled to a first bitline, and a second current electrode coupled to one of a group consisting of: a read wordline and the first power rail. | 2016-02-04 |
20160035416 | NONVOLATILE MEMORY DEVICE AND METHOD FOR DRIVING SAME - According to one embodiment, a nonvolatile memory device includes: a first interconnection layer; a second interconnection layer; an ion source provided between the first interconnection layer and the second interconnection layer; a resistance layer provided between the ion source and the first interconnection layer; and a control circuit writing multi-value data in the resistance layer by changing a setting voltage to be applied between the first interconnection layer and the second interconnection layer when performing a setting operation of writing data in the resistance layer, and the control circuit reading the multi-value data based on reading voltage to be applied between the first interconnection layer and the second interconnection layer when performing a reading operation of reading the multi-value data. | 2016-02-04 |
20160035417 | MEMORY DEVICE AND METHOD OF OPERATING THE MEMORY DEVICE - A memory device and a method of operating the memory device are provided for performing a read-retry operation. The method of operating the memory device includes starting a read-retry mode, reading data of multiple cell regions using different read conditions, and setting a final read condition for the cell regions according to results of data determination operations on data read from the cell regions. | 2016-02-04 |
20160035418 | MEMORY DEVICE ARCHITECTURE - Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array. | 2016-02-04 |
20160035419 | RECONFIGURABLE CIRCUIT AND METHOD OF PROGRAMMING THE SAME - A reconfigurable circuit according to an embodiment includes: first wiring lines; second wiring lines crossing the first wiring lines; resistive change elements disposed in intersection regions of the first and second wiring lines, each of the resistive change elements including a first terminal connected to the one of the first wiring lines and a second terminal connected to the one of the second wiring lines, and being switchable between a low-resistance state and a high-resistance state; a first control circuit controlling a voltage to be applied to the first wiring lines; a second control circuit controlling a voltage to be applied to the second wiring lines; and current limiting elements corresponding to the second wiring lines, and controlling current flowing through the resistive change elements connected to the corresponding second wiring line. | 2016-02-04 |
20160035420 | NONVOLATILE MEMORY DEVICE AND METHOD FOR CONTROLLING SAME - According to one embodiment, a device includes: word lines extending in a first direction, widths of the word lines in a second direction intersecting the first direction having a first width and a second width greater than the first width; bit lines provided above or under the word lines, the bit lines extending in the second direction, widths of the bit lines in the first direction having a third width and a forth width greater than the third width; storage elements; and a control circuit applying a potential for at least one of a plurality of non-selected word lines and a plurality of non-selected bit lines other than a selected word line and a selected bit line connected to a selected storage element, among the word lines and the bit lines, the potential applied thereto according to a width thereof. | 2016-02-04 |
20160035421 | Non-volatile memory for high rewrite cycles application - A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell. | 2016-02-04 |
20160035422 | TRANSISTOR AND CIRCUIT USING SAME - A transistor is described including a fly-over conductor. The transistor has a gate, a channel and a source/drain terminal. The fly-over conductor is disposed over the source/drain terminal. A circuit is connected to the fly-over conductor to apply a bias voltage tending to offset effects on the transistor of charge trapped in insulating material. A word line driver can include a transistor with a fly-over conductor. | 2016-02-04 |
20160035423 | NONVOLATILE MEMORY DEVICE AND WORLDLINE DRIVING METHOD THEREOF - According to example embodiments of inventive concepts, a nonvolatile memory device includes a memory cell array, an address decoder, an input/output circuit, a voltage generation circuit, and control logic. The memory cell array includes a plurality of memory blocks on a substrate. Each of the memory blocks includes a plurality of strings connected between bit lines and a common source line. The address decoder is configured to measure impedance information of word lines of a selected memory block. The voltage generation circuit is configured to generate word line voltages to be applied to word lines, and at least one of the word line voltages includes an offset voltage and a target voltage. The control logic is configured to adjust a level of the offset voltage and the offset time depending on the measured impedance information of the word lines. | 2016-02-04 |
20160035424 | Systems and methods for trimming control transistors for 3D NAND flash - Control transistors and memory cells within 3D NAND Flash memory arrays may both be created using the same technology, such as charge trapping structures, to simplify the fabrication process. However, the resulting control transistors may initially have higher variability in threshold voltages, when compared to traditional gate-oxide-based control transistors. Provided are exemplary techniques to trim control transistors to provide increased reliability and performance during array operation. | 2016-02-04 |
20160035425 | MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A programming method for a memory device is provided. The memory device includes a first transistor, a memory cell string, and a second transistor which are electrically connected in series. The memory cell string includes a target memory cell, first and second peripheral memory cells adjacent to the target memory cell, and a plurality of non-target memory cells which are not adjacent to the target memory cell. The programming method includes following steps. The first transistor is turned on, and the second transistor is turned off. A pass voltage is applied to turn on the non-target memory cells, and an assistant voltage is applied to turn on the first and second peripheral memory cells. A programming voltage is applied to program the target memory cell. The assistant voltage is greater than the pass voltage and is less than the programming voltage. | 2016-02-04 |
20160035426 | Bias To Detect And Prevent Short Circuits In Three-Dimensional Memory Device - In a three-dimensional stacked non-volatile memory device, a short circuit in a select gate layer is detected and prevented. A short circuit may occur when charges which are accumulated in select gate lines due to plasma etching, discharge through a remaining portion of the select gate layer in a short circuit path when the select gate lines are driven. To detect a short circuit, during a testing phase, an increasing bias is applied is applied to the remaining portion while a current is measured. An increase in the current above a threshold indicates that the bias has exceed a breakdown voltage of a short circuit path. A value of the bias at this time is recorded as an optimal bias. During subsequent operations involving select gate transistors or memory cells, such as programming, erasing or reading, the optimal bias is applied when the select gate lines are driven to prevent a current flow through the short circuit. | 2016-02-04 |
20160035427 | DATA STORAGE DEVICE AND OPERATION METHOD THEREOF - A data storage device includes a nonvolatile memory having a plurality of first memory cells connected to a first word line and a plurality of second memory cells connected to a second word line. A memory controller divides first data to be programmed in the first memory cells into first and second data groups and divides second data to be programmed in the second memory cells into third and fourth data groups. The nonvolatile memory device performs a third program operation of the second data group and a fourth program operation of the fourth data group after sequentially performing a first program operation of the first data group and a second program operation of the third data group. | 2016-02-04 |
20160035428 | NONVOLATILE MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A method for driving a nonvolatile memory device includes performing an erase operation with respect to a plurality of memory cells, stopping the erase operation by a suspend command, calculating a residual time of the erase operation that has not yet been performed, performing a first operation, comparing a first vacant time between a completion time point of the first operation and a start time point of a second operation with the residual time, performing the erase operation that has not yet been performed if the residual time is equal to or shorter than the first vacant time, and performing the second operation if the residual time is longer than the first vacant time. | 2016-02-04 |
20160035429 | MEMORY DEVICE AND READ METHOD OF MEMORY DEVICE - In a method of reading a memory device, difference information is generated based on a distance difference between a position of a read word-line and a position of a boundary word-line. The read word-line corresponds to a read address. The boundary word-line corresponds to a last programmed word-line in a memory block included in a memory cell array. A read word-line voltage and an adjacent word-line voltage are determined based on the difference information. The read word-line voltage is applied to the read word-line. The adjacent word-line voltage is applied to an adjacent word-line that is adjacent to the read word-line. A read data corresponding to the read address is outputted based on the read word-line voltage and the adjacent word-line voltage. The read method of the memory device according to example embodiments may be capable of increasing the performance by controlling the voltages applied to the adjacent word-line and the read word-line according to the difference information determined based on the read word-line and the boundary word-line. | 2016-02-04 |
20160035430 | Compact High Speed Sense Amplifier for Non-Volatile Memory with Reduced Layout Area and Power Consumption - A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp circuit is connected to first and second supply levels, a first level used for setting a program inhibit level on bit lines and a second level used for pre-charging bit lines for sensing operation. Outside of a data latch, the sense amp can employ only NMOS transistors. The arrangement of the circuit also allows for the discharging the bit line at the same time as transfers the sensing result out to other latches. | 2016-02-04 |
20160035431 | THREE-DIMENSIONAL NONVOLATILE MEMORY AND RELATED READ METHOD DESIGNED TO REDUCE READ DISTURBANCE - A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively. In the second interval, the device applies a turn-off voltage to unselected string selection lines and unselected ground selection lines while continuing to apply the turn-on voltage to a selected string selection line and a selected ground selection line. In both the first and second intervals, the device applies a first read voltage to a selected wordline connected to memory cells to be read by the read operation and applying a second read voltage to unselected wordlines among connected to memory cells not to be read by the read operation. | 2016-02-04 |
20160035432 | NONVOLATILE MEMORY DEVICE AND METHOD FOR SENSING THE SAME - A nonvolatile memory device includes a first resistive memory cell connected to a first word line, a second resistive memory cell connected to a second word line that is different from the first word line, a clamping unit connected between a sensing node and the first resistive memory cell to provide a clamping bias to the first resistive memory cell, a reference current supplying unit connected to the second resistive memory cell to supply a reference current, and a sense amplifier connected to the sensing node to sense a level change of the sensing node, wherein when the first word line is enabled, the second word line is disabled. | 2016-02-04 |
20160035433 | MEMORY ARRAY WITH RAM AND EMBEDDED ROM - A memory array with RAM and embedded ROM including multiple RAM cells, a ROM cell, and a ROM enable circuit. Each RAM cell has a RAM cell structure with a first and second power terminals and configured to operate as a RAM cell when the memory array is in a RAM mode. The ROM cell has the same RAM cell structure in which at least one transistor is modified to cause the ROM cell to have a predetermined logic state. The ROM enable circuit enables bit lines of the ROM cell to control supply voltages provided to the power terminals of the RAM cells so that they settle to predetermined logic states in a ROM mode. The modified transistor has a pseudo transistor structure having a modified substrate that operates as a resistance, such as a doping region in the substrate having the same polarity type as the substrate. | 2016-02-04 |
20160035434 | MEMORY ARRAY, MEMORY DEVICE, AND METHODS FOR READING AND OPERATING THE SAME - The present invention provides a memory. The memory includes a plurality of memory cells arranged as an array with a plurality of rows and a plurality of column. A memory cell is connected to at least one redundant memory cell in a same row for storing same data as the memory cell; and a column of memory cells correspond to one redundant column of redundant memory cells wherein each redundant memory cell in the redundant column stores same data as the memory cell in a same row. | 2016-02-04 |
20160035435 | MEMORY CIRCUIT - A memory circuit includes: a control part configured to output a control signal; a fuse circuit which is driven by the control signal and is configured to output a fuse signal whose signal level is determined based on a state of a first fuse element; and a holding circuit configured to update and hold a signal based on the fuse signal in response to the control signal output from the control part and output the held signal as an output signal. | 2016-02-04 |
20160035436 | APPARATUSES AND METHODS FOR OPERATING A MEMORY DEVICE - Subject matter described pertains to apparatuses and methods for operating a memory device. | 2016-02-04 |
20160035437 | TIMING-DRIFT CALIBRATION - The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit. | 2016-02-04 |
20160035438 | MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A memory device includes a non-volatile memory circuit suitable for storing system hard repair data, a temporary memory circuit suitable for storing system soft repair data, a system register circuit suitable for receiving and storing the system hard repair data or the system soft repair data during a boot-up operation, and a memory bank suitable for performing a repair operation based on first data stored in the system register circuit. | 2016-02-04 |
20160035439 | MEMORY ARRAY, MEMORY DEVICE, AND METHODS FOR READING AND OPERATING THE SAME - The present disclosure provides a memory. The memory includes an array of memory cells arranged as a plurality of rows by a plurality of columns. A memory cell is connected to at least one redundant memory cell in series in a same row for storing same data as the memory cell; and a column of memory cells correspond to at least one redundant column of redundant memory cells wherein each redundant memory cell in the at least one redundant column stores same data as the memory cell in a same row. | 2016-02-04 |
20160035440 | DEUTERIUM-DEUTERIUM NEUTRON GENERATORS - Various embodiments include apparatus and methods of using the apparatus having a neutron generator. The neutron generator can include a neutron generator tube having an inner surface and a cylindrical cavity, a field ionization array cylindrically distributed on the inner surface, and a target rod positioned in the cylindrical cavity. Additional apparatus, systems, and methods are disclosed. | 2016-02-04 |
20160035441 | FUEL ASSEMBLY - A fuel assembly for use in a core of a nuclear power reactor. The assembly includes a frame shaped and configured to fit within the nuclear reactor internal core structure; and a plurality of helically twisted fuel elements supported by the frame in a fuel rod bundle. Each of the fuel elements includes fissile material. When viewed in a cross-section that is perpendicular to an axial direction of the fuel assembly, the outermost fuel elements of the fuel rod bundle define a substantially circular perimeter. Other features, and a nuclear reactor, are also described. | 2016-02-04 |
20160035442 | CHEMICAL PROCESS FOR PRIMARY SYSTEM MATERIAL PASSIVATION DURING HOT FUNCTIONAL TESTING OF NUCLEAR POWER PLANTS - The present invention relates to a pre-core hot functional testing (HFT) preconditioning process, which includes the introduction of chemical additives, e.g., zinc, into coolant water that circulates through the primary system of a new nuclear power plant, at various temperatures. The chemical additives contact the primary system surfaces, which results in the formation of a protective zinc-containing oxide film on the fresh surfaces to control corrosion release and deposition during subsequent normal operation of the nuclear power plant. The method includes a series of three chemistry phases to optimize the passivation process: 1) an alkaline-reducing phase, 2) an acid-reducing phase and 3) an acid-oxidizing phase. | 2016-02-04 |
20160035443 | TREATMENT APPARATUS FOR WASTE STEAM GENERATOR AND INSTALLATION METHOD THEREOF - A treatment apparatus includes a cutting part for cutting a lower head of a waste steam generator, a driving part for driving the cutting part, and a support frame for supporting the cutting part and the driving part, wherein the support frame is coupled to an outer peripheral surface of the lower head in a divided state, and the cutting part is driven and cuts the lower head in a state in which the support frame is coupled to the outer peripheral surface of the lower head. Since the support frame is divided into a plurality of portions and a dedicated installation jig is provided, the treatment apparatus is easily moved and installed and installation time thereof can be shortened, and an exposure time of a worker can be minimized. | 2016-02-04 |
20160035444 | ULTRA-SAFE WET STORAGE FACILITY FOR NUCLEAR FUEL - An autonomous facility for storing spent nuclear fuel in one embodiment includes a building forming an enclosed interior space containing a water-filled spent fuel pool. The pool includes fuel racks containing spent fuel assemblies which heat the water via radioactive decay. A passive cooling system includes a submerged heat exchanger in the pool and an air cooled heat exchanger located in ambient air outside the building at a higher elevation than the pool heat exchanger. A heat transfer working fluid circulates in a closed flow loop between the heat exchangers via unpumped natural gravity driven flow to cool the fuel pool. The air cooled heat exchanger may be enclosed in a concrete reinforced silo adjoining the building for impact protection. The building may include a cask pit formed integrally with the pool to allow fuel assembles to be removed from a transport cask and loaded into the fuel rack underwater. | 2016-02-04 |
20160035445 | TREATMENT APPARATUS AND METHOD FOR WASTE STEAM GENERATOR, AND INSTALLATION METHOD OF TREATMENT APPARATUS FOR WASTE STEAM GENERATOR - Disclosed herein are a treatment apparatus and method for a waste steam generator, and an installation method of a treatment apparatus for a waste steam generator. The treatment apparatus includes a cutting part for cutting a body of a waste steam generator, a driving part for driving the cutting part, and a support frame for supporting the cutting part and the driving part, wherein the support frame is coupled to an outer peripheral surface of the body of the waste steam generator in a divided state, and the cutting part is driven and cuts the body in a state in which the support frame is coupled to the outer peripheral surface of the body. Consequently, since the treatment apparatus is easily moved and installed, an installation time of the treatment apparatus may be shortened and an exposure time of a worker can be reduced. | 2016-02-04 |
20160035446 | Novel Vertical Concrete Cask Design Used for Storing Nuclear Spent Fuel Dry Storage Canister - A concrete cask is used for storing a nuclear spent fuel dry storage canister. The cask has a shape of a vertical cylinder and is able to isolate the stored nuclear spent fuel dry storage canister from the ambient environment and shield the radiation from the stored nuclear spent fuels. An insulating ring is used for improving the dissipation and the transference uniformity of decay heat generated from the stored nuclear spent fuels. The insulating ring thus prevents the temperature of the concrete wall adjacent to the canister from exceeding specified limit. An Air inlet and an air outlet are used to generate a natural convection for moving out the decay heat. Therein, the vertical concrete cask is prevented from being overheated. Thus, the present invention improves the storage safety of a dry storage system. | 2016-02-04 |
20160035447 | Integrated System for Forming and Transporting Packaging Assemblies, and the Assembly, Filling and Disassembly Stations Thereof - The invention relates to an assembly consisting of a plurality of packaging bottles ( | 2016-02-04 |
20160035448 | PRODUCTION OF CARBON-11 USING A LIQUID TARGET - The present disclosure relates to the generation of radioisotopes, includes 11-carbon, from liquid targets. In certain embodiments, a liquid hydrazine target is employed which, when irradiated, such as with a charged particle beam, generates 11-carbon in a form that may be recovered and used in downstream processes, such as the generation of radiopharmaceuticals. | 2016-02-04 |
20160035449 | CHARGED PARTICLE ACCELERATION DEVICE - A charged particle acceleration device according to some embodiments of the current invention includes a first triboelectric element, a second tribo-electric element arranged proximate the first tribo-electric element to be brought into contact with and separated from the first triboelectric element, an actuator assembly operatively connected to at least one of the first and second triboelectric elements to bring the first and second triboelectric elements into contact with each other and to separate the first and second triboelectric elements from each other, and a charged-particle source configured to provide charged particles in a gap between the first and second triboelectric elements. | 2016-02-04 |
20160035450 | TALBOT INTERFEROMETER, TALBOT INTERFERENCE SYSTEM, AND FRINGE SCANNING METHOD - In a Talbot interferometer including a diffractive grating which forms a first intensity distribution, a shield grating which forms a second intensity distribution, a detector which acquires information on the intensity distributions, and a moving unit which moves the first intensity distribution or the shield grating, fringe scanning in the x-axis and y-axis directions is performed in response to a change in relative positions of the first intensity distribution and the shield grating in the respective directions, and the detection before or after a change in the relative positions in the respective directions. The number of movements of the first intensity distribution or the shield grating with the fringe scanning in the directions is lower than Dx×(Dy+1)−2, where Dx and Dy are the numbers of detections with the fringe scanning in the respective directions and are integers equal to or higher than 3. | 2016-02-04 |
20160035451 | RADIATION IMAGE CAPTURING SYSTEM - A radiation image capturing system capable of improving image quality of a radiation image is provided. A position of a joint of a grid is determined in consideration of displacement of an angle of incidence of radiation on a grid unit and a radiation detector group, and a joint image caused by the joint of the grid is prevented from being included in a search range of a position of a boundary in the radiation image captured by the radiation detector. The joint of the grid is provided in a position away ±(y1+2×y2)×tanβ or more from a position of a step of the radiation detector. | 2016-02-04 |
20160035452 | ALUMINUM ELECTRODE, METHOD OF FORMING AN ALUMINUM ELECTRODE AND ELECTRONIC DEVICE THEREWITH - The present disclosure relates to an aluminum electrode, a method of forming an aluminum electrode and an electronic device therewith. An aluminum electrode according to one aspect of the present disclosure comprises: a bottom layer consisting of molybdenum; a top layer consisting of molybdenum; and an aluminum layer located between the bottom layer and the top layer, wherein the bottom layer, the top layer and the aluminum layer are formed at a temperature below 120° C. An aluminum electrode according to one embodiment of the present disclosure eliminates the mouse bite phenomenon. An aluminum electrode according to another aspect of the present disclosure comprises: a bottom layer consisting of a metal or metal-alloy nitride; a top layer consisting of molybdenum; and an aluminum layer located between the bottom layer and the top layer, wherein the bottom layer, the top layer and the aluminum layer are formed at a temperature below 120° C. An aluminum electrode according to another embodiment of the present disclosure eliminates both of the mouse bite phenomenon and the undercut phenomenon, and can further arrive at a desired profile angle by controlling the content of nitrogen. | 2016-02-04 |
20160035453 | Composite Core for Electrical Transmission Cables - A composite core for use in electrical cables, such as high voltage transmission cables is provided. The composite core contains at least one rod that includes a continuous fiber component surrounded by a capping layer. The continuous fiber component is formed from a plurality of unidirectionally aligned fiber rovings embedded within a thermoplastic polymer matrix. The present inventors have discovered that the degree to which the rovings are impregnated with the thermoplastic polymer matrix can be significantly improved through selective control over the impregnation process, and also through control over the degree of compression imparted to the rovings during formation and shaping of the rod, as well as the calibration of the final rod geometry. Such a well impregnated rod has a very small void fraction, which leads to excellent strength properties. Notably, the desired strength properties may be achieved without the need for different fiber types in the rod. | 2016-02-04 |
20160035455 | PHOTONIC SINTERING OF POLYMER THICK FILM COPPER CONDUCTOR COMPOSITIONS - This invention provides a method for using a polymer thick film copper conductor composition to form an electrical conductor in an electrical circuit, the method subjecting the deposited thick film copper conductor composition to photonic sintering. The invention also provides a method for reducing the resistance of an electrical conductor formed from a polymer thick film conductor composition, the method comprising the step of subjecting the electrical conductor to photonic sintering. The invention further provides devices containing electrical conductors made by these methods. The invention also provides a polymer thick film copper conductor composition. | 2016-02-04 |
20160035456 | ELECTRICALLY CONDUCTIVE POLYMER COMPOSITIONS - Embodiments of the present invention relate to an electrically conductive composition and an article. The electrically conductive composition comprises a polymer, graphene sheets, and carbon black, wherein the ratio of the graphene sheets to carbon black is about 1:2 to about 1:20. An article comprising the electrically conductive composition. | 2016-02-04 |