05th week of 2021 patent applcation highlights part 60 |
Patent application number | Title | Published |
20210035777 | ADJUSTABLE FASTENING DEVICE FOR PLASMA GAS INJECTORS - An embodiment is an apparatus, such as a plasma chamber. The apparatus includes chamber walls and a chamber window defining an enclosed space. A chamber window is disposed between a plasma antenna and a substrate support. A gas delivery source is mechanically coupled to the chamber window. The gas delivery source comprises a gas injector having a passageway, a window at a first end of the passageway, and a nozzle at a second end of the passageway. The nozzle of the gas delivery source is disposed in the enclosed space. A fastening device is mechanically coupled to the gas delivery source. The fastening device is adjustable to adjust a sealing force against the gas injector. | 2021-02-04 |
20210035778 | MULTIPLEXED POWER GENERATOR OUTPUT WITH CHANNEL OFFSETS FOR PULSED DRIVING OF MULTIPLE LOADS - This disclosure describes systems, methods, and apparatus for a pulsed power supply assembly that distributes pulsed power to two or more loads using a single pulsed power supply. A pulsed power supply of the assembly can phase shift pulses to the different loads to ensure that there is no overlap between pulses at the outputs even where target frequencies and/or duty cycles for the different loads would otherwise call for such pulse overlaps. Variances applied by the pulsed power supply can be limited by attempts to keep average parameters of the pulse trains provided to the different loads to within predetermined variances. | 2021-02-04 |
20210035779 | APPARATUS AND SYSTEM HAVING EXTRACTION ASSEMBLY FOR WIDE ANGLE ION BEAM - An ion beam processing apparatus may include a plasma chamber, and a plasma plate, disposed alongside the plasma chamber, where the plasma plate defines a first extraction aperture. The apparatus may include a beam blocker, disposed within the plasma chamber and facing the extraction aperture. The apparatus may further include a non-planar electrode, disposed adjacent the beam blocker and outside of the plasma chamber; and an extraction plate, disposed outside the plasma plate, and defining a second extraction aperture, aligned with the first extraction aperture. | 2021-02-04 |
20210035780 | SUBSTRATE TREATMENT DEVICE - The present invention relates to a substrate processing apparatus including: a chamber; a first electrode disposed on the chamber; a second electrode disposed under the first electrode, the second electrode including a plurality of openings; a plurality of protrusion electrodes extending from the first electrode to the plurality of openings of the second electrode; a substrate supporter being opposite to the second electrode and supporting a substrate; a first discharging region between a lower surface of the first electrode and an upper surface of the second electrode; a second discharging region between a side surface of the protrusion electrode and an opening inner surface of the second electrode; a third discharging region between a lower surface of the protrusion electrode and the opening inner surface of the second electrode; and a fourth discharging region between the second electrode and the substrate, wherein plasma is generated in at least one region of the first to fourth discharging regions. | 2021-02-04 |
20210035781 | SEMICONDUCTOR PROCESSING CHAMBER AND METHODS FOR CLEANING THE SAME - A processing chamber may include a gas distribution member, a metal ring member below the gas distribution member, and an isolating assembly coupled with the metal ring member and isolating the metal ring member from the gas distribution member. The isolating assembly may include an outer isolating member coupled with the metal ring member. The outer isolating member may at least in part define a chamber wall. The isolating assembly may further include an inner isolating member coupled with the outer isolating member. The inner isolating member may be disposed radially inward from the metal ring member about an central axis of the processing chamber. The inner isolating member may define a plurality of openings configured to provide fluid access into a radial gap between the metal ring member and the inner isolating member. | 2021-02-04 |
20210035782 | SUBSTRATE SUPPORTING DEVICE AND SUBSTRATE TREATING APPARATUS INCLUDING THE SAME - Provided is an apparatus for a substrate supporting apparatus fixing a focus ring without using a clamp ring. The substrate supporting apparatus comprise a supporting plate for supporting a substrate; a side ring arranged to surround at least a part of a side surface of the supporting plate and including a first through hole; a focus ring arranged on the side ring and including a first circulation channel for circulation of a first temperature control fluid and a second through hole connecting the first circulation channel and a bottom surface therein; and a coupling bolt fixed to the focus ring penetrating through the first through hole and the second through hole from below the side ring and fixing the side ring and the focus ring to each other. | 2021-02-04 |
20210035783 | EDGE RING, SUBSTRATE SUPPORT, SUBSTRATE PROCESSING APPARATUS AND METHOD - An edge ring includes a first edge ring, and a second edge ring that has a side surface adjacent to a side surface of the first edge ring and is movable in a vertical direction along the side surface of the first edge ring. Further, the side surface of the first edge ring and the side surface of the second edge ring at least partially face each other in a movement range of the second edge ring. | 2021-02-04 |
20210035784 | SUBSTRATE PROCESSING APPARATUS - There is provided a technique that include: a process chamber including a plasma generation space and a process space; a coil electrode arranged around the plasma generation space; a substrate mounting table on which a substrate to be processed in the process space is mounted; an elevator configured to move the substrate mounting table in the process chamber; and a controller configured to control the elevator to vary a distance between the substrate and an end portion of the coil electrode according to process distribution information on the substrate. | 2021-02-04 |
20210035785 | SUBSTRATE PROCESSING APPARATUS - A substrate processing apparatus having an improved exhaust structure includes a grounded conductive extension portion configured to prevent generation of parasitic plasma in an exhaust space connected to a reaction space. The substrate processing apparatus prevents generation of parasitic plasma in an area, such as the reaction space, other than the reaction space. Thus, power loss may be prevented and a stable plasma process may be achieved. | 2021-02-04 |
20210035786 | SUBSTRATE PROCESSING APPARATUS - A substrate processing apparatus having an improved exhaust structure includes a reaction space formed between a processing unit and a substrate support unit, an exhaust unit surrounding the reaction space, an exhaust port with a channel inside, a partition wall with an exhaust line inside, wherein the channel of the exhaust port connects the exhaust unit and the exhaust line. | 2021-02-04 |
20210035787 | PLASMA PROCESSING APPARATUS AND CONTROL METHOD - A plasma processing apparatus includes a main container, one or more radio frequency antennas, a plurality of metal windows, and a plasma detector. The one or more radio frequency antennas are configured to generate inductively coupled plasma in a plasma generation region in the main container. The metal windows are disposed between the plasma generation region and the radio frequency antennas while being insulated from each other and from the main container. Further, a plasma detector is connected to each of the metal windows and configured to detect a plasma state. | 2021-02-04 |
20210035788 | PLASMA PROCESSING APPARATUS AND CONTROL METHOD - A plasma processing apparatus includes a processing chamber, a conductive annular member, a microwave radiating mechanism and a plasma detector. The processing chamber has a ceiling plate with an opening. The conductive annular member is disposed at the opening while being insulated from the ceiling plate. The microwave radiating mechanism is disposed on the ceiling plate to be coaxial with a center of the conductive annular member and configured to radiate microwaves into the processing chamber. Further, a plasma detector is connected to the conductive annular member and configured to detect a state of generated plasma. | 2021-02-04 |
20210035789 | ION-TO-ELECTRON CONVERSION DYNODE FOR ION IMAGING APPLICATIONS - A metal-channel conversion dynode comprises: a wafer comprising a first face and a second face parallel to the first face and having a thickness less than 1000 μm; and a plurality of channels passing through the wafer from the first face to the second face at an angle to a plane of the first face and a plane of the second face. In some embodiments, each inter-channel distance may be substantially the same as the wafer thickness. In some embodiments, the wafer is fabricated from tungsten. In some other embodiments, the wafer comprises a non-electrically conductive material that is fabricated by three-dimensional (3D) printing or other means and that is coated, on its faces and within its channels, with a metal or suitably conductive coating that produces secondary electrons upon impact by either positive or negative ions. | 2021-02-04 |
20210035790 | DATA PROCESSING DEVICE FOR IMAGING MASS SPECTROMETRIC ANALYSIS - The efficiency and accuracy of search for a compound exhibiting a distribution similar to that of a reference image such as an optical microscope image are improved in imaging mass spectrometric analysis. In an imaging mass spectrometer including a data processing device according to the present invention, a regression analysis executor ( | 2021-02-04 |
20210035791 | ANALYZER APPARATUS AND CONTROL METHOD - An analyzer apparatus includes: an ionization unit that ionizes molecules to analyze; a filter unit that forms a field for selectively passing ions generated by the ionization unit; a detector unit that detects ions that have passed through the filter unit; an ion drive circuitry that electrically drives the ionization unit; a field drive circuitry that electrically drives the filter unit; and a control unit that controls outputs of the ion drive circuitry and the field drive circuitry, wherein the control unit controls the ion drive circuitry to ramp up and down a filament voltage supplied to a filament of the ionization unit when the analyzer apparatus starts and stops. | 2021-02-04 |
20210035792 | Method and Apparatus for Tandem Mass Spectrometry with MALDI-TOF Ion Source - A MALDI ion source for tandem mass spectrometers includes a pulsed energy source that generates a pulse of ions from a sample on a sample plate. An ion accelerator includes an input that receives the pulse of ions from the pulsed energy source and generates an electric field that accelerates the pulse of ions. An ion decelerator that generates an electric field that is a mirror image of the electric field generated by the ion accelerator that accelerates the pulse of ions so that the ion decelerator decelerates the accelerated pulse of ions and transmits the decelerated pulse of ions through an exit aperture. | 2021-02-04 |
20210035793 | Wafer Thinning Method and Wafer Structure - A wafer thinning method and a wafer structure are provided. In the wafer thinning method, a to-be-thinned wafer is provided, and the to-be-thinned wafer is grinded on a rear surface of the to-be-thinned wafer. Then, a first planarization process is performed on a rear surface of the grinded wafer to restore surface flatness of the grinded wafer, and a second planarization process is performed on a rear surface of the wafer obtained after the first planarization process is performed until a target thinned thickness is reached. | 2021-02-04 |
20210035794 | SEMICONDUCTOR DEVICE PACKAGES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device package includes a first semiconductor device, a first redistribution layer (RDL) structure and a second RDL structure. The first semiconductor device has a first conductive terminal and a second conductive terminal. The first RDL structure covers the first conductive terminal. The second RDL structure covers the second conductive terminal and being separated from the first RDL structure. | 2021-02-04 |
20210035795 | METHODS AND APPARATUS FOR SUBSTRATE WARPAGE CORRECTION - Methods and apparatus for reducing warpage of a substrate. In some embodiments, a method of reducing substrate warpage comprises heating the substrate with an epoxy layer to at least a glass transition temperature of the epoxy layer while allowing the substrate to expand; maintaining the at least the glass transition temperature of the substrate until the substrate is constrained; constraining the substrate with a total clamping force of approximately 5000N to approximately 7000N exerted towards the substrate from a top direction and a bottom direction; applying at least one electrostatic field to the substrate with a first electrostatic chuck positioned above the substrate and a second electrostatic chuck positioned below the substrate; and rapidly cooling the substrate using a first liquid convection heat sink positioned above the substrate and a second liquid convection heat sink positioned below the substrate. | 2021-02-04 |
20210035796 | AMORPHOUS CARBON LAYER OPENING PROCESS - A method for opening an amorphous carbon layer mask below a hardmask is provided. The opening an amorphous carbon layer mask comprises performing one or more cycles, where each cycle comprises an amorphous carbon layer mask opening phase and a cleaning phase. The amorphous carbon layer mask opening phase comprises flowing an opening gas into a plasma processing chamber, wherein the opening gas comprises an oxygen containing component, creating a plasma from the opening gas, which etches features in the amorphous carbon layer mask, and stopping the flow of the opening gas. The cleaning phase comprises flowing a cleaning gas into the plasma processing chamber, wherein the cleaning gas comprises a hydrogen containing component, a carbon containing component, and a halogen containing component, creating a plasma from the cleaning gas; and stopping the flow of the cleaning gas into the plasma processing chamber. | 2021-02-04 |
20210035797 | Semiconductor Devices and Methods of Manufacturing - A single layer process is utilized to reduce swing effect interference and reflection during imaging of a photoresist. An anti-reflective additive is added to a photoresist, wherein the anti-reflective additive has a dye portion and a reactive portion. Upon dispensing the reactive portion will react with underlying structures to form an anti-reflective coating between the underlying structure and a remainder of the photoresist. During imaging, the anti-reflective coating will either absorb the energy, preventing it from being reflected, or else modify the optical path of reflection, thereby helping to reduce interference caused by the reflected energy. | 2021-02-04 |
20210035798 | Patterning Process of a Semiconductor Structure with Enhanced Adhesion - A lithography method includes forming a bottom anti-reflective coating (BARC) layer on a substrate, wherein the BARC layer includes an organic polymer and a reactive chemical group having at least one of chelating ligands and capping monomers, wherein the reactive chemical group is bonded to the organic polymer; coating a metal-containing photoresist (MePR) layer on the BARC layer, wherein the MePR being sensitive to an extreme ultraviolet (EUV) radiation; performing a first baking process to the MePR layer and the BARC layer, thereby reacting a metal chemical structure of the MePR layer and the reactive chemical structure of the BARC layer and forming an interface layer between the MePR layer and the BARC layer; performing an exposure process using the EUV radiation to the MePR layer; and developing the MePR layer to form a patterned photoresist layer. | 2021-02-04 |
20210035799 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A recess is formed in one silicon substrate. A silicon oxide film is formed in another one silicon substrate at a portion space apart from a space-to-be-formed region. The silicon oxide film has a groove surrounding the space-to-be-formed region and extending to an outer periphery of the other one silicon substrate. Further, the other one silicon substrate and the one silicon substrate are directly bonded to each other via the silicon oxide film so as to cover the groove. A gas discharge passage, a stacking structure of the silicon substrates and the silicon oxide film are formed, and the space is formed inside the stacking structure by the recess. Then, by the heat treatment, the gas inside the space is discharged to the outside of the stacking structure through the gas discharge passage. | 2021-02-04 |
20210035800 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor device includes the following operations. A substrate is provided with a device and an insulating layer disposed over the device. A silicon-containing heterocyclic compound precursor and a first oxygen-containing compound precursor are introduced to the substrate, so as to form a zeroth dielectric layer on the insulating layer. A zeroth metal layer is formed in the zeroth dielectric layer. A silicon-containing linear compound precursor and a second oxygen-containing compound precursor are introduced to the substrate to form a first dielectric layer on the zeroth dielectric layer. A first metal layer is formed in the first dielectric layer. | 2021-02-04 |
20210035801 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - There is included (a) forming a protective film on a surface of a third base by supplying a processing gas to a substrate in which a first base containing no oxygen, a second base containing oxygen, and the third base containing no oxygen and no nitrogen are exposed on a surface of the substrate; (b) modifying a surface of the second base to be fluorine-terminated by supplying a fluorine-containing gas to the substrate after the protective film is formed on the surface of the third base; and (c) selectively forming a film on a surface of the first base by supplying a film-forming gas to the substrate after the surface of the second base is modified. | 2021-02-04 |
20210035802 | METHODS FOR SELECTIVE DEPOSITION UTILIZING N-TYPE DOPANTS AND/OR ALTERNATIVE DOPANTS TO ACHIEVE HIGH DOPANT INCORPORATION - A method for forming a doped layer is disclosed. The doped layer may be used in a NMOS or a silicon germanium application. The doped layer may be created using an n-type halide species in a n-type dopant application, for example. | 2021-02-04 |
20210035803 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. In one form, the method includes: providing a base, where a bottom core material layer is formed on the base, a plurality of discrete top core layers is formed on the bottom core material layer, an area between top core layers of the plurality of adjacent top core layers is a groove, and the groove includes a connecting groove; forming a first spacer film conformally covering the plurality of discrete top core layers and the bottom core material layer; forming a blocking structure in a remainder of the connecting groove exposed from the first spacer film; removing first spacer films on a top of the top core layers of the plurality of discrete top core layers and on the bottom core material layer using the blocking structure as a mask, to form a first mask spacer; removing the plurality of top core layers; patterning the bottom core material layer using the first mask spacer and the blocking structure as a mask, to form a bottom core layer; forming a second mask spacer on a side wall of the bottom core layer; and removing the bottom core layer. Through the blocking structure, a bottom core layer at a position corresponding to the connecting groove has a relatively large width, thereby directly forming target patterns with different spacings. | 2021-02-04 |
20210035804 | METHOD OF PATTERNING MATERIAL LAYER - A method of patterning a material layer includes the following steps. A first material layer is formed over a substrate, and the first material layer includes a first metal compound. Through a first photomask, portions of the first material layer is exposed with a gamma ray, wherein a first metal ion of the first metal compound in the portions of the first material layer is chemically reduced to a first metal grain. Other portions of the first material layer are removed to form a plurality of first hard mask patterns including the first metal grain. | 2021-02-04 |
20210035805 | Method And Apparatus For Determining Expansion Compensation In Photoetching Process, And Method For Manufacturing Device - A method and an apparatus for determining expansion compensation in a photoetching process, and a method for manufacturing a semiconductor device are provided. A relative vector misalignment value of a first wafer and a second wafer after being bonded is obtained based on a relative position relationship between a first alignment pattern of the first wafer and a second alignment pattern of the second wafer in a boding structure. A relative expansion value of the first wafer and the second wafer is obtained based on the relative vector misalignment value. A developing expansion compensation value in the photoetching process is obtained. The expansion compensation value is used to the photoetching process of a first conductor layer including the first alignment pattern of the first wafer and/or a second conductor layer including the second alignment pattern of the second wafer. | 2021-02-04 |
20210035806 | SEMICONDUCTOR DEVICE HAVING A UNIFORM AND THIN SILICIDE LAYER ON AN EPITAXIAL SOURCE/ DRAIN STRUCTURE AND MANUFACTURING METHOD THEREOF - In a method of manufacturing a semiconductor device, a first layer containing an amorphous first material is formed by a deposition process over a semiconductor layer. A second layer containing a metal second material is formed over the first layer. A thermal process is performed to form an alloy layer of the amorphous first material and the metal second material. | 2021-02-04 |
20210035807 | SEMICONDUCTOR PACKAGE STRESS BALANCE STRUCTURES AND RELATED METHODS - Implementations of a semiconductor package may include a semiconductor die including a first side and a second side where the first side of the semiconductor die includes one or more electrical contacts; a layer of metal coupled to the second side of the semiconductor; and a stress balance structure coupled to one of the layer of metal or around the one or more electrical contacts. | 2021-02-04 |
20210035808 | ARTICLE MANUFACTURING METHOD, FILM FORMING METHOD, MOLD MANUFACTURING METHOD, EXPOSURE APPARATUS, INFORMATION PROCESSING METHOD, AND NON-TRANSITORY COMPUTER-READABLE MEDIUM STORING A PROGRAM - An article manufacturing method includes a first formation step of forming a focus compensation film on a substrate, a second formation step of forming a resist layer on the focus compensation film, and a transfer step of transferring a pattern of an original to the resist layer using an exposure apparatus. In the first formation step, the focus compensation film is formed such that the focus compensation film has a top surface shape corresponding to an image surface shape of the exposure apparatus. | 2021-02-04 |
20210035809 | SELF-ALIGNED DOUBLE PATTERNING PROCESS AND SEMICONDUCTOR STRUCTURE FORMED USING THEREOF - A method for fabrication of a semiconductor structure according to some embodiments of the present disclosure comprises following steps. A first mandrel is formed over a target layer over a substrate, wherein the first mandrel comprises a mandrel island connecting a first mandrel strip and a second mandrel strip. A first spacer is formed along first and second sidewalls of the mandrel island, the first mandrel strip, and the second mandrel strip. The first mandrel is then removed, and the target layer is patterned with the first spacer remains over the target layer. The first mandrel strip and the second mandrel strip are misaligned from one another. | 2021-02-04 |
20210035810 | Ultra Narrow Trench Patterning with Dry Plasma Etching - A method includes forming a polymer layer on a patterned photo resist. The polymer layer extends into an opening in the patterned photo resist. The polymer layer is etched to expose the patterned photo resist. The polymer layer and a top Bottom Anti-Reflective Coating (BARC) are etched to pattern the top BARC, in which the patterned photo resist is used as an etching mask. The top BARC is used as an etching mask to etching an underlying layer. | 2021-02-04 |
20210035811 | INJECTION METAL ASSISTED CATALYTIC ETCHING - An electroless etching process. The process produces nanostructured semiconductors in which an oxidant (Ox | 2021-02-04 |
20210035812 | CHEMICAL MECHANICAL POLISHING METHOD AND CHEMICAL MECHANICAL POLISHING DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A chemical mechanical polishing method that includes preparing a chemical mechanical polishing device including a platen, a polishing pad, and a polishing slurry supplier, supplying a hot liquid to an inside of the platen to adjust a surface temperature of the platen, disposing the semiconductor substrate and the polishing pad to face each other, supplying polishing slurry including carbon abrasives having an average particle diameter of less than about 10 nm between the semiconductor substrate and the polishing pad, and contacting the surface of the semiconductor substrate with the polishing pad to polish the semiconductor substrate., a method of manufacturing a semiconductor device using the chemical polishing method, and a chemical mechanical polishing device. | 2021-02-04 |
20210035813 | Planarization of Dielectric Topography and Stopping in Dielectric - Techniques for planarization of dielectric topography that stop in dielectric are provided. In one aspect, a method for planarization includes: depositing a first dielectric onto a wafer having a surface topography with peaks and valleys; depositing a second, different dielectric onto the first dielectric; and polishing the second dielectric down to the first dielectric to form a planar surface at an interface between the first dielectric and the second dielectric. Optionally, a follow-up CMP or etch can be performed using a ˜1:1 selective polish or etch to completely remove the second dielectric and an equivalent amount of the first dielectric to form a planar surface devoid of the peaks and valleys in the first dielectric. A device structure formed by the present techniques is also provided. | 2021-02-04 |
20210035814 | SUBSTRATE PROCESSING METHOD, SUBSTRATE PROCESSING APPARATUS AND CLEANING APPARATUS - A substrate processing method includes preparing a substrate including an etching target film and a mask; etching the etching target film through the mask by plasma; and heat-treating the substrate at a preset temperature after the etching of the etching target film. | 2021-02-04 |
20210035815 | Method for Increasing Pattern Density on a Wafer - Techniques herein include a method of patterning semiconductor wafers with improved line edge roughness (LER) and/or line width roughness (LWR), including lines below 12 nm in width. An initial bilayer mandrel is formed. The top layer is trimmed to a particular ratio. A reversal material protects uncovered portions of the lower layer, while a central portion is removed, resulting in two mandrels, each one fifth the initial mandrel width. The resulting mandrels are transferred into two underlying layers to form second bilayer mandrels. Sidewall spacers are formed on the second bilayer mandrels, and a fill material can fill remaining spaces. A planarization step can planarize the substrate to a bottom layer of the second bilayer mandrels, which results in a multi-line layer having square profile lines at 1:1 spacing ratio without spacer rounding. | 2021-02-04 |
20210035816 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, DISPLAY DEVICE, AND ELECTRONIC DEVICE - The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. Provided is a semiconductor device including an oxide semiconductor film. The semiconductor device includes a first insulating film, an oxide semiconductor film over the first insulating film, a second insulating film and a third insulating film over the oxide semiconductor film, and a gate electrode over the second insulating film. The second insulating film comprises a silicon oxynitride film. When excess oxygen is added to the second insulating film by oxygen plasma treatment, oxygen can be efficiently supplied to the oxide semiconductor film. | 2021-02-04 |
20210035817 | METHODS FOR MANUFACTURING SEMICONDUCTOR DEVICE AND WIRING STRUTURE - The present invention relates to a method for manufacturing a semiconductor device in which a circuit element including a semiconductor chip, and a through conductor connecting an insulation layer in a thickness direction are embedded in the insulation layer. A wiring structure in which a predetermined pattern of wiring conductors is formed along a planar direction on an insulation part is created, and thereafter the wiring structure is sealed in the insulation layer in a state where the wiring structure is erected vertically. Consequently, the wiring conductor of the wiring conductor is caused to function as the through conductor in the insulation layer. | 2021-02-04 |
20210035818 | SACRIFICIAL PADS TO PREVENT GALVANIC CORROSION OF FLI BUMPS IN EMIB PACKAGES - Embodiments disclosed herein include electronic packages and methods of making electronic packages. In an embodiment, the electronic package comprises a package substrate, an array of first level interconnect (FLI) bumps on the package substrate, wherein each FLI bump comprises a surface finish, a first pad on the package substrate, wherein the first pad comprises the surface finish, and wherein a first FLI bump of the array of FLI bumps is electrically coupled to the first pad, and a second pad on the package substrate, wherein the second pad is electrically coupled to the first pad. | 2021-02-04 |
20210035819 | Integrated Circuit Package Pad and Methods of Forming - A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias. | 2021-02-04 |
20210035820 | GLOB TOP ENCAPSULATION USING MOLDING TAPE - A lead frame used to assemble a semiconductor device, such as a smart card, has a first major surface including exposed leads and a second major surface including a die receiving area and one or more connection pads surrounding the die receiving area. The connection pads enable electrical connection of an Integrated Circuit (IC) die to the exposed leads. A molding tape sized and shaped like the lead frame is adhered to and covers the second major surface of the lead frame. The molding tape has a die receiving area cut-out that exposes the die receiving area and the connection pads on the second major surface of the lead frame and forms a cavity for receiving an encapsulant. The cut-out has an elevated sidewall for retaining the encapsulant within the cavity. | 2021-02-04 |
20210035821 | METHODS AND APPARATUS FOR CLEANING SUBSTRATES - A method and an apparatus for cleaning a substrate are provided. The substrate ( | 2021-02-04 |
20210035822 | WAFER CLEANING DEVICE - The present invention relates to a wafer cleaning device which can prevent a cleaning solution from leaking and enables prompt treatment. The present invention provides a wafer cleaning device comprising: a cleaning bath which receives a cleaning solution and from which the cleaning solution overflows according to the dipping of wafers; a plurality of lift parts arranged at the outside of the cleaning bath and dipping the cassette into the cleaning solution in the cleaning bath; an external water tank having the cleaning bath and the lift parts received therein and including a drain hole through which the cleaning solution is drained; and a tray which can be detachably attached to the inner bottom surface of the external water tank and collects the cleaning solution to guide same to the drain hole. | 2021-02-04 |
20210035823 | SUBSTRATE PROCESSING DEVICE - A substrate processing device for processing a substrate is provided. The substrate processing device includes: a processing container configured to accommodate a substrate; a placement stage on which the substrate is mounted in the processing container; an exhauster configured to exhaust a processing gas in the processing container; and a partition wall disposed in the processing container and surrounding the placement stage, wherein, inside the partition wall, an exhaust flow path, which communicates with the exhauster, is formed to extend in a vertical direction over an entire circumference of the partition wall, and a plurality of openings, which communicates with a substrate processing space formed inside the partition wall above the placement stage and communicates with the exhaust flow path, is formed at regular intervals in an inner circumferential direction of the partition wall. | 2021-02-04 |
20210035824 | VERTICAL BATCH FURNACE ASSEMBLY - Vertical batch furnace assembly for processing wafers comprising a cassette handling space, a wafer handling space, and a first wall separating the cassette handling space from the wafer handling space. The first wall has at least one wafer transfer opening in front of which a wafer transfer position for a wafer cassette is provided. The cassette handling space comprises a cassette storage, and a cassette handling mechanism. The cassette storage has a plurality of cassette storage positions and is configured to store a plurality of wafer cassettes. The cassette handling mechanism comprises a first cassette handler which is configured to transfer wafer cassettes between a first set of the cassette storage positions and the wafer transfer position. The cassette handling mechanism is provided with a second cassette handler which is configured to transfer wafer cassettes between a second set of the cassette storage positions and the wafer transfer position. | 2021-02-04 |
20210035825 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - A substrate processing apparatus includes a processing tub configured to store therein a processing liquid in which multiple substrates are to be immersed; multiple liquid supplies each of which includes a supply line through which the processing liquid is supplied to an inside of a water tank of the processing tub and a heating device configured to heat the processing liquid at a portion of the supply line; and multiple in-tank temperature sensors configured to measure a temperature of the processing liquid at multiple positions within the water tank of the processing tub. | 2021-02-04 |
20210035826 | LASER PROCESSING APPARATUS - A control unit of a laser processing apparatus includes: a reference image storage section that images streets before formation of modified layers by an imaging unit and stores the captured image as a reference image; a calculation section that compares the reference image stored in the reference image storage section with an image of a wafer held by a chuck table that is captured by the imaging unit, and calculates the degree of agreement of the two images; and a decision section that decides whether the wafer is an unprocessed wafer not formed with the modified layers in the case where the degree of agreement calculated by the calculation section is more than a first predetermined value, and decides whether the wafer is a processed wafer formed with the modified layers in the case where the degree of agreement is equal to or less than a second predetermined value. | 2021-02-04 |
20210035827 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - A substrate processing apparatus includes a holder having thereon an attraction surface configured to attract a substrate and including an outer attracting member configured to attract a peripheral portion of the substrate and an inner attracting member configured to attract a portion of the substrate inside the peripheral portion of the substrate attracted by the outer attracting member in a diametrical direction of the attraction surface; a moving device configured to move the outer attracting member with respect to the inner attracting member; and a controller configured to control a distortion, which is caused at the substrate attracted to the attraction surface, by controlling a movement of the outer attracting member with respect to the inner attracting member. | 2021-02-04 |
20210035828 | APPARATUS AND METHOD FOR COOLING SUBSTRATE - The inventive concept relates to a substrate cooling apparatus for cooling a substrate. The substrate cooling apparatus includes a chuck on which the substrate is placed and a cooling unit that cools the chuck. The cooling unit includes a heat dissipation plate that has the chuck placed on an upper surface thereof and that dissipates heat of the chuck. | 2021-02-04 |
20210035829 | VAPOR SHIELD REPLACEMENT SYSTEM AND METHOD - A multi-shield plate includes a plate having a substantially flat upper surface and a substantially flat lower surface, a plurality of first windows formed in the plate and extending through the plate from the upper surface to the lower surface, and a plurality of vapor shields mounted to the plate, each vapor shield of the plurality of vapor shields configured to prevent passage of a vapor through a corresponding window of the plurality of windows. The multi-shield plate includes an aperture formed in the plate, the aperture aligned with a first window of the plurality of windows along an axis corresponding to the upper surface. | 2021-02-04 |
20210035830 | SEMICONDUCTOR MANUFACTURING APPARATUS - A semiconductor manufacturing apparatus including at least one load module including a load port on which a substrate container is located, a plurality of substrates being mountable on the substrate container; at least one loadlock module including a loadlock chamber directly connected to the substrate container, the loadlock chamber interchangeably having atmospheric pressure and vacuum pressure, a first transfer robot within the loadlock chamber, and a substrate stage within the loadlock chamber, the plurality of substrates being mountable on the substrate stage; a transfer module including a transfer chamber connected to the loadlock chamber, a second transfer robot within the transfer chamber, and a substrate aligner within the transfer chamber; and at least one process module including at least one process chamber connected to the transfer module. | 2021-02-04 |
20210035831 | SUBSTRATE POSITION DETECTING METHOD, SUBSTRATE POSITION ADJUSTING METHOD, AND SUBSTRATE POSITION DETECTING APPARATUS - A substrate position detecting method, includes loading a substrate into a processing chamber such that a clean surface of the substrate faces a mounting surface of a stage provided in the processing chamber, mounting the loaded substrate on the stage, fixing the substrate to the stage, releasing the fixing of the substrate to the stage, unloading the substrate out of the processing chamber, detecting a particle distribution of particles on the clean surface of the unloaded substrate, and calculating a positional relationship between the substrate and the stage when the substrate is mounted on the stage, based on the detected particle distribution. The particles include irregularities formed at the time of contact between the clean surface of the substrate and the mounting surface. | 2021-02-04 |
20210035832 | METHOD AND APPARATUS FOR MEASURING PROCESS KIT CENTERING - Embodiments disclosed herein include a sensor wafer. In an embodiment, the sensor wafer comprises a substrate, wherein the substrate comprises a first surface, a second surface opposite the first surface, and an edge surface between the first surface and the second surface. In an embodiment, the sensor wafer further comprises a plurality of sensor regions formed along the edge surface, wherein each sensor region comprises a self-referencing capacitive sensor. | 2021-02-04 |
20210035833 | OPTICAL METROLOGY IN MACHINE LEARNING TO CHARACTERIZE FEATURES - A metrology system may include an optical metrology tool configured to produce an optical metrology output for one or more features on a processed substrate, and a metrology machine learning model that has been trained using a training set of (i) profiles, critical dimensions, and/or contours for a plurality of features, and (ii) optical metrology outputs for the plurality of features. The metrology machine learning model may be configured to: receive the optical metrology output from the optical metrology tool; and output the profile, critical dimension, and/or contour of the one or more features on the processed substrate. | 2021-02-04 |
20210035834 | SYSTEMS AND METHODS FOR INSPECTION STATIONS - In an embodiment, a workstation includes: a processing chamber configured to process a workpiece; a load port configured to interface with an environment external to the workstation; a robotic arm configured to transfer the workpiece between the load port and the processing chamber; and a defect sensor configured to detect a defect along a surface of the workpiece when transferred between the load port and the processing chamber. | 2021-02-04 |
20210035835 | SUBSTRATE PROCESSING APPARATUS, SUBSTRATE SUPPORT, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - There is provided a technique that includes a substrate support including a support column made of metal and a plurality of supports installed at the support column and configured to support a plurality of substrates in multiple stages; a process chamber configured to accommodate the plurality of substrates supported by the substrate support; and a heater configured to heat the plurality of substrates accommodated in the process chamber, wherein the plurality of supports includes at least a contact portion configured to make contact with the plurality of substrates and made of at least one selected from the group of a metal oxide and a non-metal material. | 2021-02-04 |
20210035836 | SAFEGUARDING DEVICE, WAFER TRANSPORT CONTAINER WITH AT LEAST ONE SAFEGUARDING DEVICE, SAFEGUARDING SYSTEM AND METHOD WITH THE SAFEGUARDING DEVICE - A safeguarding device, in particular a safeguarding device for a wafer transport container includes at least one positive-fit unit configured at least for a safeguarding of a wafer-transport-container opening element of a wafer transport container, which is held in its closure position by a closing mechanism. | 2021-02-04 |
20210035837 | BRIDGE APPARATUS AND METHOD FOR SEMICONDUCTOR DIE TRANSFER - An apparatus for transferring a semiconductor die (“die”) from the first substrate to the second substrate. The apparatus includes a stage configured to hold a product substrate. A first bridge holds a transfer mechanism assembly. A second bridge holds a die substrate holder configured to hold the first substrate. A controller is configured to cause the first bridge and the second bridge to move to align the transfer mechanism assembly with the die on the first substrate with a transfer position on the second substrate where the die is to be transferred. | 2021-02-04 |
20210035838 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE TRANSFER METHOD - A substrate processing apparatus includes a transfer chamber row of transfer chambers arranged linearly, a processing chamber row of processing chambers arranged on one side or both sides of the transfer chamber row, a driving mechanism for rotating/extending/contracting a transfer arm of a substrate transfer mechanism in each transfer chamber, and a controller. A center of a substrate supporting region in the processing chamber is positioned closer to the transfer chamber row than a line connecting a rotation axis of the transfer arm and a center of a gate valve. Further, when loading and unloading a substrate between the processing chamber and the adjacent transfer chamber, the controller controls the driving mechanism such that a center of the substrate held by the transfer arm passes along an outer side of a line that connects a rotation axis of the transfer arm and a center of a substrate supporting region. | 2021-02-04 |
20210035839 | VERTICAL BATCH FURNACE ASSEMBLY - A vertical batch furnace assembly for processing wafers comprising a cassette handling space, a wafer handling space, and an internal wall separating the cassette handling space and the wafer handling space. The cassette handling space is provided with a cassette storage configured to store a plurality of wafer cassettes provided with a plurality of wafers. The cassette handling space is also provided with a cassette handler configured to transfer wafer cassettes between the cassette storage and a wafer transfer position. The wafer handling space is provided with a wafer handler configured to transfer wafers between a wafer cassette in the wafer transfer position and a wafer boat in a wafer boat transfer position. The internal wall is provided with a wafer transfer opening adjacent the wafer transfer position for a wafer cassette from or to which wafers are to be transferred. The cassette storage comprises two cassette storage carousels. | 2021-02-04 |
20210035840 | VERTICAL BATCH FURNACE ASSEMBLY - A vertical batch furnace assembly for processing wafers comprising a cassette handling space, a wafer handling space, and a first wall separating the cassette handling space from the wafer handling space. The wall having a wafer transfer opening. The wafer transfer opening is associated with a cassette carrousel comprising a carrousel stage having a plurality of cassette support surfaces each configured for supporting a wafer cassette. The carrousel stage is rotatable by an actuator around a substantially vertical axis to transfer each cassette support surface to a wafer transfer position in front of the wafer transfer opening and to at least one cassette load/retrieve position, wherein the vertical batch furnace assembly is configured to load or retrieve a wafer cassette on or from a cassette support surface of the carousel stage which is in the at least one load/retrieve position. | 2021-02-04 |
20210035841 | VERTICAL BATCH FURNACE ASSEMBLY - A vertical batch furnace assembly for processing wafers comprising a cassette handling space, a wafer handling space, and an internal wall separating the cassette handling space and the wafer handling space. The cassette handling space is provided with a cassette storage configured to store a plurality of wafer cassettes. The cassette handling space is also provided with a cassette handler configured to transfer wafer cassettes between the cassette storage and a wafer transfer position. The wafer handling space is provided with a wafer handler configured to transfer wafers between a wafer cassette in the wafer transfer position and a wafer boat. The internal wall is provided with a wafer transfer opening adjacent the wafer transfer position for a wafer cassette from or to which wafers are to be transferred. The cassette storage comprises a cassette storage carousel with a diameter between 1.1 and 1.6 meter. | 2021-02-04 |
20210035842 | CASSETTE LID OPENING DEVICE - A cassette lid opening device for use in a clean room apparatus configured for cooperation with a wafer cassette. The cassette lid opening device comprises a wall structure having a separation wall having a wall opening for transferring wafers therethrough, a cassette docking port, and a lid handler provided to the wall structure. The cassette docking port is arranged at a first side of the wall structure for docking a wafer cassette. The lid handler is movable relative to the wall opening and configured to engage a cassette lid of the wafer cassette docked in the cassette docking port. The cassette lid opening device further comprises a blower having an elongated, slit-like nozzle substantially spanning a height or a width of the wall opening and configured to blow a curtain-shaped jet stream of a purge gas into a cassette interior of the wafer cassette. | 2021-02-04 |
20210035843 | SEMICONDUCTOR SUBSTRATE SUPPORTS WITH IMPROVED HIGH TEMPERATURE CHUCKING - Exemplary support assemblies may include an electrostatic chuck body defining a substrate support surface. The assemblies may include a support stem coupled with the electrostatic chuck body. The assemblies may include a heater embedded within the electrostatic chuck body. The assemblies may also include an electrode embedded within the electrostatic chuck body between the heater and the substrate support surface. The substrate support assemblies may be characterized by a leakage current through the electrostatic chuck body of less than or about 4 mA at a temperature of greater than or about 500° C. and a voltage of greater than or about 600 V. | 2021-02-04 |
20210035844 | SHEATH AND TEMPERATURE CONTROL OF PROCESS KIT - Embodiments of a process kit are provided herein. In some embodiments, a process kit for use in a substrate processing chamber includes: a ceramic ring having an upper surface and a lower surface, wherein the ceramic ring includes a chucking electrode disposed in the ceramic ring and a heating element disposed in the ceramic ring; and an edge ring disposed on the ceramic ring. | 2021-02-04 |
20210035845 | System and Method for Adhering a Semiconductive Wafer to an Electrostatic Carrier by Adjusting Relative Permittivity - A mobile electrostatic carrier (MESC) provides a structural platform to temporarily bond a semiconductive wafer and can be used to transport the semiconductive wafer or be used to perform manufacturing processes on the semiconductive wafer. The MESC uses a plurality of electrostatic field generating (EFG) circuits to generate electrostatic fields across the MESC that allow the MESC to bond to compositional impurities within the semiconductive wafer. A dielectric thin film is superimposed across the bonding surface of MESC in order to adjust the relative permittivity between the semiconductive wafer to the MESC. This adjustment in the relative permittivity allows the MESC to further adhere the semiconductive wafer to the MESC. | 2021-02-04 |
20210035846 | METHOD OF PROCESSING A SUBSTRATE - A substrate having a first side and a second side opposite the first side is processed by providing a protective film having a front surface and a back surface opposite the front surface and providing a holding frame for holding the substrate. The holding frame has a central opening. The holding frame is attached to the back surface of the protective film so as to close the central opening of the holding frame by the protective film, and the first side of the substrate or the second side of the substrate is attached to the front surface of the protective film. The substrate is processed from the side of the substrate which is opposite the side of the substrate attached to the front surface of the protective film, and/or the side of the substrate which is attached to the front surface of the protective film. | 2021-02-04 |
20210035847 | BACK GRINDING TAPE - The present disclosure relates to a back grinding tape including a polymer resin layer including a urethane (meth)acrylate resin containing 10 to 40 wt % of a repeating unit derived from a (meth)acrylate monomer or oligomer having a glass transition temperature of 0° C. or higher, wherein the polymer resin layer has a glass transition temperature of −30° C. to 0° C. The present disclosure also relates to a method of grinding a wafer using the back grinding tape. | 2021-02-04 |
20210035848 | Wafer Table with Dynamic Support Pins - A method for fabricating a wafer includes providing a wafer table, wherein the wafer table includes support pins that are movable with respect to each other; identifying features of a layer to be formed on a wafer, wherein the features have a tolerance for overlay errors below a threshold; moving one or more support pins based on the features; after the moving of the one or more support pins, mounting the wafer on the wafer table; and after the mounting of the wafer on the wafer table, forming the layer on the wafer. | 2021-02-04 |
20210035849 | CERAMIC PEDESTAL HAVING ATOMIC PROTECTIVE LAYER - A method of manufacturing a support pedestal for use in semiconductor processing includes applying a protective layer on a conductive member of the support pedestal with an atomic layer deposition (ALD) process. The support pedestal has a support plate bonded to a tubular shaft. The support plate has a substrate, an electric element embedded in the substrate, and a conductive member connected to the electric element, and the tubular shaft defines an internal chamber. The ALD process introducing first precursors into the chamber of the tubular shaft to form a first monolayer on the conductive member, and introducing second precursors into the chamber of the tubular shaft to form a second monolayer on the first monolayer. | 2021-02-04 |
20210035850 | METHODS AND APPARATUS FOR ADJUSTING SURFACE TOPOGRAPHY OF A SUBSTRATE SUPPORT APPARATUS - Systems, method and related apparatuses for adjusting support elements of a support apparatus to approximate a surface profile of a wafer. The support apparatus may include a group of mutually lateral adjacent support elements, each mutually lateral adjacent support element is configured to independently move at least vertically and comprising an upper surface. The support apparatus may further include a thermal energy transfer device operably coupled to each of the mutually lateral support elements, and an actuator system operably coupled to each of the support elements to selectively move one or more of the mutually lateral support elements vertically. | 2021-02-04 |
20210035851 | LOW CONTACT AREA SUBSTRATE SUPPORT FOR ETCHING CHAMBER - Embodiments of a substrate support for use in a processing chamber are provided herein. In some embodiments, a substrate support includes a pedestal having an upper surface configured to accommodate a lift pin, a first annular region near an edge of the pedestal, and a second annular region disposed between the first annular region and a center of the pedestal, wherein the pedestal includes a first plurality of holes extending from the upper surface at regular intervals along the first annular region and a second plurality of holes extending from the upper surface at regular intervals along the second annular region; and a non-metal ball comprising aluminum oxide disposed in each hole of the first plurality of holes and the second plurality of holes, wherein an upper surface of each of the non-metal balls is raised with respect to the upper surface of the pedestal to define a support surface. | 2021-02-04 |
20210035852 | METHOD FOR TRANSFERRING COMPOUND SEMICONDUCTOR SINGLE CRYSTAL THIN FILM LAYER AND METHOD FOR PREPARING SINGLE CRYSTAL GaAs-OI COMPOSITE WAFER - Provided are a method for transferring a compound semiconductor single crystal thin film layer and a method for preparing a single crystal GaAs-O I composite wafer, including: preparing a graphite transition layer on a first substrate; growing the compound semiconductor single crystal thin film layer on the graphite transition layer; preparing a first dielectric layer on the compound semiconductor single crystal thin film layer; preparing a second dielectric layer on a second substrate; combining the first substrate and the second substrate by bonding the first dielectric layer and the second dielectric layer; applying a lateral external pressure, such that the compound semiconductor single crystal thin film layer and the first substrate are transversely split at the graphite transition layer, and the compound semiconductor single crystal thin film layer is transferred to the second substrate. | 2021-02-04 |
20210035853 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure includes an integrated circuit, a first dielectric layer over the integrated circuit, an etch stop layer over the first dielectric layer, a barrier layer over the etch stop layer, a conductive layer over the barrier layer, and a void region vertically extending through the conductive layer, the barrier layer, and the etch stop layer. The void region has an upper portion, a middle portion below the upper portion, and a lower portion below the middle portion, the middle portion. The middle portion is narrower than the upper portion and the lower portion. | 2021-02-04 |
20210035854 | METHOD OF FORMING A STRUCTURE USING FLUORINE REMOVAL - Methods of forming structures that include a step of treating a layer to remove residual etchant compounds, such as fluorine, are disclosed. Exemplary methods can be used to fill features on a surface of a substrate during a device manufacturing process. | 2021-02-04 |
20210035855 | METHOD OF PREPARING AN ISOLATION REGION IN A HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE - A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices. | 2021-02-04 |
20210035856 | Interconnect Structure Having an Etch Stop Layer Over Conductive Lines - A multilayer interconnect structure for integrated circuits includes a first dielectric layer over a substrate and a conductive line partially exposed over the first dielectric layer. The structure further includes an etch stop layer over both the first dielectric layer and the exposed conductive line, and a second dielectric layer over the etch stop layer. The second dielectric layer and the etch stop layer provide a via hole that partially exposes the conductive line. The structure further includes a via disposed in the via hole, and another conductive line disposed over the via and coupled to the conductive line through the via. Methods of forming the multilayer interconnect structure are also disclosed. The etch stop layer reduces the lateral and vertical etching of the first and second dielectric layers when the via hole is misaligned due to overlay errors. | 2021-02-04 |
20210035857 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME, AND A TRANSISTOR - A semiconductor structure and a method for forming the same, and a transistor are provided. In one form, a method includes: providing a base, where a dummy gate layer is formed on the base, a spacer is formed on a side wall of the dummy gate layer, an interlayer dielectric layer is formed on the base exposed from the dummy gate layer and the spacer, and the interlayer dielectric layer exposes a top of the dummy gate layer and a top of the spacer; removing a portion of a height of the dummy gate layer to form a remaining dummy gate layer, where the remaining dummy gate layer and the spacer enclose a trench; thinning a spacer exposed from the remaining dummy gate layer along a direction perpendicular to a side wall of the trench; after the thinning, removing the remaining dummy gate layer to form a gate opening within the interlayer dielectric layer; and forming a metal gate structure in the gate opening. Through the thinning, a gate opening whose side wall is provided with a remaining spacer is T-shaped. That is, a dimension of a top opening of the gate opening is increased, so that difficulty in forming the metal gate structure within the gate opening is reduced. That is, forming quality of the metal gate structure within the gate opening is helped to be improved, thereby improving performance of the transistor. | 2021-02-04 |
20210035858 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for forming a semiconductor device includes forming a gate structure on a substrate, and a doped source/drain region on each side of the gate structure; forming a first interlayer dielectric layer, the top surface of the first interlayer dielectric layer leveled with the top surface of the gate structure; forming a contact hole in the first interlayer dielectric layer on each side of the gate structure; forming a cobalt layer in the contact hole, the top surface of the cobalt layer lower than the top surface of the first interlayer dielectric layer; forming a protective layer to cover the cobalt layer, the top layer of the protective layer lower than the top surface of the first interlayer dielectric layer; and forming a second interlayer dielectric layer, the top surface of the second interlayer dielectric layer leveled with the top surface of the first interlayer dielectric layer. | 2021-02-04 |
20210035859 | TRENCHES IN WAFER LEVEL PACKAGES FOR IMPROVEMENTS IN WARPAGE RELIABILITY AND THERMALS - Embodiments disclosed herein include composite dies and methods of forming such composite dies. In an embodiment, a composite die comprises a base substrate, a first die over the base substrate, and a second die over the base substrate and adjacent to the first die. In an embodiment an underfill layer is between the first die and the base substrate, between the second die and the base substrate, and between the first die and the second die. In an embodiment, a trench into the underfill layer is between the first die and the second die. In an embodiment the composite die further comprises, a mold layer over the first die and the second die, wherein the mold layer fills the trench. | 2021-02-04 |
20210035860 | Method for Forming a Buried Metal Line - A method for forming a buried metal line in a substrate includes forming, at a position between a pair of semiconductor structures protruding from the substrate, a metal line trench in the substrate at a level below a base of each semiconductor structure of the pair. Forming the metal line trench includes etching an upper trench portion in the substrate, forming a spacer on sidewall surfaces of the upper trench portion that expose a bottom surface of the upper trench portion, and, while the spacer masks the sidewall surfaces, etching a lower trench portion by etching the substrate via the upper trench portion such that a width of the lower trench portion exceeds a width of the upper trench portion. The method further includes forming the metal line in the metal line trench. | 2021-02-04 |
20210035861 | Barrier-Free Approach For Forming Contact Plugs - A method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process, so that a bottom portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source/drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metallic material on the silicon-and-nitrogen-containing layer. | 2021-02-04 |
20210035862 | Methods for Forming Self-Aligned Interconnect Structures - The present disclosure provides a method for forming interconnect structures. The method includes providing a semiconductor structure including a substrate and a conductive feature formed in a top portion of the substrate; depositing a resist layer over the substrate, wherein the resist layer has an exposure threshold; providing a radiation with an incident exposure dose to the resist layer, wherein the incident exposure dose is configured to be less than the exposure threshold of the resist layer while a sum of the incident exposure dose and a reflected exposure dose from a top surface of the conductive feature is larger than the exposure threshold of the resist layer, thereby forming a latent pattern above the conductive feature; and developing the resist layer to form a patterned resist layer. | 2021-02-04 |
20210035863 | Self-Aligned Subtractive Interconnect Patterning - Described are semiconductor devices, methods of manufacturing, and methods for device patterning. More particularly, a subtractive interconnect patterning method is described. A subtractive interconnect patterning is used in place of damascene interconnect patterning. | 2021-02-04 |
20210035864 | Electronic Device Including a Polymer Support Layer and a Process of Forming the Same - A process can be used to allow processing of thin layers of a workpiece including dies. The workpiece can include a base substrate and a plurality of layers overlying the base substrate. The process can include forming a polymer support layer over the plurality of layers; thinning or removing the base substrate within a component region of the workpiece, wherein the component region includes an electronic device; and singulating the workpiece into a plurality of dies after thinning or removing the base substrate. In another aspect, an electronic device can be formed using such process. In an embodiment, the workpiece may have a size corresponding to a semiconductor wafer to allow wafer-level, as opposed to die-level, processing. | 2021-02-04 |
20210035865 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE WITH A METAL GATE - The present disclosure provides a method of forming a semiconductor structure with a metal gate. The semiconductor structure is formed by first fabricating fins over a semiconductor substrate, followed by a formation of a source and a drain recess. A source and a drain region may then be deposited into the source and the drain recess. The gate structure may be deposited into the region between the fins. The gate structure includes dielectric and metallic layers. In the regions between the fins, the gate structure is isolated from the source and the drain region by an insulating layer. | 2021-02-04 |
20210035866 | METHOD FOR MANUFACTURING NANOSTRUCTURE WITH VARIOUS WIDTHS - Methods for manufacturing semiconductor structures are provided. The method includes alternately stacking sacrificial layers and semiconductor layers over a substrate to form a semiconductor stack and forming a first mask structure and a second mask structure over the semiconductor stack. In addition, a width of the first mask structure is substantially equal to a width of the second mask structure. The method further includes forming spacers on sidewalls of the second mask structure and patterning the semiconductor stack to form a first fin structure overlapping the first mask structure and a second fin structure overlapping the second mask structure and the spacers. In addition, the first fin structure has a first width and the second fin structure has a second width different from the first width. The method further includes removing the sacrificial layers to form first nanostructures and second nanostructures. | 2021-02-04 |
20210035867 | LOCAL ISOLATION OF SOURCE/DRAIN FOR REDUCING PARASITIC CAPACITANCE IN VERTICAL FIELD EFFECT TRANSISTORS - A vertical field effect transistor structure and method for fabricating the same. The structure includes a source/drain layer in contact with at least one semiconductor fin. An edge portion of the source/drain layer includes a notched region filled with a dielectric material. A spacer layer includes a first portion in contact with the source/drain layer and a second portion in contact with the dielectric material. A gate structure contacts the spacer layer and the dielectric material. The method includes forming a source/drain layer in contact with at least one semiconductor fin. A spacer layer is formed in contact with the source/drain layer. A portion of the spacer layer is removed to expose an end portion of the source/drain layer. The exposed end portion of the source/drain layer is recessed to form a notched region within the source/drain layer. A dielectric layer is formed within the notched region. | 2021-02-04 |
20210035868 | Semiconductor Device and Method of Manufacturing - A semiconductor device with multiple silicide regions is provided. In embodiments a first silicide precursor and a second silicide precursor are deposited on a source/drain region. A first silicide with a first phase is formed, and the second silicide precursor is insoluble within the first phase of the first silicide. The first phase of the first silicide is modified to a second phase of the first silicide, and the second silicide precursor being soluble within the second phase of the first silicide. A second silicide is formed with the second silicide precursor and the second phase of the first silicide. | 2021-02-04 |
20210035869 | SEMICONDUCTOR STRUCTURES IN A WIDE GATE PITCH REGION OF SEMICONDUCTOR DEVICES - A semiconductor device is provided that includes an active region above a substrate, a first gate structure, a second gate structure, a first semiconductor structure, a second semiconductor structure and a semiconductor bridge. The first gate semiconductor and the second semiconductor structure are in the active region and between the first and the second gate structures. The first semiconductor structure is adjacent to the first gate structure and a second semiconductor structure is adjacent to the second gate structure. The semiconductor bridge is in the active region electrically coupling the first and the second semiconductor structures. | 2021-02-04 |
20210035870 | Nano-Sheet-Based Complementary Metal-Oxide-Semiconductor Devices with Asymmetric Inner Spacers - A semiconductor device is provided. The device includes a first pair and a second pair of source/drain features over a semiconductor substrate. The first pair of source/drain features are p-type doped. The second pair of source/drain features are n-type doped. A first stack of semiconductor layers connect the first pair of source/drain features along a first direction. A second stack of semiconductor layers connect the second pair of source/drain features along a second direction. A first gate is between vertically adjacent layers of the first stack of semiconductor layers. The first gate has a first portion that has a first dimension along the first direction. A second gate is between vertically adjacent layers of the second stack of semiconductor layers. The second gate has a second portion that has a second dimension along the second direction. The second dimension is larger than the first dimension. | 2021-02-04 |
20210035871 | METHOD AND APPARATUS TO DETERMINE A PATTERNING PROCESS PARAMETER - A metrology target includes: a first structure arranged to be created by a first patterning process; and a second structure arranged to be created by a second patterning process, wherein the first structure and/or second structure is not used to create a functional aspect of a device pattern, and wherein the first and second structures together form one or more instances of a unit cell, the unit cell having geometric symmetry at a nominal physical configuration and wherein the unit cell has a feature that causes, at a different physical configuration than the nominal physical configuration due to a relative shift in pattern placement in the first patterning process, the second patterning process and/or another patterning process, an asymmetry in the unit cell. | 2021-02-04 |
20210035872 | Grinding Control Method And Device For Wafer, And Grinding Device - A grinding control method and device for a wafer, and a grinding device are provided. A grinder is controlled to grind a mass production wafer with a set grinding parameter. In a case that it is determined to perform a test using a test wafer, the grinder may be controlled to grind the test wafer with the set grinding parameter. A first total thickness variation of the grinded test wafer is acquired by a dedicated measurement device, and an updated grinding parameter is acquired based on the first total thickness variation. The grinder is controlled to grind the mass production wafer with the updated grinding parameter. In this way, a wafer with a uniform thickness can be obtained, thereby improving flatness of the grinded wafer. | 2021-02-04 |
20210035873 | STEP-TYPE STACKED CHIP PACKAGING STRUCTURE BASED ON RESIN SPACER AND PREPARATION PROCESS - A step-type stacked chip packaging structure based on a resin spacer that includes: a plastic packaging material, a circuit board, a resin spacer, a first chip, a second chip and an electrical connection assembly. The resin spacer, the first chip, and the second chip are stacked on the circuit board respectively. The second chip is stacked on the first chip in a stepped manner. The circuit board, the first chip and the second chip are electrically connected together through the electrical connection assembly. The resin spacer uses a fiber glass fabric as its base material, a weight percent of the fiber glass fabric is 10-60 wt %, and the following components are attached to the fiber glass fabric as a percentage by the total weight of the resin spacer: 8-40 wt % of epoxy resin, 10-30 wt % of quartz powder, 2-10 wt % of aluminum oxide, 1-8 wt % of calcium oxide, and 1-8 wt % of curing agent. | 2021-02-04 |
20210035874 | THROUGH ELECTRODE SUBSTRATE, MANUFACTURING METHOD THEREOF AND MOUNTING SUBSTRATE - A manufacturing method of a through electrode substrate includes: a step of preparing a substrate including a first surface and a second surface positioned oppositely to the first surface, and provided with a through hole; a step of providing a sealing layer blocking the through hole on the first surface of the substrate; an electrode forming step of forming a through electrode inside the through hole, the through electrode having a fist part extending along a sidewall of the through hole, and a second part connected to the first part and spreading along the sealing layer; and a step of removing the sealing layer. | 2021-02-04 |
20210035875 | AUTOMATIC REGISTRATION BETWEEN CIRCUIT DIES AND INTERCONNECTS - Processes for automatic registration between a solid circuit die and electrically conductive interconnects, and articles or devices made by the same are provided. The solid circuit die is disposed at a registration area of a substrate. Fluid channels extend into the registration area and have a portion underneath the bottom surface of the solid circuit die. Electrically conductive traces are formed by flowing a conductive liquid in the channels toward contact pads on the bottom surface of the circuit die to obtain the automatic registration. | 2021-02-04 |
20210035876 | SEMICONDUCTOR PACKAGE INCLUDING A CAVITY IN ITS PACKAGE BODY - A semiconductor package is disclosed. In one example, the semiconductor package includes a package body and a semiconductor component encapsulated in the package body. A cavity is formed in a bottom surface of the package body. | 2021-02-04 |