06th week of 2017 patent applcation highlights part 54 |
Patent application number | Title | Published |
20170040295 | VERTICALLY INTEGRATED WAFERS WITH THERMAL DISSIPATION - Technologies are generally described related to three-dimensional integration of integrated circuits (ICs) with spacing for heat dissipation. According to some examples, a self-aligned silicide may be formed in a temporary silicon layer and removed subsequent to bonding of the wafers to achieve improved contact between the combined ICs and enhanced heat dissipation through added spacing between the ICs. | 2017-02-09 |
20170040296 | Multi-Layer Semiconductor Devices Fabricated Using a Combination of Substrate and Via Structures and Fabrication Techniques - A multi-layer semiconductor device includes two or more semiconductor sections, each of the semiconductor sections including at least at least one device layer having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The electrical connections correspond to first conductive structures. The multi-layer semiconductor device also includes one or more second conductive structures which are provided as through oxide via (TOV) or through insulator via (TIV) structures. The multi-layer semiconductor device additionally includes one or more silicon layers. At least a first one of the silicon layers includes at least one third conductive structure which is provided as a through silicon via (TSV) structure. The multi-layer semiconductor device further includes one or more via joining layers including at least one fourth conductive structure. A corresponding method for fabricating a multi-layer semiconductor device is also provided. | 2017-02-09 |
20170040297 | SEMICONDUCTOR DEVICE HAVING THROUGH SILICON VIAS AND MANUFACTURING METHOD THEREOF - In The semiconductor device, a semiconductor substrate has first and second surfaces. A circuitry layer is formed over the first surface and a first insulating layer is further formed over the circuitry layer. A second insulating layer including a first insulating element is formed over the second surface. A third insulating layer including a second insulating element different from the first insulating element of the second insulating layer is formed over the second surface with an intervention of the second insulating layer therebetween. A penetration electrode penetrates through the semiconductor substrate, the circuitry layer, the first insulating layer, the second insulating layer and the third insulating layer. | 2017-02-09 |
20170040298 | Package-on-Package Method - A method comprises forming a trench over a top surface of a metal structure of a bottom package, dispersing an epoxy flux material in the trench, mounting a top package on the bottom package, wherein a solder ball of the top package is in direct contact with the top surface of the metal structure and performing a reflow process to form a joint structure, wherein the joint structure comprises the solder ball of the top package coupled to the metal structure in the bottom package and an epoxy protection layer having a first edge in direct contact with a top surface of the bottom package and a second edge surrounding a lower portion of the solder ball. | 2017-02-09 |
20170040299 | DISPLAY DEVICE AND LIGHT-EMITTING ARRAY MODULE THEREOF - A light-emitting array module includes a circuit substrate, a light-emitting unit, and an encapsulation body. The light-emitting unit includes a plurality of light-emitting groups arranged in matrix on the circuit substrate. The encapsulation body disposed on the circuit substrate for encapsulating the light-emitting groups. The encapsulation body includes a plurality of encapsulation portions and a plurality of thin connection portions. Therefore, light beams generated by the light-emitting group is transformed into an obvious single point light source without halation due to the design of “each thin connection portion connected between the two adjacent encapsulation portions to separate the two adjacent encapsulation portions from each other by a predetermined distance”, so that the color resolution of the light-emitting array module is increased. In addition, the present disclosure further provides a display device including the light-emitting array module. | 2017-02-09 |
20170040300 | LIGHTING DEVICE AND METHOD FOR PRODUCING A LIGHTING DEVICE - A method for producing a lighting device is disclosed. The method comprises: providing two or more light sources ( | 2017-02-09 |
20170040301 | LIGHT-EMITTING DEVICE AND BACKLIGHT INCLUDING LIGHT-EMITTING DEVICE - The light-emitting device includes a first light-emitting element having an emission peak wavelength of 430 nm or more and less than 490 nm, a second light-emitting element having an emission peak wavelength of 490 nm or more and 570 nm or less, a support body at which the first light-emitting element and the second light-emitting element are disposed, and a light-transmissive member containing a red phosphor and covering the first light-emitting element and the second light-emitting element. A content density of the red phosphor in the light-transmissive member in a space between the first and second light-emitting elements is higher in a part below an upper surface of the second light-emitting element than in a part above the upper surface thereof. | 2017-02-09 |
20170040302 | METHOD FOR PRODUCING A LIGHT EMITTING DEVICE - A method for producing a light emitting device includes a first bonding step including disposing a first bonding member a mounting substrate, placing a light emitting element on the mounting substrate such that the first bonding member is located between a mounting face of the light emitting element and the mounting substrate, and hardening the first bonding member thereby bonding the light emitting element and the mounting substrate such that, in a plan view, an entirety of the first bonding member is contained within an area of the mounting face of the light emitting element; and a second bonding step including disposing a second bonding member on the upper face of the mounting substrate such that, in a plan view, the second bonding member is located at at least a portion of an outer edge of the mounting face of the light emitting element, and hardening the second bonding member. | 2017-02-09 |
20170040303 | SEMICONDUCTOR DEVICE ASSEMBLY WITH THROUGH-PACKAGE INTERCONNECT AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS - Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device. | 2017-02-09 |
20170040304 | ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOF - An electronic package is provided, including: a substrate having opposite first and second surfaces; at least a first electronic element disposed on the first surface of the substrate; a first encapsulant encapsulating the first electronic element; at least a second electronic element and a frame disposed on the second surface of the substrate; and a second encapsulant encapsulating the second electronic element. By disposing the first and second electronic elements on the first and second surfaces of the substrate, respectively, the invention allows a required number of electronic elements to be mounted on the substrate without the need to increase the surface area of the substrate. Since the volume of the electronic package does not increase, the electronic package meets the miniaturization requirement. The present invention further provides a method for fabricating the electronic package. | 2017-02-09 |
20170040305 | OPTICAL COUPLING DEVICE - An optical coupling device includes a first receiving chip having a first region on one end and a second region on another end side. A first emitting chip is disposed on the first region. A second receiving chip has a third region on one end and a fourth region on another end. A second emitting chip is disposed on the fourth region. The first and third regions are adjacent, and the second and fourth regions are adjacent. A first connection portion is disposed on the second region and is electrically connected to the second light emitting chip through a bonding wire. A second connection portion is disposed in the third region and is electrically connected to the first light emitting chip through a bonding wire. | 2017-02-09 |
20170040306 | Electronic Devices With Soft Input-Output Components - An electronic device may have control circuitry coupled to input-output devices such as a display. A flexible input-output device may be formed from an elastomeric substrate layer. The substrate layer may have signal paths to which components are mounted. Openings may be formed in the elastomeric substrate layer between the signal paths to create a stretchable mesh-shaped substrate. The electrical components may each include an interposer having solder pads soldered to the elastomeric substrate. Electrical devices such as micro-light-emitting diodes may be soldered to the interposers. The electrical components may also include electrical devices such as sensors and actuators. A stretchable lighting unit may have a stretchable light guide illuminated by a stretchable light source. | 2017-02-09 |
20170040307 | LIGHT EMITTING DEVICE PACKAGE AND LIGHT UNIT INCLUDING THE SAME - Disclosed are a light emitting device package. The light emitting device package includes a body having recess; a first lead frame including a first and second portions on a first region of the body; a second lead frame including a third and fourth portions on a second region of the body; a third lead frame between the first and second lead frame. The body has a length of the first direction greater than a width of the second direction, wherein the second portion of the first lead frame extends toward the second lead frame and has a small width, and wherein the fourth portion of the second lead frame extends toward the first lead frame. A first light emitting device is disposed on the first portion of the first lead frame and a second light emitting device is disposed on the third portion of the second lead frame. | 2017-02-09 |
20170040308 | METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE - Embodiments of inventive concepts disclosed provide a method of manufacturing a semiconductor package. The method includes mounting a plurality of semiconductor chips on a substrate having a connecting member protruding from a top surface of the substrate, applying a non-conductive paste on the substrate and the semiconductor chips, forming a supporting layer coupling each of the semiconductor chips to the substrate, aligning an interposer on the non-conductive paste, forming a non-conductive layer by applying heat while pressing the interposer and the substrate against each other, and cutting the substrate, the non-conductive layer, and the interposer into separate unit packages, each of which include a semiconductor chip. | 2017-02-09 |
20170040309 | Chip on Chip Attach (Passive IPD and PMIC) Flip Chip BGA Using New Cavity BGA Substrate - An integrated passive device and power management integrated circuit are directly connected, active surface to active surface, resulting in a pyramid die stack. The die stack is flip-chip attached to a laminate substrate having a cavity drilled therein wherein the smaller die fits into the cavity. The die to die attach is not limited to IPD and PMIC and can be used for other die types as required. | 2017-02-09 |
20170040310 | SEMICONDUCTOR DEVICE HAVING IMPROVED CORE AND INPUT/OUTPUT DEVICE RELIABILITY - A semiconductor device includes a semiconductor substrate having a core device and an IO device. The core device includes a gate interface layer and a high-k dielectric layer on the gate interface layer. The IO device includes a gate interface layer and a high-k dielectric layer on the gate interface layer. The gate interface layer of the core device and the gate interface layer of the IO device each are doped with fluoride ions | 2017-02-09 |
20170040311 | DIODE STRING IMPLEMENTATION FOR ELECTROSTATIC DISCHARGE PROTECTION - A diode string having a plurality of diodes for ESD protection of a CMOS IC device comprises a first diode and a last diode in the diode string, wherein the first diode and the last diode are both formed on a bottom layer in a silicon substrate, and remaining diodes in the diode string. The remaining diodes are formed on a top layer placed on top of the bottom layer. The diode string further comprises a plurality of conductive lines that connect the first diode and the last diode on the bottom layer sequentially with the remaining diodes on the top layer to form a three dimensional (3D) structure of the diode string. | 2017-02-09 |
20170040312 | Avalanche-Rugged Quasi-Vertical HEMT - A semiconductor device includes a semiconductor body including first and second lateral surfaces. A first device region includes a drift region of a first conductivity type, and a drift current control region of a second conductivity type being spaced apart from the second lateral surface by the drift region. A second device region includes a barrier layer, and a buffer layer having a different band gap than the barrier layer so that a two-dimensional charge carrier gas channel arises along an interface between the buffer layer and the barrier layer. An electrically conductive substrate contact forms a low ohmic connection between the two-dimensional charge carrier gas channel and the drift region. A gate structure is configured to control a conduction state of the two-dimensional charge carrier gas. The drift current control region is configured to block a vertical current in the drift region via a space-charge region. | 2017-02-09 |
20170040313 | SEMICONDUCTOR STRUCTURE WITH RESISTOR LAYER AND METHOD FOR FORMING THE SAME - A semiconductor device structure including a resistor layer is provided. The semiconductor device structure includes a gate structure formed over the first region of the substrate and an inter-layer dielectric (ILD) layer formed adjacent to the gate structure. The semiconductor device structure further includes a resistor layer is formed over the ILD layer over the second region of the substrate, and the major structure of the resistor layer is amorphous. | 2017-02-09 |
20170040314 | MIM CAPACITOR FORMATION IN RMG MODULE - A method is provided for forming a metal-insulator-metal capacitor in a replacement metal gate module. The method includes providing a gate cap formed on a gate. The method further includes removing a portion of the gate cap and forming a recess in the gate. A remaining portion of the gate forms a first electrode of the capacitor. The method also includes depositing a dielectric on remaining portions of the gate cap and the remaining portion of the gate. The method additionally includes depositing a conductive material on the dielectric. The method further includes removing a portion of the conductive material and portions of the dielectric to expose a remaining portion of the conductive material and a remaining portion of the dielectric. The remaining portion of the conductive material forms a second electrode of the capacitor. The remaining portion of the dielectric forms an insulator of the capacitor. | 2017-02-09 |
20170040315 | DEVICES INCLUDING GATES WITH MULTIPLE LENGTHS AND METHODS OF MANUFACTURING SAME - A method for manufacturing a semiconductor device comprises forming a first dummy gate layer on a substrate, forming a second dummy gate layer on the substrate adjacent the first dummy gate layer, wherein the second dummy gate layer comprises a material which is capable of being selectively etched with respect a material of the first dummy gate layer, and patterning each of the first and second dummy gate layers into a plurality of first dummy gate stacks and a plurality of second dummy gate stacks, respectively, wherein the first dummy gate stacks are each wider along a gate length direction than each of the second dummy gate stacks, wherein the patterning is performed using a reactive ion etch (RIE) process that results in different lateral trimming between the first and second dummy gate layers. | 2017-02-09 |
20170040316 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate including a trench provided in a surface of the semiconductor substrate; a trench electrode provided in the trench; an interlayer insulating film covering a surface of the trench electrode and protruding from the surface of the semiconductor substrate; a Schottky electrode provided on the surface of the semiconductor substrate, provided in a position separated from the interlayer insulating film, and being in Schottky contact with the semiconductor substrate; an embedded electrode provided in a concave portion between the interlayer insulating film and the Schottky electrode and made of a metal different from a metal of the Schottky electrode; and a surface electrode covering the interlayer insulating film, the embedded electrode, and the Schottky electrode. | 2017-02-09 |
20170040317 | Semiconductor Device with a Laterally Varying Doping Profile, and Method for Manufacturing Thereof - A semiconductor device includes a semiconductor substrate having a first side. At least a first doping region is formed in the semiconductor substrate. The first doping region has a laterally varying doping dosage and/or a laterally varying implantation depth. | 2017-02-09 |
20170040318 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first fin-shaped structure on a first region and a second fin-shaped structure on a second region; forming a plurality of first gate structures on the first fin-shaped structure, a plurality of second gate structures on the second fin-shaped structure, and an interlayer dielectric (ILD) layer around the first gate structures and the second gate structures; forming a first patterned mask on the ILD layer; forming a second patterned mask on the second region; using the first patterned mask and the second patterned mask to remove all of the ILD layer from the first region and part of the ILD layer from the second region for forming a plurality of first contact holes in the first region and a plurality of second contact holes in the second region. | 2017-02-09 |
20170040319 | SELF-CUT SIDEWALL IMAGE TRANSFER PROCESS - A plurality of mandrels is formed on a silicon substrate. The mandrels are spaced apart at a given pitch, wherein at least one of the plurality of mandrels is formed having a first width, and at least another one of the plurality of mandrels is formed having a second width, and wherein the first width is greater than the second width. At least one structure is formed by removing at least a portion of the plurality of mandrels in a sidewall image transfer process without using a cut mask. | 2017-02-09 |
20170040320 | SEMICONDUCTOR FIN ISOLATION BY A WELL TRAPPING FIN PORTION - A bulk semiconductor substrate including a first semiconductor material is provided. A well trapping layer including a second semiconductor material and a dopant is formed on a top surface of the bulk semiconductor substrate. The combination of the second semiconductor material and the dopant within the well trapping layer is selected such that diffusion of the dopant is limited within the well trapping layer. A device semiconductor material layer including a third semiconductor material can be epitaxially grown on the top surface of the well trapping layer. The device semiconductor material layer, the well trapping layer, and an upper portion of the bulk semiconductor substrate are patterned to form at least one semiconductor fin. Semiconductor devices formed in each semiconductor fin can be electrically isolated from the bulk semiconductor substrate by the remaining portions of the well trapping layer. | 2017-02-09 |
20170040321 | GATE-ALL-AROUND NANOWIRE DEVICE AND METHOD FOR MANUFACTURING SUCH A DEVICE - The disclosed technology generally relates to a semiconductor device, and more particularly to a gate all around (GAA) semiconductor device and a method for fabricating the same. In one aspect, a semiconductor device has a vertical stack of nanowires formed on a substrate, wherein the vertical stack of nanowires comprises an n-type nanowire and a p-type nanowire each extending in a longitudinal direction parallel to a main surface of the substrate. The n-type nanowire comprises a first material and the p-type nanowire comprises an inner part having two sides and an outer part at each side of the inner part in the longitudinal direction, wherein one or both of the two outer parts comprises a second material different from the first material. The n-type nanowire and the p-type nanowire each comprises a channel region electrically coupled to respective source and drain regions. The channel region of the p-type nanowire comprises the inner part. The device additionally includes a shared gate structure circumferentially surrounding the channel regions of the n-type and p-type nanowires. | 2017-02-09 |
20170040322 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - An integrated circuit device includes a substrate including a first region and a second region, a first transistor in the first region, the first transistor being an N-type transistor and including a first silicon-germanium layer on the substrate, and a first gate electrode on the first silicon-germanium layer, and a second transistor in the second region and including a second gate electrode, the second transistor not having a silicon-germanium layer between the substrate and the second gate electrode. | 2017-02-09 |
20170040323 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device may include a strain relaxed buffer layer provided on a substrate to contain silicon germanium, a semiconductor pattern provided on the strain relaxed buffer layer to include a source region, a drain region, and a channel region connecting the source region with the drain region, and a gate electrode enclosing the channel region and extending between the substrate and the channel region. The source and drain regions may contain germanium at a concentration of 30 at % or higher. | 2017-02-09 |
20170040324 | FINFET DEVICE AND METHOD OF MAKING THE SAME - A finFET device according to some examples herein may include an active gate element above an active fin element and a dummy fin element that partially breaks the active gate element. In another example, a dummy gate element adjacent to an active gate element contains a dummy fin element that partially breaks the dummy gate element. In another example, a first dummy fin element partially breaks an active gate element and a second dummy fin element partially breaks a dummy gate element. In another example, the dummy fin element is of the same material as the active fin element. In another example, the dummy fin element partially breaks a gate element but does not extend to the substrate like the active fin element. | 2017-02-09 |
20170040325 | FIELD EFFECT TRANSISTOR DEVICE SPACERS - A method for forming field effect transistors comprises forming a first dummy gate stack over a first fin, forming a second dummy gate stack over a second fin, depositing a first layer of spacer material on the first dummy gate stack, the first fin, the second dummy gate stack, and the second fin, patterning a first masking layer on the first dummy gate stack and the first fin, etching to remove portions of the first layer of spacer material and form a spacer adjacent to the second dummy gate stack, removing the first masking layer, epitaxially growing a silicon material on the second fin, depositing a layer of oxide material on the first layer of spacer material, the first epitaxial material and the second dummy gate stack, and depositing a second layer of spacer material on the layer of oxide material. | 2017-02-09 |
20170040326 | Method of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled Rectifier Principle - Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations. A method of maintaining the data state of a semiconductor dynamic random access memory cell is provided, wherein the memory cell comprises a substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type; a second region having the second conductivity type, the second region being spaced apart from the first region; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; and a gate positioned between the first and second regions and adjacent the body region. The memory cell is configured to store a first data state which corresponds to a first charge in the body region in a first configuration, and a second data state which corresponds to a second charge in the body region in a second configuration. The method includes: providing the memory cell storing one of the first and second data states; and applying a positive voltage to a substrate terminal connected to the substrate beneath the buried layer, wherein when the body region is in the first state, the body region turns on a silicon controlled rectifier device of the cell and current flows through the device to maintain configuration of the memory cell in the first memory state, and wherein when the memory cell is in the second state, the body region does not turn on the silicon controlled rectifier device, current does not flow, and a blocking operation results, causing the body to maintain the second memory state. | 2017-02-09 |
20170040327 | Method Of Forming Conductive Material Of A Buried Transistor Gate Line And Method Of Forming A Buried Transistor Gate Line - A method of forming conductive material of a buried transistor gate line includes adhering a precursor comprising tungsten and chlorine to material within a substrate trench. The precursor is reduced with hydrogen to form elemental-form tungsten material over the material within the substrate trench from the precursor. | 2017-02-09 |
20170040328 | INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME - A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line. | 2017-02-09 |
20170040329 | METHOD FOR PRODUCING AN SGT-INCLUDING SEMICONDUCTOR DEVICE - A method for producing an SGT-including semiconductor device includes forming a gate insulating layer on an outer periphery of a Si pillar, forming a gate conductor layer on the gate insulating layer, and forming an oxide layer on the gate conductor layer. Then a hydrogen fluoride ion diffusion layer containing moisture is formed so as to make contact with the oxide layer and lie at an intermediate position of the Si pillar. A part of the oxide film in contact with the hydrogen fluoride ion diffusion layer is etched with hydrogen fluoride ions generated from hydrogen fluoride gas supplied to the hydrogen fluoride ion diffusion layer and an opening is thereby formed on the outer periphery of the Si pillar. | 2017-02-09 |
20170040330 | NON-VOLATILE MEMORY - A non-volatile memory including following elements is provided. The floating gate transistor, the select transistor and the stress-releasing transistor are disposed on the substrate and coupled in series with each other. The stress-releasing transistor is located between the floating gate transistor and the select transistor. The stress-releasing transistor has a stress release ratio represented by formula (1). A lower limit value of the stress release ratio is determined by a sustainable drain side voltage of the stress-releasing transistor of the non-volatile memory which is unselected when a program operation is performed. An upper limit value of the stress release ratio is determined by a readable drain current of the non-volatile memory which is selected when a read operation is performed. | 2017-02-09 |
20170040331 | FERROELECTRIC MEMORY DEVICE AND FABRICATION METHOD THEREOF - The disclosed technology generally relates to semiconductor devices, and more particularly to a non-volatile ferroelectric memory device and to methods of fabricating the same. In one aspect, a non-volatile memory device includes a high dielectric constant layer (high-k) layer or a metal layer on a semiconductor substrate. The non-volatile memory device additionally includes a two-dimensional (2D) semiconductor channel layer interposed between the high-k layer or metal layer and a ferroelectric layer. The non-volatile memory device additionally includes a metal gate layer on the ferroelectric layer, and further includes a source region and a drain region each electrically coupled to the 2D semiconductor channel layer. | 2017-02-09 |
20170040332 | LOW COST FLASH MEMORY FABRICATION FLOW BASED ON METAL GATE PROCESS - An integrated circuit contains a flash cell in which the top gate of the sense transistor is a metal sense gate over the floating gate. The source/drain regions of the sense transistor extend under the floating gate so that the source region is separated from the drain region by a sense channel length less than 200 nanometers. The floating gate is at least 400 nanometers wide, so the source/drain regions of the sense transistor extend under the floating gate at least 100 nanometers on each side. The integrated circuit is formed by forming the sense transistor source and drain regions before forming the floating gate. | 2017-02-09 |
20170040333 | Contact Plug Constrained By Dielectric Portions - A NAND flash memory includes active areas separated by STI structures in a substrate with a layer of a first dielectric over the substrate. Portions of a second dielectric extend over the STI structures and another layer of the first dielectric extends over both the layer and portions, with contact holes extending through the dielectric layers at locations over the active areas in the semiconductor substrate. | 2017-02-09 |
20170040334 | NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF - A non-volatile memory having memory cells is provided. A stacked gate structure has gate dielectric layer, assist gate, insulation layer, and erase gate disposed in order. The floating gate is disposed on a first sidewall of the stacked gate structure, the floating gate has a corner portion at the top portion, and erase gate covers the corner portion. The tunneling dielectric layer is disposed under the floating gate. The erase gate dielectric layer is disposed between the erase gate and the floating gate. The assist gate dielectric layer is disposed between the assist gate and the floating gate. The source region and the drain region are respectively disposed at two sides of the stacked structure and the floating gate. The control gate is disposed on the source region and the floating gate. The inter-gate dielectric layer is disposed between the control gate and the floating gate. | 2017-02-09 |
20170040335 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a plurality of memory cell arrays, and an air gap structure. The substrate includes a cell region, a peripheral circuit region, and a boundary region. The boundary region is between the cell region and the peripheral circuit region. The plurality of memory cell arrays are on the cell region. The air gap structure includes a trench formed in the boundary region of the substrate. The air gap structure defines an air gap. | 2017-02-09 |
20170040336 | SEMICONDUCTOR MEMORY DEVICES HAVING VERTICAL PILLARS THAT ARE ELECTRICALLY CONNECTED TO LOWER CONTACTS - A semiconductor memory device may include an electrode structure including a selection line on a substrate and word lines between the substrate and the selection line, vertical pillars penetrating the electrode structure and being connected to the substrate, sub-interconnections and bit lines sequentially stacked on and electrically connected to the vertical pillars, and lower contacts connecting the vertical pillars to the sub-interconnections. The selection line may include a plurality of selection lines separated from each other in a first direction by an insulating separation layer, and central axes of the lower contacts connected in common to one of the sub-interconnections may be shifted, in a second direction across the first direction and parallel to a top surface of the substrate, from central axes of the vertical pillars thereunder. | 2017-02-09 |
20170040337 | VERTICAL MEMORY DEVICES HAVING DUMMY CHANNEL REGIONS - A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions. | 2017-02-09 |
20170040338 | SEMICONDUCTOR MEMORY DEVICES HAVING CLOSELY SPACED BIT LINES - The inventive concepts relate to a semiconductor memory device. The semiconductor memory device includes a substrate including a circuit region and first and second connection regions respectively disposed at both sides of the circuit region opposite to each other, a logic structure including a logic circuit disposed on the circuit region and a lower insulating layer covering the logic circuit, and a memory structure on the logic structure. The logic circuit includes a first page buffer disposed adjacently to the first connection region and a second page buffer disposed adjacently to the second connection region. The memory structure includes bit lines extending onto at least one of the first and second connection regions. | 2017-02-09 |
20170040339 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. The semiconductor device includes an electrode disposed on a substrate and a plurality of vertical patterns passing through the electrode. The vertical patterns include first vertical patterns arranged to form a rhombus and second vertical patterns arranged to form a non-regular trapezoid or a rhombus. | 2017-02-09 |
20170040340 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes a stacked body; a semiconductor body; and charge storage film. The stacked body includes the plurality of electrode layers separately stacked each other. The semiconductor body is provided in the stacked body and extends in a stack direction of the stacked body and includes an oxide semiconductor. The charge storage film is provided between the semiconductor body and the plurality of electrode layers. | 2017-02-09 |
20170040341 | SEMICONDUCTOR MEMORY DEVICE - According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit. | 2017-02-09 |
20170040342 | METHOD FOR MANUFACTURING THIN FILM TRANSISTOR, THIN FILM TRANSISTOR, AND ARRAY SUBSTRATE AND DISPLAY DEVICE USING THE SAME - The present disclosure relates to the field of display technology and provides a method for manufacturing a TFT, the TFT, an array substrate including the TFT, and a display device. The method includes steps of forming a pattern of a gate electrode on a base substrate, forming a gate insulation layer on the base substrate, and forming patterns of a source electrode and a drain electrode arranged above the gate insulation layer. The method further includes forming an antioxidation metal protection layer on a surface or surfaces of the gate electrode, the source electrode and/or the drain electrode. | 2017-02-09 |
20170040343 | THIN FILM TRANSISTOR AND FABRICATION METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY PANEL - A thin film transistor and a fabrication method thereof, an array substrate and a display panel are provided. The thin film transistor includes: a gate electrode ( | 2017-02-09 |
20170040344 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - A low-power-consumption semiconductor device or the like is provided. Charge is accumulated in a node connected to a capacitor for a certain period to perform a current-voltage conversion. A gate of a transistor is connected to the node and the potential of one of a source and a drain of the transistor is changed gradually or continuously so that the potential is read when the transistor is turned on. The threshold voltage of the transistor and the capacitance value of the node are measured, so that the current-voltage conversion is performed more precisely. | 2017-02-09 |
20170040345 | DISPLAY DEVICE - A display device includes two or more pixels disposed in a pixel area in which two or more data lines intersect two or more gate lines; a common electrode commonly disposed on the pixels; a first gate high voltage supplied through a first gate voltage line, a portion of the first gate high voltage overlapping the common electrode; a second gate high voltage supplied through a second gate voltage line, a portion of the second gate high voltage overlapping the common electrode; a connecting line structure in contact with the common electrode, and extending from the common electrode in a direction toward a position in which the common electrode does not overlap the first gate voltage line. | 2017-02-09 |
20170040346 | METHOD FOR FABRICATING SUBSTRATE OF SEMICONDUCTOR DEVICE INCLUDING EPITAXIAL LAYER AND SILICON LAYER HAVING SAME CRYSTALLINE ORIENTATION - A method for fabricating substrate of a semiconductor device includes the steps of: providing a first silicon layer; forming a dielectric layer on the first silicon layer; bonding a second silicon layer to the dielectric layer; removing part of the second silicon layer and part of the dielectric layer to define a first region and a second region on the first silicon layer, wherein the remaining of the second silicon layer and the dielectric layer are on the second region; and forming an epitaxial layer on the first region of the first silicon layer, wherein the epitaxial layer and the second silicon layer comprise same crystalline orientation. | 2017-02-09 |
20170040347 | FLEXIBLE DISPLAY AND METHOD OF MANUFACTURING THE SAME - A flexible display and a method of manufacturing the same are disclosed. In one aspect, the display includes a flexible substrate including a display area and a peripheral area that surrounds the display area, and a thin-film transistor (TFT) layer formed on the flexible substrate and comprising an insulating layer and a TFT. The insulating layer is formed of an organic material and has an opening that surrounds the display area in the peripheral area; a pixel electrode electrically connected to the TFT. The display also includes a first metal layer formed in the opening and covering inner sides of the opening. | 2017-02-09 |
20170040348 | SEMICONDUCTOR DEVICE - A semiconductor device which includes an oxide semiconductor and in which formation of a parasitic channel due to a gate BT stress is suppressed is provided. Further, a semiconductor device including a transistor having excellent electrical characteristics is provided. The semiconductor device includes a transistor having a dual-gate structure in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode; gate insulating films are provided between the oxide semiconductor film and the first gate electrode and between the oxide semiconductor film and the second gate electrode; and in the channel width direction of the transistor, the first or second gate electrode faces a side surface of the oxide semiconductor film with the gate insulating film between the oxide semiconductor film and the first or second gate electrode. | 2017-02-09 |
20170040349 | THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A TFT array substrate includes a semiconductive oxide layer disposed on an insulating substrate and including a channel portion, a gate electrode overlapping the semiconductive oxide layer, a gate insulating layer interposed between the semiconductive oxide layer and the gate electrode, and a passivation layer disposed on the semiconductive oxide layer and the gate electrode. At least one of the gate insulating layer and the passivation layer includes an oxynitride layer, and the oxynitride layer has a higher concentration of oxygen than that of nitrogen in a location of the oxynitride layer closer to the semiconductive oxide layer. | 2017-02-09 |
20170040350 | LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE - To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10 | 2017-02-09 |
20170040351 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY DEVICE - The embodiments of the present disclosure provide an array substrate and manufacturing method thereof, and a display device, which relates to the display technical field. The manufacturing method of the array substrate comprises forming thin film transistors and signal lines, and further comprises forming signal line connecting lines, wherein the signal line connecting lines at least electrically connect the same type of signal lines. Prior to completion of manufacturing the last film layer in the manufacture procedure of said array substrate, the method further comprises etching via holes on the signal line connecting lines or at the positions of the signal lines which are close to the signal line connecting lines, said via holes being used for cutting off electric connections between the signal lines. It is for use in the manufacture of an array substrate and display device. | 2017-02-09 |
20170040352 | LASER ANNEALING APPARATUS AND METHOD OF MANUFACTURING DISPLAY APPARATUS BY USING THE SAME - A laser annealing apparatus includes a substrate supporter that receives a substrate having an amorphous silicon layer, a laser beam irradiation unit that irradiates a line laser beam onto the substrate disposed on the substrate supporter, and a substrate transport unit that moves the substrate supporter in the first direction and in a second direction crossing the first direction and rotates the substrate supporter within a first plane defined by the first direction and the second direction. The substrate transport unit rotates the substrate supporter by an angle θ less than about 90 degrees within the first plane and moves the substrate supporter both in the first direction and in the second direction at substantially the same time. The laser beam irradiation unit irradiates the line laser beam multiple times onto the substrate disposed on the substrate supporter while the substrate transport unit moves the substrate supporter. | 2017-02-09 |
20170040353 | MANUFACTURING METHOD FOR ARRAY SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY PANEL - The present discloses a manufacturing method for an array substrate, an array substrate and a display panel. The manufacturing method includes sequentially forming a first metal layer, an insulation layer, a first thin-film layer, a second metal layer and an inorganic layer on a substrate; forming a color resist layer on the inorganic layer; forming an organic layer on the inorganic layer and the color resist layer; digging a hole on the organic and the inorganic layer to form a first through hole so as to uncover a portion of the second metal layer; forming a second thin-film layer on the organic layer and the uncovered second metal layer. The present invention can reduce the damage of the metal layer and the number of the masks in the manufacturing process, and increase the yield | 2017-02-09 |
20170040354 | CAPACITOR STRUCTURE AND METHOD OF FORMING A CAPACITOR STRUCTURE - The present disclosure provides, in accordance with some illustrative embodiments, a capacitor structure comprising an active region formed in a semiconductor substrate, a MOSFET device comprising source and drain regions formed in the active region and a gate electrode formed above the active region, and a first electrode and a second electrode formed in a metallization layer above the MOSFET device, wherein the first electrode is electrically connected with the source and drain regions via respective source and drain contacts and the second electrode is electrically connected with the gate electrode via a gate contact. | 2017-02-09 |
20170040355 | ARRAY SUBSTRATE AND DISPLAY APPARATUS CONTAINING THE SAME, AND METHOD FOR FABRICATING THE SAME - The present disclosure provides an array substrate. The array substrate includes a substrate; and at least one ultraviolet (UV) detection structure. The UV detection structure includes a photosensitive pattern on the substrate, and a first electrode pattern and a second electrode pattern for providing an operating voltage for the at least one UV detection structure. | 2017-02-09 |
20170040356 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - There are provided a highly reliable semiconductor device capable of suppressing occurrence of cracks as well as securing flatness and a manufacturing method therefor. The semiconductor device includes: a semiconductor substrate; an element region; and a non-element region. The non-element region includes: a top-layer metal wiring in a top layer of metal wirings formed in the non-element region; a flattening film covering an upper surface of the top-layer metal wiring; and a protecting film formed over the flattening film. A removed part where the protecting film is removed is formed in at least part of the non-element region. | 2017-02-09 |
20170040357 | IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME - An image sensor includes a semiconductor substrate, a plurality of photoelectric transducer devices and a dielectric isolating structure. The semiconductor substrate has a backside surface and a front side surface opposite to the backside surface. The photoelectric transducer devices are disposed on the front side surface. The dielectric isolating structure extends downwards into the semiconductor substrate from the front side surface and penetrates through the backside surface, so as to from a grid structure and isolate the photoelectric transducer devices from each other. | 2017-02-09 |
20170040358 | SEMICONDUCTOR DEVICES - A semiconductor device includes a pad disposed on a semiconductor layer, an insulating layer disposed between the semiconductor layer and the pad, a through-via penetrating the semiconductor layer and the insulating layer so as to be connected to the pad, and an isolation layer penetrating the semiconductor layer and surrounding the pad when viewed from a plan view. | 2017-02-09 |
20170040359 | IMAGE PICKUP ELEMENT, METHOD OF MANUFACTURING IMAGE PICKUP ELEMENT, AND ELECTRONIC APPARATUS - An image pickup element includes: a semiconductor substrate including a photoelectric conversion section for each pixel; a pixel separation groove provided in the semiconductor substrate; and a fixed charge film provided on a light-receiving surface side of the semiconductor substrate, wherein the fixed charge film includes a first insulating film and a second insulating film, the first insulating film being provided contiguously from the light-receiving surface to a wall surface and a bottom surface of the pixel separation groove, and the second insulating film being provided on a part of the first insulating film, the part corresponding to at least the light-receiving surface. | 2017-02-09 |
20170040360 | IMAGING DEVICE AND MANUFACTURING METHOD THEREOF - An imaging device is provided, in which the dynamic range of still pictures can be suppressed from being decreased. In the imaging device, a photodiode including an n-type impurity region and a photodiode including an n-type impurity region are formed in a p-type well. An n-type impurity region is formed between the n-type impurity region on one side and that on the other side so as to contact each of the two. The impurity concentration of the last-formed n-type impurity region is set to be lower than those of the first-formed n-type impurity regions. | 2017-02-09 |
20170040361 | PHOTOELECTRIC CONVERSION DEVICE, RANGING APPARATUS, AND INFORMATION PROCESSING SYSTEM - A photoelectric conversion device includes a first photoelectric conversion portion configured to generate electrons; a second photoelectric conversion portion configured to generate holes; a charge-to-voltage conversion portion including an n-type first semiconductor region configured to collect the generated electrons and a p-type second semiconductor region configured to collect the generated holes, the charge-to-voltage conversion portion being configured to convert a charge that is based on the electrons and the holes to a voltage; and a signal generation portion configured to generate a signal corresponding to the voltage, the signal generation portion including an amplification transistor. | 2017-02-09 |
20170040362 | GERMANIUM-SILICON LIGHT SENSING APPARATUS - An image sensor array including a carrier substrate; a first group of photodiodes coupled to the carrier substrate, where the first group of photodiodes include a first photodiode, and where the first photodiode includes a semiconductor layer configured to absorb photons at visible wavelengths and to generate photo-carriers from the absorbed photons; and a second group of photodiodes coupled to the carrier substrate, where the second group of photodiodes include a second photodiode, and where the second photodiode includes a germanium-silicon region fabricated on the semiconductor layer, the germanium-silicon region configured to absorb photons at infrared or near-infrared wavelengths and to generate photo-carriers from the absorbed photons. | 2017-02-09 |
20170040363 | SOLID STATE IMAGING DEVICE AND ELECTRONIC APPARATUS - Provided is a solid state imaging device including: a pixel portion where pixel sharing units are disposed in an array shape and where another one pixel transistor group excluding transfer transistors is shared by a plurality of photoelectric conversion portions; transfer wiring lines which are connected to the transfer gate electrodes of the transfer transistors of the pixel sharing unit and which are disposed to extend in a horizontal direction and to be in parallel in a vertical direction as seen from the top plane; and parallel wiring lines which are disposed to be adjacent to the necessary transfer wiring lines in the pixel sharing unit and which are disposed to be in parallel to the transfer wiring lines as seen from the top plane, wherein voltages which are used to suppress potential change of the transfer gate electrodes are supplied to the parallel wiring lines. | 2017-02-09 |
20170040364 | IMAGE SENSORS AND IMAGE PROCESSING DEVICES INCLUDING THE SAME - Image sensors and image processing devices including the image sensors are provided. The image sensors may include a semiconductor substrate including a plurality of pixel areas, a photodiode provided in the semiconductor substrate in one of the plurality of pixel areas and a transfer transistor having a transfer gate electrode. A portion of the transfer gate electrode may be in the semiconductor substrate and may extend toward the photodiode. The image sensors may also include a floating diffusion configured to accumulate charges transferred from the photodiode by the transfer transistor, and the floating diffusion may include a first area and a second area disposed on different sides of the transfer gate electrode. | 2017-02-09 |
20170040365 | COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR IMAGE SENSORS - A complementary metal-oxide-semiconductor (CMOS) image sensor is provided. The CMOS image sensor may include an epitaxial layer having a first conductivity type and having first and second surfaces, a first device isolation layer extending from the first surface to the second surface to define first and second pixel regions, a well impurity layer of a second conductivity type formed adjacent to the first surface and formed in the epitaxial layer of each of the first and second pixel regions, and a second device isolation layer formed in the well impurity layer in each of the first and second pixel regions to define first and second active portions spaced apart from each other in each of the first and second pixel regions. | 2017-02-09 |
20170040366 | SOLID-STATE IMAGING DEVICE WITH CHANNEL STOP REGION WITH MULTIPLE IMPURITY REGIONS IN DEPTH DIRECTION AND METHOD FOR MANUFACTURING THE SAME - Channel stop sections formed by multiple times of impurity ion implanting processes. Four-layer impurity regions are formed across the depth of a semiconductor substrate (across the depth of the bulk), so that a P-type impurity region is formed deep in the semiconductor substrate; thus, incorrect movement of electric charges is prevented. Other four-layer impurity regions of another channel stop section are decreased in width step by step across the depth of the substrate, so that the reduction of a charge storage region of a light receiving section due to the dispersion of P-type impurity in the channel stop section is prevented in the depth of the substrate. | 2017-02-09 |
20170040367 | SPECTRUM-INSPECTION DEVICE - A spectrum-inspection device includes a multi-band pass filter, a filter array, and a sensing layer. The multi-band pass filter allows a first waveband, a second waveband, and a third waveband of a light beam to pass through. The light beam passes through the multi-band pass filter forms a multi-band beam. The filter array is disposed under the multi-band pass filter. The filter array includes a first filter allowing wavelengths of the multi-band beam longer than a first wavelength to pass through, a second filter allowing wavelengths of the multi-band beam longer than a second wavelength to pass through, and a third filter allowing wavelengths of the multi-band beam longer than a third wavelength to pass through. The second waveband is between the first wavelength and the second wavelength, and the third waveband is between the second wavelength and the third wavelength. | 2017-02-09 |
20170040368 | Photodiode Placement For Cross Talk Suppression - There is provided a photodiode array. The photodiode array includes a substrate that has an optical interface surface arranged for accepting external input radiation into the substrate. A plurality of photodiodes are disposed at a substrate surface opposite the optical interface surface of the substrate. Each photodiode in the plurality of photodiodes includes a photodiode material that generates light into the substrate as a result of external input radiation absorption by the photodiode. There is aperiodic photodiode placement along at least one direction of the array. | 2017-02-09 |
20170040369 | SOLID-STATE IMAGING APPARATUS AND METHOD OF MANUFACTURING THE SAME - A solid-state imaging apparatus includes: an imaging section having a light-receiving portion for receiving light from an object to image the object; and a substrate on which the imaging section is disposed, wherein a predetermined member provided on the substrate in the neighborhood of the light receiving portion is partially or entirely coated in black. | 2017-02-09 |
20170040370 | WAFER-LEVEL LENS STRUCTURE FOR CONTACT IMAGE SENSOR MODULE - A wafer-level lens structure for contact image sensor (CIS) module includes a printed circuit board (PCB) and an image sensor electrically connected to the PCB and comprising a circuit area and a light sensitive area. The light sensitive area comprises an optoelectronic conversion array, a first lens array arranged on the optoelectronic conversion array and comprising a plurality of first cover lens, each of first cover lens having a first curved face to focus the external image light to the optoelectronic conversion array, and an aperture array arranged on the first lens array and comprising a plurality of apertures to expose the first curved face, the aperture array controlling a light amount passing through the cover lens. The first curved face of the cover lens has such a curvature that a predetermined focus point can be achieved by the plurality of first cover lens. | 2017-02-09 |
20170040371 | SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD OF SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS - There is provided a solid-state imaging device including a first substrate having a pixel circuit including a pixel array unit formed thereon, and a second substrate having a plurality of signal processing circuits formed thereon so as to be arranged through a scribe region. The first substrate and the second substrate are stacked. | 2017-02-09 |
20170040372 | SENSING CHIP PACKAGE AND A MANUFACTURING METHOD THEREOF - This present invention provides a method of manufacturing a chip scale sensing chip package, comprising the steps of: providing a sensing device wafer having a first top surface and a first bottom surface opposite to each other, whereby the sensing device wafer comprises a plurality of chip areas, and each of the chip areas comprising a sensing device and a plurality of conductive pads adjacent to the sensing chip nearby the first top surface; providing a cap wafer having a second top surface and a second bottom surface opposite to each other, and bonding the second surface of the cap wafer to the first top surface of the sensing device wafer by sandwiching a first adhesive layer therebetween; providing a temporary carrier substrate, and bonding the temporary carrier substrate to the second top surface of the cap wafer by sandwiching a second adhesive layer therebetween; forming a wiring layer connecting to each of the conductive pads on the first bottom surface of the sensing device wafer; providing a first protective layer on the wiring layer; removing the temporary carrier substrate and the second adhesive layer; forming a second protective layer on the second top surface; removing the first protective layer; scribing the chip areas to generate a plurality of individual chip scale sensing chip package; and removing the second protective layer. | 2017-02-09 |
20170040373 | Integrated Circuit Devices Having Through-Silicon Via Structures - An integrated circuit (IC) device includes a first substrate and a first structure on a front surface of the first substrate. The first structure includes a first interlayer insulating layer structure including a plurality of first conductive pad layers spaced apart from one another at different levels of the first interlayer insulating layer structure. The IC device includes a second substrate on the first substrate and a second structure on a front surface of the second substrate, which faces the front surface of the first substrate. The second structure includes a second interlayer insulating layer structure bonded to the first interlayer insulating layer structure. A through-silicon via (TSV) structure penetrates the second substrate and the second interlayer insulating layer structure. The TSV structure is in contact with at least two first conductive pad layers of the plurality of first conductive pad layers located at different levels. | 2017-02-09 |
20170040374 | SEMICONDUCTOR DEVICES HAVING A PAD STRUCTURE - A semiconductor device includes a substrate, a circuit layer formed on a first surface of the substrate and including a via pad and an interlayer insulating layer covering the via pad, a via structure configured to fully pass through the substrate, partially pass through the interlayer insulating layer and be in contact with the via pad, a via isolation insulating layer configured to pass through the substrate and be spaced apart from outer side surfaces of the via structure in a horizontal direction and a pad structure buried in the substrate and exposed on a second surface of the substrate opposite the first surface of the substrate. | 2017-02-09 |
20170040375 | SEMICONDUCTOR DEVICES INCLUDING BACK-SIDE INTEGRATED CIRCUITRY - Semiconductor devices may include a semiconductor substrate comprising at least one of transistors and capacitors may be located at an active surface of the semiconductor substrate. An imperforate dielectric material may be located on the active surface, the imperforate dielectric material covering the at least one of transistors and the capacitors. Electrically conductive material in contact openings may be electrically connected to the at least one of transistors and capacitors and extend to a back side surface of the semiconductor substrate. Laterally extending conductive elements may extend over the back side surface of the semiconductor substrate and may be electrically connected to the conductive material in the contact openings. At least one laterally extending conductive element may be electrically connected to a first transistor or capacitor and may extend laterally underneath a second, different transistor or capacitor to which the laterally extending conductive element is not electrically connected. | 2017-02-09 |
20170040376 | SENSORS WITH VARIABLE SENSITIVITY TO MAXIMIZE DATA USE - Recording photons incident on an image sensor; and storing the recorded photons on the image sensor in varying densities, wherein the photons are recorded in varying densities by storing electrons non-linearly. Key words include a sensor and storing non-linearly. | 2017-02-09 |
20170040377 | SENSING DEVICE - According to one embodiment, a sensing device includes a photodiode; a first transistor including a first terminal, a second terminal and a control terminal, the first terminal being connected to the photodiode; an electrode configured to detect a potential of the measurement target; a second transistor including a third terminal, a fourth terminal and a control terminal, the third terminal being connected to the electrode; and a charge storage connected to the second terminal of the first transistor and to the fourth terminal of the second transistor. | 2017-02-09 |
20170040378 | Apparatus and Method for Reducing Optical Cross-Talk in Image Sensors - A method includes forming a plurality of pixels formed on a front surface of a semiconductor substrate, forming an array of color filters over the plurality of pixels, each color filter being adapted for allowing a wavelength of light radiation to reach at least one of the plurality of pixels, forming a plurality of micro-lenses over the array of color filters, and forming a second layer between the pixels and the color filters. The second layer further includes a structure adapted for blocking light radiation that is traveling towards a region between adjacent micro-lens, further wherein the plurality of micro-lenses are in contact with the array of color filters, and wherein the structure and the transparent material are coplanar at respective top surfaces thereof, and further wherein the structure directly contacts a bottom surface of at least one of the color filters. | 2017-02-09 |
20170040379 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - An object of the present invention is to reduce a pitch of selection transistors to select two directions in a semiconductor substrate surface of a three-dimensional vertical semiconductor storage device to reduce a dimension in the semiconductor substrate surface. | 2017-02-09 |
20170040380 | MEMORY DEVICE - According to one embodiment, a memory device includes a first electrode, a second electrode, a first layer, and a second layer. The first electrode includes a first element. The first layer is provided between the first electrode and the second electrode. The first layer includes at least one of an insulator or a first semiconductor. The second layer is provided between the first layer and the second electrode. The second layer includes a first region and a second region. The second region is provided between the first region and the second electrode. The second region includes a second element. A standard electrode potential of the second element is lower than a standard electrode potential of the first element. A concentration of nitrogen in the first region is higher than a concentration of nitrogen in the second region. | 2017-02-09 |
20170040381 | 3D Memory Having Vertical Switches with Surround Gates and Method Thereof - A vertical switching layer of a 3D memory device serves to switch a set of vertical local bit lines to a corresponding set of global bit lines, the vertical switching layer being a 2D array of TFT channels of vertical thin-film transistors (TFTs) aligned to connect to an array of local bit lines, each TFT switching a local bit line to a corresponding global bit line. The TFTs in the array have a separation of lengths Lx and Ly along the x- and y-axis respectively such that a gate material layer forms a surround gate around each TFT in an x-y plane and has a thickness that merges to form a row select line along the x-axis while maintaining a separation of length Ls between individual row select lines. The surround gate improves the switching capacity of the TFTs. | 2017-02-09 |
20170040382 | SEMICONDUCTOR APPARATUS WITH VARIABLE RESISTOR HAVING TAPERED DOUBLE-LAYERED SIDEWALL SPACERS - A method for fabricating a semiconductor apparatus includes forming a variable resistor region, and forming a spacer having a top linewidth and a bottom linewidth substantially equal to each other in the variable resistor region. The forming of the spacer includes forming a first insulating layer in the variable resistor region through a first method, forming a second insulating layer along a surface of the first insulating layer in the variable resistor region through a second method for providing step coverage superior to the first method, and etching the first and second insulating layers. | 2017-02-09 |
20170040383 | SOLID-STATE IMAGE PICKUP DEVICE AND MANUFACTURING METHOD THEREOF - There is provided a solid-state image pickup device that includes a functional region provided with an organic film, and a guard ring surrounding the functional region | 2017-02-09 |
20170040384 | ELECTRONIC DEVICE, IMAGE DISPLAY DEVICE AND SENSOR, AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE - An electronic device includes a control electrode | 2017-02-09 |
20170040385 | OLED DISPLAY APPARATUS AND METHOD FOR PRODUCING THE SAME AND COLOR FILTER SUBSTRATE AND METHOD FOR PRODUCING THE SAME - The present disclosure provides an OLED display apparatus and a method for producing the same, and a color filter substrate and a method for producing the same. The OLED display apparatus comprises: a TFT array substrate; a luminescent structure layer provided on the TFT array substrate, wherein light emitted from the luminescent structure layer is infrared light; and a light conversion layer located on the luminescent structure layer. The light conversion layer comprises a plurality of pixel areas, each of which is at least provided with three light conversion units, which are a red light conversion unit formed of an upconversion luminescent material emitting red light after stimulation by infrared light, a green light conversion unit formed of an upconversion luminescent material emitting green light after stimulation by infrared light, and a blue light conversion unit formed of an upconversion luminescent material emitting blue light after stimulation by infrared light. | 2017-02-09 |
20170040386 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A stacked body including an organic film stacked on and in contact with an inorganic substrate, a wiring pattern, a first resin layer, a light-emitting element layer, and a second resin layer is prepared. The inorganic substrate is detached from the organic film. The stacked body from which the inorganic substrate is detached, an anisotropic conductive layer containing conductive particles having a diameter larger than the thickness of the organic film, and a wiring terminal of a flexible wiring board are disposed on top one another. The stacked body, the anisotropic conductive layer, and the flexible wiring board disposed are thermocompression bonded to cause the conductive particles to enter the organic film, and the wiring pattern and the wiring terminal are electrically connected by means of the conductive particles. | 2017-02-09 |
20170040387 | CONNECT DEVICE AND ORGANIC LIGHT EMITTING DEVICE - Disclosed is a connect device, having a substrate, a connect electrode, a first to third pairs of electrodes, and the connect electrode, the first to third pairs of electrodes are paved on the substrate, and the first to third pairs of electrodes have anodes and cathodes, and the anodes of the first to third pairs of electrodes are respectively employed to connect a power supply, the anodes of the first, second organic light emitting elements, and the cathodes of the first to third pairs of electrodes are respectively employed to connect the power supply, the cathodes of the first, second organic light emitting elements for respectively and simultaneously supplying power to the first, second organic light emitting elements with the power supply. The application satisfies brightness demands to the light devices without increasing additional power consumption. An organic light emitting device is further provided. | 2017-02-09 |
20170040388 | ELECTROLUMINESCENT DISPLAY AND DISPLAY DEVICE - The present invention discloses an electroluminescent display and a display device, the electroluminescent display comprising a base substrate and a plurality of pixel units arranged in arrays on the base substrate. Each pixel unit is composed of at least four subpixel units, and each pixel unit comprises at least three luminescent material layers. Each luminescent material layer at least covers two adjacent subpixel units, and only one luminescent material layer in each subpixel unit emits light. Since each luminescent material layer at least covers two adjacent subpixel units, when a luminescent material is evaporated and coated by an evaporation coating process, the subpixel units can be made smaller with the size of the mask plate unchanged, which is helpful for improving the resolution of the display. | 2017-02-09 |
20170040389 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed is an organic light emitting display device. The organic light emitting display device includes a substrate in which at least three pixel areas are defined, a first electrode and a hole transporting layer formed on the substrate, an light-emitting material layer formed on the hole transporting layer in each of the pixel areas, and an electron transporting layer and a second electrode formed on the light-emitting material layer. An optical assistant transporting layer is formed on the light-emitting material layer at a position corresponding to one of the pixel areas, and formed of an electron transporting material. Accordingly, provided can be a high-resolution organic light emitting display device that solves an imbalance of electric charges and has an excellent light output efficiency and an enhanced service life. | 2017-02-09 |
20170040390 | ORGANIC LIGHT EMITTING DIODE DISPLAY PANEL AND MANUFACTURING METHOD THEREOF - An organic light emitting diode display panel and a manufacturing method thereof. The display panel includes a plurality of pixel units arranged in arrays, each pixel unit has a first electrode layer, a second electrode layer and at least three light emitting layers. Each light emitting layer includes a planar light emitting layer and at least two annular light emitting layers disposed concentrically with the planar light emitting layer. The first electrode layer has a planar first electrode at a location that corresponds to the planar light emitting layer, and the first electrode layer has an annular first electrode at a location that corresponds to each annular light emitting layer. | 2017-02-09 |
20170040391 | ORGANIC LIGHT EMITTING DIODE MODULE WITH OPTICAL SIGNAL TRANSMISSION - An organic light emitting diode (OLED) module with optical signal transmission includes a substrate, an OLED element, an optical signal transmission element and a spacing member. The substrate includes a light emitting region, an optical transmission region, and a spacing region spaced between the light emitting region and an optical transmission region. The OLED element is disposed in the light emitting region, and includes a first electrode layer, a second electrode layer and an organic light emitting layer. The optical signal transmission element is disposed in the optical transmission region and transmits an optical signal to the exterior. The spacing member is disposed in the spacing region, and includes a lower portion and an upper portion having a width greater than that of the lower portion. Thus, the present invention provides a simplified manufacturing process, a reduced overall volume and lowered production costs. | 2017-02-09 |
20170040392 | FLEXIBLE DISPLAY DEVICE AND METHOD FOR PACKAGING THE SAME - The present disclosure provides a flexible display device and a method for packaging the same. The flexible display device includes a light-emitting component and a packaging layer for packaging the light-emitting component. The packaging layer includes a patterned first film layer with patterned gaps, and a second film layer at least covering the patterned gaps in the first film layer. | 2017-02-09 |
20170040393 | BANK REPAIR METHOD, ORGANIC EL DISPLAY DEVICE MANUFACTURING METHOD, AND ORGANIC EL DISPLAY DEVICE - A bank repair method in a manufacturing process of an organic EL display device including first and second banks forming a matrix over a substrate. When a defect portion of a first bank is detected, in each of adjacent concave spaces between which the first bank having the defect portion is located, a candidate forming position is set and a dam portion partitioning the concave space into a first space in a vicinity of the defect portion and a second space outside the vicinity of the defect portion is formed. When denoting sub-pixel region surface area as H and denoting a surface area of a region of a candidate first space overlapping with a sub-pixel region as I, the dam portion is formed at the candidate forming position according to a first forming method when I<α×H is fulfilled, where 0.05<α<0.9. | 2017-02-09 |
20170040394 | PIXEL STRUCTURE - A pixel structure includes a metal oxide semiconductor layer, a first insulating layer, a second insulating layer, a first conductive layer, a passivation layer, a second conductive layer and a pixel electrode. The metal oxide semiconductor layer includes a second semiconductor pattern. The first insulating layer includes a first capacitance dielectric pattern disposed on the second semiconductor pattern. The second insulating layer includes a second capacitance dielectric pattern disposed on the first capacitance dielectric pattern. The first conductive layer includes a electrode pattern disposed on the second capacitance dielectric pattern. The passivation layer covers the first conductive layer. The second conductive layer includes a second electrode disposed on the passivation layer. The second electrode is electrically connected to the second semiconductor pattern. The second electrode is disposed to overlap the electrode pattern. The second semiconductor pattern, the electrode pattern and the second electrode form a storage capacitor. | 2017-02-09 |