06th week of 2011 patent applcation highlights part 55 |
Patent application number | Title | Published |
20110035528 | Storage Router and Method for Providing Virtual Local Storage - A storage router and method for providing virtual local storage on remote storage devices to devices are provided. Devices are connected to a first transport medium, and a plurality of storage devices are connected to a second transport medium. In one embodiment, the storage router maintains a map to allocate storage space on the remote storage devices to devices connected to the first transport medium by associating representations of the devices connected to the first transport medium with representations of storage space on the remote storage devices, wherein each representation of a device connected to the first transport medium is associated with one or more representations of storage space on the remote storage devices and controls access from the devices connected to the first transport medium to the storage space on the remote storage devices in accordance with the map and using native low level block protocol. | 2011-02-10 |
20110035529 | Partitioning a Crossbar Interconnect in a Multi-Channel Memory System - A method includes identifying a first set of masters and a second set of masters from a plurality of masters. The plurality of masters have access to a multi-channel memory via a crossbar interconnect. The method includes partitioning the crossbar interconnect into a plurality of partitions comprising at least a first partition corresponding to the first set of masters and a second partition corresponding to the second set of masters. The method also includes allocating a first set of buffer areas within the multi-channel memory. The first set of buffer areas correspond to the first set of masters. The method further includes allocating a second set of buffer areas within the multi-channel memory. The second set of buffers correspond to the second set of masters. | 2011-02-10 |
20110035530 | Network system, information processing apparatus, and control method for network system - A network system includes a crossbar switch, and a plurality of crossbar interfaces having ports connected to the crossbar switch. A bypass route directly connects crossbar interfaces forming a group in which a frequency of use of the ports is greater than or equal to a predetermined value amongst the plurality of crossbar interfaces. | 2011-02-10 |
20110035531 | COHERENCY CONTROL SYSTEM, COHERENCY CONTROL APPARATUS AND COHERENCY CONTROL METHOD - A coherency control system includes a logical-physical address translation unit which translates a logical address including a first tag and an index address into a physical address including a second tag and the index address, a request output unit which transmits a load request, a corresponding state storage unit which stores a relation state between an area of the second storage apparatus and an area of the first storage apparatus based on the way number included in the load request and the second tag and the index address of the physical address also included in the load request which has been received, and an invalidation instructing unit which transmits an invalidation instruction including the index address and the way number based on the second tag of the physical address included in the store request and the relation state stored in the corresponding state storage unit. | 2011-02-10 |
20110035532 | Secure Recursive Virtualization - A mechanism is provided for performing secure recursive virtualization of a computer system. A portion of memory is allocated by a virtual machine monitor (VMM) or an operating system (OS) to a new domain. An initial program for the new domain is loaded into the portion of memory. Secure recursive virtualization firmware (SVF) in the data processing system is called to request that the new domain be generated. A determination is made as to whether the call is from a privileged domain or a non-privileged domain. Responsive to the request being from a privileged domain, all access to the new domain is removed from any other domain in the data processing system. Responsive to receiving an indication that the new domain has been generated, an execution of the initial program is scheduled. | 2011-02-10 |
20110035533 | SYSTEM AND METHOD FOR DATA-PROCESSING - Disclosed is a data processing system and method. The data processing system may include a plurality of servers to process data, and a controller to shut off a power supplied to a server, among the plurality of servers, having data throughput less than a predetermined data throughput. | 2011-02-10 |
20110035534 | Dual-scope directory for a non-volatile memory storage system - A device, system, and method are disclosed. In one embodiment the device includes a non-volatile memory (NVM) storage array to store a plurality of storage elements. The device also includes a dual-scope directory structure having a background space and a foreground space. The structure is capable of storing several entries that each correspond to a location in the NVM storage array storing a storage element. The background space includes entries for storage elements written into the array without any partial overwrites of a previously stored storage element in the background space. The foreground space includes entries for storage elements written into the array with at least one partial overwrite of one or more previously stored storage elements in the background space. | 2011-02-10 |
20110035535 | Tracking a lifetime of write operations to a non-volatile memory storage - A method, device, and system are disclosed. In one embodiment method begins by incrementing a count of a total number of write operations to a non-volatile memory storage for each write operation to the non-volatile memory storage. The method then receives a request for the total count of lifetime write operations from a requestor. Finally, the method sends the total count of lifetime write operations to the requestor. | 2011-02-10 |
20110035536 | NON-VOLATILE MEMORY DEVICE GENERATING WEAR-LEVELING INFORMATION AND METHOD OF OPERATING THE SAME - A non-volatile memory device which includes a non-volatile memory core including a memory cell array and a controller configured to generate wear-leveling information from internal operation information of the memory cell array after a write operation, independent of a request from an external device. The wear-leveling information is selectively provided to the external device. | 2011-02-10 |
20110035537 | MULTIPROCESSOR SYSTEM HAVING MULTI-COMMAND SET OPERATION AND PRIORITY COMMAND OPERATION - A multiprocessor system comprises a multi-port semiconductor memory device, a first processor, and a memory link architecture. The multi-port semiconductor memory device comprises a mailbox area and a shared memory area accessible through a plurality of ports. The first processor is configured to write a multi-command set comprising multiple commands for multiple read/write operations to a command area of the shared memory, and to write a message to the mailbox area to indicate the writing of the multi-command set. The memory link architecture comprises a second processor connected to the multi-port semiconductor memory device, and a nonvolatile semiconductor memory device connected to the second processor. The second processor is configured to read the multi-command set from the mailbox area and to sequentially perform the multiple read/write operations according to the multi-command set. | 2011-02-10 |
20110035538 | NONVOLATILE MEMORY SYSTEM USING DATA INTERLEAVING SCHEME - A memory system comprises a plurality of nonvolatile memory devices configured for interleaved access. Programming times are measured and recorded for various memory cell regions of the nonvolatile memory devices, and interleaving units are formed by memory cell regions having different programming times. | 2011-02-10 |
20110035539 | STORAGE DEVICE, AND MEMORY CONTROLLER - The memory controller of a storage device includes a scramble pattern generator, a scramble processor, a logical and physical address conversion table, a memory interface, and a controller, in which the physical page is managed by dividing to a data section and a management section. For the data section, the controller controls the scramble pattern generator to generate a scramble pattern on the basis of a logical address specific to the data section, and controls the scramble processor to scramble the data of the data section corresponding to the logical address by using the scramble pattern, and for the management section, the controller controls the scramble pattern generator to generate a scramble pattern on the basis of a physical address as the write destination of the management section, and scrambling the management data by the scramble processor by using the scramble pattern, so that data is written and reading to and from the semiconductor memory. | 2011-02-10 |
20110035540 | FLASH BLADE SYSTEM ARCHITECTURE AND METHOD - A flash blade and associated methods enable improved areal density of information storage, reduced power consumption, decreased cost, increased IOPS, and/or elimination of unnecessary legacy components. In various embodiments, a flash blade comprises a host blade controller, a switched fabric, and one or more storage elements configured as flash DIMMs. Storage space provided by the flash DIMMs may be presented to a user in a configurable manner. Flash DIMMs, rather than magnetic disk drives or solid state drives, are the field-replaceable unit, enabling improved customization and cost savings. | 2011-02-10 |
20110035541 | STORAGE DEVICE AND DEDUPLICATION METHOD - This storage device performs deduplication of eliminating duplicated data by storing a logical address of one or more corresponding logical unit memory areas in a prescribed management information storage area of a physical unit memory area defined in the storage area provided by the flash memory chip, and executes a reclamation process of managing a use degree as the total number of the logical addresses used stored in the management information storage area and a duplication degree as the number of valid logical addresses corresponding to the physical unit memory area for each of the physical unit memory areas, and returning the physical unit memory area to an unused status when the difference of the use degree and the duplication degree exceeds a default value in the physical unit memory area. | 2011-02-10 |
20110035542 | ASIC including vertically stacked embedded non-flash re-writable non-volatile memory - A multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of memory planes that are vertically stacked upon one another. The vertically stacked memory planes may be used to increase data storage density and/or the number of memory types that can be emulated by the multiple-type memory. Each memory plane can emulate one or more memory types. The control logic blocks can be formed in a substrate (e.g., a silicon substrate including CMOS circuitry) and the memory blocks or the plurality of memory planes can be positioned over the substrate and in communication with the control logic blocks. The multiple-type memory may be non-volatile so that stored data is retained in the absence of power. | 2011-02-10 |
20110035543 | MEMORY DRIVE THAT CAN BE OPERATED LIKE OPTICAL DISK DRIVE AND METHOD FOR VIRTUALIZING MEMORY DRIVE AS OPTICAL DISK DRIVE - The present invention relates to a memory drive that can be virtualized as an optical disk drive and a virtualizing method thereof. One embodiment of the present invention discloses a method for virtualizing a memory drive as an optical disk drive, the memory drive comprising a storage memory and a storage memory controller, which reads or writes data from and to the storage memory. Therefore, according to one embodiment of the present invention, a solid-state which comprises a flash memory and a flash memory controller can be used like an optical disk. | 2011-02-10 |
20110035544 | MULTI-PATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE HAVING MAILBOX AREAS AND MAILBOX ACCESS CONTROL METHOD THEREOF - A multipath accessible semiconductor memory device having a mailbox area and a mailbox access control method thereof are provided. The semiconductor memory device includes N number of ports, at least one shared memory area allocated in a memory cell array, and N number of mailbox areas for message communication. The at least one shared memory area is operationally connected to the N number of ports, and is accessible through a plurality of data input/output lines to form a data access path between the at least one shared memory area and one port, having an access right to the at least one memory area, among the N number of ports. The N number of mailbox areas are provided in one-to-one correspondence with the N number of ports and are accessible through the plurality of data input/output lines when an address of a predetermined area of the at least one shared memory area is applied to the semiconductor memory device. An efficient layout of mailboxes and an efficient message access path can be obtained. | 2011-02-10 |
20110035545 | FULLY-BUFFERED DUAL IN-LINE MEMORY MODULE WITH FAULT CORRECTION - A memory system comprises first memory that includes memory cells. Content addressable memory (CAM) includes CAM memory cells, stores addresses of selected ones of the memory cells, stores data having the addresses in corresponding ones of the CAM memory cells and retrieves data having the addresses from corresponding ones of the CAM memory cells. An adaptive refresh module stores data from selected ones of the memory cells in the CAM memory cells to one of increase and maintain a time period between refreshing of the memory cells. | 2011-02-10 |
20110035546 | MANAGEMENT DEVICE AND MANAGEMENT METHOD - Timing at which a rotation of a physical disk can stop is taken to more appropriately stop the rotation of the physical disk. A management device for managing a storage device and a server includes a first recording part in which an identification number of a logic volume and a rotational state of the physical disk are recorded, a second recording part in which an operating state of the server and an identification number of the logic volume to be accessed by the server are recorded, an updating part for changing the operating state of the server recorded in the second recording part when the operating state of the server is changed, an extracting part for extracting an operating state of another server to access another logic volume of the physical disk having the logic volume to be accessed by the server set from the second recording part based on the identification number of the logic volume to be accessed by the server recorded on the first recording part, and an instructing part for giving an instruction to the storage device for changing the rotation state of the physical disk depending on the operating state after the server is changed and the operating state of the other server. | 2011-02-10 |
20110035547 | Method for utilizing mirroring in a data storage system to promote improved data accessibility and improved system efficiency - The present invention is a method for utilizing mirroring in a data storage system to promote improved data accessibility and improved system efficiency. The method includes establishing a first set of drives of the system in active mode and a second set of drives of the system in passive mode (ex.—a lower power mode). The method further includes writing a first portion of data to a first drive of the first drive set, and writing a copy of the first portion of data to a second drive of the first drive set. A third drive (ex.—from the second drive set), may be activated from passive mode to active mode. The method may further include writing a second copy of the first data portion to the third drive, re-establishing the third drive in passive mode, and deleting the copy of the first data portion from the second drive. | 2011-02-10 |
20110035548 | HYBRID MEDIA STORAGE SYSTEM ARCHITECTURE - A hybrid media storage architecture has a log-structured file system configured to control a plurality of different storage media organized as hybrid storage media that cooperate to provide a total storage space of a storage system. The log-structured file system is configured to perform initial placement and migration of data, as well as fine-grain write allocation of the data, among storage space locations of the hybrid storage media to thereby improve the performance characteristics of the media. By defining and implementing heuristics and policies directed to, e.g., types of data, the file system may initially place data on any of the different media and thereafter migrate data between the media at fine granularity and without the need for manual enforcement. | 2011-02-10 |
20110035549 | DATA STORAGE DEVICE - A data storage device is provided. The data storage device may include a buffer memory, a storage medium, and a controller. The buffer memory may be configured to sequentially store written data blocks received from a host. The storage medium may be configured to include at least one drive. The controller may be configured to calculate first parity data for data selected from the written data in the buffer memory, generate journaling data, and control the generated journaling data to be stored in the storage medium. The data storage device may decrease a number of inputs/outputs used for a parity calculation to thereby reduce overhead. | 2011-02-10 |
20110035550 | Sharing Memory Resources of Wireless Portable Electronic Devices - It is not uncommon for two or more wireless-enabled devices to spend most of their time in close proximity to one another. For example, a person may routinely carry a personal digital assistant (PDA) and a portable digital audio/video player, or a cellphone and a PDA, or a smartphone and a gaming device. When it is desirable to increase the memory storage capacity of a first such device, it may be possible to use memory on one or more of the other devices to temporarily store data from the first device. | 2011-02-10 |
20110035551 | MICROPROCESSOR WITH REPEAT PREFETCH INDIRECT INSTRUCTION - A microprocessor includes an instruction decoder for decoding a repeat prefetch indirect instruction that includes address operands used to calculate an address of a first entry in a prefetch table having a plurality of entries, each including a prefetch address. The repeat prefetch indirect instruction also includes a count specifying a number of cache lines to be prefetched. The memory address of each of the cache lines is specified by the prefetch address in one of the entries in the prefetch table. A count register, initially loaded with the count specified in the prefetch instruction, stores a remaining count of the cache lines to be prefetched. Control logic fetches the prefetch addresses of the cache lines from the table into the microprocessor and prefetches the cache lines from the system memory into a cache memory of the microprocessor using the count register and the prefetch addresses fetched from the table. | 2011-02-10 |
20110035552 | User Interface Contrast Filter - A method of defining a dynamically adjustable user interface (“UI”) of a device is described. The method defines multiple UI elements for the UI, where each UI element includes multiple pixels. The method defines a display adjustment tool for receiving a single display adjustment parameter and in response adjusting the appearance of the UI by differentiating display adjustments to a first set of saturated pixels from the display adjustments to a second set of non-saturated pixels. | 2011-02-10 |
20110035553 | METHOD AND SYSTEM FOR CACHE MANAGEMENT - Systems and methods for managing cached content are disclosed. More particularly, embodiments disclosed herein may allow cached content to be updated (e.g. regenerated or replaced) in response to a notification. Specifically, embodiments disclosed herein may process a notification pertaining to content stored in a cache. Processing the notification may include locating cached content associated with the notification. After the cached content which corresponds to the notification is found, an appropriate action may be taken. For example, the cached content may be flushed from the cache or a request may be regenerated. As a result of the action, new content is generated. This new content is then used to replace or update the cached content. | 2011-02-10 |
20110035554 | Memory Management Methods and Systems - A method and an apparatus for determining a usage level of a memory device to notify a running application to perform memory reduction operations selected based on the memory usage level are described. An application calls APIs (Application Programming Interface) integrated with the application codes in the system to perform memory reduction operations. A memory usage level is determined according to a memory usage status received from the kernel of a system. A running application is associated with application priorities ranking multiple running applications statically or dynamically. Selecting memory reduction operations and notifying a running application are based on application priorities. Alternatively, a running application may determine a mode of operation to directly reduce memory usage in response to a notification for reducing memory usage without using API calls to other software. | 2011-02-10 |
20110035555 | METHOD AND APPARATUS FOR AFFINITY-GUIDED SPECULATIVE HELPER THREADS IN CHIP MULTIPROCESSORS - Apparatus, system and methods are provided for performing speculative data prefetching in a chip multiprocessor (CMP). Data is prefetched by a helper thread that runs on one core of the CMP while a main program runs concurrently on another core of the CMP. Data prefetched by the helper thread is provided to the helper core. For one embodiment, the data prefetched by the helper thread is pushed to the main core. It may or may not be provided to the helper core as well. A push of prefetched data to the main core may occur during a broadcast of the data to all cores of an affinity group. For at least one other embodiment, the data prefetched by a helper thread is provided, upon request from the main core, to the main core from the helper core's local cache. | 2011-02-10 |
20110035556 | Reducing Remote Reads Of Memory In A Hybrid Computing Environment By Maintaining Remote Memory Values Locally - Reducing remote reads of memory in a hybrid computing environment by maintaining remote memory values locally, the hybrid computing environment including a host computer and a plurality of accelerators, the host computer and the accelerators each having local memory shared remotely with the other, including writing to the shared memory of the host computer packets of data representing changes in accelerator memory values, incrementing, in local memory and in remote shared memory on the host computer, a counter value representing the total number of packets written to the host computer, reading by the host computer from the shared memory in the host computer the written data packets, moving the read data to application memory, and incrementing, in both local memory and in remote shared memory on the accelerator, a counter value representing the total number of packets read by the host computer. | 2011-02-10 |
20110035557 | FRAGMENTATION REDUCTION USING VIRTUAL SECTORS FOR STATIC DATA - A system for facilitating enhanced storage efficiency. Operational scenarios that include, for example, many distinct files that are smaller than a read/write block size in an apparatus may result in large portions of unused memory. Sectors that would have normally fallen within a block occupied by a small file may be replaced by “virtual” sectors. The virtual sectors may be mapped in an intermediate control level so that small files may still be read using a standard block size without wasting actual physical memory space. The physical sectors that were previously virtualized may then, for example, be used to “extend” the available memory. | 2011-02-10 |
20110035558 | METHOD AND SYSTEM TO LOCATE A STORAGE DEVICE - A method of locating a storage device of a number of storage devices is provided. A request for a data item is received. The request includes a globally unique identifier (GUID) that is associated with a user. A start number is generated based on the GUID, and the storage device that stores the data item is located based on the start number. The data item is then read from the located storage device. Other techniques for locating a storage device are also described. | 2011-02-10 |
20110035559 | MEMORY CONTROLLER, MEMORY SYSTEM, SEMICONDUCTOR INTEGRATED CIRCUIT, AND MEMORY CONTROL METHOD - A memory controller ( | 2011-02-10 |
20110035560 | Memory Controller with Loopback Test Interface - In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect. | 2011-02-10 |
20110035561 | STORE QUEUE WITH TOKEN TO FACILITATE EFFICIENT THREAD SYNCHRONIZATION - Some embodiments of the present invention provide a system for operating a store queue, wherein the store queue buffers stores that are waiting to be committed to a memory system in a processor. During operation, the system examines an entry at the head of the store queue. If the entry contains a membar token, the system examines an unacknowledged counter that keeps track of the number of store operations that have been sent from the store queue to the memory system but have not been acknowledged as being committed to the memory system. If the unacknowledged counter is non-zero, the system waits until the unacknowledged counter equals zero, and then removes the membar token from the store queue. | 2011-02-10 |
20110035562 | PROVIDING MIRRORING WRITE DATA - An apparatus, method, and system are described. In one embodiment, the system is configured to store, in a non-volatile memory, mirroring data intended for a member of a set of mirroring drives that is in a powered-down state. | 2011-02-10 |
20110035563 | Data Mirroring System - A system includes a primary storage unit connected to a secondary storage unit such that data written to the primary storage unit is replicated on the secondary storage unit. The primary storage unit in at least one exemplary embodiment includes the capability to intercept input/output instructions for routing to a buffer and/or directly to the secondary storage unit. The system in at least one exemplary embodiment includes a backup storage unit for backing up data from at least the secondary storage unit offline and the capability to update the secondary storage unit once it returns to an online status. | 2011-02-10 |
20110035564 | TECHNIQUE TO PERFORM MEMORY DISAMBIGUATION - A memory access management technique. More particularly, at least one embodiment of the invention relates to a technique to issue loads to a memory ahead of older store operations corresponding to the same target address. | 2011-02-10 |
20110035565 | Storage System Condition Indicator and Method - A storage system condition indicator and method provides a visual display representing the operating condition of a set of storage devices. Various operating conditions may be defined based on available storage capacity and capacity to store data redundantly. One or more indicators may be used to represent the operating condition of the set of storage devices. The indicator(s) may be used to indicate whether additional storage capacity is recommended and, in a storage array, which slot in the array should be updated with additional storage capacity. | 2011-02-10 |
20110035566 | HASHING AND SERIAL DECODING TECHNIQUES - A technique for generating a list of all N-bit unsigned binary numbers by starting with an initial number less than some power of 2, successively multiplying the number by that power of 2 and adding the largest non-negative number less than that power of 2 such that the new number is not a duplicate of any of those already generated, and using the resulting lists to generate efficient hashing and serial decoding hardware and software. | 2011-02-10 |
20110035567 | ACTUAL INSTRUCTION AND ACTUAL-FAULT INSTRUCTIONS FOR PROCESSING VECTORS - The described embodiments include a processor that executes a vector instruction. The processor starts by receiving a vector instruction that optionally receives a predicate vector (which has N elements) as an input. The processor then executes the vector instruction. In the described embodiments, executing the vector instruction causes the processor to generate a result vector. When generating the result vector, if the predicate vector is received, for each element in the result vector for which a corresponding element of the predicate vector is active, otherwise, for each element of the result vector, the processor determines element positions for which a fault was masked during a prior operation. The processor then updates elements in the result vector to identify a leftmost element for which a fault was masked. | 2011-02-10 |
20110035568 | SELECT FIRST AND SELECT LAST INSTRUCTIONS FOR PROCESSING VECTORS - The described embodiments include a processor that executes a vector instruction. The processor starts by receiving a vector instruction that uses a first input vector, a second input vector, and a control vector, and optionally a predicate vector as inputs, wherein each of the vectors includes N elements. The processor then executes the vector instruction. In the described embodiments, when executing the vector instruction, the processor determines a key element position. If the predicate vector is received, the key element position is a predetermined active element position in the predicate vector, otherwise, the key element position is in a predetermined element position. The processor then uses the key element position to copy a result value into a result variable. When copying the result value into the result variable, if an element in the key element position of the control vector contains a predetermined value, the processor copies a value from the key element position in the second input vector into the result variable. Otherwise, the processor copies a value from the key element position in the first input vector into the result variable. | 2011-02-10 |
20110035569 | MICROPROCESSOR WITH ALU INTEGRATED INTO LOAD UNIT - A superscalar pipelined microprocessor includes a register set defined by its instruction set architecture, a cache memory, execution units, and a load unit, coupled to the cache memory and distinct from the other execution units. The load unit comprises an ALU. The load unit receives an instruction that specifies a memory address of a source operand, an operation to be performed on the source operand to generate a result, and a destination register of the register set to which the result is to be stored. The load unit reads the source operand from the cache memory. The ALU performs the operation on the source operand to generate the result, rather than forwarding the source operand to any of the other execution units of the microprocessor to perform the operation on the source operand to generate the result. The load unit outputs the result for subsequent retirement to the destination register. | 2011-02-10 |
20110035570 | MICROPROCESSOR WITH ALU INTEGRATED INTO STORE UNIT - A superscalar pipelined microprocessor includes a register set defined by an instruction set architecture of the microprocessor, execution units, and a store unit, coupled to the cache memory and distinct from the other execution units of the microprocessor. The store unit comprises an ALU. The store unit receives an instruction that specifies a source register of the register set and an operation to be performed on a source operand to generate a result. The store unit reads the source operand from the source register. The ALU performs the operation on the source operand to generate the result, rather than forwarding the source operand to any of the other execution units of the microprocessor to perform the operation on the source operand to generate the result. The store unit operatively writes the result to the cache memory. | 2011-02-10 |
20110035571 | ON-CHIP PACKET INTERFACE PROCESSOR ENCAPSULATING MEMORY ACCESS FROM MAIN PROCESSOR TO EXTERNAL SYSTEM MEMORY IN SERIAL PACKET SWITCHED PROTOCOL - A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through a gigabit Ethernet interface provided by protocol processor integrated as part of the chip. The protocol processor encapsulates the memory address and control information like Read, Write, number of successive bytes etc, as an Ethernet packet for communication among the processor and memory chips that are located on the same motherboard, or even on different circuit cards. In one embodiment, the communication over head of the Ethernet protocol is further reduced by using an enhanced Ethernet protocol with shortened data frames within a constrained neighborhood, and/or by utilizing a bit stream switch where direct connection paths can be established between elements that comprise the computing or communication architecture. | 2011-02-10 |
20110035572 | Computing device, information processing apparatus, and method of controlling computing device - Multiple data processing instructions instruct a computing device to process multiple data including first data and second data. When a multiple data processing instruction is decoded, two allocatable registers are selected. One is used to store the result of a processing operation performed on first data by one processing unit, and the other is used to store the result of a processing operation performed on second data by another processing unit. Those stored processing results are then transferred to result registers. Normal data processing instructions, on the other hand, instruct a processing operation on third data. When a normal data processing instruction is decoded, one allocatable register is selected and used to store the result of processing that a processing unit performs on the third data. The stored processing result is then transferred to a result register. | 2011-02-10 |
20110035573 | OUT-OF-ORDER X86 MICROPROCESSOR WITH FAST SHIFT-BY-ZERO HANDLING - An out-of-order execution microprocessor includes a register alias table configured to generate a first indicator that indicates whether an instruction is dependent upon a condition code result of a shift instruction. The microprocessor also includes a first execution unit configured to execute the shift instruction and to generate a second indicator that indicates whether a shift amount of the shift instruction is zero. The microprocessor also includes a second execution unit configured to receive the first and second indicators and to generate a replay signal to cause the instruction to be replayed if the first indicator indicates the instruction is dependent upon the condition code result of the shift instruction and a second indicator indicates the shift amount of the shift instruction is zero. | 2011-02-10 |
20110035574 | Running a Computer from a Secure Portable Device - An operating system is booted from a secure peripheral device on a host computer. The secure peripheral device, which includes a memory, is communicatively coupled with the with the host computer. A first operating system is booted from the memory of the secure peripheral device. A secondary operating system is launched on the first operating system. | 2011-02-10 |
20110035575 | MULTIPROCESSOR SYSTEM COMPRISING MULTI-PORT SEMICONDUCTOR MEMORY DEVICE - A multiprocessor system comprises first and second processors connected to a multi-port semiconductor memory device. The multi-port semiconductor memory device comprises a shared memory area and a plurality of mailbox areas used for inter-processor communication. The first and second processors use a single nonvolatile memory device for storing boot data and transmit information for booting via the shared memory area. | 2011-02-10 |
20110035576 | Configurable field device for use in process automation systems - A configurable field device for automation technology with a partially dynamically reconfigurable logic chip FPGA, in which function modules are dynamically configured during runtime, and to a method for operating the configurable field device. | 2011-02-10 |
20110035577 | ENHANCED DIGITAL RIGHT MANAGEMENT FRAMEWORK - Machine-readable media, methods, apparatus and system for enhanced digital right management framework are described. A server platform may receive a request of downloading content and first attestation information from a client platform. The server platform may examine if the client platform attests to a client platform characteristic that affects integrity of the client platform by using the attestation information, and then encrypt and download the content to the client platform if the client platform attests to the client platform characteristic. The server platform may further receive a request of viewing the content and second attestation information from the client platform. The server platform may then examine if the client platform attests to its integrity by using the second attestation information; and then send a content key to the client platform if the client platform attests to its integrity, so that the client platform can decrypt and view the content. | 2011-02-10 |
20110035578 | SECURE COMMUNICATION SYSTEM - A communications system ( | 2011-02-10 |
20110035579 | CONTENT DISTRIBUTION METHOD AND CONTENT DISTRIBUTION PACKAGE - A content distribution method distributes a package containing a content from a content distribution apparatus to a terminal of a content distribution destination and causes the terminal to expand and display the content contained in the distributed package by using expansion software provided in the terminal. Update data of the expansion software is inserted in the package in addition to the content. When the terminal cannot expand the content by using the expansion software provided in it, the terminal updates the expansion software provided in it by using the update data contained in the distributed package and expands the content by using the updated expansion software. | 2011-02-10 |
20110035580 | MEDIA ACCESS CONTROL SECURITY MANAGEMENT IN PHYSICAL LAYER - A media access control (MAC) security (MACsec) function block may implement MACsec protocols on a network. A physical layer device (PHY) may connect to the MACsec function block and an interface register configured to store command information for the MACsec function block. A central processing unit (CPU) may provide the command information for the MACsec function block to the PHY via a management data input/output (MDIO) bus. The PHY may execute either a read command or a write command against the MACsec function block based on the command information, receive, from the MACsec function block, a response corresponding to the execution of the read command or write command against the MACsec function block, and provide the response to the CPU via the MDIO bus. | 2011-02-10 |
20110035581 | SYSTEM FOR MANAGEMENT AND PROCESSING OF ELECTRONIC VENDOR MAIL - A computer-implemented system processes secure electronic documents from one or more content providers in accordance with subscriber instructions has a processor and modules operative within the processor. A monitoring module obtains a provider GUID, a subscriber GUID, and a transaction ID from public metadata associated with a transaction received from a particular content provider. A determination module determines any designees of the subscriber and contact information one or more of the subscriber and any designees. A transaction module distributes a transaction addressed to at least one of the subscriber and any designees. Each distributed transaction includes data that is used for management, tracking, and alerting. Also described is a station for constructing transactions for distribution to subscribers through such a system. An end-to-end system and method are described. | 2011-02-10 |
20110035582 | NETWORK AUTHENTICATION SERVICE SYSTEM AND METHOD - A network authentication service system and method are provided. The network authentication service system is applied to a network application layer and includes: a Web service security device, adapted to intercept a message exchanged in the network application layer; and an authentication server, adapted to perform authentication processing for the message intercepted by the Web service security device. The network authentication service method includes: intercepting a request message of a network application layer; performing encryption processing for the request message to obtain an encrypted message; performing authentication processing for the encrypted message; and decrypting the encrypted message that passes the authentication. Thus security processing can be performed for the transmitted message, and various security authentication manners can be available. | 2011-02-10 |
20110035583 | AUTHENTICATION APPARATUS, AUTHENTICATION SYSTEM, AUTHENTICATION METHOD AND COMPUTER READABLE MEDIUM - An authentication apparatus includes an accepting unit and an instructing unit. The accepting unit accepts a request, which requests to issue an authentication medium for a second user, from a first user who is authenticated. The instructing unit instructs to issue the authentication medium for the second user. | 2011-02-10 |
20110035584 | SECURE REMOTE SUBSCRIPTION MANAGEMENT - A method and apparatus are disclosed for performing secure remote subscription management. Secure remote subscription management may include providing the Wireless Transmit/Receive Unit (WTRU) with a connectivity identifier, such as a Provisional Connectivity Identifier (PCID), which may be used to establish an initial network connection to an Initial Connectivity Operator (ICO) for initial secure remote registration, provisioning, and activation. A connection to the ICO may be used to remotely provision the WTRU with credentials associated with the Selected Home Operator (SHO). A credential, such as a cryptographic keyset, which may be included in the Trusted Physical Unit (TPU), may be allocated to the SHO and may be activated. The WTRU may establish a network connection to the SHO and may receive services using the remotely managed credentials. Secure remote subscription management may be repeated to associate the WTRU with another SHO. | 2011-02-10 |
20110035585 | RE-ESTABLISHMENT OF A SECURITY ASSOCIATION - According to a first aspect of the present invention there is provided a method of re-establishing a session between first and second IP hosts attached to respective first and second IP access routers, the session previously having been conducted via a previous access router to which said first host was attached, and where a security association comprising a shared secret has been established between the hosts. The method comprises sending a connection request from said first host to said first access router, said request containing an IP address claimed by said second host, a new care-of-address for the first host, and a session identifier. Upon receipt of said connection request at said first access router, the router obtains a verified IP address for said second access router and sends an on link presence request to the second access router, the request containing at least an Interface Identifier part of the second host's claimed IP address, said care-of-address, and said session identifier. Said second access router confirms that said second host is attached to the second access router using the claimed Interface Identifier, sending to the second host said care-of-address and said session identifier. The second access router then reports the presence status to said first access router. Said second host uses said session identifier to identify said security association, and updates the binding cache entry for said first host with the new care-of-address. | 2011-02-10 |
20110035586 | SYSTEM AND METHOD FOR SECURING A COMPUTER COMPRISING A MICROKERNEL - A method of securing a computer comprising a microkernel and a system for interfacing with at least one virtualized operating system are presented. The microkernel includes a clock drive, a scheduler and an inter-process communication manager. The system for interfacing forms at least one virtual machine associated with each operating system and allows execution of the latter without modification. The method includes, at the level of the system for interfacing, the steps of:—intercepting any communication between a means external to the operating system and the operating system,—verifying that predefined rules of access to said external means are validated by said communication;—transmitting the communication to the recipient if the rules are validated. | 2011-02-10 |
20110035587 | DATA PROGRAMMING CONTROL SYSTEM WITH SECURE DATA MANAGEMENT AND METHOD OF OPERATION THEREOF - A method of operation of a data programming control system includes: providing a secure data management host server coupled to a network; encrypting a contract manufacturer job by the secure data management host server, including: providing a memory image file, creating a programmer encrypted file from the memory image file, and encrypting permissions and the programmer encrypted file to form the contract manufacturer job; decrypting the contract manufacturer job transmitted through the network by a secure data management local server; transmitting the programmer encrypted file by the secure data management local server to a device programmer; and programming a device with the memory image file decrypted by the device programmer. | 2011-02-10 |
20110035588 | Encoding Method and Device for Securing a Counter Meter Reading Against Subsequential Manipulations, an Inspection Method and Device for Verifying the Authenticity a Counter Meter Reading - The invention relates to an encoding method for identifying a subsequential manipulation of a counter meter reading consisting, when the counter reading is increased or decreased, in activating the computation of a new encoded meter reading and in calculating a new encoded meter reading by applying a forward chain one-way function to the encoded meter reading, wherein a complex variable domain of said forward chain one-way function is included into the antecedent domain thereof. The invention also relates to a method for verifying the authenticity of a counter meter reading consisting in subtracting test meter readings based on the meter reading for obtaining the number of tests, in producing an encoded test meter reading by applying the chain one-way function to the encoded meter reading, in applying the chain one-way function with the number of tests and in comparing the test meter reading with the final encoded meter reading and, if the test meter reading defers from the final encoded meter reading, a negative status signal is emitted. An encoding system for carrying out said encoding method and a verification system for carrying out the verification method are also disclosed. | 2011-02-10 |
20110035589 | Content usage monitor - A trusted content usage monitor for monitoring content usage is provided. A unique identifier generation unit generates a unique identifier indicative of content being rendered and a packet generator generates a trusted packet comprising the unique identifier. The trusted packet is trust signed by the trusted content usage monitor, so that it can be trusted by its recipient. The trusted content usage monitor has at least one mode of operation in which content rendering cannot be decoupled from operation of the unique identifier generation unit, so that generated packets can be trusted as truly indicative of content usage. | 2011-02-10 |
20110035590 | Method and Apparatus for Connecting a Network of Electronic Signs - A method and apparatus allows owners of electronic signs, such as retailers, real estate owners, other space owners, and content providers, such as advertisers, entertainment producers, event promoters, visual artists, and the general community to participate in an open content network, in which electronic signs are universally uniquely identified and then added to a network in a distributed fashion, after which content is selectively downloaded to the electronic signs. The times at which the content is presented are determined collaboratively by the owners of the electronic signs and the content providers. A mechanism that verifies whether the content is actually presented on the electronic signs is also disclosed. | 2011-02-10 |
20110035591 | ENTERPRISE INSTANT MESSAGE AGGREGATOR - A disclosed enterprise instant messaging (IM) service aggregator enables validation of mobile stations and/or users for enterprise IM service through a wireless communication network; and in the examples, the enterprise IM service provides a secure messaging environment that allows IM traffic to/from wireless mobile stations. The security offered may be unique to and controlled by each enterprise, for example, by enabling each enterprise to generate its own encryption key for distribution through the aggregator and by allowing mobile stations to generate their own keys for distribution back through the aggregator to the enterprise IM servers. As disclosed, the login credentials are encrypted from the mobile station to the enterprise IM server. The use of standard encryption methods within the call flows allows a simple method of ensuring that only authorized users can access the enterprise servers and that the messages will be encrypted by the strongest possible means. | 2011-02-10 |
20110035592 | AUTHENTICATION METHOD SELECTION USING A HOME ENHANCED NODE B PROFILE - An authentication method selection using a home enhanced Node B (H(e)NB) profile is disclosed. A method for selecting an H(e)NB authentication method includes authenticating at least one of the device or the hosting party module by a security gateway (SeGW). The SeGW receives a request from the H(e)NB to start the authentication process. Based on information received from the H(e)NB and an authentication information server, the SeGW determines how to authenticate the H(e)NB. The possible authentication methods include device authentication only, device authentication and hosting party module authentication, requesting the H(e)NB to perform authentication using Extensible Authentication Protocol-Authentication and Key Agreement, or authentication of both the H(e)NB and one or more WTRUs connected to or attempting to connect to the H(e)NB. | 2011-02-10 |
20110035593 | ESTABLISHING SECURE MUTUAL TRUST USING AN INSECURE PASSWORD - A process for establishing secure mutual trust includes generating a one-time-password. The one-time-password is transferred between the devices in a communication occurring off of the network. Each device generates a set of authenticators by hashing a plurality of sub-strings of the password and the device's authentication certificate with a respective set of nonces. The devices exchange the respective sets of authenticators. Each device then alternates revealing its respective set of nonces and its authentication certificate in a multi-stage process. The devices re-calculate the authenticators based upon the respective set of nonces and authentication certificate revealed by the other device along with the one-time-password sub-strings that it posses. If each device determines that the authenticators re-calculated by the given device matches the authenticators previously received from the other device, secure mutual trust is established. | 2011-02-10 |
20110035594 | Apparatus and method for providing elective message tagging - A computer-implemented apparatus and method for providing elective message tagging related services, comprising: receiving a request to receive, processing information regarding the request; and transmitting in response to the request, an elective message tag in conjunction with a second communication, wherein the elective message tag consists of any one or more of data, information, advertisements, offers, solicitations, promotions, confirmations, tickets, receipts, content, digital content, activations, authorizations, authentications, hyper-links, programs, applications, code, scripts, files, video, audio, images, avatars, pixel tags, clear gifs, web beacons, voice, text, signals, warnings, prompts, requests, restrictions, limitations, monitoring functions, management operations, rules, policies, practices, aggregated information, implementations, dissolutions, disallowances, messages, notifications, controls, communications, and/or an embodiment of information, and/or an embodiment of control functionality. | 2011-02-10 |
20110035595 | CODEWORD-ENHANCED PEER-TO-PEER AUTHENTICATION - Peer-to-peer authentication may be accomplished by sending a digital certificate to a responder, receiving a randomized codeword in response to the sending, creating a secure fingerprint based at least in part on the digital certificate and randomized codeword, creating a first bit sequence based at least in part on a first portion of the secure fingerprint and a second portion of the randomized codeword and indicating the first digital certificate is authenticated based upon whether the first bit sequence matches a second bit sequence received from the responder via an out-of-band communication in response to the sending. The size of the first bit sequence is less than the size of the secure fingerprint. According to another aspect, the first bit sequence is compared with a rendering of the second bit sequence, using an out-of-band communication, by associating the first bit sequence with one or more indices into an array of representations. | 2011-02-10 |
20110035596 | Method of Secure Broadcasting of Digital Data to an Authorized Third Party - The invention relates to a method of secure broadcasting of encrypted digital data of a proprietary entity, these data being stored in a storage module ( | 2011-02-10 |
20110035597 | SECURE INDIRECT ADDRESSING - An efficient solution for secure implementation of indirect addressing (IA) is described. IA may be used, for example, in networks of which the routing algorithms are not capable of multicast but also contain very constrained devices that, although requiring multicast, are not capable of repeated unicast. This ID is useful in wireless networks containing low-power low-cost devices. | 2011-02-10 |
20110035598 | COMPUTER PROGRAM AND METHOD FOR GRANTING MULTIPLE USERS ACCESS TO A SECURE REPOSITORY - A computer program, system, and method for granting multiple users access to a secure repository. Embodiments of the present invention provide for authenticating either of first or second users desiring access to the secure repository. In embodiments of the present invention, a respective encryption or decryption operation of files or folders transferred in or out of the secure repository is performed using a key created, at least in part, on an enrolled security template provided by said first user. Thus, even if the second user is authenticated and allowed access to the secure repository, said creation of the key is performed using the security template associated with the first user. In even further embodiments of the present invention, a single storage device contains a plurality of secure repositories. | 2011-02-10 |
20110035599 | APPARATUS AND METHOD FOR GENERATING UNPREDICTABLE PROCESSOR-UNIQUE SERIAL NUMBER FOR USE AS AN ENCRYPTION KEY - A microprocessor includes a manufacturing ID that is stored in the microprocessor during manufacture thereof in a non-volatile manner. The manufacturing ID is unique to the microprocessor. The microprocessor also includes a secret encryption key that is stored internally within the microprocessor and unreadable externally from the microprocessor. The microprocessor also includes an AES encryption engine, coupled to receive the manufacturing ID and the secret encryption key, configured to encrypt the manufacturing ID using the secret encryption key to generate an unpredictable key that is unique to the microprocessor. | 2011-02-10 |
20110035600 | METHOD AND DEVICE FOR TRANSCODING DURING AN ENCRYPTION-BASED ACCESS CHECK ON A DATABASE - A device for transcoding during an encryption-based access check of a client device to a databank, which provides a data set in an encrypted area, has: a unit for assigning a specific access level of the client device and for providing a corresponding first group key of the client device as a function of a registration parameter, wherein the client device is allowed access to a first area, which is encrypted using the first group key, and all areas of the database subordinate to the first area as a function of the assigned access level; a unit for providing a classification result depending on a classification of the data set of the particular area by one of the client devices allowed to access the particular area; and a unit for transcoding the data set and/or a data set key for the data set as a function of the classification result. | 2011-02-10 |
20110035601 | System, method and computer program product for protecting software via continuous anti-tampering and obfuscation transforms - Method, system and computer program product for applying existing anti-tampering and obfuscation technique to virtual machine technology and offers several distinct advantages. The anti-tampering and obfuscation transforms can be applied continuously to prevent adversaries from gaining information about the program through emulation or dynamic analysis. In addition, the encryption can be used to prevent hackers from gaining information using static attacks. The use of a virtual machine also allows for low overhead execution of the obfuscated binaries as well as finer adjustment of the amount of overhead that can be tolerated. In addition, more protection can be applied to specific portions of the application that can tolerate slowdown. The incorporation of a virtual machine also makes it easy to extend the technology to integrate new developments and resistance mechanisms, leading to less development time, increased savings, and quicker deployment. | 2011-02-10 |
20110035602 | DATA SCRAMBLING, DESCRAMBLING, AND DATA PROCESSING METHOD, AND CONTROLLER AND STORAGE SYSTEM USING THE SAME - A data scrambling method for scrambling raw data from a host system is provided. The data scrambling method includes generating a random number and storing the random number into a storage unit. The data scrambling method also includes receiving a user password from the host system, generating a padded value by using a first function unit based on the random number and the user password, and generating a nonce value by using a second function unit based on the padded value and a key. The data scrambling method further includes generating scrambled data corresponding to the raw data by using a third function unit based on the nonce value and the raw data. Accordingly, the raw data of the host system can be effectively protected. | 2011-02-10 |
20110035603 | Apparatus and Method for Securing Data on a Portable Storage Device - A portable storage device including a microprocessor and a secure user data area, the microprocessor operable to perform on-the-fly encryption/decryption of secure data stored on the storage device under a user password, the microprocessor also operable to exclude access to the secure user data area unless the user password is provided. | 2011-02-10 |
20110035604 | Dual-Interface Key Management - In one embodiment, a device includes a first interface, a second interface, a memory, and a processor coupled to the first and second interfaces and to the memory. The processor is configured to receive key-management information via the second interface, and to store the key-management information in a protected portion of the memory as stored key-management information. The processor is also configured to perform a challenge-response authentication interaction via the first interface. The challenge-response authentication interaction is based at least in part on the stored key-management information. The device is configured to prevent data in the protected portion of the memory from being modified in response to information received via the first interface. | 2011-02-10 |
20110035605 | Method for optimizing performance and power usage in an archival storage system by utilizing massive array of independent disks (MAID) techniques and controlled replication under scalable hashing (CRUSH) - The present invention is a method for drive management and data placement in an archival storage system having a set of drives. The method includes mapping redundant data stripes onto the drives. A first active data stripe, located on a first subset of the drives, is then selected from the mapped data stripes. The first subset is placed into a normal power state and a second subset of the drives is placed into a low power state. Data is then written to the first active data stripe. Before the first active data stripe is fully used, the method includes selecting a next active/second active data stripe from the mapped data stripes, the second active data stripe being at least partially located on the second subset. The method may be performed by a system which implements MAID techniques for drive management and CRUSH for data placement. | 2011-02-10 |
20110035606 | System And Method For Information Handling System Hybrid System Level And Power Supply Cooling - Information handling system thermal conditions are controlled by hybrid interaction between a system thermal manager and a power supply thermal manager. The system thermal manager sets a speed for system cooling fans and for a power supply cooling fan. The power supply thermal manager determines a speed for the power supply cooling fan and also receives the speed for the power supply cooling fan determined by the system thermal manager. The power supply thermal manager commands the power supply fan to run at a selected of the determined speeds based upon one or predetermined conditions, such as by the selecting the greater of the determined speeds. | 2011-02-10 |
20110035607 | Coupled Inductor With Improved Leakage Inductance Control - An M-winding coupled inductor includes a first end magnetic element, a second end magnetic element, M connecting magnetic elements, and M windings. M is an integer greater than one. Each connecting magnetic element is disposed between and connects the first and second end magnetic elements. Each winding is wound at least partially around a respective one of the M connecting magnetic elements, and each winding has a respective leakage inductance. The coupled inductor further includes at least one top magnetic element adjacent to and extending at least partially over at least two of the M connecting magnetic elements to provide a magnetic flux path between the first and second end magnetic elements. The top magnetic element forms a gap. The inductor may be included in an M-phase power supply, and the power supply may at least partially power a computer processor. | 2011-02-10 |
20110035608 | COMMUNICATION TERMINAL, COMPUTER-READABLE STORAGE MEDIUM, AND COMMUNICATION METHOD - A communication terminal includes a first communication unit having a power supply function by electromagnetic induction, and a second communication unit having a communication capability higher than that of the first communication unit. When communicating with a communication partner terminal, it is determined whether to receive power from the communication partner terminal. Upon determining to receive the power by the power supply function of the first communication unit, communication with the communication partner terminal by the second communication unit is controlled using the power supplied from the communication partner terminal by the power supply function of the first communication unit. | 2011-02-10 |
20110035609 | METHOD AND SYSTEM FOR FORCING ONE OR MORE POWER STATES ON A DISPLAY - A management controller, method and program product for forcing one or more power states on a display, the management controller comprising: a computer ( | 2011-02-10 |
20110035610 | ENERGY SAVING METHOD AND SYSTEM - A method for controlling the power consumption in a peer-to-peer (P2P) network of content delivery devices is provided. The method comprises the steps of: determining the capacity of the network to deliver each content unit stored on a device; determining the demand of the network for each content unit stored on the device; comparing the capacity with the demand for each content unit stored on the device; and controlling the power supplied to said device based on said comparison. | 2011-02-10 |
20110035611 | COORDINATING IN-BAND AND OUT-OF-BAND POWER MANAGEMENT - One embodiment provides a method of managing power in a computer system. A device of the computer system is operated at a selected power-state. The power consumption of the computer system is monitored. If the power consumption of the computer system is approaching or has exceeded a power cap selected for the computer system, then a request to reduce the power-state for the device is generated in response. The operating system is used to service the request to reduce the power-state according to the priority of the request. The reduced power state is forced out-of-band following the request to reduce the power-state if the request is not immediately serviceable by the operating system. Different approaches can be taken to force the reduced power state, using, for example, system management mode or a platform environment control interface. | 2011-02-10 |
20110035612 | DISTRIBUTED COMPUTING - On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that tend to alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems. | 2011-02-10 |
20110035613 | MICROPROCESSOR HAVING A LOW-POWER MODE AND A NON-LOW POWER MODE, DATA PROCESSING SYSTEM AND COMPUTER PROGRAM PRODUCT - A microprocessor has a low-power mode and a non-low power mode. The microprocessor includes a processor core for executing instructions provided to the microprocessor and a clock providing a clock signal, which in the non-low power mode has a first frequency and in the low power mode has a second frequency lower than the first frequency. A hardware timer is present, for scheduling an execution of an event by the microprocessor at a future point in time. The hardware timer is connected to the clock for determining a period of time between a current point in time and a point in time the event based on a number of clock cycles of the clock signal. A timer controller can determine, when the data processing system switches from the low power mode to the non-low power mode, a number of clock cycles of a clock signal with the first frequency that corresponds to a low-power mode period during which the microprocessor has been in the low power mode and adjusting the hardware timer based on the determined number. | 2011-02-10 |
20110035614 | METHODS FOR DETERMINING BATTERY STATISTICS USING A SYSTEM-WIDE DAEMON - Techniques for determining battery statistics using a system-wide daemon are described herein. According to one embodiment, a power management daemon is configured to collect operating status data of a battery of a data processing system by accessing at least one of firmware and hardware coupled to the battery. The power management daemon is a single system-wide component within the data processing system to provide the operating status data of the battery to multiple clients. The power management daemon is also configured to compute battery statistics based on the collected operating status data of the battery. In response to a query received from one of the clients via an application programming interface (API), the power management daemon is configured to return the battery statistics to the client to enable the client to determine remaining time of the battery until being recharged. Other methods and apparatuses are also described. | 2011-02-10 |
20110035615 | MEMORY CARD HAVING MEMORY DEVICE AND HOST APPARATUS ACCESSING MEMORY CARD - A memory card includes a clock I/O circuit, a data I/O circuit, a delay element, and an adjustment value holding circuit. The clock input/output circuit receives a first clock from a host apparatus. The data I/O circuit receives a second clock from the host apparatus in a write timing adjustment mode. The data I/O circuit transmits and receives data to and from the host apparatus in a data transfer mode. In the write timing adjustment mode, the delay element adjusts a phase of the second clock in accordance with the first clock so as to receive the data received in the data transfer mode in response to the first clock. The adjustment value holding circuit holds an adjustment value for the phase of the second clock adjusted. In the data transfer mode, the delay element adjusts a phase of the data in accordance with the adjustment value. | 2011-02-10 |
20110035616 | DETECTION OF UNCORRECTABLE RE-GROWN FUSES IN A MICROPROCESSOR - A microprocessor includes a first plurality of fuses, a predetermined number of which are selectively blown. Control values are provided from the first plurality of fuses to circuits of the microprocessor to control operation of the microprocessor. The microprocessor also includes a second plurality of fuses, blown with the predetermined number of the first plurality of fuses that are blown. In response to being reset, the microprocessor is configured to: read the first plurality of fuses and count a number of them that are blown; read the predetermined number from the second plurality of fuses; compare the counted number with the predetermined number read from the second plurality of fuses; and prevent itself from fetching and executing user program instructions if the number counted from reading the first plurality of fuses does not equal the predetermined number read from the second plurality of fuses. | 2011-02-10 |
20110035617 | USER-INITIATABLE METHOD FOR DETECTING RE-GROWN FUSES WITHIN A MICROPROCESSOR - A microprocessor includes a first plurality of fuses, selectively blown with a predetermined value for provision to circuits of the microprocessor to control operation of the microprocessor. The microprocessor also includes a second plurality of fuses, selectively blown with error detection information used to detect an error in the first plurality of fuses such that a blown fuse of the microprocessor returned a non-blown binary value. In response to a user program instruction, the microprocessor is configured to determine whether there is an error in the first plurality of fuses such that a blown fuse returned a non-blown binary value using the error detection information from the second plurality of fuses. | 2011-02-10 |
20110035618 | AUTOMATED TRANSITION TO A RECOVERY KERNEL VIA FIRMWARE-ASSISTED-DUMP FLOWS PROVIDING AUTOMATED OPERATING SYSTEM DIAGNOSIS AND REPAIR - A method (and structure) of operating an operating system (OS) on a computer. When a failure of the OS is detected, the computer automatically performs a diagnosis of the OS failure. The computer also attempts to automatically repair/recover the failed OS, based on the diagnosis, without requiring a reboot. | 2011-02-10 |
20110035619 | INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING APPARATUS CONTROL METHOD - An information processing apparatus includes an execution determination unit and a control unit. The execution determination unit determines whether a series of processes including multiple processes is executable at an execution time of the series of processes. The control unit selectively provides at least one recovery device for substituting for the series of processes when it is determined that the series of processes is not executable. | 2011-02-10 |
20110035620 | Virtual Machine Infrastructure With Storage Domain Monitoring - A computing device monitors multiple hosts. A first host that does not have access to a data store is identified. A determination is made as to whether other hosts have access to the data store. When the other hosts do have access to the data store, it is determined that the first host is malfunctioning. A host error notification may then be sent to an administrator. | 2011-02-10 |
20110035621 | Systems and Methods for Facilitating Storage Operations Using Network Attached Storage Devices - A system and method for communicating, browsing, verifying and routing data in storage operation systems using network attached storage devices is provided. In some embodiments, the system may include a management module and a media management component connected to the management server, which interoperate with network attached storage devices to provide the communicating, browsing, verifying and routing functions. | 2011-02-10 |
20110035622 | DETECTION AND CORRECTION OF FUSE RE-GROWTH IN A MICROPROCESSOR - A microprocessor includes a first plurality of fuses selectively blown with control values, a second plurality of fuses selectively blown collectively with an error correction value computed from the control values, control hardware that receives the control values and provides them to circuits of the microprocessor for controlling operation thereof. A state machine, serially coupled to the control hardware and to the fuses, serially scans the control values from the first fuses to the control hardware and serially scans the control values and the error correction value to a first register. The microprocessor reads the control values and error correction value from the first register, detects and corrects an error in the control values using the error correction value, writes the corrected control values to a second register, and causes the state machine to serially scan the corrected control values from the second register to the control hardware. | 2011-02-10 |
20110035623 | DETECTION OF FUSE RE-GROWTH IN A MICROPROCESSOR - A microprocessor includes a first plurality of fuses, a predetermined number of which are selectively blown. Control values are provided from the fuses to circuits of the microprocessor to control operation thereof. A second plurality of fuses are blown with the predetermined number of the first plurality of fuses that are blown and a Boolean complement of the predetermined number. In response to being reset, the microprocessor: reads the predetermined number and the Boolean complement of the predetermined number from the second plurality of fuses, Boolean complements the predetermined number read from the second plurality of fuses to generate a result, compares the result with the Boolean complement of the predetermined number read from the second plurality of fuses, and prevent itself from fetching and executing user program instructions if the result does not equal the Boolean complement of the predetermined number read from the second plurality of fuses. | 2011-02-10 |
20110035624 | INTELLIGENT POWER CONTROL - In accordance with the techniques discussed herein, a smart monitor module (SMM) can apply the rules to information gathered about a device to determine whether a device has entered a failed state. Upon entry into the failed state, the system reboots the device to restore the device to the active state. | 2011-02-10 |
20110035625 | INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD - In an information processing apparatus for storing, based on a notification sent from a monitor unit used for monitoring a state of print processing of a printing apparatus, the status item presenting the state in a storage region, or deleting the status item stored in the storage region, and for displaying the status item stored in the storage region in a storage order, a monitor unit acquires a plurality of the status items stored in the storage region, compares priority of the acquired plurality of status items and priority of a new status item stored in the storage region, and notifies a control unit to store the status items in the storage region in an order based on priority obtained as a result of the comparison. | 2011-02-10 |
20110035626 | DISTRIBUTED COMPUTING - On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that tend to alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems. | 2011-02-10 |
20110035627 | SYSTEM AND METHOD FOR SUPPORTING INFORMATION INTEROPERABILITY BETWEEN MEDICAL INSTRUMENTS - The present invention relates, in general, to Electronic Medical Record (EMR) systems, and, more particularly, to a system and method for supporting information interoperability between medical instruments which is capable of automatically combining medical test information measured by a plurality of medical instruments for performing data communication in compliance with various data interface protocols with the medical information of an EMR system. | 2011-02-10 |