07th week of 2009 patent applcation highlights part 44 |
Patent application number | Title | Published |
20090042353 | INTEGRATED CIRCUIT FABRICATION PROCESS FOR A HIGH MELTING TEMPERATURE SILICIDE WITH MINIMAL POST-LASER ANNEALING DOPANT DEACTIVATION - Post-laser annealing dopant deactivation is minimized by performing certain silicide formation process steps prior to laser annealing. A base metal layer of nickel is deposited on the source-drain regions and the gate electrode, followed by deposition of an overlying layer of a metal having a higher melting temperature than nickel. Thereafter, a rapid thermal process is performed to heat the substrate sufficiently to form metal silicide contacts at the top surfaces of the source-drain regions and of the gate electrode. The method further includes removing the remainder of the metal-containing layer and then depositing an optical absorber layer over the substrate prior to laser annealing. | 2009-02-12 |
20090042354 | INTEGRATED CIRCUIT FABRICATION PROCESS USING A COMPRESSION CAP LAYER IN FORMING A SILICIDE WITH MINIMAL POST-LASER ANNEALING DOPANT DEACTIVATION - Post-laser annealing dopant deactivation is minimized by performing certain silicide formation process steps prior to laser annealing. A base metal layer is deposited on the source-drain regions and the gate electrode, followed by deposition of an overlying compression cap layer, to prevent metal agglomeration at the silicon melting temperature. Thereafter, a rapid thermal process is performed to heat the substrate sufficiently to form metal silicide contacts at the top surfaces of the source-drain regions and of the gate electrode. The method further includes removing the remainder of the metal-containing layer and then depositing an optical absorber layer over the substrate prior to laser annealing near the silicon melting temperature. | 2009-02-12 |
20090042355 | SEMICONDUCTOR WAFER AND MANUFACTURING METHOD THEREFOR - A plurality of IC regions are formed on a semiconductor wafer, which is cut into individual chips incorporating ICs, wherein wiring layers and insulating layers are sequentially formed on a silicon substrate. In order to reduce height differences between ICs and scribing lines, a planar insulating layer is formed to cover the overall surface with respect to ICs, seal rings, and scribing lines. In order to avoid occurrence of breaks and failures in ICs, openings are formed to partially etch insulating layers in a step-like manner so that walls thereof are each slanted by prescribed angles ranging from 20° to 80°. For example, a first opening is formed with respect to a thin-film element section, and a second opening is formed with respect to an external-terminal connection pad. | 2009-02-12 |
20090042356 | Peeling Method and Method of Manufacturing Semiconductor Device - There is provided a peeling method capable of preventing a damage to a layer to be peeled. Thus, not only a layer to be peeled having a small area but also a layer to be peeled having a large area can be peeled over the entire surface at a high yield. Processing for partially reducing contact property between a first material layer ( | 2009-02-12 |
20090042357 | Method of selective oxygen implantation to dielectrically isolate semiconductor devices using no extra masks - A method of fabricating integrated circuit structures utilizes selective oxygen implantation to dielectrically isolate semiconductor structures using no extra masks. Existing masks are utilized to introduce oxygen into bulk silicon with subsequent thermal oxide growth. Since the method uses bulk silicon, it is cheaper than silicon-on-insulator (SOI) techniques. It also results in bulk-silicon that is latch-up immune. | 2009-02-12 |
20090042358 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME - The semiconductor device fabrication method according the present invention having, forming an interlayer dielectric film containing carbon above a semiconductor substrate, forming a protective film on that portion of the interlayer dielectric film, which is close to the surface and in which the carbon concentration is low, forming a trench by selectively removing a desired region of the interlayer dielectric film and protective film, such that the region extends from the surface of the protective film to the bottom surface of the interlayer dielectric film, supplying carbon to the interface between the interlayer dielectric film and protective film, and forming a conductive layer by burying a conductive material in the trench. | 2009-02-12 |
20090042359 | Structure and Method of Producing Isolation with Non-Dopant Implantation - A method of forming an isolation trench structure is disclosed, the method includes forming an isolation trench in a semiconductor body associated with an isolation region, and implanting a non-dopant atom into the isolation trench, thereby forming a region to modify the halo profile in the semiconductor body. Subsequently, the isolation trench is filled with a dielectric material. | 2009-02-12 |
20090042360 | STRAINED SEMICONDUCTOR BY FULL WAFER BONDING - One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined contour is formed in one of a semiconductor membrane and a substrate wafer. The semiconductor membrane is bonded to the substrate wafer and the predetermined contour is straightened to induce a predetermined strain in the semiconductor membrane. In various embodiments, a substrate wafer is flexed into a flexed position, a portion of the substrate wafer is bonded to a semiconductor layer when the substrate wafer is in the flexed position, and the substrate wafer is relaxed to induce a predetermined strain in the semiconductor layer. Other aspects and embodiments are provided herein. | 2009-02-12 |
20090042361 | Method for Manufacturing SOI Substrate and SOI Substrate - According to the present invention, there is provided a method for manufacturing an SOI substrate based on a bonding method, comprising at least: forming a silicon oxide film on a surface of at least one of a single-crystal silicon substrate that becomes an SOI layer and a single-crystal silicon substrate that becomes a support substrate; bonding the single-crystal silicon substrate that becomes the SOI layer to the single-crystal silicon substrate that becomes the support substrate through the silicon oxide film; and performing a heat treatment for holding at a temperature falling within the range of at least 950° C. to 1100° C. and then carrying out a heat treatment at a temperature higher than 1100° C. when effecting a bonding heat treatment for increasing bonding strength. As a result, there are provided the method for manufacturing an SOI substrate that can efficiently manufacture an SOI substrate having an excellent gettering ability with respect to metal contamination in an SOI layer, and the SOI substrate. | 2009-02-12 |
20090042362 | Manufacturing methods of SOI substrate and semiconductor device - A manufacturing method of an SOI substrate and a manufacturing method of a semiconductor device are provided. When a large-area single crystalline semiconductor film is formed over an enlarged substrate having an insulating surface, e.g., a glass substrate by an SOI technique, the large-area single crystalline semiconductor film is formed without any gap between plural single crystalline semiconductor films, even when plural silicon wafers are used. An aspect of the manufacturing method includes the steps of disposing a first seed substrate over a fixing substrate; tightly arranging a plurality of single crystalline semiconductor substrates over the first seed substrate to form a second seed substrate; forming a large-area continuous single crystalline semiconductor film by an ion implantation separation method and an epitaxial growth method; forming a large-area single crystalline semiconductor film without any gap over a large glass substrate by an ion implantation separation method again. | 2009-02-12 |
20090042363 | Method for manufacturing bonded wafer and outer-peripheral grinding machine of bonded wafer - The present invention provides a method for manufacturing a bonded wafer, which includes at least the steps of bonding a bond wafer and a base wafer, grinding an outer peripheral portion of the bonded bond wafer, etching off an unbonded portion of the ground bond wafer, and then reducing a thickness of the bond wafer, wherein, in the step of grinding the outer peripheral portion, the bonded bond wafer is ground so as to form a groove along the outer peripheral portion of the bond wafer to form an outer edge portion outside the groove; and in the subsequent step of etching, the outer edge portion is removed together with the groove portion of the bond wafer to form a terrace portion where the base wafer is exposed at the outer peripheral portion of the bonded wafer. Thus, it is possible to provide a method for manufacturing a bonded wafer, which can reduce the number of dimples formed in a terrace portion of a base wafer upon removing an outer peripheral portion of a bonded bond wafer. | 2009-02-12 |
20090042364 | Method For Manufacturing Soi Wafer and Soi Wafer - The present invention provides a method for manufacturing an SOI wafer in which a thickness of an SOI layer is increased by growing an epitaxial layer on the SOI layer of the SOI wafer having an oxide film and the SOI layer formed on a base wafer, wherein the epitaxial growth is performed in such a manner that a reflectivity of a surface of the SOI wafer on which the epitaxial layer is grown in a wavelength region of a heating light at the start of the epitaxial growth falls within the range of 30% to 80%. As a result, in the method for manufacturing the SOI wafer in which a thickness of the SOI layer is increased by growing the epitaxial layer on the SOI layer of the SOI wafer having the oxide film and the SOI layer formed on the base wafer, a method for manufacturing a high-quality SOI wafer with less slip dislocation and others is provided. | 2009-02-12 |
20090042365 | THREE-DIMENSIONAL FACE-TO-FACE INTEGRATION ASSEMBLY - A via for connecting metallization layers of chips bonded in a face-to-face configuration is provided, as well as methods of fabricating the via. The via may function as an interconnection of metallization layers in three-dimensional, stacked, integrated circuits, and may enable high density, low-resistance interconnection formation. | 2009-02-12 |
20090042366 | SEMICONDUCTOR DIE SINGULATION METHOD - In one embodiment, semiconductor die are singulated from a semiconductor wafer by etching openings completely through the semiconductor wafer. | 2009-02-12 |
20090042367 | SAWING METHOD FOR A SEMICONDUCTOR ELEMENT WITH A MICROELECTROMECHANICAL SYSTEM - The present invention relates to a sawing method for a Micro Electro-Mechanical Systems (MEMS) semiconductor device. A gum material is disposed between a wafer having at least one MEMS and a carrier, and the gum material is disposed around the MEMS. The wafer is sawed according to the position correspondingly above the gum material. Finally, the carrier and the gum material are removed. By disposing the gum material between the carrier and the wafer, the MEMS are protected, and the wafer and the MEMS can avoid the pollution of water and foreign material, so that the yield can be improved. Furthermore, the wafer is sawed from the backside till the gum material without sawing through the gum material, so that the carrier is not sawed. Therefore, the carrier can be reused, such that the cost is reduced. | 2009-02-12 |
20090042368 | Wafer processing method - A wafer processing method for dividing, along streets, a wafer having a device area where devices are formed in a plurality of areas sectioned by the plurality of streets arranged in a lattice pattern on the front surface of a substrate and a peripheral extra area and comprising electrodes which are embedded in the substrate of the device area, comprising a dividing groove forming step for forming dividing grooves having a depth corresponding to the final thickness of each device along the streets; an annular groove forming step for forming an annular groove having a depth corresponding to the final thickness of each device along the boundary between the device area and the peripheral extra area; a protective member affixing step for affixing a protective member to the front surface of the wafer; a rear surface grinding step for grinding a rear surface corresponding to the device area of the substrate of the wafer to expose the dividing grooves and the annular groove to the rear surface of the substrate of the wafer and form an annular reinforcing portion in an area corresponding to the peripheral extra area; and a rear surface etching step for etching the rear surface of the substrate of the wafer to project the electrodes from the rear surface of the substrate. | 2009-02-12 |
20090042369 | METHOD AND STRUCTURE USING SELECTED IMPLANT ANGLES USING A LINEAR ACCELERATOR PROCESS FOR MANUFACTURE OF FREE STANDING FILMS OF MATERIALS - A method for fabricating free standing thickness of materials using one or more semiconductor substrates, e.g., single crystal silicon, polysilicon, silicon germanium, germanium, group III/IV materials, and others. In a specific embodiment, the present method includes providing a semiconductor substrate having a surface region and a thickness. The method includes subjecting the surface region of the semiconductor substrate to a first plurality of high energy particles provided at a first implant angle generated using a linear accelerator to form a region of a plurality of gettering sites within a cleave region, the cleave region being provided beneath the surface region to defined a thickness of material to be detached, the semiconductor substrate being maintained at a first temperature. In a specific embodiment, the method includes subjecting the surface region of the semiconductor substrate to a second plurality of high energy particles at a second implant angle generated using the linear accelerator, the second plurality of high energy particles being provided to increase a stress level of the cleave region from a first stress level to a second stress level. In a preferred embodiment, the semiconductor substrate is maintained at a second temperature, which is higher than the first temperature. The method frees the thickness of detachable material using a cleaving process, e.g., controlled cleaving process. | 2009-02-12 |
20090042370 | METHOD OF CUTTING PCBS - The present invention relates to a method of cutting PCB module using a laser. The method includes steps of: providing a coverlay film, the coverlay film including at least one opening defined therein; attaching the coverlay film onto the PCB module such that the through holes of the PCB module are covered by the coverlay film and the laser cutting area thereof is exposed via the at least one opening; applying a laser beam to the exposed laser cutting area of the PCB module to cutt the PCB module; and removing the coverlay film. A high positioning precision of the PCB module and better cutting result can be obtained. | 2009-02-12 |
20090042371 | LASER CRYSTALLIZATION PROCESS AND LASER PROCESS - The present invention provides a laser crystallization process applicable to a fabrication of a stack device structure. The process starts with providing a substrate having active devices formed thereon. Next, a first dielectric layer is formed on the substrate, and a multi-layer reflective layer is formed on the first dielectric layer. Then, a second dielectric layer is formed on the multi-layer reflective layer, and amorphous silicon islands are formed on the second dielectric layer. After that, a laser annealing step is performed so that the amorphous silicon islands are crystallized so as to form a poly-silicon active layer. | 2009-02-12 |
20090042372 | Polysilicon Deposition and Anneal Process Enabling Thick Polysilicon Films for MEMS Applications - A method of forming a thick polysilicon layer for a MEMS inertial sensor includes forming a first amorphous polysilicon film on a substrate in an elevated temperature environment for a period of time such that a portion of the amorphous polysilicon film undergoes crystallization and grain growth at least near the substrate. The method also includes forming an oxide layer on the first amorphous polysilicon film, annealing the first amorphous polysilicon film in an environment of about 1100° C. or greater to produce a crystalline film, and removing the oxide layer. Lastly, the method includes forming a second amorphous polysilicon film on a surface of the crystalline polysilicon film in an elevated temperature environment for a period of time such that a portion of the second amorphous polysilicon film undergoes crystallization and grain growth at least near the surface of the crystalline polysilicon film. | 2009-02-12 |
20090042373 | PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A DOPED SEMICONDUCTOR LAYER - A process can include forming a doped semiconductor layer over a substrate. The process can also include performing an action that reduces a dopant content along an exposed surface of a workpiece that includes the substrate and the doped semiconductor layer. The action is performed after forming the doped semiconductor layer and before the doped semiconductor layer is exposed to a room ambient. In particular embodiments, the doped semiconductor layer includes a semiconductor material that includes a combination of at least two elements selected from the group consisting of C, Si, and Ge, and the doped semiconductor layer also includes a dopant, such as phosphorus, arsenic, boron, or the like. The action can include forming an encapsulating layer, exposing the doped semiconductor layer to radiation, annealing the doped semiconductor layer, or any combination thereof. | 2009-02-12 |
20090042374 | METHOD OF GROWING A STRAINED LAYER - A method of forming a Si strained layer | 2009-02-12 |
20090042375 | METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A method of manufacturing a silicon carbide semiconductor device includes a step of ion-implanting an impurity in a surface of a silicon carbide wafer ( | 2009-02-12 |
20090042376 | INTEGRATED CIRCUIT FABRICATION PROCESS WITH MINIMAL POST-LASER ANNEALING DOPANT DEACTIVATION - Post-laser annealing dopant deactivation is minimized by performing certain low temperature process steps prior to laser annealing. | 2009-02-12 |
20090042377 | METHOD FOR FORMING SELF-ALIGNED WELLS TO SUPPORT TIGHT SPACING - Methods include utilizing a single mask layer to form tightly spaced, adjacent first-type and second-type well regions. The mask layer is formed over a substrate in a region in which the second-type well regions will be formed. The first-type well regions are formed in the exposed portions of the substrate. Then, the second-type well-regions are formed through the resist mask. | 2009-02-12 |
20090042378 | USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FLASH MEMORY CELL TO IMPROVE TPD CHARACTERISTICS - Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line. | 2009-02-12 |
20090042379 | Method for Fabricating Semiconductor Device Capable of Adjusting the Thickness of Gate Oxide Layer - The present invention provides a method for fabricating semiconductor device, which is capable of adjusting a gate oxide layer thickness, including: providing a semiconductor substrate; growing a first oxide layer on a surface of the semiconductor substrate; patterning the first oxide layer to expose the first oxide layer corresponding to a gate to be formed; removing the exposed first oxide layer; immersing the substrate into deionized water to grow a second oxide layer; forming a polysilicon layer on the surfaces of the first oxide layer and the second oxide layer; and etching the polysilicon layer to form a gate. The method for fabricating semiconductor device according to the present invention, which is capable of adjusting the thickness of gate oxide layer, can control the thickness of gate oxide layer precisely to satisfy the requirement for different threshold voltages. | 2009-02-12 |
20090042380 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A gate dielectric film, a poly-silicon film, a film of a refractory metal such as tungsten, and a gate cap dielectric film are sequentially laminated on a semiconductor substrate. The gate cap dielectric film and the refractory metal film are selectively removed by etching. Thereafter, a double protection film including a silicon nitride film and a silicon oxide film is formed on side surfaces of the gate cap dielectric film, the refractory metal film, and the poly-silicon film. The poly-silicon film is etched using the double protection film as a mask. Thereafter, the semiconductor substrate is light oxidized to form a silicon oxide film on side surfaces of the poly-silicon film. Accordingly, a junction leakage of a MOSFET having a gate electrode of a poly-metal structure, particularly, a memory cell transistor of a DRAM, can be further reduced. | 2009-02-12 |
20090042381 | High-K Gate Dielectric and Method of Manufacture - A device and method of formation are provided for a high-k gate dielectric and gate electrode. The high-k dielectric material is formed, and a silicon-rich film is formed over the high-k dielectric material. The silicon-rich film is then treated through either oxidation or nitridation to reduce the Fermi-level pinning that results from both the bonding of the high-k material to the subsequent gate conductor and also from a lack of oxygen along the interface of the high-k dielectric material and the gate conductor. A conductive material is then formed over the film through a controlled process to create the gate conductor. | 2009-02-12 |
20090042382 | Device packages - Low volume production of electronic devices having ball attachments, e.g. solder ball arrays, is advantageously achieved using a specific method. In particular a stencil having holes in, for example, the ball grid array pattern is formed by laser ablation of the holes in materials such as paper and polymers. The stencil holes are aligned with corresponding pads on the electronic device. Balls such as solder balls are introduced into the holes and heated to induce adhesion of the balls to the corresponding pads. | 2009-02-12 |
20090042383 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A method of forming a dielectric layer having an air gap to isolate adjacent wirings or a gate stack of the semiconductor device is provided. A method of fabricating a semiconductor device includes providing a semiconductor substrate on which a plurality of wirings are formed adjacent to one another and forming a dielectric layer filling an upper portion of a space between the adjacent wirings to form air gaps by a thermal chemical vapor deposition method. | 2009-02-12 |
20090042384 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND TARGET SUBSTRATE PROCESSING SYSTEM - A semiconductor device manufacturing method includes removing copper deposits, by use of an organic acid gas and an oxidizing gas, from a surface of a second interlayer insulation film having a groove formed therein and reaching a copper-containing electric connector member. The second interlayer insulation film is disposed on a first interlayer insulation film provided with the electric connector member. The method then includes reducing a surface of the electric connector member exposed at a bottom of the groove of the second interlayer insulation film; forming a barrier layer on the second interlayer insulation film; and forming a copper-containing conductive film to fill the groove of the second interlayer insulation film. | 2009-02-12 |
20090042385 | METHOD OF MANUFACTURING METAL LINE - A method of manufacturing a metal line according to embodiments includes forming an interlayer dielectric layer over a semiconductor substrate. A dielectric layer is formed over the interlayer dielectric layer. A trench may be formed by etching the dielectric layer and the interlayer dielectric layer. A metal material may be disposed over the interlayer dielectric layer including the trench. A first planarization process may be performed on the metal material using the dielectric layer as an etch stop layer. A wet etch process may be performed on the semiconductor substrate subjected the first planarization process. A second planarization process may be performed on interlayer dielectric layer subjected to the wet etch process. | 2009-02-12 |
20090042386 | Semiconductor device using metal nitride as insulating film and its manufacture method - A first insulating film is formed on a semiconductor substrate. A second insulating film made of insulating metal nitride is formed on the first insulating film. A recess is formed through the second insulating film and reaches a position deeper than an upper surface of the first insulating film. A conductive member is buried in the recess. A semiconductor device is provided whose interlayer insulating film can be worked easily even if it is made to have a low dielectric constant. | 2009-02-12 |
20090042387 | Manufacturing method of semiconductor device - To provide a manufacturing method of a semiconductor device in which manufacturing cost can be reduced, and a manufacturing method of a semiconductor device with reduced manufacturing time and improved yield. A manufacturing method of a semiconductor device is provided, which includes the steps of forming a first layer containing a metal over a substrate, forming a second layer containing an inorganic material on the first layer, forming a third layer including a thin film transistor on the second layer, irradiating the first layer, the second layer, and the third layer with laser light to form an opening portion through at least the second layer and the third layer. | 2009-02-12 |
20090042388 | METHOD OF CLEANING A SEMICONDUCTOR SUBSTRATE - A semiconductor substrate is first provided. The semiconductor substrate includes a material layer and a patterned photoresist layer disposed on the material layer. Subsequently, a contact etching process is performed on the material layer by utilizing the patterned photoresist layer as an etching mask so to form an etched hole in the material layer. Thereafter, a solvent cleaning process is carried out on the semiconductor substrate by utilizing a cleaning solvent. Next, a water cleaning process is performed on the semiconductor substrate by utilizing deionized water. The temperature of the deionized water is in a range from 30° C. to 99° C. | 2009-02-12 |
20090042389 | Double exposure semiconductor process for improved process margin - A double exposure semiconductor process is provided for improved process margin at reduced feature sizes. During a first processing sequence, features defining non-critical dimensions of a polysilicon interconnect structure are formed, while other portions of the polysilicon layer are left un-processed. During a second processing sequence, features that define the critical dimensions of the polysilicon interconnect structure are formed without the need to execute a photoresist trimming procedure. Accordingly, only an etch process is executed, which provides higher resolution processing to create the critical dimensions needed during the second processing sequence. | 2009-02-12 |
20090042390 | ETCHANT FOR SILICON WAFER SURFACE SHAPE CONTROL AND METHOD FOR MANUFACTURING SILICON WAFERS USING THE SAME - It is possible to reduce workloads of a both-side simultaneous polishing process or a single-side polishing process, and to achieve both of the maintenance of the wafer flatness and the reduction in wafer front side roughness upon completing a flattening process. A method for manufacturing silicon wafers according to the present invention includes a flattening process | 2009-02-12 |
20090042391 | METHODS FOR FORMING PATTERNS - A method for forming patterns comprises providing a substrate. A set of seed features is formed over the substrate. At least one bi-layer comprising a first layer followed by a second layer is formed on the set of seed features. The first layer and the second layer above the set of seed features are removed. The first layer and the second layer are anisotropically etched successively at least one time to form an opening next to the set of seed features. | 2009-02-12 |
20090042392 | Polishing apparatus, substrate manufacturing method, and electronic apparatus manufacturing method - A polishing apparatus is configured to simultaneously polish both surfaces of a work and includes a sun gear provided around a rotational axis of one of a pair of polishing surfaces, a carrier having a hole configured to house the work, and including teeth so as to serve as a planetary gear which rotates and revolves around the sun gear, and a first dustproof mechanism that includes a first elastic member that contacts one surface of the carrier opposite to one of the polishing surfaces between the sun gear and the hole in the carrier. | 2009-02-12 |
20090042393 | Production method of polishing composition - A production method of a semiconductor device including: producing a polishing composition containing zirconium oxide sol; and planarizing a substrate having an uneven surface with said polishing composition, wherein the polishing composition containing zirconium oxide is produced by the steps comprising: baking at a temperature ranging from 400 to 1000° C., a zirconium compound having d50 (where d50 represents a particle diameter meaning that the number of particles having this particle diameter or less is 50% of the total number of particles) of zirconium compound particles of 5 to 25 μm and d99 (where d99 represents a particle diameter meaning that the number of particles having this particle diameter or less is 99% of the total number of particles) of zirconium compound particles of 60 μm or less, wherein d50 and d99 are measured by measuring a slurry of the zirconium compound by a laser diffractometry; and wet-grinding a powder of zirconium oxide obtained in the above baking in an aqueous medium until d50 of zirconium oxide particles becomes 80 to 150 nm and d99 of zirconium oxide particles becomes 150 to 500 nm, wherein d50 and d99 are measured by measuring a slurry of the zirconium compound by a laser diffractometry. | 2009-02-12 |
20090042394 | MANUFACTURING METHOD FOR WIRING - In the case in which a film for a resist is formed by spin coating, there is a resist material to be wasted, and the process of edge cleaning is added as required. Further, when a thin film is formed on a substrate using a vacuum apparatus, a special apparatus or equipment to evacuate the inside of a chamber vacuum is necessary, which increases manufacturing cost. The invention is characterized by including: a step of forming conductive layers on a substrate having a dielectric surface in a selective manner with a CVD method, an evaporation method, or a sputtering method; a step of discharging a compound to form resist masks so as to come into contact with the conductive layer; a step of etching the conductive layers with plasma generating means using the resist masks under the atmospheric pressure or a pressure close to the atmospheric pressure; and a step of ashing the resist masks with the plasma generating means under the atmospheric pressure or a pressure close to the atmospheric pressure. With the above-mentioned characteristics, efficiency in use of a material is improved, and a reduction in manufacturing cost is realized. | 2009-02-12 |
20090042395 | Spacer process for CMOS fabrication with bipolar transistor leakage prevention - A two-step spacer etch is used for the formation of a spacer in CMOS fabrication. A dry etch is first applied to remove part of the spacer material on the silicon substrate and leave a thin layer of the spacer material remained on the silicon substrate. Then, a wet etch is applied to completely remove the thin layer of the spacer material on the silicon substrate. The wet etch has good etch selectivity between the spacer material and silicon, and thus will not damage the surface of the silicon substrate when the spacer is formed. Therefore, the BJT on the silicon substrate is prevented from junction leakage. | 2009-02-12 |
20090042396 | METHODS OF FORMING SEMICONDUCTOR DEVICES USING SELECTIVE ETCHING OF AN ACTIVE REGION THROUGH A HARDMASK - A method of fabricating a semiconductor device is provided. The method can include forming a hard mask film including lower and upper hard mask films on a substrate in which an active region and an isolation region are defined and patterning the hard mask film to provide a hard mask pattern partially exposing the active region and the isolation region. An etchant can be applied to the active and isolation regions using the hard mask pattern as an etching mask to form a trench in the active region of the substrate while avoiding substantially etching the isolation region exposed to the etchant and a gate can be formed on the trench. | 2009-02-12 |
20090042397 | COPPER RE-DEPOSITION PREVENTING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND SUBSTRATE PROCESSING APPARATUS - A copper re-deposition preventing method includes placing inside a chamber a target substrate with a film including a copper-containing substance and formed thereon, and performing removal of the copper-containing substance from the target substrate placed inside the chamber, by dry cleaning using an organic compound. Then, the method includes unloading from the chamber the target substrate processed by the removal of the copper-containing substance, and depositing a coating film inside the chamber, in which the target substrate processed by the removal of the copper-containing substance is no longer present, thereby covering copper-containing scattered particles left inside the chamber. | 2009-02-12 |
20090042398 | Method for etching low-k material using an oxide hard mask - A method of patterning a film stack is described. The method comprises preparing a film stack on a substrate, wherein the film stack comprises a SiCOH-containing layer formed on the substrate, a silicon oxide (SiO | 2009-02-12 |
20090042399 | Method for Dry Develop of Trilayer Photoresist Patterns - A method of forming a feature on a multi-layer semiconductor is disclosed. A pattern feature is formed in an uppermost layer of the multi-layer semiconductor. The multilayer semiconductor is etched with a SO | 2009-02-12 |
20090042400 | SILICON SURFACE PREPARATION - Methods are provided for producing a pristine hydrogen-terminated silicon wafer surface with high stability against oxidation. The silicon wafer is treated with high purity, heated dilute hydrofluoric acid with anionic surfactant, rinsed in-situ with ultrapure water at room temperature, and dried. Alternatively, the silicon wafer is treated with dilute hydrofluoric acid, rinsed with hydrogen gasified water, and dried. The silicon wafer produced by the method is stable in a normal clean room environment for greater than 3 days and has been demonstrated to last without significant oxide regrowth for greater than 8 days. | 2009-02-12 |
20090042401 | COMPOSITIONS AND METHODS FOR SUBSTANTIALLY EQUALIZING RATES AT WHICH MATERIAL IS REMOVED OVER AN AREA OF A STRUCTURE OR FILM THAT INCLUDES RECESSES OR CREVICES - Methods for preventing isotropic removal of materials at corners formed by seams, keyholes, and other anomalies in films or other structures include use of etch blockers to cover or coat such corners. This covering or coating prevents exposure of the corners to isotropic etch solutions and cleaning solutions and, thus, higher material removal rates at the corners than at smoother areas of the structure or film from which material is removed. Solutions, including wet etchants and cleaning solutions, that include at least one type of etch blocker are also disclosed, as are systems for preventing higher rates of material removal at corners formed by seams, crevices, or recesses in a film or other structure. Semiconductor device structures in which etch blockers are located so as to prevent isotropic etchants from removing material from corners of seams, crevices, or recesses in a surface of a film or other structure at undesirably high rates are also disclosed. | 2009-02-12 |
20090042402 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device fabrication method by which a desired pattern can be formed. After a conductive layer which is a material for a gate electrode is formed, a SiN layer to be used as a hard mask is formed. Then a photoresist layer is formed as a second mask. Then patterning is performed on the photoresist layer. Then patterning is performed on the SiN layer with the photoresist layer as a mask. After the photoresist layer is removed, surface portions of the SiN layer are transmuted and are selectively removed. The conductive layer under the SiN layer is etched with the reduced SiN layer as the hard mask. By doing so, the photoresist layer does not, for example, deform during the process and a minute gate electrode pattern can be formed stably. | 2009-02-12 |
20090042403 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes the steps of forming a nitrogen-containing layer in an exposed portion of a copper interconnect formed in an insulating film provided on a substrate; and forming an interlayer insulating film on the nitrogen-containing layer through plasma CVD performed by using, as a material, an organic silicon compound having a siloxane (Si—O—Si) bond. | 2009-02-12 |
20090042404 | Semiconductor processing - Embodiments of the present disclosure include semiconductor processing methods and systems. One method includes forming a material layer on a semiconductor substrate by exposing a deposition surface of the substrate to at least a first and a second reactant sequentially introduced into a reaction chamber having an associated process temperature. The method includes removing residual first reactant from the chamber after introduction of the first reactant, removing residual second reactant from the chamber after introduction of the second reactant, and establishing a temperature differential substantially between an edge of the substrate and a center of the substrate via a purge process. | 2009-02-12 |
20090042405 | Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode - A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, a trench within the first dielectric layer, and a second dielectric layer on the substrate. The second dielectric layer has a first part that is formed in the trench and a second part. After a first metal layer with a first workfunction is formed on the first and second parts of the second dielectric layer, part of the first metal layer is converted into a second metal layer with a second workfunction. | 2009-02-12 |
20090042406 | SYSTEMS AND METHODS FOR FORMING METAL OXIDES USING METAL COMPOUNDS CONTAINING AMINOSILANE LIGANDS - A method of forming (and an apparatus for forming) a metal oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and one or more precursor compounds that include aminosilane ligands. | 2009-02-12 |
20090042407 | Dual Top Gas Feed Through Distributor for High Density Plasma Chamber - A gas distributor for use in a semiconductor process chamber comprises a body. The body includes a first channel formed within the body and adapted to pass a first fluid from a first fluid supply line through the first channel to a first opening. A second channel is formed within the body and adapted to pass a second fluid from a second fluid supply line through the second channel to a second opening. The first and second openings are arranged to mix the fluids outside the body after the fluids pass through the openings. | 2009-02-12 |
20090042408 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SUBSTRATE PROCESSING APPARATUS - A semiconductor device manufacturing method comprises a process of forming a film on each of multiple substrates arrayed in a processing chamber by a thermal CVD method by supplying a film forming gas into the processing chamber while heating the interior of the processing chamber, wherein in the film forming process, a cycle is performed one time or multiple times with one cycle including a step of flowing the film forming gas from one end towards the other end along the substrate array direction, and a step of flowing the film forming gas from the other end towards the one end along the substrate array direction, without forming temperature gradient along the substrate array direction in the processing chamber. | 2009-02-12 |
20090042409 | Electrical connector - An electrical connector comprises a terminal block, a terminal received in the terminal block and an elastic connecting portion electrically connecting with the terminal. The terminal block defines a first receiving cavity, a second receiving cavity opposite to the first receiving cavity and a spaced portion spacing the first receiving cavity and the second receiving cavity. The spaced portion defines a receiving channel and a inserting slot communicating with the receiving channel. The elastic connecting portion is received in the second receiving cavity and electrically connects with the terminal. | 2009-02-12 |
20090042410 | Card for Information Equipment, and Terminal for Information Equipment - A PC card has a card body portion in which a first card terminal portion is formed in one end and a second card terminal portion is formed in the other end. The card terminal portion has a chip slot. A SIM card inserted through an insertion port into the chip slot is electrically connected to a printed circuit board. The insertion port of the chip slot is opened in an outer side face of the second card terminal portion. | 2009-02-12 |
20090042411 | CONNECTOR HAVING USB AND eSATA INTERFACES - A connector having USB and eSATA interfaces is used in an electronic device for connecting with an external storage device. The electronic device includes a SATA socket on a circuit board thereof. The connector includes one or more USB ports and an eSATA port. The eSATA port is stacked with the USB ports and includes a first connecting terminal and a second connecting terminal. The first connecting terminal is electrically connected to the external storage device. The second connecting terminal is electrically connected to the SATA socket through a transmission line, so that high-speed data transmission between the external storage device and the circuit board of the electronic device is rendered. | 2009-02-12 |
20090042412 | Contact and Electrical Connector - A contact includes a substantially rectangular base plate. A linking member extends from the base plate such that the linking member is perpendicular thereto. A first elastic contact arm extends obliquely upward from a tip end of the linking member. The first elastic contact arm has a contact member for electrically connecting the first elastic contact arm to an integrated circuit socket. A second elastic contact arm extends obliquely downward from a tip end of the linking member. The second elastic contact arm has a contact member for electrically connecting the second elastic contact arm to a circuit board. | 2009-02-12 |
20090042413 | Electrical connector and electrical system using the same - The present invention provides an electrical connector system comprising an IC package and an electrical connector. The electrical connector comprises a base defining a plurality of passageways, a plurality of contacts received in the passageways, and a cover moveable relative to the base from a first position to a second position. The contacts each have a resilient arm extending out of the passageway and extending in a space defined by a lower surface of the cover and a mating surface of the base. The IC package is mounted on an upper surface of the cover, defining a plurality of pins through a plurality of through holes of the cover. During movement of the cover from the first position to the second position, the pins press on a surface of the resilient arm of the contact in a vertical direction and the resilient arms deflect toward an adjacent passageway. | 2009-02-12 |
20090042414 | LAND GRID ARRAY FABRICATION USING ELASTOMER CORE AND CONDUCTING METAL SHELL OR MESH - Methods for fabricating Land Grid Array (LGA) interposer contacts that are both conducting and elastic. Also provided are LGA interposer contacts as produced by the inventive methods. Provided is LGA type which utilizes a pure unfilled elastomer button core that is covered with an electrically-conductive material that is continuous from the top surface to the bottom surface of the button structure. In order to obviate the disadvantages and drawbacks which are presently encountered in the technology pertaining to the fabrication and structure of land grid arrays using electrically-conductive interposer contacts, there is provided both methods and structure for molding elastomer buttons into premetallized LGA carrier sheets, and wherein the non-conductive elastomer buttons are surface-metallized in order to convert them into conductive electrical contacts. | 2009-02-12 |
20090042415 | IC Socket to be Mounted on a Circuit Board - The configuration comprises a base board to be mounted a circuit board, with an IC receiving concave place and a resilient member receiving area, having an upper wall and a lower wall surrounding the resilient member receiving area, the upper wall provided with a first slot for contact and the lower wall provided with a second slot, a contact comprising a first contact portion on which a lead of the IC is loaded, a second contact portion coming into contact with a circuit lead of the circuit board, a contact main body communicating the first contact portion with the second contact portion, and a compressing portion protruding from the rear of the contact main body, the resilient member receiving area receiving the resilient member of integral structure, set in the resilient member receiving area, in which a plurality of contacts are implanted, wherein the compressing portion compresses the resilient member in order that a contact pressure can be obtained for the contact to the IC lead and the circuit lead by means of a restoring force of the resilient member. | 2009-02-12 |
20090042416 | METHOD FOR THE SOLDERLESS CONNECTION OF AN ELECTRIC ACTUATOR TO A PRINTED CIRCUIT, WHICH IS PARTICULARLY SUITABLE FOR MOTOR VEHICLE DASHBOARDS - A method of connecting an electric actuator to a printed circuit by metal contacts having an open contact zone. The metal contacts are soldered to the printed circuit using an SMD-type automated method performed at a high speed and at a high temperature, and the electrical connection pins of the actuator can be mechanically connected to the metal contacts without soldering by butting the contact zone of the metal contacts against the connection pins of the actuator once the connection pins have been inserted through the contact zone. | 2009-02-12 |
20090042417 | ELECTRICAL CONNECTORS HAVING POWER CONTACTS WITH ALIGNMENT/OR RESTRAINING FEATURES - Preferred embodiments of power contacts have alignment features that can maintain conductors of the power contacts in a state of alignment during and after insertion of the power contacts into a housing. | 2009-02-12 |
20090042418 | Camera modular connector having metal shell having deformable tab facilitating removal of connector assemble therein - A camera modular connector ( | 2009-02-12 |
20090042419 | Electrical connection assembly - An electrical connection assembly includes a substrate having first and second sides and a substrate aperture formed therein. The substrate is made of an electrically non-conductive material. A busbar is attached to the first side of the substrate. The busbar has a busbar aperture formed therein. A trace is formed on the second surface of the substrate. The busbar and trace are formed of an electrically conductive material. A pin is disposed in both the substrate aperture and the busbar aperture, wherein the pin is in electrical communication with the busbar and the trace. | 2009-02-12 |
20090042420 | Electrical connector with improved contacts and transition module - An electrical connector mounted on a mother PCB includes an insulative tongue portion and a number of contacts held in the insulative tongue portion. The contacts have four conductive contacts and at least one pair of differential contacts for transferring high speed signals. The conductive contacts are adapted for USB 2.0 protocol. The electrical connector further includes a transition module with one end connected to the contacts and the other end to be soldered to the mother PCB. | 2009-02-12 |
20090042421 | Electrical connector with improved contacts - An electrical connector includes an housing having a base portion, a tongue portion extending forwardly from the base portion and a number of passageways, the tongue portion defining a front face, a first side face and a second side face; a metal shell enclosing the tongue portion to define a receiving room therebetween, and defines a top wall, bottom wall and a pair of side walls, a first receiving room being formed between the bottom wall and the first side face; a number of contacts received in the passageways respectively and including a plurality of first contacts and second contacts, the first contacts each defining a first contacting portion, a first soldering portion and a first retaining portion, the second contacts each defining a second contacting portion, a second soldering portion and a second retaining portion. Both the second contacting portions and the first contacting portions are positioned on a same side of the second side face to be exposed to the first receiving room, the first contacting portions extend beyond the first side face. | 2009-02-12 |
20090042422 | Connection device - A cable connection device ( | 2009-02-12 |
20090042423 | Lever-Type Connector - Slide members in the lever-type connector are respectively provided with resilient latch arms and respectively have latching projections that latch on the corresponding drive projections during the temporary mating with the mating connector. Each of the resilient latch arms is formed between a pair of slits respectively extending from specified points which are located in the end portion of one of the cam grooves toward the corresponding entrance where the corresponding drive projection enters and on the side opposite from the side of the entry of the corresponding drive projection so as to undergo elastic deformation in the direction of thickness of the slide member. | 2009-02-12 |
20090042424 | Connector Boot And Connector Assembly - A connector boot for a connector having a connector housing with a cantilevered lock tab protruding rearward from an upper surface of the connector housing, comprising a boot main body connected to a rear side of the connector housing, the boot main body comprising an activator that is pivotal about a hinge, wherein the activator comprises an upper activator tab for engaging the lock tab from above and the upper activator tab being configured for a push-down operation, and wherein the activator comprises a rear activator tab located opposite the upper activator tab so that the hinge is between the upper activator tab and the rear activator tab and the rear activator tab being configured for a push-up operation is disclosed. | 2009-02-12 |
20090042425 | Apparatus to Assist in Removing an Electrical Plug from a Socket | 2009-02-12 |
20090042426 | Switch arrangement and method for changing over a hearing device - Switch arrangement for hearing devices, which includes a connector socket which can be covered by a socket cover. The connector socket and the socket cover are arranged and embodied such that an electrical switching contact can be produced by applying pressure to the socket cover covering the connector socket. A method for changing over programs in hearing devices with a behind-the-ear part is also specified, in which an electrical switching contact is produced by means of a connector socket of the behind-the-ear part and its socket cover. Space can be saved as a result. | 2009-02-12 |
20090042427 | Surface mount connector - A surface mount connector includes a housing and a movable terminal attached to the housing. The movable terminal includes a movable section to be movable relative to the housing, an adhering section connected to the movable section and having an adhering surface relative to the housing, and a connecting section connected to the adhering section via a joining section. The adhering surface includes a groove extending toward the movable section having a first width. The movable terminal further includes an opening portion connected to the groove. The opening portion extends in a first direction crossing a second direction that the adhering section is connected to the movable section and having a second width larger than the first width. | 2009-02-12 |
20090042428 | ELECTRICAL SYSTEM FOR OFFICE FURNITURE - An article of furniture having a construction adapted to efficiently accommodate electrical components. The article of furniture includes a frame or chassis having support leg assemblies, and a beam connected to the support leg assemblies to which a channel is mounted. The support leg assemblies include work surface supports which support work surfaces at adjustable heights above the channel, and a gap between the work surfaces allows access to the electrical system within the channel. The electrical system is modular in design, and includes a series of components that may be connected to one another in a manner that the location of electrical outlet modules may be easily adjusted. The channel has a plurality of knock-out openings which may be selectively used for locating electrical outlets at any desired position along the channel. | 2009-02-12 |
20090042429 | Sealed Connection Device and Sealed Connector Counterpart - The invention concerns an electrical connection device including a connector having electrical contacts, a connector counterpart having complementary electrical contacts, designed to be coupled to the connector along a coupling axis (X-X), an annular seal. The connector counterpart includes a support for said electrical contacts onto which the seal is fitted and a housing for receiving at least one part of the support, and the housing and the connector each have a peripheral support surface onto a first area and onto a second area of said seal, which areas are adjacent. The invention also concerns a connector counterpart. | 2009-02-12 |
20090042430 | Fastener for a socket connector - A fastener for a socket connector includes a frame and a pressing assembly. The frame has an opening and a plurality of protrusions. The protrusions extend from inner edges of the frame toward the opening. The pressing assembly has a cover and a buckling piece. The cover is pivotally connected to the frame. The buckling piece locks the cover on the frame. Using the above arrangement, the protrusions are used to accurately align the socket connector within the opening, thus the inter edge surface of the frame is aligned with the outer peripheral surface of the socket connector. In this way, the pressing assembly of the frame can be operated accurately to lock and press a chip module on the socket connector. | 2009-02-12 |
20090042431 | REMOTE BLIND MATE CONNECTOR RELEASE SYSTEM FOR A SCALABLE DEEP PLUG CABLE - A cable trough comprising a rigid trough securing a cable that terminates with a cable connector plug. The cable connector plug has a connector latch operable with a pull tab for selectively latching the cable connector plug to a blind mate connector inside an electronic device. The trough secures the connector plug in axial alignment with the trough and includes a release lever pivotally coupled to the proximal end of the trough. An elongate wire extends within the trough and is coupled between the release lever and the pull tab. Accordingly, the rigid trough may be directed into a guide passage aligned with the blind mate connector for coupling and latching of the connector plug to the blind mate connector. The release lever is pivotally operable to pull the wire and actuate the pull tab to release the connector latch. | 2009-02-12 |
20090042432 | RELEASABLY LOCKING AUTO-ALIGNING FIBER OPTIC CONNECTOR - A connector assembly couples signal lines for an optical catheter by providing a guided releasable latching mechanism that ensures optimal alignment with only a single vertical dimension under control. A receptacle carrying a first signal line defines a channel for receiving a plug carrying a second signal line. A spring-loaded pawl on the receptacle locks to a retaining bracket on the plug when the plug slides into the channel, imparting a retaining force on the plug, the force having a first component normal to channel and a second component parallel to the channel to maintain the first and second signal lines in optimal alignment. The retaining bracket may include a sloped edge to allow for easy release of the pawl in the presence of a release force. The release force may be set to allow disconnection of the assembly without affecting catheter installation or causing patient discomfort. | 2009-02-12 |
20090042433 | Data connector plug with internal cover and locking system - Data connector plugs having an internal extensible and retractable cover and locking system and portable memory storage devices and data transfer cables equipped with the same have an internal extensible and retractable cover member which, in an extended and locked position, is disposed inside the case of the plug to at least partially occupy the void space adjacent to the metal contacts sufficient to physically prevent unauthorized connection with a mating connector and access and transfer of data and media, and in an unlocked retracted position exposes the electrical contacts to allow connection of the plug and electrical contacts with a mating connector for transferring data. The internal cover member may be sized to substantially fill the void space in a forward extended position to prevent damage to the contacts and ingress of dirt or debris. | 2009-02-12 |
20090042434 | Electrical Connector - The electrical connector includes an electrical terminal, a housing delimiting a chamber for receiving the terminal along a reception direction (X), successively at a reception position and at a retained position, a pawl hinged to one amongst the housing and the terminal, and a stop fixed to the other amongst the housing and the terminal. Said pawl and stop cooperate for retaining the terminal at its retained position, and said housing includes a guiding wall with a guiding surface on which the terminal is pushed against by the pawl being elastically pushed back. The guiding surface comprises a raising slope inclined toward the inside of the chamber along the reception direction (X) | 2009-02-12 |
20090042435 | MOLDED ELECTRICAL CONNECTOR AND METHOD OF MAKING SAME - A connector assembly has a cable having at least one wire and a sheath surrounding the wire, a contact holder having a front end, a contact fixed in the holder, exposed at the front end, and connected to the wire with the wire is free of the sheath for a short distance from a rear end of the holder, a plastic body molded to the holder to an end of the cable sheath adjacent the holder and over the wire exposed between the sheath and the holder rear end, and an inlay only partially imbedded in the body in a non-detachable and visible manner. | 2009-02-12 |
20090042436 | On-Train Information Transmitting/Receiving System - An on-train information transmitting/receiving system is provided that can be implemented in an environment with significant external noise and allows high speed transmission to be carried out between transmitter/receivers mounted in vehicles without having to develop a new jumper cable used between the vehicles while cost increase is prevented. A transmission path that connects transmitter/receivers | 2009-02-12 |
20090042437 | Plug-In Termination of a Power Cable for Subsea Appliances - A plug-in termination of a single-phase conductor in a power cable termination assembly for submerged use. A first barrier separates an outer pressure-compensated housing from the sea. A second barrier separates an inner pressure-compensated housing from the outer pressure-compensated housing. The single-phase conductor runs through the first and second barriers and is secured in the inner pressure-compensated housing by its end being terminated within an insulator body insertable into the inner housing. The unsheathed conductor end is electrically connected within the insulator body to a conducting pin which is fixedly embedded by molding into the insulator body. | 2009-02-12 |
20090042438 | Connector - A connector includes: a housing man body including a rib extending frontward; a front holder fitted into the housing main body from the front, and capable of moving from a temporary locking position to a permanent locking position, and the front holder including a through-hole into which the rib is inserted; means for temporarily locking the front holder; and means for permanently locking the front holder. The rib is long enough for a front end of the rib to agree with, or jut out from, a rear end surface of the front holder which is located rearward in an insertion direction of the front holder while the front holder is held in the temporary locking position. The housing main body includes bendable lances for locking their corresponding terminals inserted into the housing main body. The front holder includes lance pressing part restricting the bends of the corresponding bendable lances. | 2009-02-12 |
20090042439 | COMPUTER ENCLOSURE WITH CONNECTOR - A computer enclosure includes a chassis ( | 2009-02-12 |
20090042440 | Coaxial plug-in connector comprising a contact mechanism for electrical contact - A coaxial connector for insertion of a complementary coaxial connector, in which a switching mechanism having an electrical contact is arranged and formed in the coaxial connector that the electrical contact is closed when there is not a complementary coaxial connector inserted in the coaxial connector, and the electrical contact is open when there is a complementary coaxial connector inserted in the coaxial connector, the arrangement made so that the switching mechanism has a cylindrical first conductor part which may be expanded and/or compressed radially with elastic resilience, and which makes electrical contact with a second conductor part of the switching mechanism, the first conductor part arranged and formed that a complementary coaxial connector which is inserted in the coaxial connector expands the first conductor part radially or compresses it radially, thus breaking the electrical contact between the first conductor part and the second conductor part. | 2009-02-12 |
20090042441 | COAXIAL PLUG CONNECTOR FOR A COAXIAL CABLE - A coaxial plug connector having a housing produced from an electrically insulating material, which is open at a plug end so that a mating coaxial plug connector can be inserted. An insertion area for the mating housing is provided. At a coaxial cable end, the housing has an axial opening for coaxial cable insertion. Inside the housing, an internal and external conductor elements for electrically connecting internal and external conductors of the coaxial cable, respectively, are provided. A snap-in mechanism is configured on the housing to fix the external conductor element in the housing in at least the axial direction. A sealing sleeve completely surrounds the external conductor element in the circumferential direction, and in the axial direction in at least an area that extends from a part of the housing at the coaxial cable end to the insertion area for the mating housing at the plug end. | 2009-02-12 |
20090042442 | RUBBER STOPPER FOR WATERPROOF CONNECTOR AND WATERPROOF CONNECTOR - A rubber stopper for a waterproof connector includes: a first elastic member including a first contact face, and first wire fitting grooves each having an arc cross-section; and a second elastic member including a second contact face and second wire fitting grooves each having an arc cross-section. When the first contact face contacts the second contact face, circular cross-section is formed by the arc cross-sections of the first and second wire fitting grooves to fit wires into the first and second wire fitting grooves. Arc length of the arc cross-section of the first wire fitting groove is different from arc length of the arc cross-section of the second wire fitting groove so that a center of the circular cross-section is disposed away from the first and second contact faces in a direction perpendicular to an extending direction of the first and the second contact faces. | 2009-02-12 |
20090042443 | Method for assembling an electrical connector to a metal shell - A method for assembling a terminal insert onto a metallic housing comprises the steps of: (1) providing a terminal insert defining a dowel post extending out of the surface thereof; (2) providing a metallic housing having a hole corresponding with the dowel post; (3) assembling the terminal insert on the metallic housing by aligning the dowel post with respect to the hole; (4) inserting the dowel post into the hole and then deforming a portion of the dowel post by applying adequate heat. | 2009-02-12 |
20090042444 | ELECTRONIC PART EQUIPPED UNIT - An electronic part equipped unit includes a case body that includes a first recess portion for containing an electronic part and a second recess portion for containing a relay terminal which is connected to the electronic part, a wire side terminal to which a middle portion of a wire is attached, and a cover member to which the wire side terminal is attached. A wire positioning rib is formed on the cover member and is brought into contact with the wire to position the wire. A wire position correcting rib for correcting a position of the wire is formed in the second recess portion. The wire position correcting rib which is inserted into an inner portion of the cover member corrects the position of the wire when the cover member to which the wire side terminal is attached is fitted to the second recess portion of the case body. | 2009-02-12 |
20090042445 | JOINT CONNECTOR - A joint connector ( | 2009-02-12 |
20090042446 | Adapter board, socket, and device for connecting an electronic controller to the connection leads thereof - An adapter board for connecting an electronic controller to the connection leads thereof includes a printed circuit board having at least two pins, which can be inserted into connections for the connection leads of the electronic controller. The adapter board also includes a plug-in connector, which can be plugged into a mating plug-in connector of a socket and which can be brought into a signal connection with the connection leads. The pins are connected to the plug-in connector in an electrically conductive manner via the printed circuit board. | 2009-02-12 |
20090042447 | PLUG - According to one embodiment, a plug includes four terminals arranged around a core shaft at substantially equal intervals, a housing that supports proximal ends of the four terminals, and a cylindrical cover fixed to the housing such as to surround the four terminals. The four terminals include two power terminals and two ground terminals, and at least the two power terminals have insulating coating layers respectively at their distal end portions. | 2009-02-12 |
20090042448 | Stacked electrical connector with improved signal transmission - A stacked electrical connector includes a first mating interface. The first mating interface comprises a first receiving space ( | 2009-02-12 |
20090042449 | Connector and connector housing thereof - A connector electrically connected to a peripheral component interconnect express card includes a first body and a second body. The first body includes a plurality of connection holes provided to be correspondingly plugged by a plurality of plugs having electrical contacts. The second body is connected to the first body and volumetrically less than the first body. When the first and second bodies are connected, the connected first and second bodies has a top-view projecting profile corresponding to the shape of the peripheral component interconnect express card. | 2009-02-12 |
20090042450 | Electrical connector with improved contact arrangement - An electrical connector mounted on a mother PCB includes an insulative tongue portion and a number of contacts held in the insulative tongue portion. The contacts have four conductive contacts and at least one pair of differential contacts for transferring high speed signals. The conductive contacts are adapted for USB 2.0 protocol. The contacts include a plurality of first and second tail portions to be arranged in a single row or at least two rows. | 2009-02-12 |
20090042451 | Electrical connector with improved contacts arrangement - An electrical connector ( | 2009-02-12 |
20090042452 | CONNECTOR CONNECTION STRUCTURE, CONNECTOR CONNECTION METHOD AND VEHICLE - A connector connection structure includes: a case having a side surface and a top surface, respectively extending in directions crossing each other at a first angle, and an opening; a connector terminal portion inserted into the case from the opening; a shield plate closing the opening; a bolt fastening the case and the shield plate; and a terminal block arranged in the case and connected to the connector terminal portion. The shield plate has a first portion extending along the side surface and closing the opening, a second portion extending along the top surface, and a bent portion positioned between the first portion and the second portion and bent at a second angle being smaller than the first angle. The bolt fastens the case and the second portion of the shield plate. | 2009-02-12 |