07th week of 2013 patent applcation highlights part 19 |
Patent application number | Title | Published |
20130038324 | APPARATUS METHOD AND SYSTEM OF AN ULTRA SENSITIVITY OPTICAL FIBER MAGNETO OPTIC FIELD SENSOR - An apparatus and system, capable of measuring the magnitude and direction of magnetic fields including an ultra-sensitive, wideband magneto optic (MO) sensor having magneto-optic crystals is disclosed herein. The sensor exploits the Faraday Effect and is based on a polarimetric technique. An ultra sensitivity optical-fiber magneto-optic field sensor measures a magnetic field with minimal perturbation to the field, and the sensor can be used for High-power microwave (HPM) test and evaluation; Diagnosis of radar and RF/microwave devices; Detection/measurement of weak magnetic fields (e.g., magnetic resonance imaging); Characterization of very intense magnetic fields (>100 Tesla, for example rail gun characterization); Detection of very low-frequency magnetic fields; Characterization of a magnetic field over an ultra broad frequency band (DC—2 GHz); Submarine detection; and Submarine underwater communication. | 2013-02-14 |
20130038325 | MODULAR ARRAYS OF PRIMARY SOURCE MIRRORS FOR BIOMAGNETOMETRY - Apparatus and methods enabling the improved noninvasive measurement of electric currents flowing in the body of a human being or animal or in a biological sample by means of a modular array of primary source mirrors and a magnetometer. | 2013-02-14 |
20130038326 | Method and Apparatus for Compensating for B1 Inhomogeneity in Magnetic Resonance Imaging by Nonselective Tailored RF Pulses - A method of exciting nuclear spins in a body, the method comprising the steps of: (a) immerging said body (PB) in a static magnetic field (B | 2013-02-14 |
20130038327 | METHOD TO ACQUIRE A MAGNETIC RESONANCE IMAGE DATA SET OF A TARGET VOLUME - In a method to acquire a magnetic resonance image data set of a target volume with a magnetic resonance device, wherein the target volume is composed of a number of sub-volumes defined in a two-dimensional plane orthogonal to the readout direction, for each sub-volume, in order to acquire a partial data set of a sub-volume, a targeted excitation of the sub-volume and a data acquisition from that sub-volume to measure the partial data set take place by radiation of a first radio-frequency pulse acting in a first direction of the plane and radiation of a second radio-frequency pulse acting in a second direction that is orthogonal to the first direction. The partial data sets are combined into the magnetic resonance data set. | 2013-02-14 |
20130038328 | MAGNETIC RESONANCE IMAGING APPARATUS AND GRADIENT COIL COOLING CONTROL METHOD - A feedforward control unit predicts the maximum value of the temperature of a gradient coil based on a power duty and a scan time of a pulse sequence, and a present temperature of the gradient coil. When the maximum value exceeds a predetermined upper limit, the feedforward control unit then instructs a temperature adjusting unit to start a water circulation in a chiller at the start of a prescan, and the temperature adjusting unit starts the water circulation based on the instruction. | 2013-02-14 |
20130038329 | MAGNETIC RESONANCE SYSTEM HAVING VARIABLE FREQUENCY TRANSMIT PULSES - A controller of a magnetic resonance system outputs a low frequency base signal to a conversion device. While outputting the base signal to the conversion device, the controller outputs an oscillator control signal to an oscillator. The oscillator outputs a frequency signal corresponding to the oscillator control signal to the conversion device. The conversion device converts the frequency signal into a high frequency transmit pulse with the aid of the base signal and outputs the transmit pulse to a magnetic resonance transmit antenna. The magnetic resonance transmit antenna applies a high frequency field corresponding to a transmit pulse to an examination volume of the magnetic resonance system. The controller varies the oscillator control signal output to the oscillator while outputting the base signal to the modulator. The transmit pulse) has a larger bandwidth than the base signal. | 2013-02-14 |
20130038330 | Systems, Devices, Methods, and Compositions Including Ferromagnetic Structures - Magnetic resonance systems, devices, methods, and compositions are provided. A nuclear magnetic resonance imaging composition includes, but is not limited to, a plurality of ferromagnetic microstructures configured to generate a time-invariant magnetic field within at least a portion of one or more internal surface-defined voids. In an embodiment, at least one of the plurality of ferromagnetic microstructures includes one or more targeting moieties attached thereof. | 2013-02-14 |
20130038331 | COIL CAPABLE OF GENERATING AN INTENSE MAGNETIC FIELD AND METHOD FOR MANUFACTURING SAID COIL - The invention relates to a method for manufacturing a coil for generating an intense magnetic field when an electric current passes through it, comprising the formation of turns in a cylindrical tube made of conducting or superconducting material, the formation of at least one indentation in an edge of at least one turn of said coil and the positioning of insulating material between the turn comprising the indentation and an adjacent turn, said recess being made in the edge to form with the insulating material a channel between the interior and the exterior of the tube when the coil is stressed. | 2013-02-14 |
20130038332 | Short Range Data Transmission In A Borehole - The present disclosure is directed to an antenna for transfer of information along a drill string. The antenna has an antenna coil having a long side and short side. The antenna coil is adapted to be affixed to the drill string such that the long side of the antenna coil is along the longitudinal axis of the drill string, and the short side is perpendicular to the longitudinal axis of the drill string. | 2013-02-14 |
20130038333 | DETERIORATION DEGREE CALCULATING APPARATUS FOR SECONDARY BATTERY, VEHICLE EQUIPPED WITH THE APPARATUS, AND DETERIORATION DEGREE CALCULATING METHOD FOR SECONDARY BATTERY - A deterioration degree calculating apparatus for a secondary battery of the invention includes: obtaining a voltage value at a stop time of charge and discharge of a target secondary battery; obtaining a voltage value at a first start time of charge and discharge after that; obtaining an SOC of the target secondary battery at the stop time or at the start time; obtaining a length of an unused period from the stop time to the start time (an elapsed time); obtaining a self-discharge slope of the target secondary battery by dividing an absolute value of a difference between the voltage value at the start time and the voltage value at the stop time by the elapsed time; obtaining a temperature during an unused period by use of a self-discharge map in which the SOC and the self-discharge slope is recorded for each temperature; calculating a progress degree of deterioration of the target secondary battery during the unused period based on the obtained temperature and elapsed time; and accumulating the calculated deterioration progress degree to accurately calculate the deterioration degree of the secondary battery without continuously consuming electric power during the unused period. | 2013-02-14 |
20130038334 | TEST STRUCTURE, METHOD AND CIRCUIT FOR SIMULTANEOUSLY TESTING TIME DEPENDENT DIELECTRIC BREAKDOWN AND ELECTROMIGRATION OR STRESS MIGRATION - Test structures for simultaneously testing for electromigration or stress migration fails and time dependent dielectric breakdown fails in integrated circuits, test circuits using four test structures arranged as a bridge balance circuit and methods of testing using the test circuits. The electromigration or stress migration portions of the test structures include via chains of wire segments connected in series by electrically conductive vias, the wire segments formed in at least two adjacent wiring levels of an integrated circuit. The time dependent dielectric breakdown portions of the test structures include digitized wire structures in one of the at least two adjacent wiring levels adjacent to a less than whole portion of the wire segments in the same wiring level as the digitized wire structures. | 2013-02-14 |
20130038335 | SWITCHING APPARATUS AND TEST APPARATUS - Provided is a switching apparatus comprising a contact point section that includes a first contact point; an actuator that includes a second contact point and moves the second contact point to contact or move away from the first contact point; and a control section that controls a first drive voltage. The actuator includes a first piezoelectric film that expands and contracts according to the first drive voltage and a support layer disposed on the first piezoelectric film. The control section causes the first piezoelectric film to contract by causing a change from a voltage that applies an electric field that is less than a first coercive electric field to a voltage that applies an electric field that exceeds the first coercive electric field, and causes the first piezoelectric film to expand by outputting a voltage that applies an electric field that is less than a second coercive electric field. | 2013-02-14 |
20130038336 | Probe Calibration Device and Calibration Method - A calibration device applied for a test apparatus with at least a first probe and a second probe, the calibration device comprising: a first testing region and a second testing region, the first testing region and the second testing region divides into n×n sensing units respectively, the first testing region for generating n×n average electricity corresponding to a contact degree of the first probe contacted with the calibration device, and the second testing region for generating another n×n average electricity corresponding to a contact degree of the second probe contacted with the calibration device, and the pitch is the distance between the center of the first testing region to the center of the second testing region that is the same as that of the center of the first probe to the center of the second probe. | 2013-02-14 |
20130038337 | MEASUREMENTS IN METALLURGICAL VESSELS - A method, implemented by a software-controlled computer device and/or by dedicated hardware, for probing an electrically conductive target material, e.g. molten metal or semiconductor material, in a metallurgical vessel. In the method, a measurement signal is acquired from a sensor, which is inserted into the target material, during a relative displacement between the electrically conductive target material and the sensor, the measurement signal being indicative of electrical conductivity in the vicinity of the sensor. The measurement signal is generated to represent momentary changes in an electromagnetic field around the sensor, which is created by operating at least one coil in the sensor. Based on the measurement signal, a signal profile is generated to be indicative of the electrical conductivity as a function of the relative movement. The method enables a probing of the internal distribution of the target material in the vessel at any level of detail. | 2013-02-14 |
20130038338 | Parasitic Capacitive Canceling in a Sensor Interface - In one embodiment, a method includes communicating a first voltage to a drive line of a touch sensor; setting a sense line of the touch sensor to a predetermined voltage; and communicating a second voltage to the drive line. A resulting transition at the drive line from the first voltage to the second voltage causes an amount of charge accumulated on the sense line to be communicated to an integrator. The method also includes, at the integrator, integrating the amount of charge communicated from the sense line to convert the amount of charge to an output voltage. The method also includes restoring the sense line to the predetermined voltage. | 2013-02-14 |
20130038339 | METHODS AND APPARATUS TO DETECT A PRESENCE OF A CONDUCTIVE OBJECT - A method and apparatus determine a plurality of regions, each of the plurality of regions having a detected change in capacitance value that meets or exceeds a threshold value. In an embodiment, the method and apparatus fit a shape to the plurality of regions and determine another region, the other region being within the fitted shape and not having the detected change in capacitance value that meets or exceeds the threshold value. The method and apparatus may assign an assigned change in capacitance value to the other region. | 2013-02-14 |
20130038340 | MEASURING APPARATUS AND MEASURING METHOD - A measurement apparatus comprising a serial resistor in series with an element under measurement; a switching section that sequentially selects ends of a serial circuit including the element under measurement and the serial resistor, and ends of the serial resistor; an applying section that applies an application voltage or application current corresponding to a preset setting value, to each of the sequentially selected ends; a measuring section that, for each of the sequentially selected ends, measures current when the applying section applies the application voltage corresponding to the setting value and measures voltage when the applying section applies the application current corresponding to the setting value; and a resistance calculating section that calculates the resistance value of the element under measurement, based on either the setting values set sequentially in the applying section or measured values measured sequentially by the measuring section for each of the sequentially selected ends. | 2013-02-14 |
20130038341 | CONTACTOR HEALTH MONITOR CIRCUIT AND METHOD - In one possible implementation, a method is provided for determining contactor health including measuring a differential voltage between a first utility line voltage and a second utility line voltage on a primary side of a contactor and on a secondary side of the contactor. The measuring is performed with both an unloaded current and with a load current. The unloaded and loaded measurements are performed at the primary side and the secondary side, and are made with the contactor closed. It includes determining a difference between a secondary unloaded voltage and a secondary loaded voltage and subtracting a difference between a primary unloaded voltage and a primary loaded voltage to provide a contactor voltage drop. The contactor resistance is determined by dividing the contactor voltage drop by the loaded current. | 2013-02-14 |
20130038342 | MOTOR CONTROL APPARATUS - Provided is a motor control apparatus that can easily distinguish between a current sensor abnormality and a rotation-angle sensor abnormality, without making a current sensor a duplex system. An MGECU ( | 2013-02-14 |
20130038343 | TEST CIRCUIT FOR TESTING SHORT-CIRCUIT - A test circuit includes two probes, a comparison circuit, a switch circuit, and an indication circuit. The probes are connected to an electronic component to be tested, and a low level signal is output if the electronic component is short-circuited. The comparison circuit outputs a comparison signal based on the shorting signal from the probes. The switch circuit outputs a switch signal based on the comparison signal from the comparison circuit. The indication circuit indicates that the electronic component is short-circuited or not short-circuited based on the switch signal fro m the switch circuit. | 2013-02-14 |
20130038344 | PROBE ASSEMBLY - A probe assembly includes probe heads, a first connector, and groups of second connectors. Each probe head includes a first connection portion defining two first holes, and a data cable connected to an oscilligraph. The first connector includes a fixing portion and groups of rods fixed to the fixing portion. Each group of rods includes two rods. First ends of each group of rods are detachably inserted into the first holes to electrically connect the corresponding data cable. Each group of second connectors includes a second connection portion defines two second holes, and a connection cable. Second ends of the group of rods are detachably inserted into the second holes to connect the connection cable. | 2013-02-14 |
20130038345 | PROBE STRUCTURE, PROBE APPARATUS, PROBE STRUCTURE MANUFACTURING METHOD, AND TEST APPARATUS - Probes are arranged precisely and at a narrow pitch. Provided is a probe structure receiving and transmitting an electric signal from/to a device. The probe structure includes a contact point that transmits an electric signal, a probe on which the contact point is formed, a probe pad section that is electrically coupled to the contact point, and an insulating section that is provided on the probe and that insulates a bonding wire connected to the probe pad section from the probe. A probe apparatus, a manufacturing method of a probe structure, and a test apparatus are also provided. | 2013-02-14 |
20130038346 | APPARATUS AND METHOD FOR SIGNAL TRANSMISSION OVER A CHANNEL - Apparatus and methods related to data transmission are disclosed. One such apparatus includes a transmitter, a receiver, and a channel. The transmitter includes a pair of current sources and a pair of switches. Each of the switches conducts one of the current sources to the channel in response to input data. The receiver includes a first node configured to receive a signal over the channel. The receiver also includes a resistance generating a voltage drop between the first node and a second node. The receiver further includes a first transistor and a second transistor that are together configured to provide a voltage level to the second node based at least partly on the voltage drop. The resistance provides a negative feedback to center the mean signal level, thereby reducing intersymbol interference. | 2013-02-14 |
20130038347 | CONFIGURABLE IC'S WITH LARGE CARRY CHAINS - Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each several sets of associated configurable logic circuits, the reconfigurable IC also includes a carry circuit for performing up to N carry operations sequentially, wherein N is greater than two. | 2013-02-14 |
20130038348 | LAYOUT METHOD FOR SOFT-ERROR HARD ELECTRONICS, AND RADIATION HARDENED LOGIC CELL - This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modem technologies (.ltoreq.90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors. | 2013-02-14 |
20130038349 | TIME-TO DIGITAL CONVERTER AND DIGITAL-CONTROLLED CLOCK GENERATOR AND ALL-DIGITAL CLOCK GENERATOR - An all-digital clock generator includes a digitally-controlled clock generator and a processing unit. The digitally-controlled clock generator generates a clock signal in response to an enable signal and a digital signal. The processing unit has a frequency multiplier and a reference signal having a period, digitizes the period to generate a quantized signal, generates the digital signal according to the quantized signal and the frequency multiplier, and generates the enable signal according to the reference signal, the clock signal and the frequency multiplier. | 2013-02-14 |
20130038350 | SINGLE-TO-DIFFERENTIAL CONVERSION CIRCUIT AND METHOD - A conversion circuit includes a first inverter having an input node configured to receive a single-ended signal and second and third inverters each having respective inputs coupled to an output of the first inverter. A fourth inverter has an input coupled to an output of the second inverter and has an output coupled to a first node. A fifth inverter has an input coupled to the first node and an output coupled to a second node to which an output of the third inverter is coupled. Sixth and seventh inverters are configured to respectively output a differential signal based on the single-ended signal. The sixth inverter has an input coupled to the first node, and the seventh inverter has an input coupled to the second node. | 2013-02-14 |
20130038351 | PHASE DETECTOR - A phase detection system for providing a phase signal indicative of a phase difference between first and second input signals, with the system including a pair of amplification channels for receiving the input signals, with each channel including a plurality of amplifier stages. The outputs of the two amplification channels are connected to the inputs of a multiplier arrangement, with the arrangement producing an uncompensated phase signal. Compensation circuitry is provided to receive a magnitude signal indicative of the relative magnitudes of the two input signals, with the magnitude signal being used to produce a corrected phase signal indicative of the phase difference between the two input signals. | 2013-02-14 |
20130038352 | CIRCUITS AND METHODS FOR CLOCK MALFUNCTION DETECTION - Circuit for detecting malfunction of a primary clock in SoCs comprises a primary clock circuit having a GRAY code counter for generating a GRAY code sequence based on a number of clock pulses generated Primary clock. A secondary clock circuit is configured to output a secondary clock pulse on each saturation of a secondary clock counter. A clock gated register circuit is clocked by the secondary clock pulse, and is configured to store a plurality of values of the GRAY code sequence, and update the plurality of values of the GRAY code sequence on each saturation of the secondary clock counter. An error detection circuit is configured to output a detection signal for detecting the malfunction of primary clock based on a comparison of the updated plurality of values of the GRAY code sequence with at least one predetermined threshold associated with the malfunction of primary clock. | 2013-02-14 |
20130038353 | SYSTEM AND METHOD FOR SIMULATING BIOFIDELIC SIGNALS - A system for simulating biofidelic signals includes a transducer and a neural transmitter port. The transducer is affected by a parameter and provides an alternating electrical signal based on an effect of the parameter. The neural transmitter port receives a processed electrical signal and outputs the processed electrical to a neural transmitter. The system further includes an input portion, a band-pass filter, and an integrate-and-fire mechanism. The input portion outputs a first signal based on the alternating electrical signal. The band-pass filter outputs a first filtered signal based on the first signal. The integrate-and-fire mechanism generates the processed electrical signal based on the first filtered signal. | 2013-02-14 |
20130038354 | Discharge Path Circuit of an Input Terminal for Driver IC - Disclosed is a discharge path circuit of input terminal for a driver IC (Integrated Chip), the circuit providing a discharge path to the input terminal of the driver IC including a power input port connected to a first input and an operation mode selection port connected to a second input, the discharge path circuit including an LC (Inductance Capacitance) filter interconnected between the first input and the power input port to filter noise on a power source, and a resistance element interconnected between the first input and a ground terminal, wherein the resistance element provides a discharge path for discharging power charged by the input terminal of the driver IC. | 2013-02-14 |
20130038355 | OUTPUT DRIVING CIRCUIT AND TRANSISTOR OUTPUT CIRCUIT - The present invention relates to an output driving circuit and a transistor output circuit. In accordance with an embodiment of the present invention, an output driving circuit including: a first driving circuit unit driven according to on operation of a first switch to supply high voltage power source to a gate of an output transistor; a second driving circuit unit driven by a one-shot pulse generated according to on operation of a second switch, which operates complementarily with the first switch, to discharge a gate-source capacitance of the output transistor; and an output driving voltage clamping unit disposed between a high voltage power source terminal and the gate of the output transistor in parallel with the first driving circuit unit to maintain a gate potential of the output transistor discharged according to the on operation of the second switch is provided. | 2013-02-14 |
20130038356 | OUTPUT DRIVING CIRCUIT AND TRANSISTOR OUTPUT CIRCUIT - Disclosed herein are an output driving circuit and a transistor output circuit. The output driving circuit includes: a reference voltage generating unit generating a reference voltage; a level shift unit including a transistor latch and turning off a first transistor of a driving circuit or driving the first transistor; a driving circuit unit including the first transistor that is driven to apply power to a gate of an output transistor and a second transistor that is driven complementarily to the first transistor to lower a gate voltage of the output transistor and drive the output transistor; and an withstand voltage protecting unit that is driven by receiving a reference voltage and includes a first withstand voltage protecting unit for protecting transistors of the transistor latch and the first transistor for stable operations thereof and a second withstand voltage protecting unit for protecting the output transistor for a stable operation thereof. | 2013-02-14 |
20130038357 | DYNAMIC SWITCH DRIVER FOR LOW-DISTORTION PROGRAMMABLE-GAIN AMPLIFIER - A switching circuit for switching a time-varying input signal, the switching circuit comprising: at least one switch including a N-channel MOSFET and a P-channel MOSFET, each having a gate configured to receive a drive signal to change the ON/OFF state of the switch; and a drive circuit configured and arranged so as to selectively apply a pair of drive signals to change the ON/OFF state of the switch, the drive circuit being configured and arranged to generate the drive signals as a function of (a) a pair DC signal components sufficient to change the ON/OFF state of the switch and (b) a pair of time-varying signal components as at least a partial replica of the signal present on the source terminal of each MOSFET so that when applied with the DC signals to the gates of the re-channel MOSFET and p-channel MOSFET respectively, the drive signals will be at the appropriate level to maintain the ON/OFF state of the switch and keep the gate-source voltages of each MOSFET within the gate-source breakdown limit of the MOSFETs. | 2013-02-14 |
20130038358 | WIRELESS SENSOR NODE AND METHOD - Determining time latency at a sensor node in a mesh network. A beacon time is received at the sensor node from an upstream node, the beacon time offset from global time by the latency. The latency, the global time, and a corresponding local time are determined at the sensor node. | 2013-02-14 |
20130038359 | DIGITAL GLITCH FILTER - A digital glitch filter for filtering glitches in an input signal includes first and second flip-flops and a synchronizer. The synchronizer includes third and fourth flip-flops. A glitch prone input signal is provided to the first and second flip-flops. Additionally, an input clock signal is provided to the first and second flip-flops and the synchronizer. A glitch occurring in the input signal toggles the first and second flip-flops between transmitting and non-transmitting states and first and second intermediate signals are generated. The synchronizer synchronizes the first and second intermediate signals with the input clock signal to generate a filtered output signal. | 2013-02-14 |
20130038360 | TIMING CONTROL DEVICE AND CONTROL METHOD THEREOF - Provided is a timing control device including: a storage unit that stores multiple pieces of timing control information including identification information and expected value data; a first selector that selectively outputs any of the multiple pieces of timing control information; a second selector that selectively outputs any of data items output from data output devices based on the identification information; a reference data generation unit that generates reference data based on expected value data and a data item output from the second selector in synchronization with a switching of the timing control information; a comparator that compares the reference data with the data item output from the second selector and outputs a coincidence signal when the reference data and the data item coincide with each other; and an output control unit that outputs a timing signal according to the coincidence signal. | 2013-02-14 |
20130038361 | POWER-SWITCH TEST APPARATUS AND METHOD - Power switching is facilitated. In accordance with one or more embodiments, a power-switch apparatus includes a plurality of switches coupled between a voltage supply and a switched voltage output. A test control circuit operates the switches for testing a subset thereof, therein indicating a condition of the subset, which may be indicated independently from a condition of the power-switch apparatus as a whole. In some implementations, on-chip current loads are applied to emulate off-chip loads for testing the subset of switches, or individual switches. | 2013-02-14 |
20130038362 | SEMICONDUCTOR SWITCH - According to one embodiment, a semiconductor switch includes a voltage generator, a driver, a switch section, and a power supply controller. The voltage generator is configured to generate a first potential and a negative second potential. The first potential is higher than a power supply voltage supplied to a power supply terminal. The driver is connected to an output of the voltage generator and is configured to output the first potential in response to input of high level and to output the second potential in response to input of low level. The switch section is configured to switch connection between terminals in response to an output of the driver. The power supply controller is configured to control the output of the voltage generator. | 2013-02-14 |
20130038363 | DELAY LOCKED LOOP - A delay locked loop includes a delay adjusting unit configured to delay a first clock signal in outputting a second clock signal phase-locked with the first clock signal and generate a delay control signal in response to the first clock signal and the second clock signal and a variable delay line configured to output a third clock signal by delaying the first clock signal in response to the delay control signal. | 2013-02-14 |
20130038364 | OSCILLATION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME - An oscillation circuit includes an RS flip-flop for generating output signals based on a set signal and a reset signal, an electric-charge charge/discharge unit which has first and second capacitors and charges or discharges the first and second capacitors complementarily based on the output signals, a first comparator which compares a first voltage according to electric charge accumulated in the first capacitor and a first reference voltage and outputs the set signal, a second comparator which compares a second voltage according to electric charge accumulated in the second capacitor and the first reference voltage and outputs the reset signal, and a control unit for controlling a timing at which respective voltage levels of the first reference voltage and the first voltage match and a timing at which respective voltage levels of the first reference voltage and the second voltage match according to a frequency of the output signals. | 2013-02-14 |
20130038365 | Sampling Phase Lock Loop (PLL) With Low Power Clock Buffer - A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time. | 2013-02-14 |
20130038366 | BIST CIRCUIT FOR PHASE MEASUREMENT - A BIST circuit for high speed applications includes a phase difference detection circuit, a period-to-current conversion circuit having an input coupled to an output of the phase difference detection circuit and a current-to-voltage conversion circuit coupled to an output of the period-to-current conversion circuit. The phase difference detection circuit includes first NAND logic for receiving as inputs an input clock signal and a delayed version of an inverted version of the input clock signal; second NAND logic for receiving as inputs the inverted version of the input clock signal and a delayed version of the input clock signal; third NAND logic for receiving as inputs the input clock signal and the delayed version of the input clock signal; and fourth NAND logic for receiving as inputs the inverted version of the input clock signal and a delayed version of the inverted version of the input clock signal. | 2013-02-14 |
20130038367 | DEVICE WITH AUTOMATIC DE-SKEW CAPABILITY - A source driver with an automatic de-skew capability is configured to receive a data signal and a clock signal from a timing controller, which are configured to drive a liquid crystal display panel. The source driver includes a signal delay unit, a setup time register, a hold time register, a first signal delay unit, a second delay unit and a logic circuit. In one embodiment of the present disclosure, the first data delay signal is configured to sample the second clock delay signal and the second data delay signal is configured to sample the first clock delay signal. | 2013-02-14 |
20130038368 | SEMICONDUCTOR DEVICE - A semiconductor device including a common delay circuit configured to delay an input signal in response to a delay control code to output a first delayed input signal and a second delayed input signal; a first delay circuit configured to delay the first delayed input signal in response to the delay control code and to output a first output signal; and a second delay circuit configured to delay the second delayed input signal in response to the delay control code and to output a second output signal. | 2013-02-14 |
20130038369 | Delay Cell and Digitally Controlled Oscillator - A delay cell includes a first inverted transistor pair, a second inverted transistor pair and a plurality of delay units. The first inverted transistor pair is used to receive an input signal. The second inverted transistor pair is electrically cross-coupled to the first inverted transistor pair and cross-controlled by the first inverted transistor pair. The delay units are cascaded between the first inverted transistor pair and between the second inverted transistor pair, thereby providing a plurality of signal propagation delays sequentially, wherein the input signal is delayed for a pre-determined time by the first inverted transistor pair, the second inverted transistor pair and the delay units which are operated sequentially, thereby creating an output signal corresponding to the pre-determined time. A digitally controlled oscillator including the aforementioned delay cells is provided. | 2013-02-14 |
20130038370 | MULTI-PHASE CLOCK GENERATOR - A clock generator includes a first latch configured to output a first intermediate clock phase signal based on a first clock signal and a second intermediate clock phase signal. A first phase interpolation circuit has a first input coupled to a first input of the first latch and a second input coupled to a first output of the first latch. The first phase interpolation circuit is configured to output a first clock phase signal based on the first and second intermediate clock phase signals. | 2013-02-14 |
20130038371 | SCAN TESTING - An electronic system is configured for scan testing, with a clock distribution network going to a plurality of blocks of the system, and a test capture clock being generated locally at each block. Capture clock pulses may optionally be generated at different times for different blocks, and may optionally be suppressed for some blocks. | 2013-02-14 |
20130038372 | SEMICONDUCTOR DEVICE - A second driver is provided in addition to a first driver outputting an output signal in accordance with a voltage of an input signal. When the output signal changes from a first voltage level to a second voltage level in accordance with a voltage change of the input signal, a control part controls the second driver to assist the signal change during a period from a change start time until the output signal exceeds a third voltage level. The control part controls the second driver to suppress the signal change during a period from the time when the output signal exceeds the third voltage level until it reaches the second voltage level. | 2013-02-14 |
20130038373 | INTEGRATED CIRCUIT DEVICE, CALIBRATION MODULE, AND METHOD THEREFOR - An integrated circuit device comprising at least one calibration module for calibrating an impedance of at least one on-die interconnect line driver in order to adaptively match an impedance between the at least one on-die interconnect line driver and at least one on-die interconnect line conjugated thereto. The at least one calibration module is arranged to receive an indication of an output signal of the at least one line driver, compare the received indication of an output signal to a reference signal and detect a presence or an absence of a voltage overshoot of the output signal of the at least one line driver, and upon detection of a presence or an absence of a voltage overshoot of the output signal of the at least one line driver, cause the adjustment of power supply of the at least one line driver, to be decreased or increased correspondingly. | 2013-02-14 |
20130038374 | BUFFER CIRCUIT WITH REGULATING FUNCTION AND REGULATING CIRCUIT THEREOF - A regulating circuit is used with a buffer circuit. The buffer circuit at least includes a metal-oxide-semiconductor transistor and a voltage output terminal. The voltage output terminal is connected to a drain terminal of the metal-oxide-semiconductor transistor of the buffer circuit. The regulating circuit includes a first metal-oxide-semiconductor transistor and a second metal-oxide-semiconductor transistor. The first metal-oxide-semiconductor transistor has a source terminal and a drain terminal connected to a voltage source and a connecting node, respectively. The connecting node is electrically connected to a substrate of the metal-oxide-semiconductor transistor of the buffer circuit. The second metal-oxide-semiconductor transistor has a drain terminal and a source terminal connected to the connecting node and the voltage output terminal, respectively. A substrate of the second metal-oxide-semiconductor transistor is electrically connected to the connecting node. | 2013-02-14 |
20130038375 | VOLTAGE LEVEL SHIFTER - A circuit includes a power switch and a level shifter. The level shifter has a node and an assistant circuit. The node is configured to control the power switch. The assistant circuitry is coupled to the node and configured for the node to receive a first voltage value through the assistant circuit. The first voltage value is different from a second voltage value of an input signal received by the level shifter. | 2013-02-14 |
20130038376 | Frequency Tunable Signal Source - A frequency tunable signal source ( | 2013-02-14 |
20130038377 | POOLED-RESOURCE ARCHITECTURE WITH ASYNCHRONOUS PACKET-BASED COMMUNICATION - A chip includes a pool of blocks. Each block is adapted to implement a communication protocol. A cross-connect configurably connects between the blocks. A configured connection through the cross-connect between a sending block and a receiving block includes a lane with a toggle line and multiple data lines. The receiving block uses the toggle line to determine when valid data is on the data lines. The sending block and receiving block are on different clock domains. | 2013-02-14 |
20130038378 | Touch Sensing With A Common Driver - In one embodiment, an apparatus includes a touch sensor including drive electrodes. The apparatus also includes sense electrodes arranged along a first axis and a second axis. The first and second axes are substantially perpendicular to each other. The apparatus also includes one or more computer-readable non-transitory storage media coupled to the touch sensor that embody logic that drives all the drive electrodes substantially simultaneously with a common drive signal. | 2013-02-14 |
20130038379 | MICRO STRUCTURE SUBSTRATES FOR SENSOR PANELS - A sensor panel comprises a flexible film of a thickness having a first surface and a second surface spaced apart from the first surface by the thickness of the film; an array of micro structures in the flexible film, each micro structure including a chamber formed into the flexible film from the first surface; and an array of sensors on the second surface for generating current induced by static electric charge. | 2013-02-14 |
20130038380 | IIMPLEMENTING CHIP TO CHIP CALIBRATION WITHIN A TSV STACK - A method and circuit for implementing a chip to chip calibration in a chip stack, for example, with through silicon vias (TSV) stack, and a design structure on which the subject circuit resides are provided. A first chip and a second chip are included within a semiconductor chip stack. The semiconductor chip stack includes a vertical stack optionally provided with Though Silicon Via (TSV) stacking of the chips. At least one of the first chip and the second chip includes a calibration control circuit and a performance indicator circuit coupled to the calibration control circuit to train and calibrate at least one of the first chip and the second chip to provide enhanced performance and reliability for the semiconductor chip stack. | 2013-02-14 |
20130038381 | Charge Pump Systems with Reduction in Inefficiencies Due to Charge Sharing Between Capacitances - Improvements in the efficiency of two charge pump designs are presented. As a charge pump switches between modes, capacitances are charged. Due to charge sharing between capacitances, inefficiencies are introduced. Techniques for reducing these inefficiencies are presented for two different charge pump designs are presented. For a clock voltage doubler type of pump, a four phase clock scheme is introduced to pre-charge the output nodes of the pump's legs. For a pump design where a set of capacitances are connected in series to supply the output during the charging phase, one or more pre-charging phases are introduced after the reset phase, but before the charging phase. In this pre-charge phase, the bottom plate of a capacitor is set to the high voltage level prior to being connected to the top plate of the preceding capacitor in the series. | 2013-02-14 |
20130038382 | ADJUSTABLE BODY BIAS CIRCUIT - Body biasing circuit and methods are implemented in a variety of different instances. One such instance involves placing, a first well of a first body bias island and a second well of a second body bias island in a first bias mode by controlling switches of a body bias switch circuit. The biasing is one of a reverse body bias, a nominal body bias and a forward body bias. The second well is also biased according to one of a reverse body bias, a nominal body bias and a forward body bias. In response to the bias-mode input, the first well of the first body bias island and the second well of the second body bias island are each placed in a second bias mode by controlling switches of the body bias switch circuit. The bias of the first well and second well can be changed. | 2013-02-14 |
20130038383 | PIEZOELECTRIC ELECTROMECHANICAL DEVICES - An piezoelectric electromechanical transistor has first and second terminals formed in a semiconductor region, a gate and a piezoelectric region between the gate and the semiconductor region. The piezoelectric region may be configured to drive the semiconductor region to vibrate in response to a signal applied to the gate. The transistor may be configured to produce a signal at the first terminal at least partially based on vibration of the semiconductor region. | 2013-02-14 |
20130038384 | CANCELING THIRD ORDER NON-LINEARITY IN CURRENT MIRROR-BASED CIRCUITS - A current mirror circuit is described. The current mirror circuit includes a first transistor and a second transistor. The gates of the first transistor and the second transistor are coupled at a bias voltage. The current mirror circuit also includes an auxiliary transistor that is biased into weak inversion by receiving the bias voltage at a gate of the auxiliary transistor after being reduced by an offset voltage. The sources of the first transistor, second transistor and auxiliary transistor are coupled together. A primary current from the drain of the second transistor is combined with an auxiliary current from the drain of the auxiliary transistor to produce an output current. | 2013-02-14 |
20130038385 | SEMICONDUCTOR DEVICE AND VOLTAGE DIVIDER - A semiconductor device includes first and second resistors. The first resistor is formed in a first substrate region and coupled between a first node and an output node. The second resistor is formed in a second substrate region and coupled between the output node and a second node. The first substrate region is coupled to the first node which has a first voltage. The second node has a second voltage. The second substrate region is coupled to a voltage dividing node that is set in the first resistor. | 2013-02-14 |
20130038386 | DIFFERENTIAL TRANSMISSION CIRCUIT - A differential transmission circuit comprises a sending unit that generates a pair of differential signals from an input signal, and sends the differential signals; a receiver that receives the differential signals sent by the sending unit; and a transmission path that transmits the differential signals from the sending unit to the receiver, wherein the sending unit has a selector that selects one of the input signal and a signal obtained by inverting a polarity of the input signal, and generates the differential signals from the signal selected by the selector. | 2013-02-14 |
20130038387 | Detector Circuit - A detector circuit can be used for determining the reflection coefficients of HF signals in a signal path. The detector circuit includes a bidirectional hybrid coupler, logarithmic amplifiers connected to the hybrid couple, and a subtractor having an offset connection. | 2013-02-14 |
20130038388 | AUTO-ZERO AMPLIFIER AND SENSOR MODULE USING SAME - An auto-zero amplifier is disclosed, having an amplifying circuit, a switch, and a difference signal generating circuit. The amplifying circuit receives a first input signal for generating a first output signal, and receives a second input signal for generating a second output signal. The switch is coupled between the amplifying circuit and a capacitor. The switch is conducted for charging or discharging the capacitor to a voltage with the first output signal, and the switch is not conducted for keeping the capacitor at the voltage. The difference signal generating circuit is coupled with the amplifying circuit and the capacitor for generating a difference signal of the first output signal and the second output signal, a multiple of the difference signal, a part of the difference signal, and/or a digital output value for the difference signal. | 2013-02-14 |
20130038389 | Systems and Methods of RF Power Transmission, Modulation, and Amplification, Including Embodiments for Compensating for Waveform Distortion - Methods and systems for vector combining power amplification are disclosed herein. In one embodiment, a plurality of signals are individually amplified, then summed to form a desired time-varying complex envelope signal. Phase and/or frequency characteristics of one or more of the signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time-varying complex envelope signal. In another embodiment, a time-varying complex envelope signal is decomposed into a plurality of constant envelope constituent signals. The constituent signals are amplified equally or substantially equally, and then summed to construct an amplified version of the original time-varying envelope signal. Embodiments also perform frequency up-conversion. | 2013-02-14 |
20130038390 | ATOMIC LAYER DEPOSITION ENCAPSULATION FOR POWER AMPLIFIERS IN RF CIRCUITS - Power amplifiers and methods of coating a protective film of alumina (Al | 2013-02-14 |
20130038391 | METHOD AND APPARATUS FOR REDUCING DISTORTION IN CLASS D AMPLIFIER - Provided are apparatuses and methods for reducing nonlinear distortions in Class D amplifiers by dynamically changing first and second threshold voltages in a pulse width modulator. A Class D amplifier apparatus is disclosed, comprising a pulse width modulator whose operation relies on a first and second threshold value, and a threshold controller which varies the thresholds in response to internal signals in the amplifier. Further, a method of processing Class D amplifier internal signals is disclosed, comprising steps involving measuring internal signals in a Class D amplifier and varying threshold signals in response to those measurements within the amplifier. | 2013-02-14 |
20130038392 | POWER SUPPLY METHOD AND APPARATUS - A method and apparatus for providing a power supply for an amplifier is provided. The power conversion is achieved using synchronous rectifiers in a regulated half bridge power supply, taking the sum of the positive and negative rails as feedback, in order facilitate energy transfer between positive and negative output rails. This minimizes the effects of off side charging and rail sag, as well as achieving good line regulation, while allowing use of very small, low value output capacitors. | 2013-02-14 |
20130038393 | AMPLIFIER CIRCUIT, INTEGRATING CIRCUIT, AND LIGHT-DETECTION DEVICE - A photodetecting device | 2013-02-14 |
20130038394 | OPERATIONAL AMPLIFIER - The present invention relates to an operational amplifier comprising an input-stage circuit, a floating current mirror circuit, and an output-stage circuit. The input-stage circuit receives an input signal and produces a control signal. The floating current mirror circuit is coupled to the input-stage circuit, and produces a mirror current according to the control signal. The output-stage circuit is coupled to the floating current mirror circuit, and produces a driving signal according to the mirror current. When the operational amplifier is operating in the static mode, the output-stage circuit further produces a static current according to the mirror current. Thereby, by using the floating current mirror circuit, the purpose of low power consumption can be achieved while driving to the high-voltage mode or to the low-voltage mode. | 2013-02-14 |
20130038395 | POWER AMPLIFYING CIRCUIT - A power amplifying circuit includes first and second operational amplifiers. The power amplifying circuit includes first to fourth feedback resistor. The power amplifying circuit includes a fully differential operational amplifier that is connected to the output terminal of the first operational amplifier at a non-inverting input terminal thereof, to the output terminal of the second operational amplifier at an inverting input terminal thereof, to a first signal output terminal at a non-inverting output terminal thereof, and to a second signal output terminal at an inverting output terminal thereof and maintains a constant differential gain. The power amplifying circuit includes a switching circuit. The power amplifying circuit includes first and second input resistors. The power amplifying circuit includes a midpoint potential controlling circuit that monitors a power supply voltage and controls the switching circuit. | 2013-02-14 |
20130038396 | RADIO FREQUENCY AMPLIFIER IN COMMUNICATION SYSTEM AND METHOD OF CONTROLLING THE SAME - A Radio Frequency (RF) amplifier in a communication system and a method for controlling the RF amplifier are provided. The RF amplifier includes an input unit for receiving an RF signal, a cascode unit for amplifying the RF signal according to a gain of the RF amplifier and for outputting the amplified RF signal, a load unit connected to the cascode unit, and a gain controller for controlling the gain by converting an impedance in a baseband to an impedance viewed from an RF band, the gain controller being connected in parallel to the load unit. | 2013-02-14 |
20130038397 | OSCILLATION DEVICE - An oscillation device for reducing memory capacity includes a frequency difference detecting unit and a compensation value obtaining unit. When oscillation frequencies of the first and second oscillation circuits are respectively f | 2013-02-14 |
20130038398 | ATOMIC OSCILLATOR - An atomic oscillator includes an atom that generates interaction with first and second lights in accordance with an energy level of a three-level system; and a light source that emits the first light having a first plurality of lights of a first plurality of frequency components different from each other and the second light having a second plurality of lights of a second plurality of frequency components different from each other, wherein when the first and second lights are irradiated to the atom, an electromagnetically induced transparency phenomenon occurs in accordance with one of the first plurality of lights and one of the second plurality of lights. | 2013-02-14 |
20130038399 | OSCILLATION CIRCUIT AND ASSOCIATED METHOD - An oscillation circuit and associated method, wherein the oscillation circuit provides a pair of oscillation signals at two oscillation nodes, and includes a first capacitor, a switch circuit and a second capacitor serially coupled between the two oscillation nodes; the switch circuit conducts between the first capacitor and the second capacitor on an enable voltage higher than a power voltage of the oscillation circuit. | 2013-02-14 |
20130038400 | TEMPERATURE-COMPENSATED CRYSTAL OSCILLATOR - A temperature-compensated crystal oscillator includes a crystal resonator; and an oscillator circuit for performing temperature compensation. The oscillator circuit has a temperature sensor unit that measures an ambient temperature of the crystal resonator, a temperature compensation unit that outputs a first voltage for temperature compensation based on the measured temperature, a high-temperature load capacitance adjustment unit that outputs a second voltage for temperature compensation based on the temperature measured in a high temperature area exceeding a particular temperature range, an oscillator unit having first and second variable capacitance elements used for temperature compensation within a particular temperature range, third and fourth variable capacitance elements used for temperature compensation in the high temperature area, and an oscillation integrated circuit (IC) connected to the crystal resonator to perform an oscillation operation, and a buffer that amplifies the output from the oscillator unit. | 2013-02-14 |
20130038401 | RADAR SYSTEM INCLUDING BALUN - A balun includes a first port connected with a port connection part, a second port connected with the port connection part at a point separated by λ | 2013-02-14 |
20130038402 | WIRELESS POWER COMPONENT SELECTION - A method includes providing a source resonator including a first conductive loop in parallel with a first capacitive element and in series with a first adjustable element the source resonator having a source target impedance, providing a plurality of device resonators each including a conductive loop and having a device target impedance, connecting, for each of the plurality of device resonators, a resistor corresponding to the device target impedance in series with the conductive loop of each of the plurality of device resonators, connecting a network analyzer in series with the first conductive loop and adjusting at least one of the first capacitive element and the first adjustable element until a measured impedance of the source resonator is within a predetermined range of the source target impedance. | 2013-02-14 |
20130038403 | DIFFERENTIAL COUPLER - A distributed differential coupler, including a first conductive line and two second conductive lines coupled to the first one, each second conductive line including two conductive sections electrically in series, their respective junctions points being intended to be grounded. | 2013-02-14 |
20130038404 | Duplex Filter with Recessed Top Pattern and Cavity - A duplex filter includes a block of dielectric material with top, bottom, and side surfaces and first and second spaced-apart sets of through-holes. A pair of outside walls and a center wall extend outwardly from the top surface. A pattern of metallized areas is defined on the top surface of the block including first and second electrodes that extend on the pair of outside walls respectively and third and fourth electrode antennae that extend on the center wall. The block may be two separate blocks coupled together to form an interior layer of metallization separating the first and second sets of through-holes and the center wall separates respective transmit and receive portions of the pattern of metallized areas. | 2013-02-14 |
20130038405 | ACOUSTIC WAVE DEVICE - An acoustic wave device includes: a substrate; a lower electrode formed on the substrate; at least two piezoelectric films formed on the lower electrode; an insulating film located between the at least two piezoelectric films; and an upper electrode formed on the at least two piezoelectric films, wherein an outer periphery of an uppermost piezoelectric film out of the at least two piezoelectric films in a region in which the lower electrode and the upper electrode face each other is positioned further in than an outer periphery of the upper electrode. | 2013-02-14 |
20130038406 | CIRCUIT MODULE - A circuit module includes a duplexer and a circuit substrate. A first signal path connects a first external electrode to a second external electrode. A second signal path connects a third external electrode to a fourth external electrode. A third signal path connects a fifth external electrode to a sixth external electrode. A first ground path connects a seventh external electrode to an eighth external electrode. A second ground path is connected to a ninth external electrode and is capacitively coupled to the second signal path. | 2013-02-14 |
20130038407 | WAVEGUIDE E-PLANE FILTER STRUCTURE - A waveguide E-plane filter component comprising a first main part and a second main part which in turn comprise a corresponding first and second waveguide section part. The main parts are arranged to be mounted to each other, each waveguide section part comprising a bottom wall, corresponding side walls and an open side, where the open sides are arranged to face each other. The waveguide E-plane filter component further comprises at least one electrically conducting foil that is arranged to be placed between the main parts, said foil comprising a filter part that is arranged to run between the waveguide section parts, the filter part comprising apertures, in said foil. | 2013-02-14 |
20130038408 | BULK ACOUSTIC WAVE RESONATOR DEVICE COMPRISING AN ACOUSTIC REFLECTOR AND A BRIDGE - A bulk acoustic wave (BAW) resonator device includes an acoustic reflector formed over a substrate and a resonator stack formed over the acoustic reflector. The acoustic reflector includes multiple acoustic impedance layers. The resonator stack includes a first electrode formed over the acoustic reflector, a piezoelectric layer formed over the first electrode, and a second electrode formed over the piezoelectric layer. A bridge is formed within one of the acoustic reflector and the resonator stack. | 2013-02-14 |
20130038409 | TECHNIQUES FOR DEVELOPING A NEGATIVE IMPEDANCE - Techniques to develop negative impedance circuits that may operate to their power supply rails. The techniques may include generating currents in response to voltage signals presented at respective input terminals of a negative impedance circuit. The voltage signals may be differential signals. The generated currents may be driven through a common impedance within the negative impedance circuit. The currents flowing through the common impedance may be mirrored back to the input terminals of the negative impedance circuit. The negative impedance circuit may be controlled to operate about a common-mode voltage for the circuit. | 2013-02-14 |
20130038410 | Thermally Conductive Stripline RF Transmission Cable - A thermally conductive stripline RF transmission cable has a flat inner conductor surrounded by a dielectric layer that is surrounded by an outer conductor. The dielectric layer may include a base polymer and a thermally conductive material to increase a thermal conductivity of the cable. A thermal conductivity of the dielectric layer may be increased between a midsection of the inner conductor and the outer conductor. A jacket may surround the outer conductor, the jacket including a base polymer and a thermally conductive material. Additional conductors may be applied within the dielectric layer and/or in the jacket, proximate the outer conductor. | 2013-02-14 |
20130038411 | Self-Supporting Stripline RF Transmission Cable - A stripline RF transmission cable has a flat inner conductor surrounded by a dielectric layer that is surrounded by an outer conductor. A jacket with an attachment feature surrounds the outer conductor. The attachment feature may be a fin aligned parallel or normal to the inner conductor. The attachment feature may be continuous or periodic along a longitudinal extent of the cable. The attachment feature may include male and female portions dimensioned to couple with one another, enabling adjacent cables to be attached to one another. | 2013-02-14 |
20130038412 | Corrugated Stripline RF Transmission Cable - A stripline RF transmission cable has a generally planar inner conductor surrounded by a dielectric layer that is surrounded by a corrugated outer conductor. The corrugations may be, for example, annular or helical. The outer conductor has a top section and a bottom section which transition to a pair of edge sections that interconnect the top section with the bottom section. The top section, bottom section and the inner conductor may be provided with generally equal widths. A spacing between the inner conductor and the dielectric layer may be reduced proximate a mid section of the inner conductor. The inner conductor may also be corrugated generally normal to a longitudinal extend of the inner conductor. | 2013-02-14 |
20130038413 | TRANSMISSION LINE AND ELECTRICAL APPARATUS USING THE SAME - A transmission line with a structure which is capable of forming a passive equalizer and an electrical apparatus using the same are illustrated. The transmission line has a substrate, a ground plane, a defect ground structure, a pair of transmission conducting lines, and at least one stub. The substrate has a plurality of surfaces. The ground plane is located on at least one of the surfaces. The defect ground structure is formed on the ground plane. The pair of transmission conducting lines is located on one of the surfaces, and stretching over the defect ground structure. The at least one stub is located above a plane of the defect ground structure, extending along with at least one side of two sides of the pair of the transmission conducting lines, and electrically coupled to the pair of the transmission conducting lines and the ground plane. | 2013-02-14 |
20130038414 | ACTUATOR DEVICE AND PROCESS FOR PRODUCING AN ACTUATOR DEVICE - Actuator device having an expansion unit, which includes a magnetic shape memory alloy material, and a spring unit which interacts therewith in a restoring manner, wherein at least one spring of the spring unit is assigned to the expansion unit, which is designed to perform an expansion movement along an expansion direction, in such a way that the spring can exert a restoring spring force counter to the expansion direction on the expansion unit, and wherein the spring is set up and/or predetermined in its spring characteristic curve properties in such a way that a spring force profile of the spring unit along a stroke range, determined by an expansion force profile of the expansion unit and a restoring spring force profile, of the expansion movement does not form a continuously rising curve, and/or the spring force profile, with respect to a continuously rising curve, extends and/or increases the stroke range. | 2013-02-14 |
20130038415 | REACTOR - A reactor including an assembly of a coil, a magnetic core on which the coil is disposed, and a case that houses the assembly. The case includes an installation face, a side wall that is removably attached to the installation face and surrounds the periphery of the assembly, and a heat dissipation layer formed on the inner face of the installation face and interposed between the installation face and the installation-side face of the coil. The installation face consists of aluminum, the side wall consists of an insulating resin, and the heat dissipation layer consists of an adhesive with high thermal conductivity and excellent insulation. The installation face is separate from the side wall, making it easy to form the heat dissipation layer, and having excellent heat dissipation. The side wall consists of an insulating resin, thus reducing the gap between it and the coil. | 2013-02-14 |
20130038416 | LAMINATED INDUCTOR AND MANUFACTURING METHOD THEREOF - Provided is a laminated inductor having a magnetic body, a conductor part covered in a manner directly contacting the magnetic body, and external terminals provided on the outside of the magnetic body and conducting to the conductor part; wherein the magnetic body is a laminate constituted by layers containing soft magnetic alloy grains, and the soft magnetic alloy grain contacting the conductor part is flattened on the conductor part side. | 2013-02-14 |
20130038417 | COIL COMPONENT AND MANUFACTURING METHOD THEREOF - There are provided a coil component and a manufacturing method thereof which secure coupling force between a coil and a substrate. The coil component includes: a substrate unit including a first substrate layer, an insulating layer stacked on the first substrate, and a second substrate layer stacked on the insulating layer; and coil layers each interposed between the first substrate layer and the insulating layer and between the insulating layer and the second substrate layer. | 2013-02-14 |
20130038418 | CONTACTLESS COMMUNICATIONS USING FERROMAGNETIC MATERIAL - A communications structure comprises a first semiconductor substrate having a first coil, and a second semiconductor substrate having a second coil above the first semiconductor substrate. Inner edges of the first and second coils define a boundary of a volume that extends below the first coil and above the second coil. A ferromagnetic core is positioned at least partially within the boundary, such that a mutual inductance is provided between the first and second coils for wireless transmission of signals or power between the first and second coils. | 2013-02-14 |
20130038419 | LAMINATED INDUCTOR - A laminated inductor having a laminate structure constituted by magnetic layers and internal conductive wire-forming layers, wherein the magnetic layer is formed by soft magnetic alloy grains, the internal conductive wire-forming layer has an internal conductive wire and a reverse pattern portion around it, and the reverse pattern portion is formed by soft magnetic alloy grains whose constituent elements are of the same types as those of, and whose average grain size is greater than that of, the soft magnetic alloy grains constituting the magnetic layer. | 2013-02-14 |
20130038420 | GREEN COMPACT, METHOD OF MANUFACTURING THE SAME, AND CORE FOR REACTOR - Provided are a green compact from which a low-loss core can be formed, a method of manufacturing the green compact, and a core for a reactor using the green compact. Parts of outer circumferential surfaces of green compacts | 2013-02-14 |
20130038421 | MAGNETIC DETECTOR AND METHOD FOR MANUFACTURING THE SAME - A first short-circuit layer and a second short-circuit layer are electrically connected to and integrally stacked onto only a first magnetoresistance effect element layer and a first resistance element layer, respectively, so as to achieve short-circuiting, and thereby adjusting electrical resistances of the first magnetoresistance effect element layer and the first resistance element layer. | 2013-02-14 |
20130038422 | METHOD AND SYSTEM OF REDUCING THE TEMPERATURE OF AN INTEGRATED CIRCUIT AND A DIGITAL COMMUNICATION SYSTEM USING SAME - A method and system for reducing the temperature of a communication system are disclosed. The method and system comprise detecting a temperature of the communication system. The method and system further includes providing a signal based upon the detected temperature, and determining a desired idle time between transmit packets based upon the signal. Finally, the method and system includes sending the desired idle time between transmit packets to the communication system. | 2013-02-14 |
20130038423 | Security Barrier with Emergency Release Mechanism - In certain embodiments, a system includes a security barrier attached to a structure such that the security barrier is operable to move from a first position, in which the security barrier blocks an exterior opening of the structure, to a second position, in which the security barrier does not block the exterior opening of the structure. The system further includes a latch mechanism operable to control movement of the security barrier from the first position to the second position and a sensor operable to generate an emergency signal indicating an emergency condition within the structure. The system further includes a control unit operable to access the emergency signal generated by the sensor and generate, in response to the emergency signal, a release signal to be communicated to the latch mechanism. The release signal is operable to cause the latch mechanism to permit the security barrier to move from the first position to the second position. | 2013-02-14 |