07th week of 2019 patent applcation highlights part 60 |
Patent application number | Title | Published |
20190051610 | STAIRCASE ETCH CONTROL IN FORMING THREE-DIMENSIONAL MEMORY DEVICE - Embodiments of three-dimensional (3D) memory devices and methods for controlling a photoresist (PR) trimming rate in the formation of the 3D memory devices are disclosed. In an example, a method includes forming a dielectric stack over a substrate, measuring a first distance between the first trimming mark and the PR layer along a first direction, and trimming the PR layer along the first direction. The method also includes etching the dielectric stack using the trimmed PR layer as an etch mask to form a staircase, forming a second trimming mark using the first trimming mark as an etch mask, measuring a second distance between the second trimming mark and the trimmed PR layer, comparing the first distance with the second distance to determine a difference between an actual PR trimming rate and an estimated PR trimming rate, and adjusting PR trimming parameters based on the difference. | 2019-02-14 |
20190051611 | SEMICONDUCTOR PACKAGE BLOCKING ELECTROMAGNETIC INTERFERENCE AND ELECTRONIC SYSTEM HAVING THE SAME - A semiconductor package includes a substrate, semiconductor chips disposed on the substrate, and a ground pad disposed on or in the substrate and adjacent to any one or any combination of the semiconductor chips. The semiconductor package further includes an encapsulant disposed to seal an upper portion of the substrate, the semiconductor chips, and the ground pad, a trench disposed through the encapsulant to the ground pad, to isolate the semiconductor chips, and an electromagnetic interference (EMI) shielding film disposed to cover a surface of the encapsulant and the trench, the EMI shielding film including an adhesive resin, and the EMI shielding film being electrically connected to the ground pad. | 2019-02-14 |
20190051612 | SEMICONDUCTOR PACKAGES - A semiconductor package including a heat spreading layer having at least one hole, a first semiconductor chip below the heat spreading layer, a redistribution structure below the first semiconductor chip, a first mold layer between the heat spreading layer and the redistribution structure, a shielding wall extending from the redistribution structure and the heat spreading layer and surrounding the first semiconductor chip, and a first conductive pillar extending from the redistribution structure into the hole may be provided. | 2019-02-14 |
20190051613 | MULTILAYER FRAME PACKAGES FOR INTEGRATED CIRCUITS HAVING A MAGNETIC SHIELD INTEGRATED THEREIN, AND METHODS THEREFOR - An integrated circuit package may comprise a multilayer frame package including: a bottom layer; and a magnetic shield layer, including a sub-frame and a magnetic shield disposed within a periphery of the sub-frame; and an integrated circuit die provided on or above the magnetic shield layer of the multilayer frame package. | 2019-02-14 |
20190051614 | SEMICONDUCTOR PACKAGES WITH ELECTROMAGNETIC INTERFERENCE SHIELDING - Semiconductor packages having an electromagnetic interference (EMI) shielding layer and methods for forming the same are disclosed. The method includes providing a base carrier defined with an active region and a non-active region. A fan-out redistribution structure is formed over the base carrier. A die having elongated die contacts are provided. The die contacts corresponding to conductive pillars. The die contacts are in electrical communication with the fan-out redistribution structure. An encapsulant having a first major surface and a second major surface opposite to the first major surface is formed. The encapsulant surrounds the die contacts and sidewalls of the die. An electromagnetic interference (EMI) shielding layer is formed to line the first major surface and sides of the encapsulant. An etch process is performed after forming the EMI shielding layer to completely remove the base carrier and singulate the semiconductor package. | 2019-02-14 |
20190051615 | SYSTEMS, METHODS, AND APPARATUSES FOR IMPLEMENTING AN ORGANIC STIFFENER WITH AN EMI SHIELD FOR RF INTEGRATION - In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing an organic stiffener with an EMI shield for RF integration. For instance, in accordance with one embodiment, there is an apparatus having therein: a substrate layer having electrical traces and a ground plane therein; a functional semiconductor die electrically interfaced to the electrical traces of the substrate layer; a heat pipe thermally interfaced to a top surface of the functional semiconductor die; one or more interposers of an organic dielectric material electrically connected to the ground plane of the substrate layer and electrically connected to the heat pipe; in which the one or more interposers form the electromagnetic shield to electrically shield the functional semiconductor die; and further in which the one or more interposers form the organic stiffener are to mechanically retain the substrate layer in a planer form. Other related embodiments are disclosed. | 2019-02-14 |
20190051616 | SEMICONDUCTOR DEVICE HAVING CONDUCTIVE WIRE WITH INCREASED ATTACHMENT ANGLE AND METHOD - A semiconductor device includes a shielding wire formed across a semiconductor die and an auxiliary wire supporting the shielding wire, thereby reducing the size of a package while shielding the electromagnetic interference generated from the semiconductor die. In one embodiment, the semiconductor device includes a substrate having at least one circuit device mounted thereon, a semiconductor die spaced apart from the circuit device and mounted on the substrate, a shielding wire spaced apart from the semiconductor die and formed across the semiconductor die, and an auxiliary wire supporting the shielding wire under the shielding wire and formed to be perpendicular to the shielding wire. In another embodiment, a bump structure is used to support the shielding wire. In a further embodiment, an auxiliary wire includes a bump structure portion and wire portion and both the bump structure portion and the wire portion are used to support the shielding wire. | 2019-02-14 |
20190051617 | DIE-ATTACH METHOD TO COMPENSATE FOR THERMAL EXPANSION - In sonic examples, a method includes pre-stressing a flange, heating the flange to a die-attach temperature, and attaching a die to the flange at the die-attach temperature using a die-attach material. In some examples, the flange includes a metal material, the die-attach temperature may be at least two hundred degrees Celsius, and the die-attach material may include solder and/or an adhesive. In some examples, the method includes cooling the semiconductor die and metal flange to a room temperature after attaching the semiconductor die to the metal flange at the die-attach temperature using a die-attach material. | 2019-02-14 |
20190051618 | LAMINATING DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE USING THE SAME - A method of fabricating a semiconductor package using a laminating device is provided. The method includes placing a substrate on a substrate stand; providing a pressurizing unit which is expandable and includes a convex surface facing an upper surface of the substrate stand, on the substrate stand; injecting air into the pressurizing unit using a plate which is connected to the pressurizing unit; and supplying a film by a film supply unit which supplies the film between the substrate stand and the pressurizing unit, wherein the pressurizing unit attaches the film onto the substrate, while expanding. | 2019-02-14 |
20190051619 | FAN-OUT SEMICONDUCTOR PACKAGE - A fan-out semiconductor package includes: a semiconductor chip; a first connection member including a plurality of redistribution layers and one or more layer of vias; an encapsulant; and a second connection member, wherein the encapsulant has first openings exposing at least portions of the first connection member, the first connection member has second openings exposing at least portions of a redistribution layer disposed at an uppermost portion among the plurality of redistribution layers, at least portions of the first openings and the second openings overlap each other, and a content of a metal constituting the plurality of redistribution layers and the one or more layer of vias is higher in a lower portion of the first connection member than in an upper portion of the first connection member. | 2019-02-14 |
20190051620 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE - A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer. | 2019-02-14 |
20190051621 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a substrate, a die disposed over a first surface of the substrate, a RDL disposed over a second surface of the substrate, a conductive structure disposed within the RDL. The conductive structure is configured as a seal ring protecting the RDL and the substrate from damages caused by cracks, chippings or other contaminants during fabrication or singulation. As such, delamination of components or damages on the semiconductor structure during fabrication or singulation can be minimized or prevented. | 2019-02-14 |
20190051622 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a die, a molding surrounding the die, an interconnect structure disposed over the die and the molding, and a first seal ring. The interconnect structure includes a dielectric layer and a conductive member disposed within the dielectric layer. The first seal ring is disposed within the dielectric layer and disposed over the molding. | 2019-02-14 |
20190051623 | SEMICONDUCTOR DEVICES HAVING DISCRETELY LOCATED PASSIVATION MATERIAL, AND ASSOCIATED SYSTEMS AND METHODS - Semiconductor devices having discretely located passivation material are disclosed herein. In one embodiment, a semiconductor device assembly can include a bond pad having a bonding surface with a process artifact. A passivation material can be positioned to at least partially fill a portion of the process artifact. A conductive structure can be positioned to extend across the bonding surface of the bond pad. | 2019-02-14 |
20190051624 | Solder Metallization Stack and Methods of Formation Thereof - A semiconductor device includes a contact metal layer disposed over a semiconductor surface of a substrate, a diffusion barrier layer disposed over the contact metal layer, an inert layer disposed over the diffusion barrier layer, and a solder layer disposed over inert layer. | 2019-02-14 |
20190051625 | SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a redistribution structure, at least one package structure and a second encapsulant. The redistribution structure has a first surface and a second surface opposite to the first surface. The package structure is over the first surface and includes at least one die, a first encapsulant, a redistribution layer, and a plurality of second conductive terminals. The die has a plurality of first conductive terminals thereon. The first encapsulant encapsulates the die and exposes at least part of the first conductive terminals. The redistribution layer is over the first encapsulant and is electrically connected to the first conductive terminals. The second conductive terminals are electrically connected between the redistribution layer and the redistribution structure. The second encapsulant, encapsulates the package structure and exposes at least part of the second conductive terminals. | 2019-02-14 |
20190051626 | MANUFACTURING METHOD OF CHIP PACKAGE STRUCTURE - A manufacturing method of a chip package structure includes: dicing a wafer to separate chips formed thereon; mounting the chips on a carrier, wherein an active surface and pads of each chip are buried in an adhesive layer disposed on the carrier, and a top surface of the adhesive layer between the chips is bulged away from the carrier; forming an encapsulant to encapsulate the chips and cover the adhesive layer, wherein the encapsulant has a concave surface covering the top surface of the adhesive layer and a back surface opposite to the concave surface; removing the carrier and the adhesive layer; forming a first dielectric layer to cover the concave surface and the active surface; forming a patterned circuit layer on the first dielectric layer, to electrically connect to the pads through openings in the first dielectric layer; and forming a second dielectric layer on the patterned circuit layer. | 2019-02-14 |
20190051627 | WIRE BOND CONNECTION WITH INTERMEDIATE CONTACT STRUCTURE - Techniques and mechanisms for provide interconnection with integrated circuitry. In an embodiment, a packaged device includes a substrate and one or more integrated circuit (IC) dies. A first conductive pad is formed at a first side of a first IC die, and a second conductive pad is formed at a second side of the substrate or another IC die. Wire bonding couples a wire between the first conductive pad and the second conductive pad, wherein a distal end of the wire is bonded, via a bump, to an adjoining one of the first conductive pad and the second conductive pad. A harness of the bump, which is less than a hardness of the wire, mitigates damage to the adjoining pad that might otherwise occur as a result of wire bonding stresses. In another embodiment, the wire includes copper (Cu) and the bump includes gold (Au) or silver (Ag). | 2019-02-14 |
20190051628 | Hybrid Bonding Systems and Methods for Semiconductor Wafers - Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together. | 2019-02-14 |
20190051629 | METHOD OF MANUFACTURING AN ELECTRONIC DEVICE AND ELECTRONIC DEVICE MANUFACTURED THEREBY - Various aspects of this disclosure provide a method of manufacturing an electronic device and an electronic device manufactured thereby. As a non-limiting example, various aspects of this disclosure provide a method of manufacturing an electronic device, and an electronic device manufactured thereby, that utilizes ink to form an intermetallic bond between respective conductive interconnection structures of a semiconductor die and a substrate. | 2019-02-14 |
20190051630 | METHODS AND SYSTEM FOR PROCESSING SEMICONDUCTOR DEVICE STRUCTURES - Methods of detaching semiconductor device structures from carrier structures may involve directing a laser through a carrier structure comprising a semiconductor material to a barrier material located between the carrier structure and a semiconductor device structure adhere to an opposite side of the barrier material. A bond between the carrier structure and an adhesive material temporarily securing the carrier structure to the semiconductor device structure may be released in response to heating of the barrier material by the laser beam. The carrier structure may be removed from the semiconductor device structure, the barrier material removed, and an adhesive bonding the semiconductor device structure to the barrier material removed. | 2019-02-14 |
20190051631 | PACKAGE-ON-PACKAGE SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING ONE OR MORE WINDOWS AND RELATED METHODS AND PACKAGES - Semiconductor device packages for incorporation into semiconductor device assemblies may include a substrate including an array of electrically conductive elements located on a lower surface of the substrate. A window may extend through the substrate from the lower surface to an upper surface of the substrate. The array of electrically conductive elements may at least partially laterally surround a periphery of the window, and the substrate may extend laterally beyond the array of electrically conductive elements. At least a portion of a heat-management structure may be located within the window. At least a portion of an outer periphery of an underlying substrate may laterally overlap with an inner portion of the substrate defining the periphery of the window. | 2019-02-14 |
20190051632 | Fan-out wafer level multilayer wiring package structure - A fan-out wafer level multilayer wiring package structure, wherein the package structure comprises a plurality of semiconductor chips, a multilayer interposer, a vertical interconnection interposer, molding materials and a redistribution layer; the back surface of the semiconductor chip is bonded to the back surface of the multilayer wiring interposer with the bonding material, and is placed on the same horizontal plane as the vertical interconnection interposer and packaged as a whole with the molding material, the redistribution layer is provided on the surface of the structure; the semiconductor chip, the multilayer interposer, the conductive material of the vertical interconnection interproser and the solder ball are connected by the conductive metal layer of the redistribution layer to achieve the signal interconnection between the semiconductor chip and the multilayer interposer and the I/O signal transfer of the semiconductor chip. | 2019-02-14 |
20190051633 | MOLDED CHIP COMBINATION - Various molded chip combinations and methods of manufacturing the same are disclosed. In one aspect, a molded chip combination is provided that includes a first semiconductor chip that has a first PHY region, a second semiconductor chip that has a second PHY region, an interconnect chip interconnecting the first PHY region to the second PHY region, and a molding joining together the first semiconductor chip, the second semiconductor chip and the interconnect chip. | 2019-02-14 |
20190051634 | SEMICONDUCTOR PACKAGES - A semiconductor package includes a substrate including a signal pattern on an upper surface thereof, a chip stack on the substrate, and a first semiconductor chip and one or more spacers between the substrate and the chip stack. The chip stack includes one or more second semiconductor chips stacked on the substrate. The one or more spacers and the first semiconductor chip are adjacent to respective corners of a lowermost second semiconductor chip, in plan view. The one or more spacers have the same planar shape as the first semiconductor chip. | 2019-02-14 |
20190051635 | CHIP PACKAGE STRUCTURE - A chip package structure is provided. The chip package structure includes a chip structure. The chip package structure includes a first ground bump below the chip structure. The chip package structure includes a conductive shielding film disposed over the chip structure and extending onto the first ground bump. The conductive shielding film is electrically connected to the first ground bump. | 2019-02-14 |
20190051636 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first and a second metal layer, the second provided on a same plane as the first layer, and first second and third terminals. A first metal wiring layer is electrically connected to the first terminal. A second metal wiring layer is electrically connected to the second terminal and the second metal layer and disposed over the first metal wiring layer. A third metal wiring layer is electrically connected to the third terminal and the first metal layer. A first semiconductor chip is provided between the first metal wiring layer and the first metal layer. A second semiconductor chip is provided between the third metal wiring layer and the second metal layer. The first chip has electrodes connected to the first metal wiring layer and the first metal layer. The second chip has electrodes connected to the third metal wiring layer and the second metal layer. | 2019-02-14 |
20190051637 | MICRO LIGHT EMITTING DIODE DEVICE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a micro light emitting diode device is provided. A plurality of first type epitaxial structures are formed on a first substrate and the first type epitaxial structures are separated from each other. A first connection layer and a first adhesive layer are configured between the first type epitaxial structures and the first substrate. The first connection layer is connected to the first type epitaxial structures. The first adhesive layer is located between the first connection layer and the first type epitaxial substrate. The Young's modulus of the first connection layer is larger than the Young's modulus of the first adhesive layer. The first connection layer located between any two adjacent first type epitaxial structures is removed so as to form a plurality of first connection portions separated from each other. Each of the first connection portions is connected to the corresponding first type epitaxial structure. | 2019-02-14 |
20190051638 | WELD JOINT WITH CONSTANT OVERLAP AREA - A packaged semiconductor device has a plurality of leads. A respective lead is to be welded to an electrical coupling that has a substantially rectangular end section. The end section has a width that is greater than a width of the respective lead. The respective lead is aligned within the width of the end section, such that the respective lead extends in a direction substantially perpendicular to the width of the end section. With the respective lead and the end section aligned, the respective lead is welded to the end section. | 2019-02-14 |
20190051639 | STICKER ELECTRONICS - Electronic stickers may be manufactured on flexible substrates as layers and packaged together. The package may then have an adhesive applied to one side to provide capability for sticking the electronic devices to surfaces. The stickers can be wrappable, placed on surfaces, glued on walls or mirrors or wood or stone, and have electronics which may or may not be ultrathin. Packaging for the electronic sticker can use polymer on cellulose manufacturing and/or three dimensional (3-D) printing. The electronic stickers may provide lighting capability, sensing capability, and/or recharging capabilities. | 2019-02-14 |
20190051640 | SEMICONDUCTOR MODULE - In a semiconductor module, first and second semiconductor chips each include a transistor and a temperature-detecting diode connected between first and second control pads. The first control pad of the first semiconductor chip is connected to a first control terminal, the second control pad of the first semiconductor chip and the first control pad of the second semiconductor chip are connected to a second control terminal, and the second control pad of the second semiconductor chip is connected to a third control terminal. | 2019-02-14 |
20190051641 | LOGIC DRIVE BASED ON STANDARDIZED COMMODITY PROGRAMMABLE LOGIC SEMICONDUCTOR IC CHIPS - A chip package includes an interposer comprising a silicon substrate, multiple metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the interposer; multiple first metal bumps between the interposer and the FPGA IC chip; a first underfill between the interposer and the FPGA IC chip, wherein the first underfill encloses the first metal bumps; a non-volatile memory (NVM) IC chip over the interposer; multiple second metal bumps between the interposer and the NVM IC chip; and a second underfill between the interposer and the NVM IC chip, wherein the second underfill encloses the second metal bumps. | 2019-02-14 |
20190051642 | MULTI-DIE PACKAGES WITH EFFICIENT MEMORY STORAGE - Methods and apparatus to implement efficient memory storage in multi-die packages are disclosed. An example multi-die package includes a multi-die stack including a first die and a second die. The second die is stacked on the first die. The multi-die package further includes a third die adjacent the multi-die stack. The multi-die package also includes a silicon-based connector to communicatively couple the multi-die stack and the third die. The silicon-based connector includes at least one of a logic circuit or a memory circuit. | 2019-02-14 |
20190051643 | PROTECTION OF AN INTEGRATED CIRCUIT - A circuit for protecting an integrated circuit against fault injection attacks includes an element including a dielectric which is destroyed, resulting in the occurrence of a short-circuit. The element is connected between two terminals that receive a power supply voltage of the integrated circuit. | 2019-02-14 |
20190051644 | ESD PROTECTION DEVICE AND SIGNAL TRANSMISSION LINE - An ESD protection device that includes a semiconductor substrate that has a first main surface, terminal electrodes formed on the first main surface, a terminal electrode that is connected to the ground, and a wiring electrode that connects the terminal electrodes to each other and that forms a part of a main line. Moreover, the semiconductor substrate has a rectangular cuboid shape in a plan view and further includes a first semiconductor region that is connected to the wiring electrode, a second semiconductor region that is connected to the third terminal electrode, and a third semiconductor region. The first semiconductor region and the second semiconductor region are arranged along short sides of the semiconductor substrate and electrically connected to each other with the third semiconductor region that extends along the short sides interposed therebetween. | 2019-02-14 |
20190051645 | SEMICONDUCTOR DEVICE - A semiconductor device includes a sub-collector layer disposed on a substrate, a bipolar transistor including a collector layer formed of a semiconductor having a lower carrier concentration than the sub-collector layer, a base layer, and an emitter layer, and a protection diode including a Schottky electrode. The Schottky electrode forms, in a partial region of an upper surface of the collector layer, a Schottky junction to the collector layer and is connected to one of the base layer and the emitter layer. In the collector layer, a part that forms a junction to the base layer and a part that forms a junction to the Schottky electrode are electrically connected to each other via the collector layer. | 2019-02-14 |
20190051646 | APPARATUSES FOR COMMUNICATION SYSTEMS TRANSCEIVER INTERFACES - An integrated circuit device for protecting circuits from transient electrical events is disclosed. An integrated circuit device includes a first bipolar junction transistor (BJT) and a second BJT cross-coupled with the first BJT to operate as a first semiconductor-controlled rectifier (SCR), where a base of the first BJT is connected to a collector of the second BJT, and a base of the second BJT is connected to an emitter or a collector of the first BJT. The integrated circuit device additionally includes a triggering device comprising a first diode having a cathode electrically connected to the base of the first BJT. The integrated circuit device further includes a third BJT cross-coupled with the second BJT to operate as a second SCR, where the third BJT has a collector connected to the base of the second BJT and a base connected to the collector of the second BJT. | 2019-02-14 |
20190051647 | Semiconductor Device and a Manufacturing Method Therefor - A semiconductor device includes a semiconductor body having first and second opposing sides, an active area, and an inactive area which is, in a projection onto to the first and/or second side, arranged between the active area and an edge of the semiconductor body. A transistor structure in the active area includes a source region adjacent the first side and forms a first pn-junction in the semiconductor body. A gate electrode insulated from the semiconductor body is arranged adjacent to the first pn-junction. A capacitor in the inactive area includes first and second conductors arranged over each other on the first side. A source contact structure arranged above the capacitor is in Ohmic connection with the source region and the first conductor. A gate contact structure is arranged above the capacitor, spaced apart from the source contact structure and in Ohmic connection with the gate electrode and the second conductor. | 2019-02-14 |
20190051648 | DIODE AND SEMICONDUCTOR DEVICE - A diode includes a first-conductivity-type barrier region disposed between a drift region and a second impurity region and having an impurity concentration higher than that of the drift region and a second-conductivity-type field extension prevention region disposed between the barrier region and the drift region. The diode also includes a trench gate disposed to extend from a second main surface of a semiconductor substrate through the second impurity region and the barrier region and reach the field extension prevention region. The trench gate has a gate electrode for applying a gate voltage. A gate electrode is applied with a parasitic gate voltage, as the gate voltage. The parasitic gate voltage has an absolute value of a potential difference with a second electrode being equal to or greater than a threshold voltage of a parasitic transistor formed of the second impurity region, the barrier region, and the field extension prevention region. | 2019-02-14 |
20190051649 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes a buffer layer formed with a semiconductor adapted to produce piezoelectric polarization, and a channel layer stacked on the buffer layer, wherein a two-dimensional hole gas, generated in the channel layer by piezoelectric polarization of the buffer layer, is used as a carrier of the channel layer. On a complementary semiconductor device, the semiconductor device described above and an n-type field effect transistor are formed on the same compound semiconductor substrate. Also, a level shift circuit is manufactured by using the semiconductor device. Further, a semiconductor device manufacturing method includes forming a compound semiconductor base portion, forming a buffer layer on the base portion, forming a channel layer on the buffer layer, forming a gate on the channel layer, and forming a drain and source with the gate therebetween on the channel layer. | 2019-02-14 |
20190051650 | SILICON PMOS WITH GALLIUM NITRIDE NMOS FOR VOLTAGE REGULATION - This disclosure pertains to a gallium nitride transistor that is formed in a trench etched into a silicon substrate. A gallium nitride layer is on the trench of the silicon substrate. A source electrode and a drain electrode reside on the gallium nitride layer. A gate electrode resides on the gallium nitride layer between the source electrode and the drain electrode. A first polarization layer resides on the gallium nitride layer between the source electrode and the gate electrode, and a second polarization layer resides on the gallium nitride layer between the gate electrode and the drain electrode. The silicon substrate can include a silicon 111 substrate. | 2019-02-14 |
20190051651 | Double Density Nonvolatile Nanotube Switch Memory Cells - Under one aspect, a non-volatile nanotube diode device includes first and second terminals; a semiconductor element including a cathode and an anode, and capable of forming a conductive pathway between the cathode and anode in response to electrical stimulus applied to the first conductive terminal; and a nanotube switching element including a nanotube fabric article in electrical communication with the semiconductive element, the nanotube fabric article disposed between and capable of forming a conductive pathway between the semiconductor element and the second terminal, wherein electrical stimuli on the first and second terminals causes a plurality of logic states. | 2019-02-14 |
20190051652 | SEMICONDUCTOR MEMORY DEVICES - Semiconductor memory devices are provided. A semiconductor memory device includes an isolation layer in a first trench and a first gate electrode portion on the isolation layer. The semiconductor memory device includes a second gate electrode portion in a second trench. In some embodiments, the second gate electrode portion is wider, in a direction, than the first gate electrode portion. Moreover, in some embodiments, an upper region of the second trench is spaced apart from the first trench by a greater distance, in the direction, than a lower region of the second trench. Related methods of forming semiconductor memory devices are also provided. | 2019-02-14 |
20190051653 | Array Of Recessed Access Gate Lines - An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods. | 2019-02-14 |
20190051654 | CONTACTS AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing contacts is provided in the present invention, which include the steps of forming a plurality of mask bars on a substrate, forming a circular mask surrounding each mask bar, wherein the circular masks connect each other and define a plurality of opening patterns collectively with the mask bars, using the mask bars and the circular masks as etch masks to perform an etch process and to transfer the opening patterns and form a plurality recesses in the substrate, and filling up the recesses with metal to form contacts. | 2019-02-14 |
20190051655 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device may include a first cell structure, a second cell structure, a pad structure, a circuit, and an opening. The pad structure may include a first stepped structure and a second stepped structure located between the first cell structure and the second cell structure. The first stepped structure may include first pads electrically connected to the first and second cell structures and stacked on top of each other, and the second stepped structure may include second pads electrically connected to the first and second cell structures and stacked on top of each other. The circuit may be located under the pad structure. The opening may pass through the pad structure to expose the circuit, and may be located between the first stepped structure and the second stepped structure to insulate the first pads and the second pads from each other. | 2019-02-14 |
20190051656 | VOID FORMATION IN CHARGE TRAP STRUCTURES - Electronic apparatus and methods of forming the electronic apparatus may include one or more charge trap structures for use in a variety of electronic systems and devices, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric on a charge trap region of the charge trap structure. In various embodiments, a void is located between the charge trap region and a region on which the charge trap structure is disposed. In various embodiments, a tunnel region separating a charge trap region from a semiconductor pillar of a charge trap structure, can be arranged such that the tunnel region and the semiconductor pillar are boundaries of a void. Additional apparatus, systems, and methods are disclosed. | 2019-02-14 |
20190051657 | APPARATUSES AND METHODS FOR READING MEMORY CELLS - Apparatuses and methods for reading memory cells are described. An example method includes sharing a first voltage to increase a voltage of a first sense line coupled to a first capacitor plate of a ferroelectric capacitor of a memory cell, sharing a second voltage to decrease a voltage of a second sense line coupled to a second capacitor plate of the ferroelectric capacitor of the memory cell, sharing a third voltage to increase the voltage of the second sense line, and sharing a fourth voltage to decrease the voltage of the first sense line. A voltage difference between the first sense line and the second sense line that results from the voltage sharing is amplified, wherein the voltage difference is based at least in part on a polarity of the ferroelectric capacitor. | 2019-02-14 |
20190051658 | MEMORY DEVICE - A memory device may be provided that includes: a substrate; a coupling layer which is located on the substrate and has electrical conductivity; a meta-atomic layer which is located on or under the coupling layer; a memory layer which is located on the meta-atomic layer; and an electrode layer which is located on the memory layer and has electrical conductivity. The memory layer is composed of a material which produces spontaneous polarization at a voltage equal to or higher than a predetermined voltage. Through this, the memory device can be electrically driven and can continuously maintain modulated optical characteristics. Also, the memory device according to the embodiment of the present invention can modulate optical characteristics by multiple electrical inputs. | 2019-02-14 |
20190051659 | INTEGRATED CIRCUIT STRUCTURE HAVING VFET AND EMBEDDED MEMORY STRUCTURE AND METHOD OF FORMING SAME - The disclosure is directed to an integrated circuit structure and method of forming the same. The integrated circuit structure may include: a first device region including: a floating gate structure substantially surrounding a first fin that is over a substrate; a first bottom source/drain within the substrate, and beneath the first fin and the floating gate structure; a first top source/drain over the first fin and the floating gate structure; a first spacer substantially surrounding the first top source/drain and disposed over the floating gate structure; and a gate structure substantially surrounding and insulated from the floating gate structure, the gate structure being disposed over the substrate and having a height greater than a height of the floating gate. | 2019-02-14 |
20190051660 | VOID FORMATION FOR CHARGE TRAP STRUCTURES - Various embodiments include methods and apparatus having a number of charge trap structures, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric region, the blocking dielectric region located on a charge trap region of the charge trap structure. At least a portion of the gate can be separated by a void from a region which the charge trap structure is directly disposed. Additional apparatus, systems, and methods are disclosed. | 2019-02-14 |
20190051661 | CHARGE TRAP STRUCTURE WITH BARRIER TO BLOCKING REGION - Various embodiments, disclosed herein, include methods and apparatus having charge trap structures, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric on a charge trap region of the charge trap structure. In various embodiments, material of the dielectric barrier of each of the charge trap structures may have a dielectric constant greater than that of aluminum oxide. Additional apparatus, systems, and methods are disclosed. | 2019-02-14 |
20190051662 | THREE DIMENSIONAL MEMORY DEVICE HAVING ISOLATED PERIPHERY CONTACTS THROUGH AN ACTIVE LAYER EXHUME PROCESS - A three dimensional memory device is described having an array region and a periphery region. The array region has a three dimensional stack of storage cells. The periphery region has contacts that extend from above the three dimensional stack of storage cells to below the three dimensional stack of storage cells. The periphery region is substantially devoid of conducting and/or semi-conducting layers of the three dimensional stack of storage cells. | 2019-02-14 |
20190051663 | METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film. | 2019-02-14 |
20190051664 | MEMORY DEVICES - A memory device may include multiple channel regions extending in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate to be adjacent at least a portion of the plurality of channel regions, an interlayer insulating layer disposed on the plurality of gate electrode layers, a plurality of cell contact plugs passing through the interlayer insulating layer. Each of the plurality of cell contacts is connected to each of the plurality of gate electrode layers. A vertical insulating layer extends from the interlayer insulating layer disposed between the plurality of channel regions and the plurality of cell contact plugs and has a portion surrounded by at least one of the plurality of gate electrode layers. | 2019-02-14 |
20190051665 | SEMICONDUCTOR DEVICES AND METHODS FOR FORMING THE SAME - A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element. | 2019-02-14 |
20190051666 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device includes a substrate having a frontside and a backside. The substrate includes a semiconductor layer and a buried insulator layer. A transistor is disposed on the semiconductor layer. An interlayer dielectric (ILD) layer is disposed on the frontside and covering the transistor. A contact structure penetrates through the ILD layer, the semiconductor layer and the buried insulator layer. A silicide layer caps an end surface of the contact structure on the backside. A passive element is disposed on the backside of the substrate. The contact structure is electrically connected to the passive element. | 2019-02-14 |
20190051667 | AN ARRAY SUBSTRATE AND A MANUFACTURING METHOD THEREOF, A DISPLAY PANEL, AS WELL AS A DISPLAY DEVICE - The present disclosure discloses an array substrate and a manufacturing method thereof, a display panel, as well as a display device. The array substrate comprises common electrodes and common electrode lines. The common electrode lines are parallel to the data lines. The data lines and the common electrode lines are distributed alternately between columns of sub-pixel units. The common electrode lines are in direct contact and electrically connected with the common electrodes. Each data line is connected with two columns of sub-pixel units adjacent to the data line. One gate line is distributed at each side of each row of sub-pixel units, and two gate lines are distributed between two adjacent rows of sub-pixel units. Two adjacent sub-pixel units in each row connected to a same data line are respectively connected with different gate lines distributed at two sides of the row of sub-pixel units. | 2019-02-14 |
20190051668 | ARRAY SUBSTRATE - An array substrate includes a substrate, first signal lines, sub-pixels, reference potential lines, first bonding pads, second bonding pads, first fan-out lines, second fan-out lines, first connection lines, second connection lines, and a first reference potential line. An accommodation space exists between a first connection line closest to the second bonding pads and a second connection line closest to the first bonding pads. The first reference potential line is disposed in the accommodation space and electrically connected with the reference potential lines. | 2019-02-14 |
20190051669 | THIN FILM TRANSISTOR ARRAY SUBSTRATE, DISPLAY APPARATUS, AND METHOD OF MANUFACTURING THIN FILM TRANSISTOR ARRAY SUBSTRATE - A thin film transistor array substrate includes: a first conductive layer including first lines for transmitting data signals to the thin film transistors; a second conductive layer disposed on the first conductive layer and including second lines for supplying a driving voltage to the thin film transistors; a first insulating layer disposed between a semiconductor layer and the first conductive layer and including a first material layer; a second insulating layer disposed between the first conductive layer and the second conductive layer and including a second material layer having a dielectric constant greater than that of the first material layer; and a contact plug penetrating the second insulating layer and the first insulating layer, and connecting the second conductive layer to the semiconductor layer. A taper angle of the contact plug in the second material layer is greater than that of the contact plug in the first material layer. | 2019-02-14 |
20190051670 | ARRAY SUBSTRATE AND DISPLAY PANEL - An array substrate and a display panel are provided. The array substrate includes a non-display area and a display area. The non-display area includes a first non-display area and a second non-display area, and the display area includes a normal display area and a wiring area. The normal display area is surrounded by the first non-display area, the wiring area is surrounded by the normal display area, and the second non-display area is surrounded by the wiring area. The second non-display area comprises an opening area. In the solution, since the number of data lead lines in the same layer in the wiring area is reduced, a line distance between adjacent data lead lines is increased, thereby reducing coupling capacitance between adjacent data lead lines arranged in the same layer. | 2019-02-14 |
20190051671 | DISPLAY SUBSTRATE, METHOD OF MANUFACTURING THE SAME AND DISPLAY DEVICE - A display substrate, a method of manufacturing the same and a display device are provided. The display substrate includes a base substrate, a plurality of metal particles dispersedly disposed on the base substrate and forming a discontinuous film, a light shielding layer disposed on a side of the base substrate on which the plurality of metal particles are disposed and covering the plurality of metal particles, and a thin film transistor located on a side of the light shielding layer far away from the base substrate. | 2019-02-14 |
20190051672 | THIN FILM TRANSISTOR SUBSTRATE, AND DISPLAY PANEL AND DISPLAY DEVICE INCLUDING SAME - A thin film transistor substrate according to an embodiment includes: a substrate; and a thin film transistor disposed on the substrate, wherein the thin film transistor includes a channel layer including a nitride-based semiconductor layer, a source electrode electrically connected to a first region of the channel layer, a drain electrode electrically connected to a second region of the channel layer, a gate electrode disposed on the channel layer, and a depletion forming layer disposed between the channel layer and the gate electrode. | 2019-02-14 |
20190051673 | OXIDE SEMICONDUCTOR, THIN FILM TRANSISTOR, AND DISPLAY DEVICE - An object is to control composition and a defect of an oxide semiconductor, another object is to increase a field effect mobility of a thin film transistor and to obtain a sufficient on-off ratio with a reduced off current. A solution is to employ an oxide semiconductor whose composition is represented by InMO | 2019-02-14 |
20190051674 | DISPLAY SUBSTRATE AND METHOD OF REPAIRING DEFECTS THEREOF - A display substrate includes a gate metal pattern including a gate line extending in a first direction, a gate electrode electrically connected to the gate line and a storage line, a data metal pattern including a data line extending in a second direction crossing the first direction, a source electrode electrically connected to the data line and a drain electrode spaced apart from the source electrode, a repair electrode extending in the second direction and overlapping the storage line, an organic layer disposed on the data metal pattern and a pixel electrode disposed on the organic layer and electrically connected to the drain electrode. | 2019-02-14 |
20190051675 | DISPLAY DEVICE - A display device includes a flexible substrate, a plurality of TFTs, a first electrode arranged between a channel of one of the plurality of TFTs and the flexible substrate, at least one inorganic insulating film arranged between one of the plurality of TFTs and the first electrode, a second electrode arranged on the opposite side to the side where one of the plurality of TFTs is arranged with respect to the first electrode, and an organic insulating film arranged between the first electrode and the second electrode. | 2019-02-14 |
20190051676 | DISPLAY APPARATUS HAVING A STEPPED PART - Provided is a display apparatus including a substrate and a semiconductor layer including first and second semiconductor layers. A first gate insulating layer is formed on the semiconductor layer. A first gate wiring overlapping the first semiconductor layer is formed on the first gate insulating layer. A second gate insulating layer is formed on the first gate wiring. A second gate wiring overlapping the second semiconductor layer is formed on the second gate insulating layer. A third gate insulating layer covers the second gate wiring. A driving voltage line intersecting the first and second gate wirings is formed on the third gate insulating layer. A data line intersecting the first and second gate wirings is formed on the third gate insulating layer. A short circuit protection area is formed between the first gate wiring, the second gate wiring, the driving voltage line and the data line. | 2019-02-14 |
20190051677 | ARRAY SUBSTRATE, PREPARATION METHOD THEREOF, AND DISPLAY DEVICE - The embodiments of the present disclosure provide an array substrate, a preparation method thereof, and a display device. The preparation method of an array substrate comprises: forming the active layer, a gate insulating layer, the gate metal layer and the patterned photoresist sequentially on a substrate; forming a gate electrode transition pattern by etching a gate metal layer via a patterned photoresist, using a wet etching process and a dry etching process sequentially; and doping an area of the active layer not sheltered by the gate electrode transition pattern with ions to form a heavily doped area of the active layer. | 2019-02-14 |
20190051678 | METHOD OF PRODUCING DISPLAY PANEL BOARD - A method includes a conductive film forming process of forming a conductive film | 2019-02-14 |
20190051679 | Array Substrate and Display Device - Disclosed is an array substrate and a display device. The array substrate includes: a plurality of gate lines and a plurality of data lines formed on a base substrate, and a plurality of pixel units defined by the plurality of gate lines and the plurality of data lines intersecting each other, wherein each pixel unit includes a thin film transistor and a pixel electrode connected with the thin film transistor, the pixel electrode, the data line, as well as an active layer, a source and a drain of the thin film transistor are disposed in a same layer and are formed through a single patterning process, | 2019-02-14 |
20190051680 | SOLID-STATE IMAGING DEVICE, DRIVING METHOD, AND ELECTRONIC EQUIPMENT - The present disclosure relates to a solid-state imaging device, a driving method, and electronic equipment that permit imaging of a wide dynamic range image with higher quality. | 2019-02-14 |
20190051681 | A QUANTUM DOT PHOTODETECTOR APPARATUS AND ASSOCIATED METHODS - An apparatus comprising at least one pair of a first inner and second outer photodetector, each photodetector comprising a channel member, respective source and drain electrodes configured to enable a flow of electrical current through the channel member between the source and drain electrodes, and a plurality of quantum dots configured to generate electron-hole pairs on exposure to incident electromagnetic radiation to produce a detectable change in the electrical current flowing through the channel member. The first inner and second outer photodetectors are configured to generate electron-hole pairs which produce an increase and decrease in electrical current through the channel members. The first inner and the second outer photodetectors share a common channel member, which is partitioned by one or more of the respective source and drain electrodes respectively extending in two dimensions such that the first inner photodetector is defined within the second outer photodetector. | 2019-02-14 |
20190051682 | SOLID-STATE IMAGING DEVICE AND METHOD OF MANUFACTURING THE SAME - The solid-state imaging device according to the present disclosure includes a substrate, a first impurity region of a first conductive type disposed in the substrate, light receiving elements of a second conductive type disposed in the first impurity region, an overflow drain region of the second conductive type disposed below the first impurity region, a second impurity region of the second conductive type configuring, together with the overflow drain region, a drain path for excessive charge from the light receiving elements, and a reflective film. | 2019-02-14 |
20190051683 | ELECTRONIC DEVICE - An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire. | 2019-02-14 |
20190051684 | IMAGING DEVICE AND IMAGE ACQUISITION DEVICE - An imaging device includes a pixel comprising a photoelectric conversion layer having a first surface and a second surface opposite to the first surface; a pixel electrode on the first surface; an auxiliary electrode on the first surface, the auxiliary electrode being spaced from the pixel electrode; an upper electrode on the second surface, the upper electrode facing the pixel electrode and the auxiliary electrode; and an amplification transistor having a gate coupled to the pixel electrode. The imaging device also includes voltage application circuitry that generates a first voltage and a second voltage different from the first voltage, the voltage application circuitry being coupled to the auxiliary electrode. The voltage application circuitry selectively supplies either the first voltage or the second voltage to the auxiliary electrode. | 2019-02-14 |
20190051685 | IMAGING DEVICE AND METHOD OF MANUFACTURING IMAGING DEVICE - A method of manufacturing an imaging device, including a first buried diode including a first semiconductor region and a second semiconductor region and a second buried diode including a third semiconductor region and a fourth semiconductor region, includes implanting first impurity ions of a first conductivity type into a first region and a third region between the first region and a second region, and implanting second impurity ions of the first conductivity type into the second region and the third region, wherein the first semiconductor region is formed by implanting the first impurity ions, the third semiconductor region is formed by implanting the second impurity ions, and a fifth semiconductor region having a higher impurity concentration than the first and the second semiconductor regions is formed in the third region by implanting the first and second impurity ions. | 2019-02-14 |
20190051686 | SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS - The present technology relates to a solid-state imaging device that can achieve a higher resolution while increasing sensitivity. In a pixel array unit, pixels are formed with a combination of a first pixel that performs photoelectric conversion on light of a first color component with a first photoelectric conversion unit, and photoelectric conversion on light of a third color component with a second photoelectric conversion unit; a second pixel that performs photoelectric conversion on light of the first color component with a first photoelectric conversion unit, and on light of a fifth color component with a second photoelectric conversion unit; and a third pixel that performs photoelectric conversion on light of the first color component with a first photoelectric conversion unit, and on light of a sixth color component with a second photoelectric conversion unit. The first color component and the sixth color component are mixed, to generate white (W). | 2019-02-14 |
20190051687 | IMAGING ASSEMBLY, METHOD AND MOLDING MOLD FOR FABRICATING SAME, CAMERA MODULE, AND SMART TERMINAL - The present application provides an imaging assembly, a method and molding mold for fabricating same, a camera module, and a smart terminal. According to an aspect of the present application, the imaging assembly includes a photosensitive element and a molded encapsulation portion. The photosensitive element has a photosensitive area. The molded encapsulation portion is formed around the photosensitive area and is in contact with the photosensitive element. The molded encapsulation portion has an inclined inner side surface and a top surface higher than the photosensitive area. A height difference between the top surface of the molded encapsulation portion and the photosensitive area of the photosensitive element is less than or equal to 0.7 mm, and the inclined inner side surface and the top surface have different surface roughnesses. | 2019-02-14 |
20190051688 | IMAGE SENSORS WITH COLOR FILTER VARIATIONS - Color filters may affect imaging performance attributes such as low light sensitivity, color accuracy, and modulation transfer function (MTF). In an image pixel array, these factors are influenced by both the spectral absorption and pattern of the color filter elements. Different portions of an image sensor may prioritize different imaging performance attributes. Accordingly, in certain applications it may be beneficial for color filter characteristics to vary across an image sensor. Different color filters of the same color may have different structures to optimize imaging performance across the image sensor. | 2019-02-14 |
20190051689 | Backside Illuminated CMOS Image Sensor and Method of Manufacturing the Same - The present invention relates to a backside illuminated CMOS image sensor. | 2019-02-14 |
20190051690 | IMAGING ASSEMBLY, METHOD AND MOLDING MOLD FOR FABRICATING SAME, CAMERA MODULE, AND SMART TERMINAL - The present application provides an imaging assembly, a method and molding mold for fabricating same, a camera module, and a smart terminal. According to an aspect of the present application, the imaging assembly includes a photosensitive element and a molded encapsulation portion. The photosensitive element has a photosensitive area. The molded encapsulation portion is formed around the photosensitive area and is in contact with the photosensitive element. The molded encapsulation portion has an inclined inner side surface and a top surface higher than the photosensitive area. A height difference between the top surface of the molded encapsulation portion and the photosensitive area of the photosensitive element is less than or equal to 0.7 mm, and the inclined inner side surface and the top surface have different surface roughnesses. | 2019-02-14 |
20190051691 | SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS - Disclosed herein is a solid-state imaging device including: a laminated semiconductor chip configured to be obtained by bonding two or more semiconductor chip sections to each other and be obtained by bonding at least a first semiconductor chip section in which a pixel array and a multilayer wiring layer are formed and a second semiconductor chip section in which a logic circuit and a multilayer wiring layer are formed to each other in such a manner that the multilayer wiring layers are opposed to each other and are electrically connected to each other; and a light blocking layer configured to be formed by an electrically-conductive film of the same layer as a layer of a connected interconnect of one or both of the first and second semiconductor chip sections near bonding between the first and second semiconductor chip sections. The solid-state imaging device is a back-illuminated solid-state imaging device. | 2019-02-14 |
20190051692 | SEMICONDUCTOR INTEGRATED CIRCUIT, ELECTRONIC DEVICE, SOLID-STATE IMAGING APPARATUS, AND IMAGING APPARATUS - A semiconductor integrated circuit includes a first semiconductor substrate in which a part of an analog circuit is formed between the analog circuit and a digital circuit which subjects an analog output signal output from the analog circuit to digital conversion; a second semiconductor substrate in which the remaining part of the analog circuit and the digital circuit are formed; and a substrate connection portion which connects the first and second semiconductor substrates to each other. The substrate connection portion transmits an analog signal which is generated by a part of the analog circuit of the first semiconductor substrate to the second semiconductor substrate. | 2019-02-14 |
20190051693 | IMAGING DEVICE INCLUDING UNIT PIXEL CELL - An imaging device having a pixel including a photoelectric converter that generates electric signal; first transistor having a gate coupled to the photoelectric converter; second transistor one of a source and a drain of which is coupled to one of a source and a drain of the first transistor; third transistor one of a source and a drain of which is coupled to the other of the source and the drain of the second transistor, the other of the source and the drain of the third transistor coupled to the photoelectric converter; first capacitor having a first and second ends, the first end coupled to the other of the source and the drain of the second transistor, first reference voltage applied to the second end; and second capacitor having a third and fourth ends, the third end coupled to the first end, the fourth end coupled to the photoelectric converter. | 2019-02-14 |
20190051694 | METHOD OF MAKING AND DEVICE HAVING A COMMON ELECTRODE FOR TRANSISTOR GATES AND CAPACITOR PLATES - Disclosed herein is a circuit comprising a first thin film transistor (TFT) and storage capacitor having a first electrode and a second electrode configured to face to each other. A second TFT is coupled to the capacitor, wherein a first gate electrode of the first TFT, a first electrode of the storage capacitor and a second gate electrode of the second TFT are integrally formed. | 2019-02-14 |
20190051695 | DEVICE COMPRISING A PLURALITY OF DIODES - A device including a plurality of interconnected concentric coplanar diodes. | 2019-02-14 |
20190051696 | LIGHT EMITTING DIODE DISPLAY PANEL AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - A light emitting diode display panel and a manufacturing method thereof, and a display device. The light emitting diode display panel includes a substrate, a plurality of light emitting diodes arranged in an array on the substrate; a plurality of polarization layers located on a light exit side of the plurality of light emitting diodes respectively, and the plurality of polarization layers are in a one-to-one correspondence to the plurality of light emitting diodes; the plurality of polarization layers include a plurality of first polarization layers and a plurality of second polarization layers having different polarization directions. | 2019-02-14 |
20190051697 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes: a substrate, a bonding metal layer, a reflective layer, a first conductive layer, an active layer, a second conductive layer, first electrode(s) and second electrode(s). The first electrode(s) extends, from one side of the bonding metal layer away from the substrate, to the first conductive layer, to be connected with the bonding metal layer and the first conductive layer. The second electrode(s) penetrates through the substrate and the bonding metal layer to be in contact with the reflective layer. The semiconductor device, forming a structure sharing the first conductive layer, has more uniform illumination and a higher light extraction rate, and eliminates interferences between pixel units, achieves better uniformity of emitted light wavelength and makes distribution of electric current flowing through different pixel units more even. | 2019-02-14 |
20190051698 | LIGHT-EMITTING DEVICE - This disclosure discloses a light-emitting display module display. The light-emitting display module comprises: a board; and a plurality of light-emitting diode modules arranged in an array configuration on the board; wherein one of the light-emitting diode modules comprises a plurality of encapsulated light-emitting units spaced apart from each other; and one of the encapsulated light-emitting units comprises a plurality of optoelectronic units, a first supporting, and a fence; and wherein the plurality of optoelectronic units are covered by the first supporting structure, and the fence surrounds the first supporting structure and the plurality of optoelectronic units. | 2019-02-14 |
20190051699 | SPATIAL RESOLUTION AND SIMULTANEOUS MULTIPLE SINGLE PHOTON DETECTION USING SUPERCONDUCTING STRUCTURED PARALLEL NANOWIRES - A multiple arrayed parallel nanowire device includes one or more arrays connected in series, wherein each array includes a plurality of narrow nanowires flanked by one or more wide nanowires, a top electrode, an applied current, a bottom ground electrode, and one or more lateral electrodes where one or more currents or one or more probing voltages can be applied to detect voltage changes in each array. The device detects single and multiple photons without destroying superconductivity in all the nanowires in the array and is thus capable of remaining sensitive to subsequent photon impacts. Moreover, the device can resolve the location of each photon impact. | 2019-02-14 |
20190051700 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY MANUFACTURING APPARATUS - A first memory device includes a first magnetoresistive cell having a plurality of deposition layers. A second memory device includes a second magnetoresistive cell having a plurality of deposition layers. Each of the plurality of deposition layers of the second magnetoresistive cell corresponds to one of the plurality of deposition layers of the first magnetoresistive cell. One of the plurality of deposition layers of the second magnetoresistive cell is thinner than a corresponding deposition layer of the plurality of deposition layers of the first magnetoresistive cell. | 2019-02-14 |
20190051701 | VERTICAL CROSS-POINT MEMORY ARRAYS - A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F | 2019-02-14 |
20190051702 | Resistive Switching Random Access Memory with Asymmetric Source and Drain - A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate. The resistive element includes a top electrode, a bottom electrode, and a resistive material layer positioned between the top electrode and the bottom electrode. The RRAM structure further includes a field effect transistor (FET) formed on the semiconductor substrate, the FET having a source and a drain. The drain of the FET has a higher doping concentration than the source of the FET. The resistive memory element is coupled with the drain via a portion of an interconnect structure. | 2019-02-14 |
20190051703 | TWO-DIMENSIONAL ARRAY OF SURROUND GATE VERTICAL FIELD EFFECT TRANSISTORS AND METHOD OF MAKING THEREOF - A two-dimensional array of vertical field effect transistors is provided, which includes a one-dimensional array of ladder-shaped gate electrode lines. Each of the ladder-shaped gate electrode lines includes a pair of rail portions that laterally extend along a first horizontal direction and spaced among one another along a second horizontal direction and rung portions extending between the pair of rail portions along the second horizontal direction. The vertical field effect transistors include gate dielectrics located in each opening defined by a neighboring pair of rung portions, and vertical semiconductor channels laterally surrounded by a respective one of the gate dielectrics and extending along a vertical direction. The two-dimensional array of vertical field effect transistors can be employed to select vertical bit lines of a three-dimensional ReRAM device. | 2019-02-14 |
20190051704 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed is a display device including a solar cell so as to use power produced by a solar energy, and a method for manufacturing the same, wherein the display device includes light-emitting areas provided on a lower substrate, and a solar cell layer provided on an upper substrate confronting the lower substrate, and provided to produce power by absorbing light, wherein the light-emitting areas include first to third light-emitting areas, and the solar cell layer includes first to third organic solar cell layers which are disposed to areas corresponding to the first to third light-emitting areas. | 2019-02-14 |
20190051705 | FOLDABLE OLED DEVICE WITH COMPATIBLE FLEXURAL STIFFNESS OF LAYERS - A flexible OLED display device that includes an upper module having a cover window film, a lower module, and a display module between the upper and lower modules. The display module includes an OLED and an OLED substrate. The stiffnesses of components in the display device are controlled to satisfy a particular relationship such that the bending stiffnesses of the upper and lower modules are tuned in order to position the neutral bending plane below the display module, which places the display into a state of compressive strain as opposed to zero strain. This design is suitable for a bifold flexible display in which the upper module can be folded to face itself. | 2019-02-14 |
20190051706 | ORGANIC LIGHT EMITTING DISPLAY - An organic light emitting display including a substrate, a first electrode and a second electrode on the substrate and facing each other, at least two organic light emitting layers between the first electrode and the second electrode, and at least two color filters on the second electrode, the organic light emitting layers emitting a first color light, and the color filters emitting a second color light and a third color light. | 2019-02-14 |
20190051707 | OLED TOUCH DISPLAY PANEL AND OLED TOUCH DISPLAY - The present disclosure provides an organic light emitting diode (OLED) touch display panel and an organic light emitting diode (OLED) touch display. The OLED touch display panel includes an array substrate, an OLED layer disposed on the array substrate, an encapsulation layer disposed on the OLED layer and the array substrate, and a touch structural layer disposed on the encapsulation layer. According to the present disclosure, the touch structural layer is directly disposed on the encapsulation layer without the need to use a specific glass substrate, therefore reducing thickness of the OLED touch display panel. | 2019-02-14 |
20190051708 | DISPLAY DEVICE HAVING AN INPUT SENSING UNIT - A display device includes a display panel and an input-sensing unit located on the display panel. The input-sensing unit includes a plurality of sensor portions. At least one of the sensor portions is different from the others in terms of area or distance. | 2019-02-14 |
20190051709 | DISPLAY SYSTEM COMPRISING AN IMAGE SENSOR - A display system including a display screen having first and second display sub-pixels where each first display sub-pixel includes a first light-emitting component emitting a first radiation and covered with a first colored filter and first conductive tracks and where each second display sub-pixel includes a second light-emitting component emitting a second radiation and covered with a second colored filter and second conductive tracks. The display system further includes an image sensor detecting the first or second radiation or a third radiation. The first display sub-pixels include first elements absorbing the first radiation and the second radiation and covering the first conductive tracks. The first absorbing elements and/or the first colored filter delimit a first passageway along the stacking direction for the first, second, or third radiation. | 2019-02-14 |