07th week of 2011 patent applcation highlights part 29 |
Patent application number | Title | Published |
20110039333 | DEFINED CONDITIONS FOR HUMAN EMBRYONIC STEM CELL CULTURE AND PASSAGE - The invention relates to human pluripotent cells. More specifically, the invention provides a chemically defined xeno-free culture system that allows for long term expansion of human pluripotent cells. This culture system allows for human pluripotent cell lines to be maintained in the pluripotent state for an extended time while maintaining a normal karyotype and the ability to differentiate into all three germ layers. | 2011-02-17 |
20110039334 | CHIMERIC OLIGOMERIC COMPOUNDS FOR MODULATION OF SPLICING - Disclosed herein are compounds, compositions and methods for modulating splicing of a selected target mRNA. Further provided are uses of the disclosed compounds and compositions in the manufacture of a medicament for treatment of diseases and disorders. Methods of enhancing cellular uptake, modulating tissue distribution and enhancing pharmacological activity of RNase H-independent antisense oligonucleotides are also provided. | 2011-02-17 |
20110039335 | Compositions and Methods for Inhibiting Cell Migration - The finding that Dickkopf1 (Dkk1) is a dual function protein demonstrates a mechanism for the coordination of cell migration and antagonism of Wnt/β-catenin signaling during developmental and pathological processes. The profile of Dkk proteins expressed by human breast cancers correlates with indicators of outcome: Dkk1 associates with markers of poor prognosis whereas expression of single function Dkk2 or Dkk3 (which inhibit Wnt/β-catenin signaling and promote migration, respectively) correlates with phenotypes reflective of good prognosis. Therefore, the pro-migratory activities of Dkk1 and 3 identified here offer new insights into breast cancer progression and a potential avenue for therapeutic intervention. | 2011-02-17 |
20110039336 | PRODUCT FOR CELL CULTURE - The present invention relates to a product for cell culture. In particular, the invention relates to a cell growth surface having a coating comprising an animal protein free coating. The coating is derived from an enzymatic hydrolysate of a plant protein, preferably soy peptone. The cell culture product is preferably a microcarrier intended for culture of any anchorage-dependent cells. | 2011-02-17 |
20110039337 | METHODS AND DEVICES FOR DISPERSING SOMATIC PLANT EMBRYOS - Methods and devices for dispersion of clusters of somatic plant embryos suspended in a liquid are disclosed. The methods comprise i) subjecting the clusters of embryos to fluid dynamics forces causing axially extensional strain and radially compressional strain and ii) subjecting the clusters of embryos to fluid dynamics forces causing axially compressional strain and radially extensional strain fluid dynamics and iii) repeating said steps in sequence until the individual embryos are separated from each other. The devices may comprise a flow channel including at least one constriction, such that clusters of embryos flowing through the flow channel are first subjected to axially extensional strain and radially compressional strain, and then to axially compressional strain and radially extensional strain from fluid dynamics forces. | 2011-02-17 |
20110039338 | METHOD OF EFFICIENTLY ESTABLISHING INDUCED PLURIPOTENT STEM CELLS - Provided is a method of improving the efficiency of establishment of induced pluripotent stem cells, comprising culturing somatic cells under hypoxic conditions in the step of nuclear reprogramming thereof. | 2011-02-17 |
20110039339 | Process, Vectors and Engineered Cell Lines for Enhanced Large-Scale Transfection - Processes vectors and engineered cell lines for large-scale transfection and protein production in mammalian cells, especially Chinese Hamster Ovary (CHO) cells are described in which transfection efficiencies are realized through the use of a single vector system, the use of functional oriP sequences in all plasmids, the use of codon-optimized Epstein-Barr virus nuclear antigen-1 (EBNA1) constructs the use of a fusion protein between a truncated Epstein-Barr virus nuclear antigenen-1c (EBNA1c) protein and a herpes simplex virus protein VP16, the use of a 40 kDa fully deacetylated poly(ethylenimine) as a transfection reagent, the use of co-expression of a fibroblast growth factor (FGF) and/or the use of protein kinase B to potentiate heterologous gene expression enhancement by valproic acid (VPA). | 2011-02-17 |
20110039340 | COMPOSITIONS AND RELATED METHODS FOR MODULATING TRANSCRIPTIONAL ACTIVATION BY INCORPORATING GAG MOTIFS UPSTREAM OF CORE PROMOTER ELEMENTS - Compositions and methods for genetically modifying the production levels of nicotine and other alkaloids in plants are provided. An expression vector which comprises a tripartite GAG motif is also disclosed. | 2011-02-17 |
20110039341 | Method for detecting nucleotide polymor-phisms using semiconductor particles - A method for detecting anomalies in genetic material is provided, the method comprising supplying the genetic material; establishing electronic communication between the genetic material and a semi-conductor particle so as to create a composite; contacting the composite with a first metal ion; and subjecting the contacted composite to energy in an amount and for a time sufficient to reduce the first metal ion to a first elemental metal. Also provided is a device for detecting single nucleotide mismatching in genetic material, the device comprising a semiconductor particle; a ligand attached to the particle; the genetic material in electronic communication with the ligand so as to form an organic-inorganic composite; metal ion in electronic communication with the composite, such that the metal ion reduces to elemental metal when the semiconductor particle is exposed to radiation of a predetermined energy level. | 2011-02-17 |
20110039342 | DIAGNOSTIC MARKERS OF WOUND INFECTION - A method of diagnosis or prediction of infection of a mammalian wound, said method comprising the step of detecting the presence of a cytokine selected from the group comprising procalcitonin, amino procalcitonin (N-ProCT), eotaxin, granulocyte macrophage colony stimulating factor (GM-CSF), interleukins IB monocyte chemotactic protein-1 (MCP-1), macrophage inflammatory protein-1 alpha (MIP-1a), regulated upon activation normal T expressed and secreted (RANTES) in fluid taken from the wound. Also claimed is the device for use in the method. | 2011-02-17 |
20110039343 | METHOD FOR THE IDENTIFICATION OF PATIENTS IN NEED OF THERAPY HAVING MINOR COGNITIVE DISORDERS AND THE TREATMENT OF SUCH PATIENTS - A method for the identification of patients in need of therapy and for the preventive treatment of such patients having minor cognitive disorders, wherein an increased risk can be determined for said patients to develop clinically manifested Alzheimer's disease during a preceding risk stratification as a result of an increase in circulation-relevant peptide biomarkers measurable in the circulation of said patients, using drugs that comprise one or more active ingredients of cardiovascular agents, which are selected from the group consisting of ACE inhibitors, angiotensin II receptor antagonists, betablockers and blood pressure-lowering diuretics and the combinations thereof, or using drugs comprising one or more ANP receptor antagonists or one or more adenosine receptor antagonists. | 2011-02-17 |
20110039344 | METHOD AND TESTING A SUBJECT THOUGHT TO BE PREDISPOSED TO LUNG CANCER - The present invention concerns a method of testing a human thought to be predisposed to having lung cancer which comprises the step of analyzing a biological sample from said human for detecting the presence of a polymorphism on chromosome 15q25 associated with lung cancer. | 2011-02-17 |
20110039345 | SYSTEM AND METHOD FOR ELECTROCHEMICAL DETECTION OF BIOLOGICAL COMPOUNDS - The present invention relates to an electrochemical method for detecting a target polynucleotide. An electrode comprising an electrode surface is provided. The electrode surface includes at least one probe molecule reversibly immobilized with respect to the electrode surface. A first electrochemical signal indicative of an amount of probe molecule immobilized with respect to the electrode surface is obtained. The electrode surface is contacted with a liquid comprising the target polynucleotide. Upon the contacting step, at least some of the probe molecule immobilized with respect to the electrode surface dissociates therefrom. A second electrochemical signal indicative of an amount of probe molecule immobilized with respect to the electrode surface is obtained. The presence of the target polynucleotide is determined at least partially on the basis of the first and second electrochemical signals. | 2011-02-17 |
20110039347 | Analytical Method and Apparatus - A method for determining the amount of a chemical species in a sample, in particular the amount of weak acid dissociable cyanide or total cyanide in a sample, and an apparatus for performing said method. The method comprises the steps of: i) treating the sample to liberate the chemical species into a gaseous stream; ii) directing the gaseous stream to a scrubber; iii) absorbing the chemical species into a scrubber solution; and iv) determining the amount of chemical species absorbed into the scrubber solution, wherein any remaining chemical species not absorbed into the scrubber solution is directed or recirculated to the scrubber in the gaseous stream and step iii) is repeated to increase absorption of the chemical species prior to performing step iv). | 2011-02-17 |
20110039348 | METHOD OF EVALUATING REACTION BETWEEN DISSOLVED HYDROGEN AND DISSOLVED OXYGEN AND METHOD OF EVALUATING ABILITY OF DISSOLVED HYDROGEN TO SCAVENGE ACTIVE OXYGEN IN WATER - Provided are novel technical means for obtaining useful knowledge in practical application of antioxidation action of dissolved hydrogen and in practical application of active oxygen scavenging action in water. | 2011-02-17 |
20110039349 | SAMPLE TESTING APPARATUS, INFORMATION MANAGEMENT APPARATUS AND SAMPLE TESTING METHOD - A sample testing apparatus comprising: a receiving section which receives identification information inputted by an operator; a testing section which tests a sample to obtain a test result; a memory which stores the test result, which is obtained by the testing section, so as to be associated with the identification information received by the receiving section; and a controller, wherein the controller is configured to: make a display section display only the test result associated with the identification information corresponding to a first attribute in the test results stored in the memory when the identification information received by the receiving section corresponds to the first attribute; and make the display section display test results which are stored in the memory when the identification information received by the receiving section corresponds to the second attribute is disclosed. An information management apparatus and sample testing method are also disclosed. | 2011-02-17 |
20110039350 | HIGH YIELD ATMOSPHERIC PRESSURE ION SOURCE FOR ION SPECTROMETERS IN VACUUM - Gaseous analyte molecules are ionized at atmospheric pressure and provided to an inlet capillary of an ion spectrometer vacuum system by passing the ions through a reaction tube that ends in a conical intermediate piece for a gastight and smooth transition into the inlet capillary. The reaction tube is shaped so that the atmospheric pressure gas stream passing therethrough form the entrance of the tune to the intermediate piece is stably laminar. Analyte molecules from gas chromatographs, spray devices or vaporization devices can be introduced into the entrance of the reaction tube and ionized within the tube by single- or multi-photon ionization, by chemical ionization, by reactant ions or by physical ionization. For single- or multi-photon ionization, a beam from a laser can be passed axially down the reaction tube. Reactant ions can be produced by any means outside of the reaction tube and mixed with the analyte molecules within the tube. | 2011-02-17 |
20110039351 | High Temperature High Pressure Vessel for Microwave Assisted Chemistry - A method of conducting microwave-assisted high pressure high temperature chemistry is disclosed. The method includes the steps of digesting a sample in a strong acid at a temperature of at least 200° C. in a pressure resistant vessel that includes a lid while exerting a defined force against the lid in order to maintain gases under pressure in the vessel; directing gas under excess pressure from the vessel into a circumferential passage defined by the vessel and its pressure resistant lid; and directing the gas from the circumferential passage outwardly from the lid while preventing gas from flowing outwardly over the edge of the vessel. | 2011-02-17 |
20110039352 | METHODS TO MEASURE DISSOCIATION RATES FOR LIGANDS THAT FORM REVERSIBLE COVALENT BONDS - The crystal structure of the ligand binding domain of ERR-α in complex with a ligand that forms a reversible thioether bond to Cys325 of ERR-α, methods to measure dissociation rates for ligands that form reversible covalent bonds, and methods to design ligands that form reversible covalent bonds for use as modulators of ERR-α activity are disclosed. The crystal structure and methods provide a novel molecular mechanism for modulation of the activity of ERR-α and provide the basis for rational drug design to obtain potent specific ligands for use as modulators of the activity of this new drug target. | 2011-02-17 |
20110039353 | METHOD FOR DIRECT DETECTION OF ISCHEMIA-MODIFIED ALBUMIN USING A PARTNER FOR BINDING TO AN ALDEHYDE DERIVATIVE RESULTING FROM THE PEROXIDATION OF LIPIDS IN BOUND FORM - The present invention relates to the use of at least one partner for binding to an aldehyde derivative resulting from the peroxidation of lipids in protein-bound form, for instance to 4-hydroxy-2-nonenal, to 4-hydroxy-2-hexenal or to malondialdehyde, for the detection of ischemia-modified albumin (IMA) in a biological sample. | 2011-02-17 |
20110039354 | Method of Characterizing and Quantifying Calcifying Nanoparticles - A method of characterizing calcifying nanoparticles (CNPs) can include creating a test sample comprising CNPs isolated from a biological source, a buffer solution, a plurality of calibration beads, and a fluorescent marker specifically linked to the CNPs; evaluating the test sample using a flow cytometer; and analyzing results from the flow cytometer to determine a characterizing feature of the calcifying nanoparticles. The characterizing feature of the calcifying nanoparticles can be the number of CNPs, concentration of CNPs, size of CNPs, level of CNP aggregation, size and light dispersion characteristics of CNPs, fluorescence intensity of the CNPs when labeled with a specific antibody, or a combinations thereof The method can also include evaluating an isotype control comprising CNPs isolated from the biological source, the buffer solution, a plurality of calibration beads, and a fluorescent marker that is not linked to the CNPs. | 2011-02-17 |
20110039355 | Plasma Generation Controlled by Gravity-Induced Gas-Diffusion Separation (GIGDS) Techniques - The invention can provide apparatus and methods of processing a substrate using plasma generation by gravity-induced gas-diffusion separation techniques. By adding or using gases including inert and process gases with different gravities (i.e., ratio between the molecular weight of a gaseous constituent and a reference molecular weight), a two-zone or multiple-zone plasma can be formed, in which one kind of gas can be highly constrained near a plasma generation region and another kind of gas can be largely separated from the aforementioned gas due to differential gravity induced diffusion and is constrained more closer to a wafer process region than the aforementioned gas. | 2011-02-17 |
20110039356 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND APPARATUS FOR MANUFACTURING SAME - A method for manufacturing a semiconductor device includes: irradiating a growth substrate with laser light to focus the laser light into a prescribed position inside a crystal for a semiconductor device or inside the growth substrate, the crystal for the semiconductor device being formed on a first major surface of the growth substrate; moving the laser light in a direction parallel to the first major surface; and peeling off a thin layer including the crystal for the semiconductor device from the growth substrate, a wavelength of the laser light being longer than an absorption end wavelength of the crystal for the semiconductor device or the growth substrate, the laser light being irradiated inside a crystal for the semiconductor device or inside the growth substrate. | 2011-02-17 |
20110039357 | METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A POST/BASE HEAT SPREADER AND AN ADHESIVE BETWEEN THE BASE AND A TERMINAL - A method of making a semiconductor chip assembly includes providing a thermal post, a signal post, a base and a terminal, mounting an adhesive on the base including inserting the thermal post into a first opening in the adhesive and the signal post into a second opening in the adhesive, mounting a conductive layer on the adhesive including aligning the thermal post with a first aperture in the conductive layer and the signal post with a second aperture in the conductive layer, then flowing the adhesive upward between the thermal post and the conductive layer and between the signal post and the conductive layer and downward between the base and the terminal, solidifying the adhesive, providing a conductive trace that includes a pad, the terminal and the signal post, wherein the pad includes a selected portion of the conductive layer, mounting a semiconductor device on a heat spreader that includes the thermal post and the base, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader. | 2011-02-17 |
20110039358 | Methods and apparatus for forming uniform layers of phosphor material on an LED encapsulation structure - A method for forming a layer of phosphor material on an LED encapsulant structure includes forming a layer of a phosphor material on a first surface, disposing the first surface to cause the phosphor material to be in contact with a surface of the LED encapsulant structure, applying a pressure between the first surface and the surface of the LED encapsulant structure, and causing the layer of the phosphor material to be attached to the LED encapsulant structure. | 2011-02-17 |
20110039359 | Light emitting device and method of manufacturing the same - A method of manufacturing a light emitting device. The method includes: mounting a light emitting chip on a substrate; forming a transparent resin portion and a phosphor layer by using a liquid droplet discharging apparatus, the transparent resin portion being formed in a shape of a dome and covering the light emitting chip to fill an exterior thereof on the substrate, a phosphor layer containing phosphor and being formed on an exterior of the transparent resin portion close to at least a top side thereof; and forming a reflecting layer at a position exterior of the transparent resin portion and the phosphor layer close to the substrate. | 2011-02-17 |
20110039360 | Selective Decomposition Of Nitride Semiconductors To Enhance LED Light Extraction - A method of texturing a surface within or immediately adjacent to a template layer of a LED is described. The method uses a texturing laser directed through a substrate to decompose and pit a semiconductor material at the surface to be textured. By texturing the surface, light trapping within the template layer is reduced. Furthermore, by patterning the arrangement of pits, metal coating each pit can be arranged to spread current through the template layer and thus through the n-doped region of a LED. | 2011-02-17 |
20110039361 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A liquid crystal display device includes a plurality of gate lines and data lines crossing each other to define a plurality of pixel regions, a plurality of thin film transistors, each disposed in one of the pixel regions, and a plurality of pixel electrodes, each disposed in one of the pixel regions, wherein the thin film transistor includes at least one Ti layer. | 2011-02-17 |
20110039362 | MANUFACTURING METHOD OF FILM PATTERN OF MICRO-STRUCTURE AND MANUFACTURING METHOD OF TFT-LCD ARRAY SUBSTRATE - A method of forming a film pattern with micro-pattern and a method of manufacturing a thin film transistor liquid crystal display (TFT-LCD) array substrate are provided. The method of manufacturing the film pattern with micro-pattern comprises: depositing a thin film on a substrate; jetting or dropping etchant on the thin film with a predetermined etching pattern by an inkjet print device; etching the thin film by the etchant; and cleaning the thin film to form a film pattern on the substrate. | 2011-02-17 |
20110039363 | ORGANIC THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF - An organic thin film transistor array panel according to an embodiment of the present invention includes: a substrate; a data line disposed on the substrate; an insulating layer disposed on the data line and having a contact hole exposing the data line; a first electrode disposed on the insulating layer and connected to the data line through the contact hole; a second electrode disposed on the insulating layer; an organic semiconductor disposed on the first and the second electrodes; a gate insulator disposed on the organic semiconductor; and a gate electrode disposed on the gate insulator. | 2011-02-17 |
20110039364 | MANUFACTURING METHOD OF MICROSTRUCTURE - A manufacturing method of a microstructure which enables production of a deep and narrow microstructure in a GaN semiconductor with high precision is provided. The manufacturing method of a microstructure for forming a microscopic structure in a semiconductor has a configuration having a first step of forming a first GaN semiconductor layer on a substrate, a second step of forming a first hole by using etching on the first GaN semiconductor layer formed in the first narrow, and a third step of performing heat-treatment at a temperature from 850° C. to 950° C. inclusive under a gas atmosphere including nitrogen, in order to form a second narrow in which a diameter of the first hole h formed in the second step is made narrower than the diameter of the first hole in an in-plane direction of the substrate. | 2011-02-17 |
20110039365 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes: the step (a) of forming a vibrating film on a predetermined region of each of a plurality of chips included in a semiconductor wafer; the step (b) of forming, on the semiconductor wafer, an intermediate film containing a sacrifice layer located on the vibrating film of each of the chips; and the step (c) of forming a fixed film on the intermediate film. This method further includes, after the step (c), the step (d) of subjecting the semiconductor wafer to blade dicing to separate the chips, and the step (e) of removing, by etching, the sacrifice layer to provide a cavity between the vibrating film and the fixed film. | 2011-02-17 |
20110039366 | METHOD AND APPARATUS FOR DEPOSITION OF GRADED OR MULTI-LAYER TRANSPARENT FILMS - In one embodiment, a continuous electroless deposition method and a system to form a solar cell buffer layer with a varying composition through its thickness are provided. The composition of the buffer layer is varied by varying the composition of a chemical bath deposition solution applied onto an absorber surface on which the buffer layer with varying composition is formed. In one example, the buffer layer with varying composition includes a first section containing CdS, a second section containing CdZnS formed on top of the already deposited CdS, and a third section containing ZnS is formed on the second section All the process steps are applied in a roll-to-roll fashion. In another embodiment, a transparent conductive layer including a first transparent conductive film such as aluminum doped zinc oxide and a second transparent conductive film such as indium tin oxide is deposited over the buffer layer with the varying composition. | 2011-02-17 |
20110039367 | MASKED ION IMPLANT WITH FAST-SLOW SCAN - An improved method of producing solar cells utilizes a mask which is fixed relative to an ion beam in an ion implanter. The ion beam is directed through a plurality of apertures in the mask toward a substrate. The substrate is moved at different speeds such that the substrate is exposed to an ion dose rate when the substrate is moved at a first scan rate and to a second ion dose rate when the substrate is moved at a second scan rate. By modifying the scan rate, various dose rates may be implanted on the substrate at corresponding substrate locations. This allows ion implantation to be used to provide precise doping profiles advantageous for manufacturing solar cells. | 2011-02-17 |
20110039368 | METHODS FOR MAKING SUBSTRATES AND SUBSTRATES FORMED THEREFROM - A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving substrate and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition. | 2011-02-17 |
20110039369 | PROCESS FOR PRODUCING SEMICONDUCTIVE PORCELAIN COMPOSITION/ELECTRODE ASSEMBLY - A semiconductive porcelain composition/electrode assembly which is low in room temperature resistivity of 100 Ω·cm or less and is reduced in change with the passage of time due to energization with regard to the semiconductive porcelain composition in which a part of Ba of BaTiO | 2011-02-17 |
20110039370 | Electronic parts packaging structure and method of manufacturing the same - In an electronic parts packaging structure of the present invention constructed by stacking a plurality of sheet-like units in a thickness direction, each of the units includes a first insulating layer, wirings formed on one surface of the first insulating layer, a semiconductor chip (electronic parts) connected to the wirings, a second insulating layer formed on an one surface side of the first insulating layer to cover the semiconductor chip, and connecting portions (terminals and contact vias) for connecting electrically the wirings and wirings of other unit, wherein arrangement of the first insulating layer, the semiconductor chip, the wirings, and the second insulating layer is symmetrical between units adjacent in a thickness direction. | 2011-02-17 |
20110039371 | FLIP CHIP CAVITY PACKAGE - A process for forming a semiconductor package. The process comprises forming a first leadframe strip mounted upon an adhesive tape. The first leadframe strip is at least partially encased in a first mold compound thereby forming a molded leadframe strip. At least one flip chip semiconductor device is mounted on the molded leadframe strip. The semiconductor device has conductive masses attached thereon to effectuate electrical contact between the semiconductor device and the molded leadframe. The conductive masses can be substantially spherical or cylindrical. Liquid encapsulant is dispensed on the semiconductor device to encapsulate the flip chip semiconductor device. A cavity is formed between the semiconductor device and the molded leadframe. The molded leadframe strip, the semiconductor device, and the conductive masses are at least partially encased in a second mold compound. The second mold compound can be molded so that a surface of the flip chip semiconductor device that is not attached to the molded leadframe is substantially exposed or molded to produce a globular form on the flip chip semiconductor device. The molded leadframe strip is singulated to form discrete semiconductor packages. | 2011-02-17 |
20110039372 | MEMS PACKAGE AND A METHOD FOR MANUFACTURING THE SAME - A method is provided for manufacturing a plurality of packages. The method comprises the steps of: applying a means for adhering two or more covers to a substrate; positioning the two or more covers onto the substrate to create one or more channels bounded by the two or more covers and the substrate; coupling the covers to the substrate; depositing a material into the one or more channels; performing a process on the material to affix the material; and singulating along the channels to create the plurality of packages. | 2011-02-17 |
20110039373 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The present invention provides a thin and bendable semiconductor device utilizing an advantage of a flexible substrate used in the semiconductor device, and a method of manufacturing the semiconductor device. The semiconductor device has at least one surface covered by an insulating layer which serves as a substrate for protection. In the semiconductor device, the insulating layer is formed over a conductive layer serving as an antenna such that the value in the thickness ratio of the insulating layer in a portion not covering the conductive layer to the conductive layer is at least 1.2, and the value in the thickness ratio of the insulating layer formed over the conductive layer to the conductive layer is at least 0.2. Further, not the conductive layer but the insulating layer is exposed in the side face of the semiconductor device, and the insulating layer covers a TFT and the conductive layer. In addition, a substrate covering an element formation layer side is a substrate having a support on its surface is used in the manufacturing process. | 2011-02-17 |
20110039374 | METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A BUMP/BASE HEAT SPREADER AND A CAVITY IN THE BUMP - A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The heat spreader includes a bump, a base and a flange. The conductive trace includes a pad and a terminal. The semiconductor device extends into a cavity in the bump, is electrically connected to the conductive trace and is thermally connected to the bump. The bump extends from the base into an opening in the adhesive, the base extends vertically from the bump opposite the cavity and the flange extends laterally from the bump at the cavity entrance. The conductive trace is located outside the cavity and provides signal routing between the pad and the terminal. | 2011-02-17 |
20110039375 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To aim at improvement of reliability of a semiconductor device of flip chip connection type. | 2011-02-17 |
20110039376 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A high positional accuracy of a semiconductor chip is attained to stabilize the quality of a semiconductor device. In a die bonding process during assembly of an SIP, a microcomputer chip not required to have a high positional accuracy is picked up with a surface non-contact type collet and is die-bonded onto a first chip mounting portion, thereafter, an ASIC chip required to have a high positional accuracy is picked up with a surface contact type collet and die-bonded onto a second chip mounting portion. By thus using two types of collets properly, not only a high positional accuracy of the ASIC chip which has been die-bonded with the surface contact type collet is attained, but also the quality of the SIP is stabilized. | 2011-02-17 |
20110039377 | Semiconductor on Insulator - A method and apparatus for producing a relatively thin, relatively uniform semiconductor layer which has improved carrier mobility. In an embodiment, a lattice-matched insulator layer is formed on a semiconductor substrate, and a lattice-matched semiconductor layer is formed on the insulator layer to form a relatively thin, relatively uniform semiconductor on insulator apparatus. In embodiments of the method and apparatus, energy band characteristics may be used to facilitate the extraction of the well-region minority carriers. | 2011-02-17 |
20110039378 | METHOD OF FABRICATING ESD DEVICES USING MOSFET AND LDMOS ION IMPLANTATIONS - A method of forming complementary metal-oxide-silicon logic field effect transistors, high power transistors and electrostatic discharge protection diodes and/or electrostatic discharge protection shunt transistors on the same integrated circuit chip using ion implantations used to fabricate the field effect transistors and high-power transistor to simultaneously fabricate the electrostatic discharge protection diodes and/or electrostatic discharge protection shunt transistors. | 2011-02-17 |
20110039379 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: an isolation region formed in a semiconductor substrate; active regions surrounded by the isolation region and including p-type and n-type regions, respectively; an NMOS transistor formed in the active region including the p-type region and including an n-type gate electrode; a PMOS transistor formed in the active region including the n-type region and including a p-type gate electrode; and a p-type resistor formed on the isolation region. The p-type resistor has an internal stress greater than that of the p-type gate electrode. | 2011-02-17 |
20110039380 | Method for Forming a Floating Gate Non-Volatile Memory Cell - Method for manufacturing a non-volatile memory comprising at least one array of memory cells on a substrate of a semiconductor material, the memory cells being self-aligned to and separated from each other by STI structures, the memory cells comprising a floating gate having an inverted-T shape in a cross section along the array of memory cells, wherein the inverted T shape is formed by oxidizing an upper part of the sidewalls of the floating gates thereby forming sacrificial oxide, and subsequently removing the sacrificial oxide simultaneously with further etching back the STI structures. | 2011-02-17 |
20110039381 | Semiconductor Devices Semiconductor Pillars and Method of Fabricating the Same - A semiconductor device includes a trench isolation region provided on a substrate and defining first and second active regions separated from each other. A first semiconductor pillar protruding upward from the first active region is provided. A second semiconductor pillar protruding upward from the second active region is provided. A first gate mask extending to cross over the first and second active regions is provided. The first gate mask surrounds upper sidewalls of the first and second semiconductor pillars. A first gate line formed below the first gate mask, separated from the first and second active regions, and surrounding parts of sidewalls of the first and second semiconductor pillars is provided. | 2011-02-17 |
20110039382 | Semiconductor device and method for manufacturing the same - A semiconductor device including a plurality of units having identical structures, each unit includes: a drain electrode; a drift layer that includes a low concentration layer on the drain electrode and a reference concentration layer on the low concentration layer, a gate electrode on the reference concentration layer; a pair of source regions that are provided on an upper surface of the reference concentration layer and in the vicinity of both ends of the gate electrode; a pair of base regions that surround outer surfaces of the source regions; a source electrode electrically connected to the source regions and the base regions; and a pair of depletion-layer extension regions that are respectively provided under the base regions in the reference concentration region. Boundaries between the depletion-layer extension regions and the low concentration layer are positioned lower than a boundary between the reference concentration layer and the low concentration layer. | 2011-02-17 |
20110039383 | Shielded gate trench MOSFET device and fabrication - A method for fabricating a semiconductor device includes forming a plurality of trenches, including applying a first mask, forming a first polysilicon region in at least some of the plurality of trenches, forming a inter-polysilicon dielectric region and a termination protection region, including applying a second mask, forming a second polysilicon region in the at least some of the plurality of trenches, forming a first electrical contact to the first polysilicon region and forming a second electrical contact to the second polysilicon region, including applying a third mask, disposing a metal layer, and forming a source metal region and a gate metal region, including applying a fourth mask. | 2011-02-17 |
20110039384 | Power MOSFET With Recessed Field Plate - A trench MOSFET contains a recessed field plate (RFP) trench adjacent the gate trench. The RFP trench contains an RFP electrode insulated from the die by a dielectric layer along the walls of the RFP trench. The gate trench has a thick bottom oxide layer, and the gate and RFP trenches are preferably formed in the same processing step and are of substantially the same depth. When the MOSFET operates in the third quadrant (with the source/body-to-drain junction forward-biased), the combined effect of the RFP and gate electrodes significantly reduces in the minority carrier diffusion current and reverse-recovery charge. The RFP electrode also functions as a recessed field plates to reduce the electric field in the channel regions when the MOSFET source/body to-drain junction reverse-biased. | 2011-02-17 |
20110039385 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and a memory gate electrode formed via a second dielectric film formed of an ONO multilayered film having a charge storing function. The first dielectric film functions as a gate dielectric film, and includes a third dielectric film made of silicon oxide or silicon oxynitride and a metal-element-containing layer made of a metal oxide or a metal silicate formed between the select gate electrode and the third dielectric film. A semiconductor region positioned under the memory gate electrode and the second dielectric film has a charge density of impurities lower than that of a semiconductor region positioned under the select gate electrode and the first dielectric film. | 2011-02-17 |
20110039386 | LATERAL POCKET IMPLANT CHARGE TRAPPING DEVICES - A charge trapping memory cell is described, having pocket implants along the sides of the channel and having the same conductivity type as the channel, and which implants have a concentration of dopants higher than in the central region of the channel. This effectively disables the channel in the region of non-uniform charge trapping caused by a bird's beak or other anomaly in the charge trapping structure on the side of the channel. The pocket implant can be formed using a process compatible with standard shallow trench isolation processes. | 2011-02-17 |
20110039387 | Fully Isolated High-Voltage MOS Device - A semiconductor structure includes a semiconductor substrate; an n-type tub extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the n-type tub comprises a bottom buried in the semiconductor substrate; a p-type buried layer (PBL) on a bottom of the tub, wherein the p-type buried layer is buried in the semiconductor substrate; and a high-voltage n-type metal-oxide-semiconductor (HVNMOS) device over the PBL and within a region encircled by sides of the n-type tub. | 2011-02-17 |
20110039388 | Multi-Thickness Semiconductor With Fully Depleted Devices And Photonic Integration - Techniques are disclosed that facilitate fabrication of semiconductors including structures and devices of varying thickness. One embodiment provides a method for semiconductor device fabrication that includes thinning a region of a semiconductor wafer upon which the device is to be formed thereby defining a thin region and a thick region of the wafer. The method continues with forming on the thick region one or more photonic devices and/or partially depleted electronic devices, and forming on the thin region one or more fully depleted electronic devices. Another embodiment provides a semiconductor device that includes a semiconductor wafer defining a thin region and a thick region. The device further includes one or more photonic devices and/or partially depleted electronic devices formed on the thick region, and one or more fully depleted electronic devices formed on the thin region. An isolation area can be formed between the thin region and the thick region. | 2011-02-17 |
20110039389 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Provided is a manufacturing method of a semiconductor device, the manufacturing method including forming a first thin film on a substrate; forming a second thin film, which is different from the first thin film, on the first thin film; forming a sacrificial film, which is a film different from the second thin film, on the second thin film; forming a sacrificial film pattern by processing the sacrificial film into a pattern having desired intervals through etching; coating a silicon oxide film on the sacrificial film pattern by intermittently supplying a silicon-containing precursor and an oxygen-containing gas onto the substrate; forming sidewall spacers on the sidewalls of the sacrificial film by etching the silicon oxide film; removing the sacrificial film; and processing the first film and the second film by using the sidewall spacers as a mask. | 2011-02-17 |
20110039390 | Reducing Local Mismatch of Devices Using Cryo-Implantation - A method of forming an integrated circuit includes providing a semiconductor wafer, and forming a metal-oxide-semiconductor (MOS) device. The step of forming the MOS device includes forming a gate stack on the semiconductor wafer, and performing a cryo-implantation to form an implantation region adjacent the gate stack at a wafer temperature lower than 0° C. The step of performing the cryo-implantation is selected from the group consisting essentially of implanting the semiconductor wafer to form a pre-amorphized implantation (PAI) region; implanting the semiconductor wafer to form a lightly-doped source/drain region; implanting the semiconductor wafer to form a pocket/halo region; implanting the semiconductor wafer to form a deep source/drain region, and combinations thereof | 2011-02-17 |
20110039391 | Fabricating Bipolar Junction Select Transistors for Semiconductor Memories - A bipolar junction transistor may act as a select device for a semiconductor memory. The bipolar junction transistor may be formed of a stack of base and collector layers. Sets of parallel trenches are formed in a first direction down to the base and in a second direction down to the collector. The trenches may be used to form local enhancement implants into the exposed portion of the base and collector in each trench. As a result of the local enhancement implants, in some embodiments, leakage current may be reduced, active current capability may be higher, gain may be higher, base resistance may be reduced, breakdown voltage may be increased, and parasitic effects with adjacent junctions may be reduced. | 2011-02-17 |
20110039392 | SEMICONDUCTOR DEVICE WITH RESISTOR AND FUSE AND METHOD OF MANUFACTURING THE SAME - A fuse element is laminated on a resistor and the resistor is formed in a concave shape below a region in which cutting of the fuse element is carried out with a laser. Accordingly, there can be provided a semiconductor device which occupies a small area, causes no damage on the resistor in the cutting of the fuse element, has a small contact resistance occurred between elements, and has stable characteristics, and a method of manufacturing the same. | 2011-02-17 |
20110039393 | METHOD OF FABRICATING A SEMICONDUCTOR MICROSTRUCTURE - Provided is a method of fabricating a semiconductor microstructure, the method including forming a lower material layer on a semiconductor substrate, the lower material layer including a nitride of a Group III-element; forming a mold material layer on the lower material layer; forming an etching mask on the mold material layer, the etching mask being for forming a structure in the mold material layer; anisotropic-etching the mold material layer and the lower material layer by using the etching mask; and isotropic-etching the mold material layer and the lower material layer. | 2011-02-17 |
20110039394 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To provide a manufacturing method of a semiconductor device in which manufacturing cost can be reduced, and a manufacturing method of a semiconductor device with reduced manufacturing time and improved yield. A manufacturing method of a semiconductor device is provided, which includes the steps of forming a first layer containing a metal over a substrate, forming a second layer containing an inorganic material on the first layer, forming a third layer including a thin film transistor on the second layer, irradiating the first layer, the second layer, and the third layer with laser light to form an opening portion through at least the second layer and the third layer. | 2011-02-17 |
20110039395 | METHOD FOR MANUFACTURING SOI SUBSTRATE - To improve bonding strength and improve reliability of an SOI substrate in bonding a semiconductor substrate and a base substrate to each other even when an insulating film containing nitrogen is used as a bonding layer, an oxide film is provided on the semiconductor substrate side, a nitrogen-containing layer is provided on the base substrate side, and the oxide film formed on the semiconductor substrate and the nitrogen-containing layer formed over the base substrate are bonded to each other. Further, plasma treatment is performed on at least one of the oxide film and the nitrogen-containing layer before bonding the oxide film formed on the semiconductor substrate and the nitrogen-containing layer formed over the base substrate to each other. Plasma treatment can be performed in a state in which a bias voltage is applied. | 2011-02-17 |
20110039396 | Semiconductor device and method of fabricating semiconductor device - A method of fabricating a semiconductor device from a semiconductor wafer, having external connecting terminals on one side of the semiconductor wafer and a cover layer on another side of the semiconductor wafer, includes forming a groove with a first width from the one side to at least an interface between the semiconductor wafer and the cover layer in the semiconductor wafer, and cutting the cover layer with a second width from a bottom side of the groove. The second width is narrower than the first width. | 2011-02-17 |
20110039397 | Structures and methods to separate microchips from a wafer - Structures and methods for separating chips or ICs from a wafer are disclosed. To save area and manufacturing costs, deep trench formation combining with mechanical bending or lateral etch is used to separate chips or ICs from a wafer. | 2011-02-17 |
20110039398 | EFFICIENT POWER MANAGEMENT METHOD IN INTEGRATED CIRCUIT THROUGH A NANOTUBE STRUCTURE - Efficient power management method in integrated circuit through a nanotube structure is disclosed. In one embodiment, a method includes patterning a nanotube structure adjacent to a transistor layer of an integrated circuit. The transistor layer may be above a semiconductor substrate. The transistor layer above the semiconductor substrate may comprise a plurality of transistors. The method also includes supplying power to the plurality of transistors through one or more power sources. In addition, the method includes coupling the plurality of transistors in the transistor layer to the one or more power sources based on a state of the nanotube structure. | 2011-02-17 |
20110039399 | MANUFACTURING APPARATUS AND METHOD FOR SEMICONDUCTOR DEVICE - A manufacturing apparatus for a semiconductor device includes: a chamber configured to load a wafer into the chamber; a gas supplying mechanism configured to supply processed gas into the chamber; a gas discharging mechanism configured to discharge the gas from the chamber; a wafer supporting member configured to mount the wafer; a heater including a heater element configured to heat the wafer up to a predetermined temperature and a heater electrode molded integrally with the heater element; an electrode part connected to the heater electrode and configured to applied a voltage to the heater element via the heater electrode; a base configured to fix the electrode part; and a rotational drive control mechanism configured to rotate the wafer; wherein at least a part of a connection portion of the heater electrode and the electrode part is positioned under the upper surface of the base. | 2011-02-17 |
20110039400 | METHOD FOR FABRICATING GaNAsSb SEMICONDUCTOR - Disclosed is a method for fabrication of a semiconductor of gallium nitride arsenide antimonide (GaNAsSb) on a substrate wherein the fabrication is performed at a fabrication temperature followed by annealing at an annealing temperature for an annealing time; wherein at least one of: | 2011-02-17 |
20110039401 | Apparatus and Method for Depositing a Material on a Substrate - Apparatus and a method for depositing a material on a substrate utilizes a distributor including a permeable member through which a carrier gas and a material are passed to provide a vapor that is deposited on a conveyed substrate. A secondary gas can be provided to promote uniform distribution of the material on the substrate. | 2011-02-17 |
20110039402 | METHOD FOR MANUFACTURING MICROCRYSTALLINE SEMICONDUCTOR FILM AND THIN FILM TRANSISTOR - A microcrystalline semiconductor film with high crystallinity is manufactured. In addition, a thin film transistor with excellent electric characteristics and high reliability, and a display device including the thin film transistor are manufactured with high productivity. A deposition gas containing silicon or germanium is introduced from an electrode including a plurality of projecting portions provided in a treatment chamber of a plasma CVD apparatus, glow discharge is caused by supplying high-frequency power, and thereby crystal particles are formed over a substrate, and a microcrystalline semiconductor film is formed over the crystal particles by a plasma CVD method. | 2011-02-17 |
20110039403 | Method for Implanting Ions In Semiconductor Device - The present invention provides various methods for implanting ions in a semiconductor device that substantially compensate for a difference in threshold voltages between a central portion and edge portions of a substrate generated while performing uniform ion implantation to entire surfaces of a substrate. Other methods for fabricating a semiconductor device improve distribution of transistor parameters across a substrate by forming a nonuniform channel doping layer or by forming a nonuniform junction profile, across the substrate. | 2011-02-17 |
20110039404 | Methods of Forming a Plurality of Transistor Gates, and Methods of Forming a Plurality of Transistor Gates Having at Least Two Different Work Functions - A method of forming a plurality of transistor gates having at least two different work functions includes forming first and second transistor gates over a substrate having different widths, with the first width being narrower than the second width. A material is deposited over the substrate including over the first and second gates. Within an etch chamber, the material is etched from over both the first and second gates to expose conductive material of the first gate and to reduce thickness of the material received over the second gate yet leave the second gate covered by the material. In situ within the etch chamber after the etching, the substrate is subjected to a plasma comprising a metal at a substrate temperature of at least 300° C. to diffuse said metal into the first gate to modify work function of the first gate as compared to work function of the second gate. | 2011-02-17 |
20110039405 | METHOD FOR FABRICATING A SONOS MEMORY - The present invention provides a method for making SONOS memory, comprising the following steps: depositing silicon oxide layer and silicon oxynitride layer in sequence on underlayer; coating a layer of photoresist on the silicon oxynitride layer; removing part of the photoresist and form the logic area; removing silicon oxynitride layer in the logic area; removing the bottom oxide layer in the logic area; growing top oxide layer on the silicon oxynitride layer and logic area; removing the top oxide layer in the logic area; growing gate oxide layer; forming device structure of SONOS and logic area. The present invention can avoid the damage of top oxide layer and lateral etching in wet etching so as to improve the defect-free rate of devices. | 2011-02-17 |
20110039406 | Methods of Etching Nanodots, Methods of Removing Nanodots From Substrates, Methods of Fabricating Integrated Circuit Devices, Methods of Etching a Layer Comprising a Late Transition Metal, and Methods of Removing a Layer Comprising a Late Transition Metal From a Substrate - Embodiments of the invention include methods of etching nanodots, to methods of removing nanodots from substrates, and to methods of fabricating integrated circuit devices. In one embodiment, a method of etching nanodots that include a late transition metal includes exposing such nanodots to a gas comprising a phosphorus and halogen-containing compound and an oxidizing agent. After the exposing, the nanodots which are remaining and were exposed are etched (either partially or completely) with an aqueous solution comprising HF. | 2011-02-17 |
20110039407 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method, the method including: forming an insulation layer having a protruding portion, the insulation layer having a surface and a rising surface that protrudes upward from the surface, on a semiconductor substrate; forming a conductive layer to cover the insulation layer having the protruding portion; and removing a predetermined region of the conductive layer by patterning the predetermined region according to an etching process using microwave plasma, which uses a microwave as a plasma source, while applying bias power of 70 mW/cm | 2011-02-17 |
20110039408 | Semiconductor Device and Fabrication Method Thereof - Semiconductor devices and methods for fabricating the same. The devices includes a substrate, a first etch stop layer, a dielectric layer, an opening, and an anti-diffusion layer. The first etch stop layer overlies the substrate. The dielectric layer overlies the first etch stop layer. The opening extends through the dielectric layer and the first etch stop layer, and exposes parts of the substrate. The anti-diffusion layer overlies at least sidewalls of the opening, preventing contamination molecule diffusion from at least the first etch stop layer, wherein the anti-diffusion layer is respectively denser than the first etch stop layer and the dielectric layer. | 2011-02-17 |
20110039409 | METHOD OF DESIGNING SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a capacitor including a lower electrode and a upper electrode, and a capacitive film formed therebetween; a first via group including one or more first vias which is electrically connected to the lower electrode; and a second via group including one or more second vias which is electrically connected to the upper electrode and formed simultaneously with the first via group. The semiconductor device is designed by a method including a step of setting the number of the first vias and the second vias so that a value obtained by dividing a capacitance value of the capacitor by the total number of the first vias and the second vias included in the first via group and the second via group is set to be equal to or less than a predetermined value. | 2011-02-17 |
20110039410 | Apparatus and Method for Substrate Electroless Plating - A substrate is secured on a chuck that maintains a top surface of the substrate in a substantially level orientation. The chuck is positioned within a cavity of a vessel such that a body portion of the chuck is maintained in a spaced apart relationship with a surface of the cavity. An electroless plating solution is disposed in a region between the body portion of the chuck and the surface of the cavity such that an upper surface of the electroless plating solution is at a level lower than the substrate. The chuck is lowered within the cavity to cause the electroless plating solution to be displaced upward and flow over the top surface of the substrate in a substantially uniform manner from a periphery of the substrate to a center of the substrate. The chuck is then raised such that the electroless plating solution flows off of the substrate. | 2011-02-17 |
20110039411 | Method For Producing A Polished Semiconductor Wafer - A polished semiconductor wafer of high flatness is produced by the following ordered steps:
| 2011-02-17 |
20110039412 | CHEMICAL MECHANICAL POLISHING SLURRY COMPOSITION INCLUDING NON-IONIZED, HEAT ACTIVATED NANO-CATALYST AND POLISHING METHOD USING THE SAME - Disclosed herein are a chemical mechanical polishing slurry composition for chemical mechanical planarization of metal layers, which comprises a non-ionized, heat-activated nano-catalyst, and a polishing method using the same. The polishing slurry composition comprises: a non-ionized, heat-activated nano-catalyst which releases electrons and holes by energy generated in a chemical mechanical polishing process; an abrasive; and an oxidizing agent. The non-ionized, heat-activated nano-catalyst and the abrasive are different from each other, and the non-ionized, heat-activated nano-catalyst is preferably a semiconductor material which releases electrons and holes at a temperature of 10 to 100° C. in an aqueous solution state, more preferably a transition metal silicide selected from the group consisting of CrSi, MnSi, CoSi, ferrosilicon (FeSi), mixtures thereof, and most preferably, a semiconductor material such as nano ferrosilicon. The content of the content of the non-ionized, heat-activated nano-catalyst is 0.00001 to 0.1 wt % based on the total weight of the slurry composition. | 2011-02-17 |
20110039413 | METHOD FOR FORMING TRENCHES HAVING DIFFERENT WIDTHS AND THE SAME DEPTH - A lithographic material stack including a photo-resist and an organic planarizing layer is combined with an etch process that generates etch residues over a wide region from sidewalls of etched regions. By selecting the etch chemistry that produces deposition of etch residues from the organic planarizing layer over a wide region, the etch residue generated at the sidewalls of the wide trench is deposited over the entire bottom surface of the wide trench. An etch residue portion remains at the bottom surface of the wide trench when the organic planarizing layer is etched through in the first trench region. The etch residue portion is employed in the next step of the etch process to retard the etch rate in the wide trench, thereby producing the same depth for all trenches in the material layer into which the pattern of the lithographic material stack is transferred. | 2011-02-17 |
20110039414 | PLASMA PROCESSING METHOD AND PLASMA PROCESSING APPARATUS - An upper electrode | 2011-02-17 |
20110039415 | METHOD OF FABRICATING DUAL DAMASCENE STRUCTURE - A semiconductor wafer includes a substrate, a conductive layer, a dielectric layer having a via, a hard mask defined a trench pattern, and a sacrificial layer. Then a sequential of etching processes is performed upon the semiconductor wafer in a chamber to form a trench and expose the conductive layer. By operating all procedures within one chamber, manufacturing time is efficiently shortened and yield is thus increased. | 2011-02-17 |
20110039416 | Method for patterning an ARC layer using SF6 and a hydrocarbon gas - A method of pattern etching a Si-containing anti-reflective coating (ARC) layer is described. The method comprises etching a feature pattern into the silicon-containing ARC layer using plasma formed from a process gas containing SF | 2011-02-17 |
20110039417 | PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - A dielectric board ( | 2011-02-17 |
20110039418 | METHOD FOR INSULATING FILM FORMATION, STORAGE MEDIUM FROM WHICH INFORMATION IS READABLE WITH COMPUTER, AND TREATMENT SYSTEM - In order to form an insulating film, which constitutes a flat interface with silicon, by CVD, a surface of silicon is oxidized to form a silicon oxide film using a plasma treatment apparatus in which microwaves are introduced into a chamber through a flat antenna having a plurality of holes. A silicon oxide film is formed as an insulating film on the silicon oxide film by CVD. Further, in the plasma treatment apparatus, a treating gas containing a noble gas and oxygen is introduced into the chamber, and, further, microwaves are introduced into the chamber through the flat antenna. Plasma is generated under a pressure in the range of not less than 6.7 Pa and not more than 533 Pa to modify the insulating film with the plasma. | 2011-02-17 |
20110039419 | METHODS FOR FORMING DIELECTRIC LAYERS - Methods for forming a dielectric layer on a substrate are provided herein. In some embodiments a method for forming a dielectric layer on a substrate may include exposing the substrate to a first source gas comprising a silicon (Si) precursor and an oxidizer for a first period of time to form a first layer comprising silicon and oxygen; and exposing the substrate to a second source gas comprising a metal precursor and the silicon precursor for a second period of time to form a second layer comprising silicon and a metal, where in the first layer and the second layer form the dielectric layer. | 2011-02-17 |
20110039420 | FILM FORMING APPARATUS AND FILM FORMING METHOD - A wall surface of a film forming container is heated to or above a vaporization temperature of a material monomer, which is used to form an organic film, by using an external heater formed along the wall surface of the film forming container, substrates are heated to a thermal polymerization reaction temperature by using an internal heater that is disposed apart from the external heater and near a substrate-supporting container in which the substrates are received, and the organic film is formed through thermal polymerization occurring on the substrates by supplying the material monomer into the film forming container. | 2011-02-17 |
20110039421 | HEAT TREATMENT METHOD - A heat treatment method which can prevent heat deformation of a substrate caused during a heat treatment process on the substrate with a thin film formed on its surface is provided. The heat treatment method in accordance with the present invention includes (a) stacking a second substrate | 2011-02-17 |
20110039422 | TERMINAL BLOCK AND BOARD ASSEMBLY FOR AN ELECTRICAL CONNECTOR - A terminal block for electrically coupling conductors and terminal contacts. The terminal block includes a terminal base portion that has a mounting side configured to be mounted to a surface of an electrical component. The base portion has contact slots that extend from the mounting side therethrough. The contact slots are configured to receive terminal contacts that are electrically coupled to the electrical component. The terminal block also includes an organizer portion that extends from the base portion and includes channels that extend substantially parallel to the surface of the electrical component. The channels are configured to receive corresponding conductors. The contact slots of the base portion align with corresponding channels of the organizer portion so that the terminal contacts electrically couple the conductors. | 2011-02-17 |
20110039423 | MULTI-PORT CONNECTOR SYSTEM - An electrical connector assembly includes a housing, a connector and a conductor. The housing extends from a mating interface to a back end along a longitudinal axis and from a top side to a mounting interface along a vertical axis. The connector is disposed at the mating interface and is configured to mate with a mating connector. The conductor extends from the electrical connector to the mounting interface to provide a conductive pathway between the mating connector and the circuit board. The conductor includes a mating portion oriented along the longitudinal axis and a mounting portion oriented along the vertical axis. One of the mating portion and the mounting portion includes a bifurcated end having opposing contact tips and the other of the mating portion and the mounting portion includes an interconnection end that is received between the contact tips to electrically couple the mating portion and the mounting portion. | 2011-02-17 |
20110039424 | MINIATURE ELECTRICAL SOCKET ASSEMBLY WITH SELF-CAPTURING MULTIPLE-CONTACT-POINT COUPLING - A socket assembly formed of hollow tubes for connecting an array of terminals off opposing electronic structures with both axial and lateral resilience, wherein the resilience is achieved through angular cuts in the tubes. | 2011-02-17 |
20110039425 | BURN-IN SOCKET ASSEMBLY WITH BASE HAVING PROTRUDING STRIPS - A burn-in socket assembly comprises a base, a loading member and a plurality of contacts. The base has a bottom wall, a plurality of sidewalls and a cavity surrounded by the bottom wall and the sidewalls, the bottom wall defines a plurality of contact receiving holes. The loading member is assembled within the base for loading an integrated circuit package and defines a plurality of passageways corresponding to the contact receiving holes of the base. The contacts are received in the contact receiving holes of the base and the passageways of the loading member. The bottom wall is further formed with a plurality of protruding strips on a top surface thereof and between two adjacent rows of the contact receiving holes to support the loading member. | 2011-02-17 |
20110039426 | USB Application Device - An USB application device includes a casing and a printed circuit board received in the casing. The printed circuit board includes a top surface disposed a plurality of contacts, and a bottom surface disposed a plurality of electrical elements. A first supporting portion is received in the casing and located between the bottom surface of the printed circuit board and the casing, which supports the printed circuit board and is in front of all the electrical elements and abuts against up front one of the electrical elements disposed on the bottom surface of the printed circuit board. Therefore, the first supporting portion supports a central portion of the printed circuit board to resist an external pressing force in order to prevent the printed circuit board from damage. Furthermore, the first supporting portion positions the printed circuit board during the fabricating procedure of the USB application device. | 2011-02-17 |
20110039427 | FEMALE CONNECTOR, MALE CONNECTOR ASSEMBLED TO THE SAME, AND ELECTRIC/ELECTRONIC APPARATUS USING THEM - A female connector which is useful for space saving and height reduction of a connector connection portion is a female connector including: an insulating film having flexibility; a plurality of pad portions formed at predetermined positions on one face of the insulating film in an arranged manner; female terminal portions composed of openings formed at one lateral portions within faces of the pad portions so as to extend up to the other face of the insulating film; and spacer bumps formed at positions corresponding to the other lateral positions within the faces of the pad portions in a standing manner within the other face of the insulating film, proximal portions of the spacer bumps being electrically connected to the pad portions. | 2011-02-17 |
20110039428 | PRESS-IN CONTACT HAVING A BASE, A CONTACT PIN AND A SECOND PIN - A press-in contact having a base, a contact pin and a second pin which extends parallel to the contact pin. The second pin projects beyond the contact pin and has a greatest circumference at the same level as a tip of the contact pin. Simple and accurate positioning between a circuit board and a contact pin disposed in a housing is made possible by the second pin which acts as a pre-centering pin. | 2011-02-17 |
20110039429 | CONNECTOR WITH REINFORCED MOUNTING STRUCTURE AND METHOD OF MANUFACTURING CONNECTOR - A connector includes a wiring board; a lead connecting the wiring board electrically to an external board; and a conductive layer connecting the lead to the wiring board so as to allow the lead to move when the conductive layer is melted. The lead includes first through third regions. The first region, in contact with the conductive layer, is sandwiched between the second and third regions lower in wettability with respect to the liquid melt of the conductive layer than the first region. The wiring board includes a first region and second regions. The first region, in contact with the conductive layer, is sandwiched between the second regions lower in wettability with respect to the liquid melt than the first region. The center of the first region of the lead is offset and away from the external board relative to the center of the first region of the wiring board. | 2011-02-17 |
20110039430 | FASTENING ASSEMBLY AND METHOD - A fastening and grounding apparatus adapted to be positioned against a channel of a metallic support frame member. A metallic bolt has a threaded shaft and an enlarged head portion at one end thereof. A metallic leaf spring has a central portion and a pair of opposing end portions, with the threaded shaft extending through the hole. At least one of the opposing end portions has a tooth projecting therefrom. The metallic leaf spring maintains the threaded shaft in an upright orientation extending from the channel. The tooth digs into a surface of the metallic support frame member to effect an electrical current signal path through the fastening apparatus to the metallic support frame member. | 2011-02-17 |
20110039431 | ELECTRICAL GROUNDING DEVICE AND SYSTEM - An electrical grounding device includes a first collar member having first inner and outer wall surfaces, a first flange projecting from the first inner wall surface, and a first shoulder projection extending radially from the first outer wall surface. The device further includes a second collar member having second inner and outer wall surfaces, a second flange projecting from the second inner wall surface, and a second shoulder projection extending radially from the second outer wall surface. Further, the device includes a thickened wall region including an aperture passing transversely therethrough, wherein the thickened wall region is disposed in the outer wall surface of at least one of the first and second collar members. A fastener is operably associated with the first and second shoulder projections to removably couple the first and second shoulder projections together. Such coupling configures the first and second inner wall surfaces to define an opening disposed through the electrical grounding device. | 2011-02-17 |
20110039432 | POWER SUPPLY SYSTEM AND ELETRICAL PLUG CONNECTOR - A power supply system for the internal power supply of a supporting mast of a wind power installation is provided in order to assist the work of servicing personnel in a wind power installation. The power supply system includes a power bus line, at least one tap on the power bus line for tapping off an electrical potential, and an electrical appliance connected to the tap. The electrical appliance is both electrically connected and mechanically adapted to the tap. An electrical plug connector is also provided. | 2011-02-17 |
20110039433 | PRODUCT STRUCTURE WITH EJECTOR - A product structure includes a base and an ejector including a core, a sliding sheet, a guiding rod and an elastic member. The core has a sliding slot, which has a circulating path, one end formed with a positioning point, the other end formed with a starting point, and a bottom surface formed with unidirectional stopper blocks, so that the path unidirectionally circulates from the starting point sequentially to the positioning point and to the starting point. The sliding sheet having a pushing portion may slide back and forth relatively to the base. The rod has one end engaged with the slot and can slide along the path. The elastic member provides an elastic force for returning the sliding sheet, after being moved into the base, to a home position. The core has a seat and a metal baseplate, which is engaged with the seat and has the stopper blocks. | 2011-02-17 |