07th week of 2022 patent applcation highlights part 49 |
Patent application number | Title | Published |
20220051652 | NOISE MANAGEMENT DURING AN ONLINE CONFERENCE SESSION - Managing noise during an online conference session includes obtaining audio data from an endpoint participating in an online conference session. The audio data is derived from audio captured at the endpoint that includes musical sounds. The audio data is processed to identify a portion of the audio data in which a decibel level of the musical sounds is stable for a period of time. Non-musical noise present, if any, in the audio data with the musical sounds is identified and the non-musical noise is attenuated from the audio data to generate noise-reduced musical audio data. The noise-reduced musical audio data is transmitted for play out at one or more other endpoints participating in the online conference session. | 2022-02-17 |
20220051653 | ENGINE SOUND ENHANCEMENT - Methods, systems, devices and apparatuses for a sound enhancement system. The sound enhancement system includes an airflow sensor. The airflow sensor is configured to measure an airflow into an engine of the vehicle. The sound enhancement system includes an electronic control unit. The electronic control unit is coupled to the airflow sensor. The electronic control unit is configured to determine a time of when to output an audio signal that mimics or enhances engine sound based on the airflow into the engine of the vehicle. The electronic control unit is configured to generate the audio signal based on the airflow into the engine of the vehicle. The sound enhancement system includes an audio device. The audio device is configured to output the audio signal based on the timing of when to output the audio signal. | 2022-02-17 |
20220051654 | Two-Level Speech Prosody Transfer - A method includes receiving an input text utterance to be synthesized into expressive speech having an intended prosody and a target voice and generating, using a first text-to-speech (TTS) model, an intermediate synthesized speech representation tor the input text utterance The intermediate synthesized speech representation possesses the intended prosody. The method also includes providing the intermediate synthesized speech representation to a second TTS model that includes an encoder portion and a decoder portion. The encoder portion is configured to encode the intermediate synthesized speech representation into an utterance embedding that specifies the intended prosody The decoder portion is configured to process the input text utterance and the utterance embedding to generate an output audio signal of expressive speech that has the intended prosody specified by the utterance embedding and speaker characteristics of the target voice. | 2022-02-17 |
20220051655 | ACOUSTIC MODEL LEARNING DEVICE, VOICE SYNTHESIS DEVICE, AND PROGRAM - An acoustic model learning device is provided for obtaining an acoustic model used to synthesize voice signals with intonation. The device includes a first learning unit that learns the acoustic model to estimate synthetic acoustic feature values using voice and speaker determination models based on acoustic feature values of speakers, language feature values corresponding to the acoustic feature values and speaker data items, a second learning unit that learns the voice determination model to determine whether the synthetic acoustic feature value is a predetermined acoustic feature value or not based on the acoustic feature values and the synthetic acoustic feature values, and a third learning unit that learns the speaker determination model to determine whether the speaker of the synthetic acoustic feature value is a predetermined speaker or not based on the acoustic feature values and the synthetic acoustic feature values. | 2022-02-17 |
20220051656 | SYSTEM AND METHOD USING CLOUD STRUCTURES IN REAL TIME SPEECH AND TRANSLATION INVOLVING MULTIPLE LANGUAGES, CONTEXT SETTING, AND TRANSCRIPTING FEATURES - A system for using cloud structures in real time speech and translation involving multiple languages is provided. The system comprises a processor, a memory, and an application stored in the memory that when executed on the processor receives audio content in a first spoken language from a first speaking device. The system also receives a first language preference from a first client device, the first language preference differing from the spoken language. The system also receives a second language preference from a second client device, the second language preference differing from the spoken language. The system also transmits the audio content and the language preferences to at least one translation engine and receives the audio content from the engine translated into the first and second languages. The system also sends the audio content to the client devices translated into their respective preferred languages. | 2022-02-17 |
20220051657 | CHANNEL SELECTION APPARATUS, CHANNEL SELECTION METHOD, AND PROGRAM - A channel in which an utterance of a keyword is included is selected from acoustic signals of multiple channels. An addition unit | 2022-02-17 |
20220051658 | MACHINE LEARNING FRAMEWORK FOR TUNING INTERACTIVE VOICE RESPONSE SYSTEMS - An artificial intelligence (“AI”) system for tuning a machine learning interactive voice response system is provided. The AI system may perform analysis of outputs generated by the machine learning models. The AI system may determine an expected model output for a given test input. The AI system may determine accuracy, precision and recall scores for an actual output garneted in response to the test input. The system may determine performance metrics for interim outputs generated by individual machine learning models within the interactive voice response system. The AI system may replace malfunctioning models with replacement models. | 2022-02-17 |
20220051659 | KEYWORD DETECTION APPARATUS, KEYWORD DETECTION METHOD, AND PROGRAM - An object is to prevent a keyword from being falsely detected from an utterance that is not intended for keyword detection. A keyword detection unit | 2022-02-17 |
20220051660 | Hearing Device User Communicating With a Wireless Communication Device - The disclosed technology relates to conversation between a wireless communication device with a hearing device user. Based on the context of an initiated conversation, an initiating module within the hearing device can send a listening initiator to a speech recognition module within the hearing device, which can use the listening initiator to determine keywords that are potentially applicable in that a context. The speech recognition module within the hearing device can determine whether keywords associated with the context of a conversation are spoken by the user. Accordingly, the hearing device does not need a large vocabulary speech recognition module or computation resources equivalent to a laptop or desktop, which saves power and resources and makes a hearing device integrated keyword detection useful for different contexts. | 2022-02-17 |
20220051661 | ELECTRONIC DEVICE PROVIDING MODIFIED UTTERANCE TEXT AND OPERATION METHOD THEREFOR - Disclosed is an operation method of an electronic device that communicates with a server including receiving a domain and a category, transmitting the domain and the category to the server, receiving a modified utterance text corresponding to the domain and the category from the server, and displaying the modified utterance text. The modified utterance text is generated through a generation model or a transfer learning model based on user utterance data stored in advance in the server. The server is configured to convert voice data, which is delivered to the server by an external electronic device receiving a user utterance, into a text and to store the text as the user utterance data. Besides, various embodiments as understood from the specification are also possible. | 2022-02-17 |
20220051662 | SYSTEMS AND METHODS FOR EXTRACTION OF USER INTENT FROM SPEECH OR TEXT - A computer system is provided. The computer system includes a memory and at least one processor configured to recognize one or more intent keywords in text provided by a user; identify an intent of the user based on the recognized intent keywords; select a workflow context based on the identified intent; determine an action request based on analysis of the text in association with the workflow context, wherein the action request comprises one or more action steps and the action steps comprise one or more data points; obtaining a workspace context associated with the user; and evaluate the data points based on the workspace context. | 2022-02-17 |
20220051663 | TRANSIENT PERSONALIZATION MODE FOR GUEST USERS OF AN AUTOMATED ASSISTANT - Implementations set forth herein relate to an automated assistant that can operate in a transient personalization mode, and/or assist a separate automated assistant with providing output according to a transient personalization mode. The transient personalization mode can allow a guest user of an assistant enabled-device to receive personalized responses from the assistant-enabled device—despite not being signed into the assistant-enabled device. A host automated assistant of the assistant-enabled device can securely communicate with a guest user's automated assistant through a backend process. In this way, input queries from the guest user to the host automated assistant can be personalized according to the guest automated assistant—without the guest user directly engaging with their own personal device. | 2022-02-17 |
20220051664 | SEMI-DELEGATED CALLING BY AN AUTOMATED ASSISTANT ON BEHALF OF HUMAN PARTICIPANT - Implementations are directed to using an automated assistant to initiate an assisted call on behalf of a given user. The assistant can, during the assisted call, receiving a request, from an additional user on the assisted call, for information that is not known to the assistant. In response, the assistant can render a prompt for the information and, while awaiting responsive input from the given user, continue the assisted call using already resolved value(s) for the assisted call. If responsive input is received within a threshold duration of time, synthesized speech, corresponding to the responsive input, is rendered as part of the assisted call. Implementations are additionally or alternatively directed to using the automated assistant to provide, during an ongoing call between a given user and an additional user, output that is based on a value requested by the additional user during the ongoing call. | 2022-02-17 |
20220051665 | ARTIFICIAL INTELLIGENCE (AI) BASED USER QUERY INTENT ANALYZER - An Artificial Intelligence (AI) based user intent analyzer system analyzes a received user query to determine an intent of the user query and enables execution of processes on a backend system based on the user intent. The user query is divided into a plurality of portions and the portions with extraneous information are discarded. The remaining portions are parsed with a plurality of parsers. The output from the plurality of parsers is processed for extraction of the entities, entity attributes, verbs, and verb arguments. The entities and verbs are further filtered using knowledge graphs and the remaining entities and verbs are mapped to sub-intents using intent mapping rules retrieved from the knowledge graphs. The sub-intents are mapped to the final intent using process rules associated with the process to be executed by the backend system in response to the user query. | 2022-02-17 |
20220051666 | AUGMENTED REALITY ENABLED COMMAND MANAGEMENT - The exemplary embodiments disclose a method, a computer program product, and a computer system for managing user commands. The exemplary embodiments may include a user giving one or more commands to one or more devices, collecting data of the one or more commands, extracting one or more features from the collected data, and determining which one or more of the commands should be executed on which one or more of the devices based on the extracted one or more features and one or more models. | 2022-02-17 |
20220051667 | METHOD AND DEVICE FOR CONTROLLING OPERATION MODE OF TERMINAL DEVICE, AND MEDIUM - A method and a device for controlling an operation mode of a terminal device, and a medium are provided. The method includes that: based on a received voice mode activation instruction under a preset condition, a voice operation learning mode is entered and a voice operation learning interface is displayed. The voice operation learning interface is configured to guide a user to output a voice instruction. The method further includes that: upon completion of the voice operation learning mode, a voice operation mode is entered; voice information is received in the voice operation mode; and the terminal device is controlled according to the voice instruction in the received voice information to execute an operation corresponding to the voice instruction. | 2022-02-17 |
20220051668 | SPEECH CONTROL METHOD, TERMINAL DEVICE, AND STORAGE MEDIUM - A speech control method, for a terminal device, includes: receiving an input speech control instruction, obtaining a recognition result of the speech control instruction; searching for an execution object matching the recognition result step by step within a preset search range; and responding to the speech control instruction based on a search result; in which the preset search range at least includes any one of: a current interface of the terminal device when receiving the speech control instruction, at least one application currently running on the terminal device when receiving the speech control instruction, and a system of the terminal device. | 2022-02-17 |
20220051669 | INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, COMPUTER PROGRAM, AND INTERACTION SYSTEM - Provided are an information processing device, an information processing method, a computer program, and an interaction system for processing an interaction with a user. The information processing device includes a determination section that determines a state or a tendency of a user, and a decision section that decides an output to the user on the basis of a determination result obtained by the determination section. The determination section determines the state or the tendency of the user on the basis of a sensing result on the user or operation of an apparatus being used by the user. Further, the decision section decides a timing for talking to the user, a condition for talking to the user, or a speech for talking to the user. | 2022-02-17 |
20220051670 | LEARNING SUPPORT DEVICE, LEARNING SUPPORT METHOD, AND RECORDING MEDIUM - A learning support device acquires sound data; extracts a letter string representing content of an utterance for each utterance by a learner included in the sound data; identify, for each utterance, a learner who has made the utterance from among a plurality of learners based on the sound data; identify emotion information representing an emotion of the learner in the utterance, based on at least one of the sound data and data of a moving image captured together with the sound data; and outputs, for each group to which learner belongs, the plurality of pieces of emotion information in time series order with being associated with the plurality of letter strings. | 2022-02-17 |
20220051671 | INFORMATION PROCESSING APPARATUS FOR SELECTING RESPONSE AGENT - To provide an information processing apparatus including: a selection unit that selects a response agent that responds to a user according to a response type on the basis of an utterance content of the user from a plurality of agents having different outputs with respect to an input; and a response control unit that controls a response content made by the response agent. Therefore, the agent can respond to the user's intention without an explicit command. | 2022-02-17 |
20220051672 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND PROGRAM - An information processing apparatus that includes a control unit ( | 2022-02-17 |
20220051673 | INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD - The present technology relates to an information processing apparatus and an information processing method capable of providing a dialog response more appropriately. | 2022-02-17 |
20220051674 | Network Nodes and Methods Performed Therein for Handling Media Channels during an Ongoing Media Session - Embodiments herein relate to a method performed by a first network node ( | 2022-02-17 |
20220051675 | MULTIMODAL RESPONSES - Systems, methods, and apparatus for using a multimodal response in the dynamic generation of client device output that is tailored to a current modality of a client device is disclosed herein. Multimodal client devices can engage in a variety of interactions across the multimodal spectrum including voice only interactions, voice forward interactions, multimodal interactions, visual forward interactions, visual only interactions etc. A multimodal response can include a core message to be rendered for all interaction types as well as one or more modality dependent components to provide a user with additional information. | 2022-02-17 |
20220051676 | HEADSET BOOM WITH INFRARED LAMP(S) AND/OR SENSOR(S) - In one aspect, a headset assembly may include a headset housing, at least one processor, and a microphone boom coupled to the headset housing. The microphone boom may include an infrared (IR) sensor on a distal end segment, where the IR sensor may be accessible to the at least one processor. The microphone boom may further include at least one microphone accessible to the at least one processor. Additionally, the headset assembly may include storage accessible to the at least one processor. The storage may include instructions executable by the at least one processor to receive input from the IR sensor and, based on the input from the IR sensor, perform mouth feature extraction. The instructions may also be executable to execute at least one function based on the mouth feature extraction. | 2022-02-17 |
20220051677 | INTELLIGENT VOICE ENABLE DEVICE SEARCHING METHOD AND APPARATUS THEREOF - An intelligent voice enable device searching method and apparatus are disclosed. A method for searching a plurality of voice enable devices according to one embodiment of the present disclosure includes receiving first device information from a first device receiving a wake-up voice; searching a first account associated with the first device based on the first device information; searching devices of a first group registered in the first account; searching a second account associated with a second device other than the first device among the devices of the first group; searching devices of a second group registered in the second account; searching devices of a third group sharing an IP address with the devices of the first group or the devices of the second group; and selecting a voice enable device to respond to the wake-up voice among the devices of the first group, the second group, and the third group. The method has an effect that a device that responds to a wake-up voice may be searched more accurately than in a conventional approach. | 2022-02-17 |
20220051678 | STAGED USER ENROLLMENT USING AUDIO DEVICES - Disclosed are various embodiments for staged user enrollment using audio devices. In one embodiment, among others, a system includes a computing device and program instructions. The program instructions can cause the computing device to receive a configuration profile for configuring a client device. The configuration profile includes a device policy associated with an organizational group. The program instructions can further cause the computing device to generate a sound payload based on encoding the configuration profile onto a sound signal. A request is received a request from a voice assistant service for configuring the client device. The request is associated with configuring the client device according to the device policy. The sound payload is transmitted to the voice service for broadcasting from a speaker device. The sound payload is broadcast within an audible distance of the client device. | 2022-02-17 |
20220051679 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND PROGRAM - A control section performs control to give notification of information regarding a previous dialogue on the basis of each status of participants in dialogue. For example, the information regarding the previous dialogue includes information regarding a significant word extracted from a speech of the previous dialogue. In this case, the information regarding the previous dialogue further includes, for example, additional information related to the significant word. For example, when one of utterers currently in dialogue makes an utterance indicative of intention to call up information, the control section perform control to give notification of the information regarding a previous dialogue in which all utterers currently in dialogue participated. | 2022-02-17 |
20220051680 | Stereo Signal Processing Method and Apparatus - A stereo signal processing method includes performing delay estimation on a stereo signal of a current frame to determine an inter-channel time difference of the current frame, identifying a sign of the inter-channel time difference of the current frame is different from a sign of an inter-channel time difference of a previous frame of the current frame, performing delay alignment processing on the first-channel signal of the current frame based on the inter-channel time difference of the current frame, and performing delay alignment processing on the second-channel signal of the current frame based on the inter-channel time difference of the previous frame. | 2022-02-17 |
20220051681 | AUDIO ENCODER AND DECODER USING A FREQUENCY DOMAIN PROCESSOR , A TIME DOMAIN PROCESSOR, AND A CROSS PROCESSING FOR CONTINUOUS INITIALIZATION - An audio encoder for encoding an audio signal includes: a first encoding processor for encoding a first audio signal portion in a frequency domain, wherein the first encoding processor includes: a time frequency converter for converting the first audio signal portion into a frequency domain representation having spectral lines up to a maximum frequency of the first audio signal portion; a spectral encoder for encoding the frequency domain representation; a second encoding processor for encoding a second different audio signal portion in the time domain; a cross-processor for calculating, from the encoded spectral representation of the first audio signal portion, initialization data of the second encoding processor, so that the second encoding processing is initialized to encode the second audio signal portion immediately following the first audio signal portion in time in the audio signal; a controller configured for analyzing the audio signal and for determining, which portion of the audio signal is the first audio signal portion encoded in the frequency domain and which portion of the audio signal is the second audio signal portion encoded in the time domain; and an encoded signal former for forming an encoded audio signal including a first encoded signal portion for the first audio signal portion and a second encoded signal portion for the second audio signal portion. | 2022-02-17 |
20220051682 | DOWNSCALED DECODING - A downscaled version of an audio decoding procedure may more effectively and/or at improved compliance maintenance be achieved if the synthesis window used for downscaled audio decoding is a downsampled version of a reference synthesis window involved in the non-downscaled audio decoding procedure by downsampling by the downsampling factor by which the downsampled sampling rate and the original sampling rate deviate, and downsampled using a segmental interpolation in segments of ¼ of the frame length. | 2022-02-17 |
20220051683 | DOWNSCALED DECODING - A downscaled version of an audio decoding procedure may more effectively and/or at improved compliance maintenance be achieved if the synthesis window used for downscaled audio decoding is a downsampled version of a reference synthesis window involved in the non-downscaled audio decoding procedure by downsampling by the downsampling factor by which the downsampled sampling rate and the original sampling rate deviate, and downsampled using a segmental interpolation in segments of 1/4 of the frame length. | 2022-02-17 |
20220051684 | DOWNSCALED DECODING - A downscaled version of an audio decoding procedure may more effectively and/or at improved compliance maintenance be achieved if the synthesis window used for downscaled audio decoding is a downsampled version of a reference synthesis window involved in the non-downscaled audio decoding procedure by downsampling by the downsampling factor by which the downsampled sampling rate and the original sampling rate deviate, and downsampled using a segmental interpolation in segments of ¼ of the frame length. | 2022-02-17 |
20220051685 | METHOD FOR TRANSFORMING AUDIO SIGNAL, DEVICE, AND STORAGE MEDIUM - A method for transforming an audio signal comprises obtaining a plurality of segmental original frequency-domain signal segments and a plurality of segmental target frequency-domain signal segments by segmenting and performing a Fourier transform on an original audio signal and an initial target audio signal obtained by pitch shifting on the original audio signal; obtaining a plurality of original formant envelopes by respectively filtering the plurality of segmental original frequency-domain signal segments according to a plurality of original segment window functions, and obtaining a plurality of target formant envelopes by respectively filtering the plurality of segmental target frequency-domain signal segments according to a plurality of target segment window functions; and determining a pitch-shifted audio signal based on the plurality of segmental target frequency-domain signal segments, the plurality of original formant envelopes, and the plurality of target formant envelopes. | 2022-02-17 |
20220051686 | AUDIO SYSTEMS AND METHODS FOR VOICE ACTIVITY DETECTION - Audio systems, methods, and processor instructions are provided that detect voice activity of a user and provide an output voice signal. The systems, methods, and instructions receive a plurality of microphone signals and combine the plurality of microphone signals according to a first combination and a second combination. The first combination produces a primary signal having enhanced response in the direction of the user's mouth, and the second combination produces a reference signal having reduced response in the direction of the user's mouth. The primary signal and the reference signal are added and subtracted to produce a summation signal and a difference signal, respectively. The summation signal and the difference signal are compares and an output voice signal is provided based upon the comparison. | 2022-02-17 |
20220051687 | SOUND PROCESSING METHOD - A sound processing apparatus includes a feature value extractor configured to perform a Fourier transform and then a cepstral analysis of a sound signal and to extract, as feature values of the sound signal, values including frequency components obtained by the Fourier transform of the sound signal and a value based on a result obtained by the cepstral analysis of the sound signal. | 2022-02-17 |
20220051688 | DEVICE AND METHOD FOR WIRELESSLY COMMUNICATING ON BASIS OF NEURAL NETWORK MODEL - Disclosed are a device and method for wirelessly communicating. The device according to one example embodiment of the present disclosure may comprise a transceiver and a controller connected to the transceiver, wherein the controller is configured to identify at least one additional sample on the basis of a digital signal by using a neural network model and upscale the digital signal by adding the at least one identified additional sample to a plurality of samples of the digital signal. | 2022-02-17 |
20220051689 | CONTACTLESS COUGH DETECTION AND ATTRIBUTION - Methods, devices, and systems for contactless cough detection and attribution are presented herein. Audio data may be received using a microphone. A cough may be identified as having occurred based on the received audio data. Radar data may be received indicative of reflected radio waves from a radar sensor. A state analysis process may be performed using the received radar data. The detected cough may be attributed to a particular user based at least in part on the state analysis process performed using the radar data. | 2022-02-17 |
20220051690 | METHODS AND APPARATUS TO PERFORM SIGNATURE MATCHING USING NOISE CANCELLATION MODELS TO ACHIEVE CONSENSUS - Examples are disclosed to perform signature matching using noise cancellation models to achieve consensus. Example apparatus disclosed herein include a signature matcher to compare a first stream of monitored media signatures to streams of reference signatures representative of corresponding reference media to determine a first signature match, and compare a second stream of monitored media signatures to the streams of reference signatures to determine a second signature match; a match selector to use at least one the first signature match or the second signature match to identify a first one of the reference media corresponding to the monitored media data; and a creditor interface to output identification data for the first one of the reference media identified with the at least one the first signature match or the second signature match, the identification data to be used to credit a media exposure corresponding to the monitored media. | 2022-02-17 |
20220051691 | Communication Issue Detection Using Evaluation of Multiple Machine Learning Models - Techniques are provided for evaluating multiple machine learning models to identify issues with a communication. One method comprises applying an audio signal associated with a communication to at least two of: (i) a trigger word analysis module that evaluates contextual information to determine if a trigger word is detected in the audio signal; (ii) an audio activity pattern analysis module that determines if a silence pattern anomaly is detected; and (iii) a communication application analysis module that evaluates features provided by a communication application relative to applicable thresholds; and combining results of the at least two of the trigger word analysis module, the audio activity pattern analysis module and the communication application analysis module to identify a communication issue. The combining may evaluate an accuracy of the trigger word analysis module, the audio activity pattern analysis module and/or the communication application analysis module to combine the results. | 2022-02-17 |
20220051692 | CLEANING ENABLING DEVICE, CLEANING DEVICE, AND MAGNETIC TAPE DEVICE - In order to reduce the possibility of occurrence of retraction of a cleaning member during cleaning of a magnetic head and the possibility of the cleaning member not being able to return to a retraction position due to stopping part way, the cleaning enabling device is provided with: a holding member having a first surface capable of holding the cleaning member for cleaning the magnetic head, and a second surface capable of lifting a magnetic tape from the magnetic head; a transmission part which transmits a first driving force for driving a first driving member; and a first force application part which applies, to the holding member, a first force in a direction that causes the cleaning member to remain in the retraction position when the cleaning member is in the retraction position and releases the first force when the cleaning member is drawn away from the retraction position. | 2022-02-17 |
20220051693 | MAGNETIC RECORDING MEDIUM, METHOD OF MANUFACTURING THE SAME, AND MAGNETIC RECORDING/REPRODUCING APPARATUS - According to one embodiment, a magnetic recording medium includes a substrate, a magnetic recording layer on the substrate, and a first protective layer of carbon formed on the magnetic recording layer by thermal CVD. | 2022-02-17 |
20220051694 | THIN-FILM CRYSTALLINE STRUCTURE WITH SURFACES HAVING SELECTED PLANE ORIENTATIONS - A method of forming a thin film structure involves performing one or more repetitions to form a template on a wafer. The repetitions include: depositing a layer of a template material to a first thickness T1; and ion beam milling the layer of the template material to remove thickness T2, where T22022-02-17 | |
20220051695 | EVENT BASED RECONCILE OPERATION FOR HIERARCHICAL STORAGE MANAGEMENT - In an approach to automatically reconciling data in HSM without affecting system performance, responsive to migrating a file on a hierarchical storage system from a primary storage to one or more tape drives, one or more file migration records are recorded in a reconcile database. Responsive to the occurrence of a file event on the primary storage, the one or more file migration records in the reconcile database are updated. Responsive to receiving a command to unmount a first mounted tape on one of the one or more tape drives, a reconcile function is performed on the first mounted tape, wherein the reconcile function updates the first mounted tape with the one or more file migration records in the reconcile database. | 2022-02-17 |
20220051696 | METHOD AND APPARATUS FOR GENERATING A VIDEO BASED ON A PROCESS - A method and apparatus for generating a video using a process diagram and using a process documentation guide storing screenshots and user inputs associates each node of a process diagram with a respective screenshot stored in the process documentation guide. A video is generated displaying each respective screenshot associated with each node of the process diagram in a sequence identified by the process diagram. The process diagram is generated by a user or by the process video server based on information in the process documentation guide. | 2022-02-17 |
20220051697 | Multimedia Distribution System - A multimedia file and methods of generating, distributing and using the multimedia file are described. Multimedia files in accordance with embodiments of the present invention can contain multiple video tracks, multiple audio tracks, multiple subtitle tracks, a complete index that can be used to locate each data chunk in each of these tracks and an abridged index that can enable the location of a subset of the data chunks in each track, data that can be used to generate a menu interface to access the contents of the file and ‘meta data’ concerning the contents of the file. Multimedia files in accordance with several embodiments of the present invention also include references to video tracks, audio tracks, subtitle tracks and ‘meta data’ external to the file. One embodiment of a multimedia file in accordance with the present invention includes a series of encoded video frames, a first index that includes information indicative of the location within the file and characteristics of each encoded video frame and a separate second index that includes information indicative of the location within the file of a subset of the encoded video frames. | 2022-02-17 |
20220051698 | SEMICONDUCTOR DEVICE - Provided herein may be a semiconductor device. The semiconductor device may include a stack including word lines, a bit line penetrating the stack, a global bit line disposed above the stack, global word lines disposed above the stack, a common select line disposed above the stack, a first contact plug coupling the global bit line and the bit line to each other and penetrating the common select line, and second contact plugs coupling the global word lines and the word lines to each other respectively and penetrating the common select line. | 2022-02-17 |
20220051699 | MICROELECTRONIC DEVICES INCLUDING SEMICONDUCTIVE PILLAR STRUCTURES, AND RELATED METHODS AND ELECTRONIC SYSTEMS - A microelectronic device comprises semiconductive pillar structure comprising a central portion, a first end portion, and a second end portion on a side of the central portion opposite the first end portion, the first end portion oriented at an angle with respect to the central portion and extending substantially parallel to the second end portion, a digit line contact on the central portion of the semiconductive pillar structure, a first storage node contact on the first end portion, and a second storage node contact on the second end portion. Related microelectronic devices, electronic systems, and methods are also described. | 2022-02-17 |
20220051700 | MICROELECTRONIC DEVICES INCLUDING SEMICONDUCTIVE PILLAR STRUCTURES, AND RELATED METHODS AND ELECTRONIC SYSTEMS - A microelectronic device comprises semiconductive pillar structures each individually comprising a digit line contact region disposed laterally between two storage node contact regions. At least one semiconductive pillar structure of the semiconductive pillar structures comprises a first end portion comprising a first storage node contact region, a second end portion comprising a second storage node contact region, and a middle portion between the first end portion and the second end portion and comprising a digit line contact region, a longitudinal axis of the first end portion oriented at an angle with respect to a longitudinal axis of the middle portion. Related microelectronic devices, electronic systems, and methods are also described. | 2022-02-17 |
20220051701 | VOLTAGE GENERATING CIRCUIT AND A NONVOLATILE MEMORY APPARATUS USING THE VOLTAGE GENERATING CIRCUIT - A voltage generating circuit includes a voltage supplying circuit and a current biasing circuit. The voltage supplying circuit is configured to supply a first power voltage to an output node based on a first enable signal. The current biasing circuit is configured to control a bias current to flow from the output node based on a second enable signal. The second enable signal is enabled after the first enable signal is enabled. | 2022-02-17 |
20220051702 | Memory Device - A method of operating a memory device is provide. A clock signal is received. Each clock cycle of the clock signal initiates a write operation or a read operation in a memory device. A power nap period is then determined. The power nap period is compare with a clock cycle period to determine that the power nap period is less that the clock cycle period of the clock signal. A header control signal is generated in response to determining that the power nap period is less than the clock cycle period. The header control signal turns off a header of a component of the memory device. | 2022-02-17 |
20220051703 | VALIDATION OF DRAM CONTENT USING INTERNAL DATA SIGNATURE - Systems, methods, and apparatus related to validating data stored in a memory system. In one approach, a DRAM stores data for a host device. A controller that manages the DRAM receives a command from the host device to generate a signature. The controller also receives data from the host device that indicates a region of the DRAM. In response to receiving the command, the controller reads data from the indicated region. A signature is generated by the controller based on the data read from the indicated region. The generated signature is sent to the host device in response to the command. | 2022-02-17 |
20220051704 | Circuits and Methods for Capacitor Modulation - In a particular implementation, a circuit comprises: a memory array including a plurality of bit cells, where each of the bit cells are coupled to a respective bit path; a first multiplexer comprising a plurality of column address locations, where each of the plurality of column address locations is coupled to the memory array and corresponds to a respective bit path capacitance; and a variable capacitance circuit coupled to a reference path and configured to substantially match reference path capacitance to each of the respective bit path capacitances. | 2022-02-17 |
20220051705 | DRAM INTERFACE MODE WITH IMPROVED CHANNEL INTEGRITY AND EFFICIENCY AT HIGH SIGNALING RATES - An IC memory controller includes a first controller command/address (C/A) interface to transmit first and second read commands for first and second read data to a first memory C/A interface of a first bank group of memory. A second command/address (C/A) interface transmits third and fourth read commands for third and fourth read data to a second memory C/A interface of a second bank group of memory. For a first operating mode, the first and second read data are received after respective first delays following transmission of the first and second read commands and at a first serialization ratio. For a second operating mode, the first and second read data are received after respective second and third delays following transmission of the first and second read commands. The second and third delays are different from the first delays and from each other. The first and second data are received at a second serialization ratio that is different than the first serialization ratio. | 2022-02-17 |
20220051706 | BUFFER CONTROL OF MULTIPLE MEMORY BANKS - Disclosed herein are related to operating a memory system including memory banks and buffers. Each buffer may perform a write process to write data to a corresponding memory bank. In one aspect, the memory system includes a buffer controller including a queue register, a first pointer register, a second pointer register, and a queue controller. In one aspect, the queue register includes entries, where each entry may store an address of a corresponding memory bank. The first pointer register may indicate a first entry storing an address of a memory bank, on which the write process is predicted to be completed next. The second pointer register may indicate a second entry to be updated. The queue controller may configure the queue register according to the first pointer register and the second pointer register, and configure one or more buffers to perform the write process, according to the entries. | 2022-02-17 |
20220051707 | FIRST IN FIRST OUT MEMORY AND MEMORY DEVICE - A First In First Out (FIFO) memory includes storage units. Outputs of the storage units are connected to one node. The storage unit includes storage sub-units, a selector, and a drive. An input of the selector is connected to outputs of the storage sub-units. An input of the drive is connected to an output of the selector. Driven by a first pointer signal, the storage sub-units receive storage data. Driven by a second pointer signal, the drive outputs the storage data. | 2022-02-17 |
20220051708 | MAGNETIC DOMAIN WALL DISPLACEMENT ELEMENT, MAGNETIC RECORDING ARRAY, AND SEMICONDUCTOR DEVICE - A magnetic domain wall displacement element includes a first ferromagnetic layer, a second ferromagnetic layer extending in a second direction and magnetically recordable, a nonmagnetic layer, and a first conductive part having a first intermediate layer and a second conductive part having a second intermediate layer, in which the first intermediate layer is sandwiched between first and second magnetization regions and exhibiting first and second magnetization directions, the second intermediate layer is sandwiched between a third magnetization region and exhibiting the second magnetization direction and a fourth magnetization region exhibiting the first magnetization direction in the first direction, and an area of the first magnetization region is larger than an area of the second magnetization region and an area of the third magnetization region is smaller than an area of the fourth magnetization region in a cross section in the first direction and the second direction. | 2022-02-17 |
20220051709 | ROW-WISE TRACKING OF REFERENCE GENERATION FOR MEMORY DEVICES - The present disclosure relates to a structure including a plurality of magnetic random access memory (MRAM) bitcells including a first circuit and a second circuit, the second circuit being connected to a same wordline as the first circuit such that the second circuit is configured as a parallel series connection to generate a reference resistance value for sensing. | 2022-02-17 |
20220051710 | MEMORY DEVICE WHICH GENERATES IMPROVED WRITE VOLTAGE ACCORDING TO SIZE OF MEMORY CELL - Disclosed is a memory device including a magnetic memory element. The memory device includes a memory cell array including a first region and a second region, the second region configured to store a value of a write voltage, the write voltage based on a value of a reference resistor for determining whether a programmed memory cell is in a parallel state or anti-parallel state, a voltage generator configured to generate a code value based on the value of the write voltage, and a write driver configured to drive a write current based on the code value, the write current being a current for storing data in the first region. | 2022-02-17 |
20220051711 | APPARATUSES, SYSTEMS, AND METHODS FOR VOLTAGE BASED RANDOM NUMBER GENERATION - Apparatuses, systems, and methods for voltage based random number generation. A memory may include a number of different voltages, which may be used to power various operations of the memory. During access operations to the memory, the voltage may vary, for example as word lines of the memory are accessed. The variability of the voltage may represent a source of randomness and unpredictability in the memory. A random number generator may provide a random number based on the voltage. For example, an analog to binary converter (ADC) may generate a binary number based on the voltage, and the random number may be based on the binary number. | 2022-02-17 |
20220051712 | SENSE AMPLIFIER DRIVERS, AND RELATED DEVICES, SYSTEMS, AND METHODS - Drivers for sense amplifiers are disclosed. A driver may include two or more drain areas extending in a first direction and two or more source areas extending in the first direction. The driver may also include a drain interconnection including two or more first drain-interconnection portions which extend in the first direction above the two of more drain areas and one or more second drain-interconnection portions extending in a second direction between the two or more first drain-interconnection portions. The driver may also include a source interconnection including two or more first source-interconnection portions extending in the first direction above the two or more source areas and one or more second source-interconnection portions extending in the second direction between the two or more first source-interconnection portions. Associated systems are also disclosed. | 2022-02-17 |
20220051713 | SENSE AMPLIFIER, MEMORY, AND METHOD FOR CONTROLLING SENSE AMPLIFIER - A sense amplifier includes an amplification module and a control module electrically connected to the amplification module. Herein, in a case of reading a data in a memory cell on a first bit line, at an offset compensation stage of the sense amplifier, the control module is arranged to configure the amplification module to include a first diode structure, a first current mirror structure, and a first inverter with an input terminal and an output terminal connected to each other. In a case of reading a data in a memory cell on a second bit line, at the offset compensation stage of the sense amplifier, the control module is arranged to configure the amplification module to include a second diode structure, a second current mirror structure, and a second inverter with an input terminal and an output terminal connected to each other. | 2022-02-17 |
20220051714 | NONVOLATILE MEMORY DEVICE AND READ METHOD OF NONVOLATILE MEMORY DEVICE - Disclosed are a nonvolatile memory device and a read method of the nonvolatile memory device. The nonvolatile memory device includes a memory cell array, a row decoder circuit, and a page buffer circuit including first latches and second latches. The page buffer circuit respectively latches first sensing values, which are based on data stored in adjacent memory cells, at the first latches and respectively latches second sensing values, which are based on data stored in selected memory cells, at the second latches at least two times. | 2022-02-17 |
20220051715 | ELECTRONIC DEVICES MITIGATING DEGRADATION OF MOS TRANSISTORS - An electronic device includes a flag generation circuit and a delay circuit. The flag generation circuit is configured to generate a flag signal, wherein a level of the flag signal changes based on a first internal command. The delay circuit is configured to generate a delay signal by delaying one of an operation signal and the flag signal by a predetermined period according to whether a predetermined operation is performed. | 2022-02-17 |
20220051716 | APPARATUSES, SYSTEMS, AND METHODS FOR MEMORY DIRECTED ACCESS PAUSE - Apparatuses, systems, and methods for a memory-directed access pause. A controller may perform access operations on a memory by providing commands and addresses. The memory may monitor the addresses to determine if one or more forms of attack (deliberate or inadvertent) is occurring. If an attack is detected, the memory may issue an alert signal (e.g., along an alert bus) and also provide pause data (e.g., along a data bus). The pause data may specify a length of time, and responsive to the alert and the pause data, the controller may suspend access operations on the memory for the length of time specified in the pause data. The memory may use the time when access operations are paused to refresh itself, for example to heal the damage caused by the attack. | 2022-02-17 |
20220051717 | PROCESSING APPARATUS AND ELECTRONIC DEVICE INCLUDING THE SAME - Provided are processing and an electronic device including the same. The processing apparatus includes a bit cell line comprising bit cells connected in series, a mirror circuit unit configured to generate a mirror current by replicating a current flowing through the bit cell line at a ratio, a charge charging unit configured to charge a voltage corresponding to the mirror current as the mirror current replicated by the mirror circuit unit is applied, and a voltage measuring unit configured to output a value corresponding to a multiply-accumulate (MAC) operation of weights and inputs applied to the bit cell line, based on the voltage charged by the charge charging unit. | 2022-02-17 |
20220051718 | PHYSICALLY UNCLONABLE FUNCTION (PUF) GENERATION INVOLVING PROGRAMMING OF MARGINAL BITS - Stochastic or near-stochastic physical characteristics of resistive switching devices are utilized for generating data distinct to those resistive switching devices. The distinct data can be utilized for applications related to electronic identification. As one example, data generated from physical characteristics of resistive switching devices on a semiconductor chip can be utilized to form a distinct identifier sequence for that semiconductor chip, utilized for verification applications for communications with the semiconductor chip or utilized for generating cryptographic keys or the like for cryptographic applications. | 2022-02-17 |
20220051719 | SOURCE LINE CONFIGURATION FOR A MEMORY DEVICE - Methods, systems, and devices for source line configurations for a memory device are described. In some cases, a memory cell of the memory device may include a first transistor having a floating gate for storing a logic state of the memory cell and a second transistor coupled with the floating gate of the first transistor. The memory cell may be coupled with a word line, a digit line, and a source line. During a write operation, the source line may be clamped to the digit line using one or more memory cells in the memory device. During a read operation, the source line may be grounded using one or more memory cells in the memory device. | 2022-02-17 |
20220051720 | 3D MEMORY DEVICE INCLUDING SHARED SELECT GATE CONNECTIONS BETWEEN MEMORY BLOCKS - Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a data line, a first memory cell string including first memory cells located in different levels of the apparatus, first access lines to access the first memory cells, a first select gate coupled between the data line and the first memory cell string, a first select line to control the first select gate, a second memory cell string including second memory cells located in different levels of the apparatus, second access lines to access the second memory cells, the second access lines being electrically separated from the first access lines, a second select gate coupled between the data line and the second memory cell string, a second select line to control the second select gate, and the first select line being in electrical contact with the second select line. | 2022-02-17 |
20220051721 | PRE-BOOSTING SCHEME DURING A PROGRAM OPERATION IN A MEMORY SUB-SYSTEM - Control logic in a memory device initiates, subsequent to a program verify phase of a program operation, a new program operation on the memory array, the new program operation comprising a pre-boosting phase occurring prior to a program phase. The control logic causing one or more positive pre-boosting voltages to be applied to corresponding subsets of a plurality of word lines of a block of the memory array during the pre-boosting phase and causes the one or more positive pre-boosting voltages to be ramped down to a ground voltage during the pre-boosting phase in a designated order based on a location of the corresponding subsets of the plurality of word lines to which the one or more positive pre-boosting voltages were applied. | 2022-02-17 |
20220051722 | THRESHOLD VOLTAGE BASED ON PROGRAM/ERASE CYCLES - A method includes during a first portion of a service life of a memory device, programming at least one memory cell of the memory device to a first threshold voltage corresponding to a desired data state. The method can include during a second portion of the service life of the memory device subsequent to the first portion of the service life of the memory device, programming at least one memory cell of the memory device to a second threshold voltage corresponding to the desired data state. The second threshold voltage can be different than the first threshold voltage. | 2022-02-17 |
20220051723 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - Provided herein is a semiconductor memory device and a method of operating the same, The semiconductor memory device includes a memory block, a peripheral circuit, and a control logic. The memory block includes a plurality of sub-blocks coupled to a plurality of source select lines, respectively. The peripheral circuit performs a program operation on the memory block. The control logic is configured to control the peripheral circuit to increase a voltage of a common source line that is coupled to the memory block, increase a voltage of at least one source select line, among the plurality of source select lines, to a first voltage level, and set a voltage of a bit line that is coupled to the memory block and increase the voltage of at least one source select line from the first voltage level to a second voltage level. | 2022-02-17 |
20220051724 | MULTI-STAGE ERASE OPERATION FOR A MEMORY DEVICE - Control logic in a memory device initiates an erase operation on a memory array and causes an erase voltage signal to be applied to a source terminal of a string of memory cells in a data block of the memory array during the erase operation. The control logic further causes a first voltage signal to be applied to a first word line of the data block and a second voltage signal to be applied to a second word line of the data block, wherein the first word line is coupled to a first device in the string of memory cells and the second word line is coupled to a second device in the string of memory cells, and wherein the first voltage signal and the second voltage signal both have a common first voltage offset with respect to the erase voltage signal during a first stage of the erase operation. The control logic further determines an end of the first stage of the erase operation and causes the first voltage signal to decrease to a second voltage offset with respect to the erase voltage signal and causes the second voltage signal to decrease to a third voltage offset with respect to the erase voltage signal during a second stage of the erase operation, wherein the second offset is greater than the third offset. | 2022-02-17 |
20220051725 | MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A memory device having a plurality of memory blocks compensates for a characteristic change of a memory cell due to stopping an erase operation. The memory device also includes a voltage generator configured to generate voltages used by the memory device in performing an erase operation on a selected memory block among the plurality of memory blocks. The memory device further includes an erase stop controller configured to control stopping and resuming the erase operation, and counting the number of times the erase operation is stopped to generate a stop count value when the erase is stopped. The memory device additionally includes a count value storage configured to store and output the stop count value. | 2022-02-17 |
20220051726 | STORAGE STRUCTURE AND ERASE METHOD THEREOF - The invention provides a storage structure and an erase method thereof, which can perform an erase operation on memory blocks B | 2022-02-17 |
20220051727 | NON-VOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF, CONTROLLER FOR CONTROLLING THE SAME, AND STORAGE DEVICE INCLUDING THE SAME - An operating method of a storage device includes reading a wear-out pattern of a memory block when a controller determines the memory block is a re-use memory block of a non-volatile memory device; selecting an operation mode corresponding to the read wear-out pattern using the controller; and transmitting the selected operation mode to the non-volatile memory device using the controller. | 2022-02-17 |
20220051728 | MEMORY DEVICE AND METHOD OF OPERATING THE SAME - The present technology relates to an electronic device. A memory device capable of reducing a time consumed in a program operation includes a memory cell array, a page buffer group connected to the memory cell array through a plurality of bit lines and a voltage generator configured to generate voltages to apply to each of a plurality of page buffers included in the page buffer group. Each of the plurality of page buffers includes a precharge circuit that controls a potential levels of the plurality of bit lines to be maintained at precharge levels. | 2022-02-17 |
20220051729 | PAGE BUFFER CIRCUITS AND NONVOLATILE MEMORY DEVICES INCLUDING THE SAME - A nonvolatile memory device includes a memory cell array including memory cells and a page buffer circuit. The page buffer circuit includes page buffer units and cache latches. The cache latches are spaced apart from the page buffer units in a first horizontal direction, and correspond to respective ones of the plurality of page buffer units. Each of the page buffer units includes a pass transistor connected to each sensing node and driven in response to a pass control signal. The page buffer circuit being configured to perform a data transfer operation, based on performing a first data output operation to output data, provided from a first portion of page buffer units, from a first portion of cache latches to a data input/output (I/O) line, the data transfer operation configured to dump sensed data from a second portion of page buffer units to a second portion of cache latches. | 2022-02-17 |
20220051730 | STORAGE DEVICE PERFORMING READ OPERATION BY RESTORING ON CELL COUNT (OCC) FROM POWER LOSS PROTECTION AREA OF NON-VOLATILE MEMORY - A storage device performs a read operation by restoring an ON cell count (OCC) from a power loss protection (PLP) area of a nonvolatile memory. The nonvolatile memory includes a memory blocks, a buffer memory and a controller. The buffer memory stores a first ON cell count (OCC | 2022-02-17 |
20220051731 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes a memory cell unit which includes memory cell arrays including a plurality of memory cells; a peripheral circuit which performs voltage transmission control including a write operation, a read operation, and an erasing operation with respect to the memory cell unit; and signal lines which connect the peripheral circuit to the memory cell unit, and at least a portion of the signal lines is formed in a non-facing region, the non-facing region being a region where the memory cell unit does not face the peripheral circuit, the non-facing region being in a peripheral region formed around a periphery of the memory cell arrays of the memory cell unit. | 2022-02-17 |
20220051732 | FEEDBACK FOR POWER MANAGEMENT OF A MEMORY DIE USING CAPACITIVE COUPLING - A memory device may include a pin for receiving a direct current (DC) voltage indicating an operating configuration setting of the memory device and for communicating an alternating current (AC) voltage signal that provides feedback to a power management component. The memory device may determine that a supply voltage is outside of a target range, and may drive the AC signal onto the pin based on determining that the supply voltage is outside the range. The pin may be coupled with a capacitive component the passes the AC signal and blocks the DC signal. The power management component may receive the capacitively coupled AC signal and may maintain or adjust the supply voltage based on the received AC signal. | 2022-02-17 |
20220051733 | STORAGE DEVICES AND METHODS OF OPERATING STORAGE DEVICES - A storage device includes a semiconductor memory device and a storage controller. The semiconductor memory device receives write data based on a data strobe signal and data signals, and outputs read data based on the data strobe signal and the data signals. The storage controller transmits the data strobe signal and the data signals in parallel to the semiconductor memory device through signal lines. The storage controller includes a first delay circuit that delays the data signals such that some edges of windows of the data signals on the signal lines are desynchronized by first skew offsets which are different from one another. | 2022-02-17 |
20220051734 | MULTI-STATE PROGRAMMING OF MEMORY CELLS - The present disclosure includes apparatuses, methods, and systems for multi-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of four possible data states by applying a first voltage pulse to the memory cell wherein the first voltage pulse has a first polarity and a first magnitude, and applying a second voltage pulse to the memory cell wherein the second voltage pulse has a second polarity and a second magnitude, and the second voltage pulse is applied for a shorter duration than the first voltage pulse. | 2022-02-17 |
20220051735 | STABILIZATION OF SELECTOR DEVICES IN A MEMORY ARRAY - A variety of applications can include memory devices designed to provide stabilization of selector devices in a memory array of the memory device. A selector stabilizer pulse can be applied to a selector device of a string of the memory array and to a memory cell of multiple memory cells of the string with the memory cell being adjacent to the selector device in the string. The selector stabilizer pulse can be applied directly following an erase operation to the string to stabilize the threshold voltage of the selector device. The selector stabilizer pulse can be applied as part of the erase algorithm of the memory device. Additional devices, systems, and methods are discussed. | 2022-02-17 |
20220051736 | MEMORY SYSTEM AND MEMORY CONTROL METHOD - A memory system comprises a nonvolatile memory having a plurality of memory cells and a memory controller for controlling the nonvolatile memory. The plurality of memory cells is divided into different groups, and each group is assigned a threshold read count value from a predetermined range of read count values. The memory controller includes a counter which tracks a read count for each group, a determination circuit configured to compare the read count for each group tracked by the counter to the assigned threshold read count value for the group, and a nonvolatile memory read/write circuit configured to read data from the group when the determination circuit indicates the read count for the group has reached the assigned threshold read count value. | 2022-02-17 |
20220051737 | REFRESHING DATA STORED AT A MEMORY COMPONENT BASED ON A MEMORY COMPONENT CHARACTERISTIC COMPONENT - One or more write operations are performed on a memory component. First data stored at the memory component is read. A determination is made as to whether an error rate associated with the first data stored at the memory component exceeds an error rate threshold. If the error rate exceeds the error rate threshold, a threshold value is adjusted. A determination is made as to whether a number of the plurality of write operations performed on the memory component since performance of a refresh operation on the memory component exceeds the threshold value. In response to determining that the number of write operations performed on the memory component exceeds the threshold value, a memory cell of the memory component is identified based on the plurality of write operations. Second data stored at memory cells of the memory component that are proximate to the identified memory cell is refreshed. | 2022-02-17 |
20220051738 | NONVOLATILE MEMORY DEVICE AND METHOD OF DETECTING DEFECTIVE MEMORY CELL BLOCK OF NONVOLATILE MEMORY DEVICE - A method of detecting, by a nonvolatile memory system, a defective memory cell block from among memory cell blocks, includes performing, after performing an erase operation, a read operation on at least some memory cells included in a target memory cell block based on an off-cell detection voltage that is different from a read reference voltage that distinguishes an off-cell on which no data is written from an on-cell on which data is written; counting a number of hard off-cells having a higher threshold voltage than the off-cell detection voltage from among the memory cells based on a result of performing the read operation; and identifying whether the target memory cell block is a defective memory cell block based on the number of counted hard off-cells. | 2022-02-17 |
20220051739 | MEMORY DEVICE AND METHOD OF OPERATING THE SAME - Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of memory cells, each having an erased state or any one of a plurality of program states, a peripheral circuit configured to perform a program operation including a plurality of program loops, and an operation controller configured to control the peripheral circuit so that, in response to a pass in verification for an N-th program state among the plurality of program states in a verify phase included in an x-th program loop among the plurality of program loops, verification for an N+M-th program state among the plurality of program states starts in a verify phase included in an x+1-th program loop among the plurality of program loops. | 2022-02-17 |
20220051740 | SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF - Providing a semiconductor memory device capable of knowing whether a reading of the setting information which is set during the power-on operation had been completed correctly or not. The flash memory in the present invention reads the fuse memory when it is detected that the power supply has reached the power-on detection level, and determines whether the reading of the fuse memory had been completed correctly. When not completed correctly, the fuse memory is read again within the maximum read count, and the setting information (which was read from the fuse memory) is written into the CF register. Furthermore, the identification information (that identifies whether the reading of the fuse memory has been completed correctly or not) is stored in the register. | 2022-02-17 |
20220051741 | TEST CIRCUIT, MEMORY DEVICE, STORAGE DEVICE, AND METHOD OF OPERATING THE SAME - Provided herein may be a test circuit, a memory device, a storage device, and a method of operating the same. The word line test circuit may include an operation signal generator configured to generate a plurality of operation signals in response to a test command, a comparison result generator configured to, in response to the plurality of operation signals, generate a target voltage based on a test current, in which a current of a target word line varying with a test voltage is reflected, and to generate a comparison signal based on a result of a comparison between the target voltage and a reference voltage, and a word line defect detector configured to detect a defect in the target word line based on at least one reference count and a count of a reference clock, cycles of which are counted until a level of the comparison signal changes from a first level to a second level. | 2022-02-17 |
20220051742 | RECEIVER TRAINING OF REFERENCE VOLTAGE AND EQUALIZER COEFFICIENTS - In a receiver having at least a first equalizer and a sampler, a calibration module jointly calibrates a reference voltage and one or more equalizer coefficients. For each of a set of test reference voltages, an equalizer coefficient for the first equalizer may be learned that maximizes a right eye boundary of an eye diagram of a sampler input signal to a sampler of the receiver following the equalization stage. Then, from the possible pairs of reference voltages and corresponding optimal equalizer coefficients, a pair is identified that maximizes an eye width of the eye diagram. After setting the reference voltage, the first equalizer coefficient may then be adjusted together with learning a second equalizer coefficient for the second equalizer using a similar technique. | 2022-02-17 |
20220051743 | FLASH MEMORY DEVICE - Aspects of the disclosure provide a semiconductor memory device. The semiconductor memory device includes a memory cell array and peripheral circuitry coupled with the memory cell array. The memory cell array includes a plurality of memory cells. The peripheral circuitry includes programmable logic circuit that is configured, after the semiconductor memory device is powered on, to perform logic functions. | 2022-02-17 |
20220051744 | MEMORY CONTROLLER WITH ADAPTIVE REFRESH RATE CONTROLLED BY ERROR BIT INFORMATION - The present invention provides a memory controller including a decoder, an error bit counter and a refresh rate control circuit. The decoder is configured to receive and decode data from a memory module to generate decoded data. The error counter is coupled to the decoder, and is configured to generate error bit information of the data. The refresh rate control circuit is coupled to the error counter, and is configured to determine a refresh rate of the memory module according to the error bit information. | 2022-02-17 |
20220051745 | MEMORY DEVICE AND METHOD OF OPERATING THE MEMORY DEVICE - The present technology relates to an electronic device. According to the present technology, a memory device having reduced latency includes a plurality of memory cells, an optimum read voltage information storage configured to store optimum read voltage information determined according to a cell count value, which is the number of memory cells read as a first memory cell based on data read from the plurality of memory cells among the plurality of memory cells, and a read voltage controller configured to calculate a cell count value corresponding to a default read voltage based on the data read from the plurality of memory cells using the default read voltage, in response to an optimum read voltage setting command input from a memory controller, and generate a first optimum read voltage based on the cell count value corresponding to the default read voltage and the optimum read voltage information. | 2022-02-17 |
20220051746 | SOFT BIT REFERENCE LEVEL CALIBRATION - Calibration of soft bit reference levels in a non-volatile memory system is disclosed. A set of memory cells are sensed at a hard bit reference level and test soft bit reference levels. The test soft bit reference levels are grouped around the hard bit reference level. A metric is determined for the test soft bit reference levels. Bins are defined based on the hard bit reference level and the set of test soft bit reference levels. A metric may be determined for each of the bins. The new soft bit reference levels are determined based on the metric. In one aspect, the metric is how many memory cells have a value for a physical parameter within each bin. The soft bit reference levels may be established based on a target percentage for the bins. In one aspect, the metric is how many unsatisfied counters are within each bin. | 2022-02-17 |
20220051747 | PROGRAM AND OPERATING METHODS OF NONVOLATILE MEMORY DEVICE - A program method of a nonvolatile memory device including a plurality of memory cells, each storing at least two bits of data, includes performing a first program operation based on a plurality of program voltages having a first pulse width to program first page data into selected memory cells connected to a selected word line among the plurality of memory cells; and performing a second program operation based on a plurality of program voltages having a second pulse width different from the first pulse width to program second page data into the selected memory cells in which the first page data is programmed. | 2022-02-17 |
20220051748 | EXECUTION METHOD OF FIRMWARE CODE, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT - An execution method of a firmware code, a memory storage device and a memory control circuit unit are disclosed. The method includes: executing a firmware code in a read only memory; after executing a first part of the firmware code, querying reference information in a reference memory according to index information in the firmware code; and determining, according to the reference information, to continuously execute a second part of the firmware code or switch to execute a replacement program code in the reference memory, so as to complete a startup procedure. | 2022-02-17 |
20220051749 | RECOVERY MANAGEMENT OF RETIRED SUPER MANAGEMENT UNITS - A system includes a memory component, and a processing device coupled with the memory component. The processing device to identify a group of management units of the memory component, wherein the group of management units is included in a set of retired groups of management units, select a management unit from the group of management units, perform a media integrity check on the management unit to determine a failed bit count of the management unit, and in response to the failed bit count of the management unit failing to satisfy a threshold criterion, remove the group of management units from the set of retired groups of management units. | 2022-02-17 |
20220051750 | HIGH-TEMPERATURE BIMETAL - A high-temperature bimetal capable of being inhibited from considerably shifting from an original position when the temperature has fallen to an ordinary temperature is provided. This high-temperature bimetal ( | 2022-02-17 |
20220051751 | ANCESTRY COMPOSITION DETERMINATION - Presenting ancestral origin information, comprising: receiving a request to display ancestry data of an individual; obtaining ancestry composition information of the individual, the ancestry composition information including information pertaining to a proportion of the individual's genotype data that is deemed to correspond to a specific ancestry; and presenting the ancestry composition information to be displayed. | 2022-02-17 |