07th week of 2022 patent applcation highlights part 54 |
Patent application number | Title | Published |
20220052152 | SIDEWALL DOPANT SHIELDING METHODS AND APPROACHES FOR TRENCHED SEMICONDUCTOR DEVICE STRUCTURES - Semiconductor devices and methods of forming a semiconductor device that includes a deep shielding pattern that may improve a reliability and/or a functioning of the device. An example method may include forming a wide band-gap semiconductor layer structure on a substrate, the semiconductor layer structure including a drift region that has a first conductivity type; forming a plurality of gate trenches in an upper portion of the semiconductor layer structure, the gate trenches spaced apart from each other, each gate trench having a bottom surface, a first sidewall, a second sidewall, and an upper opening; forming an obstruction over a portion of each gate trench that partially obscures the upper opening; and implanting dopants having a second conductivity type that is opposite the first conductivity type into the bottom surfaces of the gate trenches, where the dopants implanted into the bottom surface of the gate trenches form deep shielding patterns. | 2022-02-17 |
20220052153 | AVALANCHE-PROTECTED TRANSISTORS USING A BOTTOM BREAKDOWN CURRENT PATH AND METHODS OF FORMING THE SAME - An avalanche-protected field effect transistor includes, within a semiconductor substrate, a body semiconductor layer and a doped body contact region having a doping of a first conductivity type, and a source region a drain region having a doping of a second conductivity type. A buried first-conductivity-type well may be located within the semiconductor substrate. The buried first-conductivity-type well underlies, and has an areal overlap in a plan view with, the drain region, and is vertically spaced apart from the drain region, and has a higher atomic concentration of dopants of the first conductivity type than the body semiconductor layer. The configuration of the field effect transistor induces more than 90% of impact ionization electrical charges during avalanche breakdown to flow from the source region, to pass through the buried first-conductivity-type well, and to impinge on a bottom surface of the drain region. | 2022-02-17 |
20220052154 | SUPERJUNCTION TRANSISTOR DEVICE - A method and a transistor device are disclosed. The transistor device includes: a semiconductor body; first regions of a first doping type and second regions of a second doping type in an inner region and an edge region of the semiconductor body; transistor cells in the inner region of the semiconductor body, each transistor cell including a body region and a source region, the transistor cells including a common drain region; and a buffer region arranged between the drain region and the first and second regions. A dopant dose in the first and second regions decreases towards an edge surface of the semiconductor body. A dopant dose in the buffer region decreases towards the edge surface. | 2022-02-17 |
20220052155 | Leakage Reduction in Gate-All-Around Devices - A semiconductor device includes a substrate; a well of a first conductivity-type and including an anti-punch-through (APT) layer of the first conductivity-type; source and drain features of a second conductivity-type over the APT layer; a strap feature of the first conductivity-type over the well; multiple vertically-stacked channel layers over the APT layer and connecting the source and drain features; a gate wrapping around each channel layer; source and drain contacts electrically coupled to the source and drain features; source and drain vias landed on the source and drain contacts; a strap contact electrically coupled to the strap feature; and a strap via landed on the strap contact. The source via and the strap via are configured to be coupled to different voltages during a non-active mode of the semiconductor device and to be coupled to a substantially same voltage during an active mode of the semiconductor device. | 2022-02-17 |
20220052156 | SEMICONDUCTOR DEVICE - A semiconductor device includes a source region, a drain region, and a gate dielectric layer formed on a substrate; a gate electrode formed on the gate dielectric layer; a first dielectric pattern, formed contacting a sidewall of the gate electrode, extending from the source region to a portion of an upper surface of the gate electrode; a spacer formed on another sidewall of the gate electrode between the gate electrode and the drain region; and a gate silicide layer formed between the first dielectric pattern and the spacer. | 2022-02-17 |
20220052157 | Dual Side Contact Structures in Semiconductor Devices - A semiconductor device with dual side source/drain (S/D) contact structures and methods of fabricating the same are disclosed. The semiconductor device includes first and second S/D regions, a nanostructured channel region disposed between the first and second S/D regions, a gate structure surrounding the nanostructured channel region, first and second contact structures disposed on first surfaces of the first and second S/D regions, a third contact structure disposed on a second surface of the first S/D region, and an etch stop layer disposed on a second surface of the second S/D region. The third contact structure includes a metal silicide layer, a silicide nitride layer disposed on the metal silicide layer, and a conductive layer disposed on the silicide nitride layer. | 2022-02-17 |
20220052158 | FINFET WITH SHORTER FIN HEIGHT IN DRAIN REGION THAN SOURCE REGION AND RELATED METHOD - A FinFET includes a semiconductor fin, and a source region and a drain region in the same semiconductor fin. The drain region has a first fin height above a trench isolation; and the source region has a second fin height above the trench isolation. The first fin height is less than the second fin height. The FinFET may be used, for example, in a scaled laterally diffused metal-oxide semiconductor (LDMOS) application, and exhibits reduced parasitic capacitance for improved radio frequency (RF) performance. A drain extension region may have the first fin height, and a channel region may have the second fin height. A method of making the FinFET is also disclosed. | 2022-02-17 |
20220052159 | Forming Source And Drain Features In Semiconductor Devices - A method includes forming a first portion of a spacer layer over a first fin and a second portion of the spacer layer over a second fin, performing a first etching process to recess the first portion of the spacer layer with respect to the second portion of the spacer layer to form first spacers on sidewalls of the first fin, subsequently performing a second etching process to recess the second portion of the spacer layer with respect to the first spacers to form second spacers on sidewalls of the second fin, where the second spacers are formed to a height greater than that of the first spacers, and forming a first epitaxial source/drain feature and a second epitaxial source/drain feature between the first spacers and the second spacers, respectively, where the first epitaxial source/drain feature is larger than that of the second epitaxial source/drain feature. | 2022-02-17 |
20220052160 | SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - A semiconductor device is provided. The semiconductor device includes a semiconductor fin over a substrate, and a gate structure along sidewalls and the top surface of the semiconductor fin. The gate structure covers the first portion of the semiconductor fin. The semiconductor device also includes a source/drain feature adjacent to the gate structure. The semiconductor device further includes a source/drain contact connected to the source/drain feature. The source/drain contact extends downwards to a position that is lower than the top surface of the first portion of the semiconductor fin. | 2022-02-17 |
20220052161 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate including an active region in a first direction, a plurality of channel layers on the active region and disposed in a direction perpendicular to an upper surface of the substrate, a gate electrode respectively surrounding the plurality of channel layers, and a source/drain structure respectively disposed on both sides of the gate electrode in the first direction and connected to each of the plurality of channel layers. The gate electrode extends in a second direction crossing the first direction. The gate electrode includes an overlapped portion in a region of the gate electrode on an uppermost channel layer of the plurality of channel layers. The overlapped portion of the gate electrode overlaps the source/drain structure in the first direction and has a side surface inclined toward the upper surface of the substrate. | 2022-02-17 |
20220052162 | GATE STRUCTURES IN TRANSISTORS AND METHOD OF FORMING SAME - A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric around the first nanostructure; a second high-k gate dielectric around the second nanostructure; and a gate electrode over the first and second high-k gate dielectrics. The gate electrode includes a first work function metal; a second work function metal over the first work function metal; and a first metal residue at an interface between the first work function metal and the second work function metal, wherein the first metal residue has a metal element that is different than a metal element of the first work function metal. | 2022-02-17 |
20220052163 | GATE CONTROL FOR HEMT DEVICES USING DIELECTRIC BETWEEN GATE EDGES AND GATE FIELD PLATES - In a high electron mobility transistor (HEMT), dielectric material may be included between edge portions of a HEMT gate and gate field plates in contact with a HEMT gate electrode. At least some portions of the HEMT gate and HEMT gate electrode remain in direct contact with one another, and the HEMT gate electrode and gate field plates may be further connected to a gate metal. | 2022-02-17 |
20220052164 | TRANSISTOR DEVICE WITH BURIED FIELD ELECTRODE CONNECTION - A semiconductor device includes: a semiconductor substrate; trenches formed in the substrate and extending lengthwise in parallel with one another, the trenches having connecting regions which interconnect adjacent ones of the trenches; semiconductor mesas separated from one another by the trenches in a first lateral direction and by the connecting regions in a second lateral direction transverse to the first lateral direction; a gate electrode and a field electrode below the gate electrode in at least some of the trenches, and dielectrically insulated from each other and from the semiconductor substrate; first contacts vertically extending into one or more transistor device regions in the semiconductor mesas; and second contacts vertically extending into the field electrodes in the connecting regions such that the gate electrodes are uninterrupted by the second contacts. Corresponding methods of producing such a semiconductor device are also described. | 2022-02-17 |
20220052165 | SEMICONDUCTOR DEVICE INCLUDING A LATERAL INSULATOR - A semiconductor device, and methods of forming the same. In one example, the semiconductor device includes a trench in a substrate having a top surface, and a shield within the trench. The semiconductor device also includes a shield liner between a sidewall of the trench and the shield, and a lateral insulator over the shield contacting the shield liner. The semiconductor device also includes a gate dielectric layer on an exposed sidewall of the trench between the lateral insulator and the top surface. The lateral insulator may have a minimum thickness at least two times thicker than a maximum thickness of the gate dielectric layer. | 2022-02-17 |
20220052166 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR FORMING THE SAME - A high electron mobility transistor (HEMT) and method for forming the same are disclosed. The high electron mobility transistor includes a substrate, a mesa structure disposed on the substrate, a passivation layer disposed on the mesa structure, and at least a contact structure disposed in the passivation and the mesa structure. The mesa structure includes a channel layer and a barrier layer disposed on the channel layer. The contact structure includes a body portion and a plurality of protruding portions. The body portion is through the passivation layer. The protruding portions connect to a bottom surface of the body portion and through the barrier layer and a portion of the channel layer. | 2022-02-17 |
20220052167 | Method for Forming Source/Drain Contacts Utilizing an Inhibitor - A device includes a substrate, a gate structure over the substrate, a gate spacer on a sidewall of the gate structure, a source/drain (S/D) region adjacent to the gate spacer, a silicide on the S/D region, a dielectric liner over a sidewall of the gate spacer, wherein a bottom surface of the dielectric liner is spaced away from the silicide by a gap, and an S/D contact over the silicide and at least partially filling the gap. | 2022-02-17 |
20220052168 | COMMON RAIL CONTACT - A method according to the present disclosure includes receiving a workpiece including a gate structure, a first source/drain (S/D) feature, a second S/D feature, a first dielectric layer over the gate structure, the first S/D feature, the second S/D feature, a first S/D contact over the first S/D feature, a second S/D contact over the second S/D feature, a first etch stop layer (ESL) over the first dielectric layer, and a second dielectric layer over the first ESL, forming a S/D contact via through the second dielectric layer and the first ESL to couple to the first S/D contact, forming a gate contact opening through the second dielectric layer, the first ESL, and the first dielectric layer to expose the gate structure, and forming a common rail opening adjoining the gate contact opening to expose the second S/D contact, and forming a common rail contact in the common rail opening. | 2022-02-17 |
20220052169 | Semiconductor Device and Method - In an embodiment, a device includes: a gate structure over a substrate; a gate spacer adjacent the gate structure; a source/drain region adjacent the gate spacer; a first inter-layer dielectric (ILD) on the source/drain region, the first ILD having a first concentration of an impurity; and a second ILD on the first ILD, the second ILD having a second concentration of the impurity, the second concentration being less than the first concentration, top surfaces of the second ILD, the gate spacer, and the gate structure being coplanar; and a source/drain contact extending through the second ILD and the first ILD, the source/drain contact coupled to the source/drain region. | 2022-02-17 |
20220052170 | MOSFET WITH DISTRIBUTED DOPED P-SHIELD ZONES UNDER TRENCHES - A vertical trench MOSFET is formed with deep P-shield regions below portions of each gate trench. The deep P-shield regions are effectively downward extensions of the P-body/well, and are electrically coupled to the top source electrode. The P-shield regions abut the bottom portions and lower sides of the gate trenches, so that those small portions of the gate trench do not create N-channels and do not conduct current. Accordingly, each trench comprises an active gate portion that creates an N-channel and a small non-active portion that abuts the P-shield regions. The spacing of the P-shield regions along each gate trench is selected to achieve the desired electric field spreading to protect the gate oxide from punch-through. No field plate trenches are needed to be formed in the active area of the MOSFET. The deep P-shield regions are formed by implanting P-type dopants through the bottom of the trenches. | 2022-02-17 |
20220052171 | TRANSISTOR COMPONENT HAVING GATE ELECTRODES AND FIELD ELECTRODES - A transistor includes: gate electrodes and field electrodes, wherein in each case one gate electrode and one field electrode are arranged one above another in a vertical direction in a common trench of a semiconductor body; a gate pad to which the gate electrodes are connected; and a source metallization arranged above the semiconductor body. The field electrodes of a first group include at least one contact section. The at least one contact section is arranged between two sections of a gate electrode arranged in the same trench and is connected to the source metallization. The two sections of the gate electrode are separated from one another in a region of the contact section. At least one of the two sections of the gate electrode arranged in the same trench is electrically connected to a gate electrode arranged in a further trench by way of a gate connecting electrode. | 2022-02-17 |
20220052172 | VERTICAL THIN FILM TRANSISTOR WITH PERFORATED OR COMB-GATE ELECTRODE CONFIGURATION AND FABRICATION METHODS FOR SAME - The present invention provides a vertical-type thin film transistor (TFT) and methods of fabricating vertical TFTs. The vertical TFT may comprise a source electrode and a drain electrode, the drain electrode and the source electrode being positioned on vertically separated planes. A semiconductor layer may be arranged in between the source electrode and the drain electrode. At least one gate electrode may be embedded in the semiconductor layer. At least one of the source electrode and the drain electrode comprise patterned electrodes. One or all of the gate electrodes, the source electrode and the drain electrode may be patterned electrodes. The patterned electrodes may comprise one or more of fingers or combs, micro perforations, a mesh structure, or a lattice structure. Back side exposed fabrication techniques may be used to fabricate various of the vertical TFT embodiments. | 2022-02-17 |
20220052173 | Semiconductor Device and Method - In an embodiment, a device includes: a gate dielectric over a substrate; a gate electrode over the gate dielectric, the gate electrode including: a work function tuning layer over the gate dielectric; a glue layer over the work function tuning layer; a fill layer over the glue layer; and a void defined by inner surfaces of at least one of the fill layer, the glue layer, and the work function tuning layer, a material of the gate electrode at the inner surfaces including a work function tuning element. | 2022-02-17 |
20220052174 | Spacer Structure for Semiconductor Device - The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over the fin structure, a first inner spacer layer formed in the fin structure and adjacent to the gate structure, and a second inner spacer layer extending through the first inner spacer layer. | 2022-02-17 |
20220052175 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THEREOF - A semiconductor structure includes a substrate, a conductive region, a first insulation layer, a second insulation layer, a gate structure, a low-k spacer, a gate contact, and a conductive region contact. The low-k spacer is formed between a sidewall of the gate structure and the first insulation layer. The gate contact is landed on a top surface of the gate structure. A proximity distance between a sidewall of the gate contact and the conductive region contact along a top surface of the second insulation layer is in a range of from about 4 nm to about 7 nm. A method for manufacturing a semiconductor structure is also provided. | 2022-02-17 |
20220052176 | SILICON CARBIDE METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present disclose relates to a SiC MOSFET device and a manufacturing method thereof. The method includes providing a semiconductor base of a first doping type; forming a patterned first barrier layer on an upper surface; forming a source region extending from the upper surface to the interior of the semiconductor base by taking the first barrier layer as a mask, wherein the source region is of the first doping type; etching a part of the first barrier layer to form a second barrier layer, and allowing anion implantation window of the second barrier layer to be larger than the ion implantation window of the first barrier layer; forming a first type base region by taking the second barrier layer as a mask, wherein the first type base region is of a second doping type; and forming a contact region of the second doping type. | 2022-02-17 |
20220052177 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device of the present invention includes a semiconductor layer, a gate trench that defines a source region of a first conductivity type in the semiconductor layer, a channel region of a second conductivity type of a lower part of the source region, a source trench that passes through the source region and the channel region, an impurity region of the second conductivity type of a bottom part and a side part of the source trench, a source electrode on the semiconductor layer, and a highly-concentrated impurity region of the second conductivity type, the highly-concentrated impurity region having a contact portion connected to the source electrode at a surface of the semiconductor layer, the highly-concentrated impurity region passing through the source region and extending to a position deeper than the source region, the highly-concentrated impurity region having a concentration higher than the impurity region. | 2022-02-17 |
20220052178 | SELF-ALIGNED NANOWIRE - A method comprising: forming a substrate; forming a first nanowire over the substrate; forming a second nanowire over the substrate; forming a gate over a portion of the first and second nanowires; implanting a dopant such that a region between the first and second nanowires under the gate does not receive the dopant while a region between the first and second nanowires away from the gate receives the dopant, wherein the dopant amorphize a material of the region between the first and second nanowires away from the gate; and isotopically etching of the region between the first and second nanowires away from the gate. | 2022-02-17 |
20220052179 | METHOD FOR MAKING A QUANTUM DEVICE WITH NUCLEAR SPIN QUBITS - A method for making a quantum device including:
| 2022-02-17 |
20220052180 | Manufacturing Method For A Semiconductor Device - The present invention provides a manufacturing method for a semiconductor memory device. The method comprises: providing a substrate, wherein a gate structure of a memory transistor is formed on a memory area of the substrate, and a first layer used for forming a gate structure of a peripheral transistor is formed on a peripheral area of the substrate; performing lightly doped drain ion implantation on an upper part of a portion, on two sides of the gate structure of the memory transistor, of the memory area of the substrate by applying the first layer as a mask of the peripheral area; and etching the first layer to form the gate structure of the peripheral transistor. According to the present invention, an ion diffusion degree of source and drain electrodes of the memory area may be effectively increased, and the uniformity of a memory cell device is improved. | 2022-02-17 |
20220052181 | NANOSHEET FIELD-EFFECT TRANSISTOR DEVICE AND METHOD OF FORMING - A method of forming a semiconductor device includes: forming a dummy gate structure over a nanostructure, where the nanostructure overlies a fin that protrudes above a substrate, where the nanostructure comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the nanostructure on opposing sides of the dummy gate structure, the openings exposing end portions of the first semiconductor material and end portions of the second semiconductor material; recessing the exposed end portions of the first semiconductor material to form first sidewall recesses; filling the first sidewall recesses with a multi-layer spacer film; removing at least one sublayer of the multi-layer spacer film to form second sidewall recesses; and forming source/drain regions in the openings after removing at least one sublayer, where the source/drain regions seal the second sidewall recesses to form sealed air gaps. | 2022-02-17 |
20220052182 | Method for Producing a Superjunction Device - Disclosed is a method for producing a semiconductor device, the method including forming a plurality of semiconductor arrangements one above the other, wherein forming each of the plurality of semiconductor arrangements includes forming a semiconductor layer, forming a plurality of trenches in a first surface of the semiconductor layer, and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches. Forming of at least one of the plurality of semiconductor arrangements further includes forming a protective layer covering mesa regions between the plurality of trenches of the respective semiconductor layer, and covering a bottom, the first sidewall and the second sidewall of each of the plurality of trenches that are formed in the respective semiconductor layer. | 2022-02-17 |
20220052183 | FinFETs With Epitaxy Regions Having Mixed Wavy and Non-Wavy Portions - A method includes forming a first fin-group having has a plurality of semiconductor fins, and a second fin-group. The plurality of semiconductor fins include a first semiconductor fin, which is farthest from the second fin-group among the first fin-group, a second semiconductor fin, and a third semiconductor fin, which is closest to the second fin-group among the first fin-group. The method further includes performing an epitaxy process to form an epitaxy region based on the plurality of semiconductor fins. The epitaxy region includes a first portion and a second portion. The first portion is in middle between the first semiconductor fin and the second semiconductor fin. The first portion has a first top surface. The second portion is in middle between the second semiconductor fin and the third semiconductor fin. The second portion has a second top surface lower than the first top surface. | 2022-02-17 |
20220052184 | Profile Control In Forming Epitaxy Regions for Transistors - A method includes etching a silicon layer in a wafer to form a first trench in a first device region and a second trench in a second device region, performing a pre-clean process on the silicon layer, performing a baking process on the wafer, and performing an epitaxy process to form a first silicon germanium region and a second silicon germanium region in the first trench and the second trench, respectively. The first silicon germanium region and the second silicon germanium region have a loading in a range between about 5 nm and about 30 nm. | 2022-02-17 |
20220052185 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. One form of a method for forming a semiconductor structure includes: providing a base, the base including a first device region and a second device region, the base including an initial substrate and one or more initial channel stacks located on the initial substrate, and the initial channel stack including a sacrificial material layer and a channel material layer located on the sacrificial material layer; forming a discrete combined pattern on the initial channel stack, the combined pattern including a mandrel layer and a spacer layer located on a side wall of the mandrel layer, and the combined pattern exposing a boundary between the first device region and the second device region; forming a dielectric wall running through the initial channel stack at the boundary between the first device region and the second device region; and removing the mandrel layer. In embodiments and implementations of the present disclosure, the spacer layer has good uniformity, and the initial channel stack is etched by using the spacer layer as a mask to form a separate channel stack which has good morphology uniformity, which is conducive to improving the uniformity of the semiconductor structure performance. | 2022-02-17 |
20220052186 | MULTIPLE PLANES OF TRANSISTORS WITH DIFFERENT TRANSISTOR ARCHITECTURES TO ENHANCE 3D LOGIC AND MEMORY CIRCUITS - Microfabrication of a collection of transistor types on multiple transistor planes in which both HV (high voltage transistors) and LV (low-voltage transistors) stacks are designed on a single substrate. As high voltage transistors require higher drain-source voltages (Vds), higher gate voltages (Vg), and thus higher V | 2022-02-17 |
20220052187 | SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device and a semiconductor device, the method including forming an active pattern on a substrate such that the active pattern includes sacrificial patterns and semiconductor patterns alternately and repeatedly stacked on the substrate; and forming first spacer patterns at both sides of each of the sacrificial patterns by performing an oxidation process, wherein the first spacer patterns correspond to oxidized portions of each of the sacrificial patterns, wherein the sacrificial patterns include a first semiconductor material containing impurities, wherein the semiconductor patterns include a second semiconductor material different from the first semiconductor material, and wherein the impurities include an element different from semiconductor elements of the first semiconductor material and the second semiconductor material. | 2022-02-17 |
20220052188 | HETEROJUNCTION BIPOLAR TRANSISTOR AND METHOD FOR FORMING THE SAME - A heterojunction bipolar transistor includes an emitter layer on a base layer on a collector layer on an upper sub-collector layer over a bottom sub-collector layer, a first dielectric film over the bottom sub-collector layer, the base layer and the emitter layer, a base electrode on the first dielectric film, electrically connected to the base layer through at least one first via hole in the first dielectric film, a second dielectric film on the first dielectric film and the base electrode, and a conductive layer on the second dielectric film, with conductive layer electrically connected to base electrode through a second via hole disposed in the second dielectric film, first dielectric film between the base electrode and first sidewall of a stack including the base layer and the collector layer, and second via hole laterally separated from the base layer. | 2022-02-17 |
20220052189 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor chip having a first electrode and a second electrode on a first surface and having a third electrode on a second surface that is opposite to the first surface; a second semiconductor chip having a first electrode and a second electrode on a first surface and having a third electrode on a second surface that is opposite to the first surface; a first electrode plate bonded to the second electrode of the first semiconductor chip by a bonding material; a second electrode plate bonded to the third electrode of the second semiconductor chip by a bonding material; and a third electrode plate placed between the first semiconductor chip and the second semiconductor chip and having a first area sandwiched between the first semiconductor chip and the second semiconductor chip and a second area not sandwiched between the first semiconductor chip and the second semiconductor chip, wherein one surface of the first area of the third electrode plate is bonded to the second electrode of the second semiconductor chip by a bonding material, and another surface of the first area of the third electrode plate is bonded to the third electrode of the first semiconductor chip by a bonding material, and wherein in the third electrode plate, the first area is thinner than the second area. | 2022-02-17 |
20220052190 | Power Semiconductor Device Including First and Second Trench Structures - A power semiconductor device first trench structures extending from a first main surface into a semiconductor body up to a first depth. The first trench structures extend in parallel along a first lateral direction. Each first trench structure includes a first dielectric and a first electrode. The power semiconductor device further includes second trench structures extending from the first main surface into the semiconductor body up to a second depth that is smaller than the first depth. The second trench structures extend in parallel along a second lateral direction and intersect the first trenches at intersection positions. Each second trench structure includes a second dielectric and a second electrode. The second dielectric is arranged between the first electrode and the second electrode at the intersection positions. | 2022-02-17 |
20220052191 | SEMICONDUCTOR STRUCTURE AND PREPARATION METHOD THEREFOR - Disclosed are a semiconductor structure and a preparation method therefor. The semiconductor structure includes: a substrate, a channel layer, a barrier layer, a gate structure, a source, and a drain, where the gate structure includes a p-type semiconductor layer, an n-type semiconductor layer, and a gate. In this way, a control capability of a gate to a channel is improved; a threshold voltage of a semiconductor device is improved, avoiding vertical electric leakage of a gate structure, and reducing side electric leakage of the gate structure; and channel degradation is avoided, improving overall output characteristics of the device. | 2022-02-17 |
20220052192 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure is provided. The semiconductor structure includes fin structures and a gate structure across the fin structures. The gate structure includes a gate dielectric layer over fin structures, a work function layer over the gate dielectric layer, and a contact layer over the work function layer. In some embodiments, a portion of the work function layer is located between the fin structures, and a top surface of the portion is higher than a top surface of the fin structures. A method for forming a semiconductor structure is also provided. | 2022-02-17 |
20220052193 | SINGLE DIFFUSION BREAKS INCLUDING STACKED DIELECTRIC LAYERS - Structures for a single diffusion break and methods of forming a structure for a single diffusion break. A cut is formed in a semiconductor fin. A single diffusion break includes a first dielectric layer in the cut and a second dielectric layer over the first dielectric layer. The first dielectric layer is comprised of a first material, and the second dielectric layer is comprised of a second material having a different composition than the first material. The second dielectric layer includes a first portion over the first dielectric layer and a second portion over the first portion. The first portion of the second dielectric layer has a first horizontal dimension, and the second portion of the second dielectric layer has a second horizontal dimension that is greater than the first horizontal dimension. | 2022-02-17 |
20220052194 | SPLIT-GATE TRENCH POWER MOSFET WITH SELF-ALIGNED POLY-TO-POLY ISOLATION - A semiconductor substrate has a trench extending from a front surface and including a lower part and an upper part. A first insulation layer lines the lower part of the trench, and a first conductive material in the lower part is insulated from the semiconductor substrate by the first insulating layer to form a field plate electrode of a transistor. A second insulating layer lines sidewalls of the upper part of said trench. A third insulating layer lines a top surface of the first conductive material at a bottom of the upper part of the trench. A second conductive material fills the upper part of the trench. The second conductive material forms a gate electrode of the transistor that is insulated from the semiconductor substrate by the second insulating layer and further insulated from the first conductive material by the third insulating layer. | 2022-02-17 |
20220052195 | TRENCH GATE TRENCH FIELD PLATE VERTICAL MOSFET - A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions. | 2022-02-17 |
20220052196 | HIGH VOLTAGE SEMICONDUCTOR DEVICE - A high voltage semiconductor device includes a semiconductor substrate, a gate structure, a drift region, a drain region, and an isolation structure. The gate structure is disposed on the semiconductor substrate. The drift region is disposed in the semiconductor substrate and partially disposed at a side of the gate structure. The drain region is disposed in the drift region. The isolation structure is at least partially disposed in the drift region. A part of the isolation structure is disposed between the drain region and the gate structure. The isolation structure includes a curved bottom surface. | 2022-02-17 |
20220052197 | SEMICONDUCTOR DEVICE - There is provided a high withstand voltage LDMOS field-effect transistor that enables the compatibility of an increase of its withstand voltage and a decrease of its ON resistance. The high withstand voltage LDMOS is characterizing in including: a first electroconductive type body region formed on a main surface of a semiconductor substrate; a second electroconductive type source region formed on a surface of the body region; a second electroconductive type drift region formed so as to have contact with the body region; a second electroconductive type drain region formed on the drift region; a first electroconductive type buried region having contact with the body region and formed below the drift region; a gate electrode formed above the body region between the source region and the drift region and above the drift region nearer to the source region via a gate insulating film; a first field plate that extends from the gate electrode toward the drain region and that is formed above the drift region via a first insulating film; and a second field plate that has contact with the source region or the gate electrode and that is formed above the first field plate via a second insulating film, in which a distance between the buried region and the drain region is smaller than a distance between the first field plate and the drain region and larger than a distance between the second field plate and the drain region. | 2022-02-17 |
20220052198 | SCHOTTKY BARRIER THIN FILM TRANSISTOR AND ITS METHOD OF MANUFACTURE - Device and method A Schottky barrier thin-film transistor (SBTFT) | 2022-02-17 |
20220052199 | FIN STRUCTURE FOR FIN FIELD EFFECT TRANSISTOR AND METHOD FOR FABRICATION THE SAME - The invention provides a fin structure for a fin field effect transistor, including a substrate. The substrate includes a plurality of silicon fins, wherein a top of each one of the silicon fins is a round-like shape in a cross-section view. An isolation layer is disposed on the substrate between the silicon fins at a lower portion of the silicon fins while an upper portion of the silicon fins is exposed. A stress buffer layer is disposed on a sidewall of the silicon fins between the isolation layer and the lower portion of the silicon fins. The stress buffer layer includes a nitride portion. | 2022-02-17 |
20220052200 | TRANSISTOR STRUCTURES WITH A METAL OXIDE CONTACT BUFFER - Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition. | 2022-02-17 |
20220052201 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a first fin structure over the substrate, and a FeFET device over a first region of the substrate. The FeFET includes a first gate stack across the first fin structure. The semiconductor device structure also includes first gate spacer layers alongside the first gate stack, and a ferroelectric layer over the first gate stack. At least a portion of the ferroelectric layer is located between upper portions of the first gate spacer layers and is adjacent to the first gate stack. | 2022-02-17 |
20220052202 | ELECTRONIC DEVICE INCLUDING FERROELECTRIC LAYER - An electronic device includes a ferroelectric layer arranged on a channel region and a gate electrode arranged on the ferroelectric layer. The ferroelectric layer includes a plurality of first oxide monolayers and a second oxide monolayers that is arranged between the substrate and the gate electrode and include a material different from a material of the first oxide monolayers. The first oxide monolayers include oxide monolayers that are alternately formed and include materials different from one another. | 2022-02-17 |
20220052203 | EPITAXIAL STRUCTURES FOR SEMICONDUCTOR DEVICES - The present disclosure describes a semiconductor device and methods for forming the same. The semiconductor device includes nanostructures on a substrate and a source/drain region in contact with the nanostructures. The source/drain region includes epitaxial end caps, where each epitaxial end cap is formed at an end portion of a nanostructure of the nanostructures. The source/drain region also includes an epitaxial body in contact with the epitaxial end caps and an epitaxial top cap formed on the epitaxial body. The semiconductor device further includes gate structure formed on the nanostructures. | 2022-02-17 |
20220052204 | AMORPHOUS SILICON THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - The present invention provides an amorphous silicon thin film transistor and a manufacturing method of the amorphous silicon thin film transistor, which comprise: a substrate, a gate electrode layer, a gate insulating layer, an active layer, a source/drain electrode layer, an N+-doped layer, a protective insulating layer, and a passivation layer. The N+-doped layer is disposed between the active layer and the source/drain electrode layer. The protective insulating layer is disposed on the source/drain electrode layer. A channel is formed in the source/drain electrode layer and penetrates the N+-doped layer and the protective insulating layer. The passivation layer covers the channel and the protective insulating layer. The protective insulating layer and the source/drain electrode layer are flush with each other in the channel. | 2022-02-17 |
20220052205 | STRUCTURE WITH POLYCRYSTALLINE ACTIVE REGION FILL SHAPE(S), AND RELATED METHOD - A structure includes a semiconductor-on-insulator (SOI) substrate including a semiconductor substrate, a buried insulator layer over the semiconductor substrate, and an SOI layer over the buried insulator layer. At least one polycrystalline active region fill shape is in the SOI layer. A polycrystalline isolation region may be in the semiconductor substrate under the buried insulator layer. The at least one polycrystalline active region fill shape is laterally aligned over the polycrystalline isolation region, where provided. Where provided, the polycrystalline isolation region may extend to different depths in the semiconductor substrate. | 2022-02-17 |
20220052206 | Multigate Devices with Varying Channel Layers - Multigate devices and methods for fabricating such are disclosed herein. An exemplary multigate device includes a first FET disposed in a first region; and a second FET disposed in a second region of a substrate. The first FET includes first channel layers disposed over the substrate, and a first gate stack disposed on the first channel layers and extended to warp around each of the first channel layers. The second FET includes second channel layers disposed over the substrate, and a second gate stack disposed on the second channel layers and extended to warp around each of the second channel layers. A number of the first channel layers is greater than a number of the second channel layers. A bottommost one of the first channel layers is below a bottommost one of the second channel layers. | 2022-02-17 |
20220052207 | SEMICONDUCTOR DEVICE STRUCTURES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device structure and a method for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a third nitride semiconductor layer, a first electrode and a second electrode. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The third nitride semiconductor layer is disposed on the second nitride semiconductor layer. The first electrode is disposed on the second nitride semiconductor layer and spaced apart from the third nitride semiconductor layer. The second electrode covers an upper surface of the third nitride semiconductor layer and is in direct contact with the first nitride semiconductor layer. | 2022-02-17 |
20220052208 | SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE - The capacity of a MOS capacitor is increased. A semiconductor element includes a first semiconductor region, an insulation film, a gate electrode, and a second semiconductor region. The first semiconductor region is arranged on a semiconductor substrate and has a recess on the surface. The insulation film is arranged adjacent to the surface of the first semiconductor region. The gate electrode is arranged adjacent to the insulation film and constitutes a MOS capacitor with the first semiconductor region. The second semiconductor region is arranged adjacent to the first semiconductor region on the semiconductor substrate, formed in the same conductive type as the first semiconductor region, and supplies a carrier to the first semiconductor region when the MOS capacitor is charged and discharged. | 2022-02-17 |
20220052209 | Feed-Through Wiring Solution for Solar Cell Modules - The present disclosure provides a solar cell module, comprising (a) a laminate substrate having a first surface and a second surface opposite the first surface, (b) a solar cell positioned on the first surface of the laminate substrate, (c) a first contact pad positioned on the first surface of the laminate substrate adjacent to the solar cell, (d) a second contact pad positioned on the second surface of the laminate substrate, (e) one or more vias positioned through the laminate substrate to electrically connect the first contact pad to the second contact pad, and (f) one or more interconnects extending from the solar cell and electrically coupling the solar cell to the first contact pad. | 2022-02-17 |
20220052210 | HIGH SPEED PHOTOSENSITIVE DEVICES AND ASSOCIATED METHODS - High speed optoelectronic devices and associated methods are provided. In one aspect, for example, a high speed optoelectronic device can include a silicon material having an incident light surface, a first doped region and a second doped region forming a semiconductive junction in the silicon material, and a textured region coupled to the silicon material and positioned to interact with electromagnetic radiation. The optoelectronic device has a response time of from about 1 picosecond to about 5 nanoseconds and a responsivity of greater than or equal to about 0.4 A/W for electromagnetic radiation having at least one wavelength from about 800 nm to about 1200 nm. | 2022-02-17 |
20220052211 | METHOD FOR MANUFACTURING POROUS POLYSILOXANE FILM, POROUS POLYSILOXANE FILM MANUFACTURED THEREBY, AND SOLAR CELL MODULE COMPRISING SAME - The purpose of the present invention is to provide a method for manufacturing a solar cell module, comprising the steps of: placing a mixture solution comprising a polysiloxane and a curing agent in a humidified condition and sealing same; forming a polysiloxane film by curing the mixture solution; and manufacturing a porous polysiloxane film by evaporating water drops formed on the surface of the polysiloxane film. By applying the porous polysiloxane film manufactured by the present invention to a solar cell module, weight reduction and efficiency improvement effects of the solar cell module can be obtained. | 2022-02-17 |
20220052212 | Photodetector based on PtSe2 and silicon nanopillar array and preparation method thereof - A photodetector based on PtSe | 2022-02-17 |
20220052213 | SUPERLATTICE ABSORBER FOR DETECTOR - A superlattice absorber for a detector is provided. The superlattice absorber includes a plurality of material periods deposited successively. Each of the material periods includes a first layer of InAs, InGaAs, InAsSb or InGaAsSb; and a plurality of second layers of InGaAsSb. The second layers comprise at least two InGaAsSb layers with at least two different content combinations. The content of the second layers is different from that of the first layer. | 2022-02-17 |
20220052214 | OBTAINING A PV FILM STRUCTURE BY MEANS OF A ROOM TEMPERATURE METHOD AND ROOM TEMPERATURE METHOD FOR PRODUCING A PV FILM STRUCTURE - The invention provides a suitable method and an appropriate, PV film structure. This aim is achieved by a room temperature method in which aqueous dispersions are printed onto a substrate and cured by an accompanying reaction. The accompanying reaction forms gradients and also nanoscale structures at the film boundaries, which produce a PV active film having standard performance and a higher stability. At around 10% efficiency, stability and no initial loss in performance in the climatic chamber test can be obtained and over a 20 year test period, consistently less fluctuation can be achieved. The method is free from tempering or sintering steps, enables the use of technically pure, advantageous starting materials and makes the PV film structure available as a finished, highly flexible cell for a fraction of the typical investment in production or distribution. | 2022-02-17 |
20220052215 | CONCENTRATOR PHOTOVOLTAIC SYSTEM - A photovoltaic solar concentrator comprising a non-tracking lens adapted to reach the limits of Etendue conservation for acceptance of a direct and a diffuse solar insolation and to emit a focused light onto an upper surface of a luminescent solar concentrator (LSC). The LSC comprises a crystal with an un-doped semiconductor with high luminescence efficiency in the form of a waveguide that includes a top-hat multi-layer reflector to reflect photo-luminescence within an escape cone of the crystal. A mirror attached to the bottom surface. Mirrors attached to all edges of the crystal except for one of the edges. A solar cell mounted on an un-mirrored edge, or optically connected to the un-mirrored edge of the crystal by a second waveguide, to receive the photo-luminescence trapped within the waveguide. | 2022-02-17 |
20220052216 | PHOTOELECTRIC CONVERSION ELEMENT AND METHOD FOR MANUFACTURING PHOTOELECTRIC CONVERSION ELEMENT - A photoelectric conversion element having a photoelectric conversion layer formed between a first electrode layer and a second electrode layer, in which the photoelectric conversion layer contains Cu and Ag, which are Group I elements, In and Ga, which are Group III elements, and Se and S, which are Group VI elements. A portion at which a minimum value of a band gap appears in a thickness direction of the photoelectric conversion layer is included in the intermediate region. When a ratio of a mole amount of Ag to a sum of mole amounts of the Group I elements other than Ag, the Group III elements, and the Group VI elements is defined as an Ag concentration, a portion at which a maximum value of the Ag concentration appears in the thickness direction of the photoelectric conversion layer is included in the intermediate region. | 2022-02-17 |
20220052217 | Monolithic Silicon Photomultiplier Array - An optical system may include a substrate and a plurality of silicon photomultipliers (SiPMs) monolithically integrated with the substrate. Each SiPM may include a plurality of single photon avalanche diodes (SPADs). The optical system also includes an aperture array having a plurality of apertures. The plurality of SiPMs and the aperture array are aligned so as to define a plurality of receiver channels. Each receiver channel includes a respective SiPM of the plurality of SiPMs optically coupled to a respective aperture of the plurality of apertures. | 2022-02-17 |
20220052218 | SILICON CARBIDE-BASED FULL-SPECTRUM-RESPONSIVE PHOTODETECTOR AND METHOD FOR PRODUCING SAME - The present application relates to semiconductor photodetectors, in particular to a silicon carbide-based UV-visible-NIR full-spectrum-responsive photodetector and a method for fabricating the same. The photodetector includes a silicon carbide substrate, and metal counter electrodes and a surface plasmon polariton nanostructure arranged thereon. The silicon carbide substrate and the metal counter electrodes constitute a metal-semiconductor-metal photodetector with coplanar electrodes. When the ultraviolet light is input, free carriers directly generated in silicon carbide are collected by an external circuit to generate electrical signals. When the visible light is input, hot carriers generated in the surface plasmon polariton nanostructure tunnel into the silicon carbide semiconductor to become free carriers to generate electrical signals. | 2022-02-17 |
20220052219 | ARRAY SUBSTRATE, FABRICATION METHOD FOR ARRAY SUBSTRATE, AND DISPLAY PANEL - Embodiments of the present application provide an array substrate, a fabrication method for an array substrate, and a display panel. The array substrate includes a substrate, a gate, a gate insulating layer, a seed layer, and a semiconductor layer that are sequentially stacked. A surface of the semiconductor layer away from the seed layer has a concave-convex structure formed by growth of nanocrystalline grains, which enhances light absorption of the semiconductor layer and solves the problems of poor light sensitivity and slow response speed of semiconductor devices. | 2022-02-17 |
20220052220 | METHOD FOR RECOVERING RESOURCE FROM CIGS THIN-FILM SOLAR CELL - A method for recovering a resource from a CIGS thin-film solar cell to be recycled includes a) providing the CIGS thin-film solar cell, and b) subjecting the CIGS thin-film solar cell to a cooling treatment at a predetermined temperature, such that a light absorbing unit of the CIGS thin-film solar cell can be recovered due to thermal strain difference of materials of the CIGS thin-film solar cell. | 2022-02-17 |
20220052221 | REDUCED DARK CURRENT PHOTODETECTOR WITH CHARGE COMPENSATED BARRIER LAYER - A photodetector comprising a photoabsorber, comprising a doped semiconductor, a contact layer comprising a doped semiconductor and a barrier layer comprising a charge carrier compensated semiconductor, the barrier layer compensated by doping impurities such that it exhibits a valence band energy level substantially equal to the valence band energy level of the photo absorbing layer and a conduction band energy level exhibiting a significant band gap in relation to the conduction band of the photo absorbing layer, the barrier layer disposed between the photoabsorber and contact layers. The relationship between the photo absorbing layer and contact layer valence and conduction band energies and the barrier layer conduction and valance band energies is selected to facilitate minority carrier current flow while inhibiting majority carrier current flow between the contact and photo absorbing layers. | 2022-02-17 |
20220052222 | PIXEL DEVICE AND DISPLAY USING A MONOLITHIC BLUE/GREEN LED COMBINED WITH RED LUMINESCENCE MATERIALS - An LED has: a substrate formed as a substrate layer; a buffer layer formed on the substrate layer; and an N− doped layer formed on the buffer layer. A first dual color blue/green MQW active region, a negative electrode, and a second dual color blue/green MQW active region formed on the N− doped layer. A first P− doped layer is formed on the first dual color blue green MQW active region. A second P− doped layer is formed on the second dual color blue green MQW active region. A first P+ doped layer is formed on the first P− doped layer. A second P+ doped layer is formed on the second P− doped layer. A first positive electrode is formed on the first P+ doped layer. A second positive electrode is formed on the second P+ doped layer. A blue/green LED with red luminescence materials emits a full spectrum. | 2022-02-17 |
20220052223 | ADVANCED ELECTRONIC DEVICE STRUCTURES USING SEMICONDUCTOR STRUCTURES AND SUPERLATTICES - Semiconductor structures and methods for forming those semiconductor structures are disclosed. For example, a semiconductor structure with a p-type superlattice region, an i-type superlattice region, and an n-type superlattice region is disclosed. The semiconductor structure can have a polar crystal structure with a growth axis that is substantially parallel to a spontaneous polarization axis of the polar crystal structure. In some cases, there are no abrupt changes in polarisation at interfaces between each region. At least one of the p-type superlattice region, the i-type superlattice region and the n-type superlattice region can comprise a plurality of unit cells exhibiting a monotonic change in composition from a wider band gap (WBG) material to a narrower band gap (NBG) material or from a NBG material to a WBG material along the growth axis to induce p-type or n-type conductivity. | 2022-02-17 |
20220052224 | LIGHT-EMITTING DIODE, MANUFACTURING METHOD THEREOF AND DISPLAY - A light emitting diode (LED) is provided in the disclosure. The LED includes a first contact electrode, a first semiconductor layer, a light emitting layer, a second semiconductor layer, a current diffusion layer and a second contact electrode that are successively stacked. Multiple micro-structures extend through the light emitting layer and the second semiconductor layer in a stacking direction of the light emitting layer and the second semiconductor layer, where the multiple micro-structures each defines a borehole space. The borehole space has opposite ends which are respectively closed by the first semiconductor layer and the current diffusion layer. Quantum dots are filled in the borehole space of the multiple micro-structures. Lights of corresponding colors are emitted by exciting corresponding quantum dots with a part of blue lights emitted by the micro-structures. | 2022-02-17 |
20220052225 | DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE - A display substrate includes a base, a plurality of light-emitting devices disposed on a side of the base, and a light adjustment layer. The plurality of light-emitting devices are spaced apart from each other. At least part of the light adjustment layer is located in gaps among the plurality of light-emitting devices, so that side walls of at least one of the plurality of light-emitting devices are surrounded by the light adjustment layer. A material of the light adjustment layer includes a light-absorbing material. The light adjustment layer is configured to absorb light incident on the light adjustment layer. | 2022-02-17 |
20220052226 | BREATHABLE MICRO LIGHT EMITTING DIODE DISPLAY - A micro light emitting diode display includes a substrate, an electrode layer disposed on the substrate, a micro light emitting diode device disposed on the electrode layer, a metal layer disposed on the substrate and connected to the electrode layer, and first and second encapsulation layers. The substrate has an air passage extending to opposite surfaces thereof. The first encapsulation layer wraps the micro light emitting diode device. The second encapsulation layer covers the metal layer and has a material different from that of the first encapsulation layer. The metal layer has a visible area in a display region of the substrate that is not covered by the micro light emitting diode device. A part of the visible area is covered by the second encapsulation layer, and a proportion of the part to the visible area is equal to or greater than 60%. | 2022-02-17 |
20220052227 | LIGHT-EMITTING ELEMENT, METHOD OF FABRICATING THE LIGHT-EMITTING ELEMENT, AND DISPLAY DEVICE - A light-emitting element includes a first semiconductor layer doped to have a first polarity, a second semiconductor layer doped to have a second polarity different from the first polarity, a light-emitting layer disposed between the first and second semiconductor layers, a shell layer formed on side surfaces of the first semiconductor layer, the light-emitting layer, and the second semiconductor layer, the shell layer including a divalent metal element, and an insulating film covering an outer surface of the shell layer and surrounding the side surface of the light-emitting layer. | 2022-02-17 |
20220052228 | PIXEL AND DISPLAY DEVICE INCLUDING THE SAME - A display device includes a base layer including a pixel area, and a pixel in the pixel area. The pixel includes a first area, and a second area enclosing the first area in a plan view, bank patterns at the pixel area, extending in a first direction, spaced from each other by a first distance in the first area, and spaced from each other by a third distance that is greater than the first distance in the second area, a first electrode and a second electrode at an area of the bank patterns, and spaced from each other by a second distance that is less than the first distance in the first area, a first insulating layer at a portion of the pixel area including the first area to cover the first electrode and the second electrode and removed from another portion of the pixel area including opposite edge portions. | 2022-02-17 |
20220052229 | LIGHT-EMITTING DEVICE PACKAGE CAPABLE OF IMPLEMENTING SURFACE LIGHT SOURCE, LIGHT-EMITTING MODULE, AND MANUFACTURING METHOD THEREFOR - A surface light source slim module mounted to a vehicle includes: a substrate; a plurality of packages; a first reflective layer formed on top of the substrate and having a plurality of holes; a molding member, which is formed on top of the first reflective layer, covers the plurality of packages and the first reflective layer, and includes a front portion through which light is output and a rear portion facing the front portion; and a second reflective layer formed on top of the molding member. | 2022-02-17 |
20220052230 | LIGHT-EMITTING DEVICE, LIGHT-EMITTING ASSEMBLY, AND INTEGRATED CIRCUIT FLIP-CHIP - A light-emitting device, a light-emitting assembly and an integrated circuit (IC) flip-chip are provided. The light-emitting device includes the IC flip-chip, a plurality of light-emitting diode (LED) flip-chips and a substrate. The IC flip-chip includes a plurality of flip-chip pads. The LED flip-chips are spaced apart from the IC flip-chip. The substrate carries the IC flip-chip and the LED flip-chips. The LED flip-chips have a plurality of electrodes, and the flip-chip pads of the IC flip-chip and the electrodes of the LED flip-chips are disposed on the substrate by way of soldering. The LED flip-chips are electrically coupled to the IC flip-chip through the substrate. | 2022-02-17 |
20220052231 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a mounting board; and a semiconductor element disposed on the mounting board via metal bumps, wherein the semiconductor element includes a semiconductor stacked structure and first electrodes, the mounting board includes second electrodes, the metal bumps include a first layer in contact with the first electrodes of the semiconductor element and a second layer located on a side opposite to the first electrodes, an average crystal grain size of crystals included in the first layer is larger than an average crystal grain size of crystals included in the second layer, and the second layer is spaced apart from the first electrodes of the semiconductor element. | 2022-02-17 |
20220052232 | LIGHT-ALTERING PARTICLE ARRANGEMENTS FOR LIGHT-EMITTING DEVICES - Solid-state lighting devices including light-emitting diodes (LEDs), and more particularly LED devices with light-altering particle arrangements are disclosed. An LED device may include an LED chip with a light-altering material arranged to redirect light in a desired emission direction. The light-altering material may include light-altering particles with a median particle size that is determined based on a wavelength of light provided by the LED chip. Such light-altering particles may be arranged proximate sidewalls of the LED chip to redirect lateral emissions. LED devices may further include lumiphoric materials and other light-altering particles arranged proximate the lumiphoric materials with a median particle size that is determined based on a wavelength of light provided by the lumiphoric materials. By selectively arranging different light-altering particles in different areas of an LED device based on what wavelengths of light are most concentrated, the amount of overall light redirected may be increased, thereby improving efficiency. | 2022-02-17 |
20220052233 | PHOSPHOR SUBSTRATE, LIGHT EMITTING SUBSTRATE, AND LIGHTING DEVICE - A phosphor substrate having a plurality of light emitting elements mounted on one surface, and includes an insulating substrate, a first electrode group which is disposed on one surface of the insulating substrate and includes a plurality of electrodes bonded to the plurality of light emitting elements, and a phosphor layer which is disposed on one surface of the insulating substrate and includes a phosphor in which a light emission peak wavelength, in a case where light emitted by the light emitting element is used as excitation light, is in a visible light region, and the insulating substrate contains a bismaleimide resin and glass cloth. | 2022-02-17 |
20220052234 | -LED, -LED DEVICE, DISPLAY AND METHOD FOR THE SAME - The invention relates to various aspects of a μ-LED or a μ-LED array for augmented reality or lighting applications, in particular in the automotive field. The μ-LED is characterized by particularly small dimensions in the range of a few μm. | 2022-02-17 |
20220052235 | -LED, -LED DEVICE, DISPLAY AND METHOD FOR THE SAME - The invention relates to various aspects of a μ-LED or a μ-LED array for augmented reality or lighting applications, in particular in the automotive field. The μ-LED is characterized by particularly small dimensions in the range of a few μm. | 2022-02-17 |
20220052236 | SEMICONDUCTOR DEVICES WITH STRUCTURES FOR EMITTING OR DETECTING LIGHT - The invention relates to a semiconductor device, e.g. for the emission or absorption of light, preferably in the deep ultraviolet (DUV) range. The device, e.g. a resonant cavity light emitting diode (RCLED) or a laser diode, is formed from: a substrate layer ( | 2022-02-17 |
20220052237 | SURFACE SHIELDING ASSEMBLY FOR LED PACKAGE - A surface shielding assembly for LED packaging, including: an LED luminescent module ( | 2022-02-17 |
20220052238 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING LIGHT EMITTING DEVICE - A method of manufacturing a light emitting device that comprises a first cover member and a second cover member, includes: providing a package that comprises a substrate, a plurality of resin walls, and a recessed part defined by an upper surface of the substrate and lateral surfaces of the plurality of resin walls, wherein the substrate includes a grooved part surrounding a first region; mounting a light emitting element in the first region; forming the second cover member in a region between the lateral surfaces defining the recessed part to an upper edge of an outer perimeter of the grooved part; forming the first cover member, which comprises depositing an uncured resin on the second cover member, and allowing the uncured resin to flow into a groove of the grooved part; and forming a light transmitting member on the first cover member and the light emitting element. | 2022-02-17 |
20220052239 | MICRO DISPLAY PANEL, MANUFACTURING METHOD THEREOF, AND SPLICED DISPLAY PANEL - In the embodiments of the present invention, a glass substrate in a micro display panel includes a first surface and a second surface arranged opposite to one another, and a first terminal and a second terminal arranged opposite to one another. An insulation layer disposed on the first surface. A thin film transistor layer disposed on a surface of the insulation layer away from the glass substrate. A micro light-emitting diode layer disposed on a surface of the thin film transistor layer away from the insulation layer. A terminal of the insulation layer, the thin film transistor layer, and the micro light-emitting diode layer close to the first terminal is bent toward a side away from the second surface, and an interval is defined between a terminal of the insulation layer close to the first terminal and the first terminal. | 2022-02-17 |
20220052240 | DISPLAY DEVICE AND TILED DISPLAY DEVICE INCLUDING THE SAME - A display device includes: a substrate including a display area and a non-display area, the substrate having a first portion of a through hole penetrating in a thickness direction thereof in the display area, an etching stopper on one surface of the substrate, the etching stopper having a second portion of the through hole connected to one end of the first portion of the through hole, a display layer on one surface of the etching stopper, and the display layer including a connection line on the second portion of the through hole, an insulating layer on other surface opposite to the one surface of the substrate, the insulating layer having a third portion of the through hole connected to the other end of the first portion of the through hole, and a pad unit on an other surface of the insulating layer and connected to the connection line. | 2022-02-17 |
20220052241 | ELECTRONIC DEVICE AND MANUFACTURING METHOD OF ELECTRONIC DEVICE - An electronic device, including a substrate, an edge wire, a first protection layer, and a second protection layer, is provided. The substrate has a first surface, a second surface, and a side surface connecting the first surface and the second surface. A normal vector of the side surface is different from the first surface and the second surface. The edge wire is configured on the substrate, extending from the first surface to the second surface while passing through the side surface. The first protection layer is configured on the edge wire. The edge wire is sandwiched between the substrate and the first protection layer. The edge wire and the first protection layer form an undercut structure. The second protection layer is configured on the substrate and fills the undercut structure. A manufacturing method of an electronic device is also provided. | 2022-02-17 |
20220052242 | DISPLAY DEVICE - A display device includes a substrate having a hole, a plurality of pixels provided to the substrate, and a plurality of light emitting elements provided to the respective pixels. the light emitting elements include a first light emitting element having a predetermined chip size, and a second light emitting element having a chip size smaller than the chip size of the first light emitting element, the first light emitting element and the second light emitting element emit light in a common color, and the light emitting elements disposed around the hole include at least one second light emitting element. | 2022-02-17 |
20220052243 | DISPLAY APPARATUS COMPRISING LIGHT EMITTING DEVICES COUPLED TO A WIRING BOARD WITH CONDUCTIVE ADHESIVE - Discussed is a display apparatus including a wiring board having wiring electrodes; a conductive adhesive layer covering the wiring electrodes; a plurality of semiconductor light emitting devices coupled to the conductive adhesive layer and electrically connected to the wiring electrodes; and an insulating material disposed between the plurality of adhesive regions to fill between the plurality of semiconductor light emitting devices, wherein each electrode of the plurality of semiconductor light emitting devices includes a first conductive electrode, a first conductive semiconductor layer on the first conductive electrode, an active layer on the first conductive semiconductor layer, a second conductive semiconductor layer on the active layer, and a second conductive electrode on the second conductive semiconductor layer, and wherein the second conductive electrode is disposed on one surface of the second conductive semiconductor layer. | 2022-02-17 |
20220052244 | DISPLAY APPARATUS HAVING A BACKLIGHT UNIT - A display apparatus includes a display panel, a panel guide supporting a lower edge of the display panel, and a backlight unit supplying light to the display panel. The backlight unit includes at least one first substrate, a plurality of light emitting elements, and a plurality of light guide structures disposed on the at least first one substrate and arranged relative to one or more of the plurality of light emitting elements. | 2022-02-17 |
20220052245 | THERMOELECTRIC CONVERSION TECHNIQUE - The present disclosure provides a thermoelectric conversion material having a composition represented by a chemical formula of Li | 2022-02-17 |
20220052246 | IMPROVEMENTS RELATING TO THERMOELECTRIC MATERIALS - A thermoelectric material comprising carbon nanotubes and lignin. The carbon nanotubes are present as fibres and the lignin is present in pores and/or voids in the carbon nanotube fibres. The lignin may act as a dopant to increase the thermoelectric efficiency of the carbon nanotubes, multi-walled carbon nanotubes in particular. A method of forming a thermoelectric material involving impregnating fibres of carbon nanotubes with lignin, is also provided. A thermoelectric element, a fabric and a thermoelectric device comprising the thermoelectric material are also provided. The thermoelectric material may be particularly useful for the production of wearable thermoelectric devices. | 2022-02-17 |
20220052247 | THERMOELECTRIC CONVERSION ELEMENT - A thermoelectric conversion element that has a power generation layer containing an iron-aluminum based magnetic alloy material containing equal to or more than 70 weight percent of iron and aluminum in total. The power generation layer generates an electromotive force, due to an anomalous Nernst effect that develops in the magnetic alloy material in response to a temperature gradient applied thereto, in a direction intersecting both the magnetization direction of the magnetic alloy material and the direction of the applied temperature gradient. | 2022-02-17 |
20220052248 | HIGH CRITICAL TEMPERATURE METAL NITRIDE LAYER WITH OXIDE OR OXYNITRIDE SEED LAYER - A superconducting device includes a substrate, a metal oxide or metal oxynitride seed layer on the substrate, and a metal nitride superconductive layer disposed directly on the seed layer. The seed layer is an oxide or oxynitride of a first metal, and the superconductive layer is a nitride of a different second metal. | 2022-02-17 |
20220052249 | A-axis Josephson Junctions with Improved Smoothness - According to various implementations of the invention, high quality a-axis XBCO may be grown with low surface roughness. According to various implementations of the invention, low surface roughness may be obtained by: 1) adequate substrate preparation; 2) calibration of flux rates for constituent atoms; and/or 3) appropriate control of temperature during crystal growth. According to various implementations of the invention, a wafer comprises a smoothing layer of c-axis XBCO; a first conducting layer of a-axis XBCO formed on the smoothing layer; an insulating layer formed on the first conducting layer; and a second conducting layer of a-axis XBCO formed on the insulating layer, where, for a same surface roughness, a thickness of the smoothing layer and the first conducting layer combined is greater than a thickness of the first conducting layer without the smoothing layer. | 2022-02-17 |
20220052250 | Vibrator Device - A vibrator device includes a package including a base that is a semiconductor substrate and a lid that is a semiconductor substrate and has a housing section, a vibrator element and a passive element housed in the housing section and placed at the base, an oscillation circuit placed at the base and electrically coupled to the vibrator element, and a circuit that is placed at the base or the lid, is electrically coupled to the passive element, and operates based on an oscillation signal from the oscillation circuit. | 2022-02-17 |
20220052251 | VIBRATING PLATE-BONDED-BODY - A vibrating plate-bonded body includes a supporting substrate composed of silicon, a vibrating plate composed of a highly rigid ceramics and having a thickness of 100 μm or smaller, and a bonding layer between the supporting substrate and vibrating plate, contacting a bonding surface of the vibrating plate and composed of α-Si. The arithmetic average roughness Ra of the bonding surface of the vibrating plate is 0.01 nm or more and 10.0 nm or less, and the pit density of the bonding surface of the vibrating plate is 10 counts or more per 100 μm | 2022-02-17 |