07th week of 2016 patent applcation highlights part 46 |
Patent application number | Title | Published |
20160049365 | INTERCONNECT STRUCTURE - An interconnect structure and fabrication method are provided. A substrate can include a semiconductor device disposed therein. A porous dielectric layer can be formed on the substrate. A surface treatment can be performed to the porous dielectric layer to form an isolation layer on the porous dielectric layer to prevent moisture absorption of the porous dielectric layer. An interconnect can be formed at least through the isolation layer and the porous dielectric layer to provide electrical connection to the semiconductor device disposed in the substrate. | 2016-02-18 |
20160049366 | INTEGRATED CIRCUITS WITH ELECTRONIC FUSE STRUCTURES - Integrated circuits including electronic fuse structures are disclosed. In some examples, the electronic fuse structure includes a fuse part and first and second pre-heating lines positioned generally parallel to and co-planar with the fuse part, and electrically connected with the fuse part. The electronic fuse structure also includes a cathode physically and electrically connected to the first pre-heating line and an anode physically and electrically connected to the second pre-heating line. | 2016-02-18 |
20160049367 | INTEGRATED CIRCUIT STRUCTURE INCLUDING FUSE AND METHOD THEREOF - An integrated circuit structure includes a fuse. The integrated circuit structure further includes a first dielectric layer and a patterned dummy. The fuse is disposed on a substrate. The first dielectric layer covers the fuse. The patterned dummy is disposed on the first dielectric layer and the patterned dummy has a first recess exposing a part of the first dielectric layer directly above the fuse. A method of forming the integrated circuit structure including a fuse is also provided. | 2016-02-18 |
20160049368 | SEMICONDUCTOR DEVICE - To reinforce power supply wirings without sacrificing the interconnectivity of semiconductor devices. When three wirings are formed in parallel in the same wiring layer and the center wiring among them is shorter than the outer wirings, a projecting portion integrated into the outer wiring is formed utilizing a free space remaining on the extension of the center wiring. For example, when the outer wirings are used as power supply wirings, the power supply wirings can be reinforced by adding the projecting portion. At this time, because the projecting portion is arranged in the free space, the interconnectivity is not sacrificed. | 2016-02-18 |
20160049369 | SYSTEM-ON-CHIP, ELECTRONIC APPARATUS INCLUDING THE SAME, AND METHOD OF DESIGNING THE SAME - A system-on-chip includes a substrate, a plurality of unit cells on the substrate, a first power mesh, and a second power mesh. The first power mesh includes a power rail that is connected to power terminals of the plurality of unit cells and is provided in a first metallization layer. The first power mesh also includes a power strap in a second metallization layer. The second power mesh is provided in a third metallization layer and a fourth metallization layer. | 2016-02-18 |
20160049370 | METHODS OF FORMING MIS CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES BY SELECTIVE DEPOSITION OF INSULATING MATERIAL AND THE RESULTING DEVICES - One method disclosed herein includes, among other things, forming at least one layer of insulating material above a semiconductor layer, performing at least one contact opening etching process to form a contact opening in the at least one layer of insulating material that exposes a portion of the semiconductor layer, selectively depositing a metal-oxide insulating material through the contact opening on the exposed surface of the semiconductor layer, and forming a conductive contact in the contact opening that contacts the metal-oxide insulating material. | 2016-02-18 |
20160049371 | INTERCONNECT STRUCTURE COMPRISING FINE PITCH BACKSIDE METAL REDISTRIBUTION LINES COMBINED WITH VIAS - A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a “plate through resist” type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow. | 2016-02-18 |
20160049372 | Ceramic substrate, package substrate, semiconductor chip package component and manufacturing method thereof - A method for manufacturing a ceramic substrate is characterized in using a preformed trench, a patterned protective layer and a sand blasting process to manufacture a cavity in a ceramic substrate and control the cavity size and shape of the ceramic substrate. The ceramic substrate is collocated with a base substrate to form a package substrate for packaging a semiconductor chip. The manufacturing method set forth above can lower the manufacturing cost and raise the accuracy of the size and shape of the cavity of the ceramic substrate. The abovementioned method can reduce the fabrication cost and increase the precision of the shape and size of a ceramic substrate. | 2016-02-18 |
20160049373 | VIA PRE-FILL ON BACK-END-OF-THE-LINE INTERCONNECT LAYER - In some embodiments, the present disclosure relates to a conductive interconnect layer. The conductive interconnect layer has a dielectric layer disposed over a substrate. An opening with an upper portion above a horizontal plane and a lower portion below the horizontal plane extends downwardly through the dielectric layer. A first conductive layer fills the lower portion of the opening. An upper barrier layer is disposed over the first conductive layer covering bottom and sidewall surfaces of the upper portion of the opening. A second conductive layer is disposed over the upper barrier layer filling the upper portion of the opening. | 2016-02-18 |
20160049374 | RADIO FREQUENCY MODULE INCLUDING SEGMENTED CONDUCTIVE GROUND PLANE - A radio frequency (RF) module comprises an electrical reference, or ground, plane to which one or more RF devices disposed on the module are electrically coupled, and may be disposed beneath the RF devices. The reference plane may be segmented as to form one or more segments of the reference plane that are at least partially electrically isolated from surrounding segments or devices. A module may have a plurality of devices disposed thereon, wherein separate, at least partially isolated reference planes, correspond to different devices of the module. The reference plane may be etched or cut to achieve such segmentation. | 2016-02-18 |
20160049375 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate which includes a first face. The device also includes a buffer layer, a semiconductor layer, source and drain electrodes, and a gate electrode. A trench is formed on the semiconductor layer so that the trench surrounds the source electrode, the drain electrode, and the gate electrode in a plan view, the trench passes through the semiconductor layer and the buffer layer, and a bottom of the trench reaches at least an inside of the substrate. A distance from the first face of the substrate to the bottom of the trench is 100 nm or more in a thickness direction of the substrate. | 2016-02-18 |
20160049376 | METHOD FOR FABRICATING PACKAGE STRUCTURE - A method for fabricating a package structure is provided, which includes the steps of: providing an encapsulant encapsulating at least an electronic element; forming a shaping layer on a surface of the encapsulant, wherein the shaping layer has at least an opening exposing a portion of the surface of the encapsulant; forming at least a through hole corresponding in position to the opening and penetrating the encapsulant; and forming a conductor in the through hole. The shaping layer facilitates to prevent deformation of the through hole. | 2016-02-18 |
20160049377 | SEMICONDUCTOR DEVICES AND PACKAGE SUBSTRATES HAVING PILLARS AND SEMICONDUCTOR PACKAGES AND PACKAGE STACK STRUCTURES HAVING THE SAME - A semiconductor device, a semiconductor package, and a package stack structure include a semiconductor substrate, a first bonding pad disposed on a first surface of the semiconductor substrate, and a first pillar disposed on the first bonding pad. An upper surface of the first pillar has a concave shape. Side surfaces of the first pillar are substantially planar. | 2016-02-18 |
20160049378 | INTEGRATED DEVICE COMPRISING A HEAT-DISSIPATION LAYER PROVIDING AN ELECTRICAL PATH FOR A GROUND SIGNAL - Provided herein is an integrated device that includes a substrate, a die, a heat-dissipation layer located between the substrate and the die, and a first interconnect configured to couple the die to the heat-dissipation layer. The heat-dissipation layer may be configured to provide an electrical path for a ground signal. The first interconnect may be further configured to conduct heat from the die to the heat-dissipation layer. The integrated device may also include a second interconnect configured to couple the die to the substrate. The second interconnect may be further configured to conduct a power signal between the die and the substrate. The integrated device may also include a dielectric layer located between the heat-dissipation layer and the substrate, and a solder-resist layer located between the die and the heat-dissipation layer. | 2016-02-18 |
20160049379 | PRINTED CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE USING THE SAME - Embodiments of the inventive aspect include a printed circuit board and a semiconductor package using the same. The semiconductor package includes a substrate having one or more connection pads, semiconductor chips mounted on the substrate, an underfill layer filling a region between the semiconductor chips and the substrate, and solder bumps electrically connecting the connection pads and the semiconductor chips in the underfill layer. The substrate includes void preventing patterns protruding on a top surface of the substrate under the underfill layer. | 2016-02-18 |
20160049380 | WIRE BONDS FOR ELECTRONICS - A circuit element includes a semiconductor chip and a wire for connecting between the semiconductor chip and an additional circuit element. A plurality of wire bond connections electrically connect the wire and the semiconductor chip. The plurality of wire bond connections can be disposed on a surface of the semiconductor chip and on a surface of the wire. | 2016-02-18 |
20160049381 | LASER ASSISTED BONDING FOR SEMICONDUCTOR DIE INTERCONNECTIONS - Laser assisted bonding for semiconductor die interconnections is disclosed and may, for example, include forming flux on a circuit pattern on a circuit board, placing a semiconductor die on the circuit board where a bump on the semiconductor die contacts the flux, and reflowing the bump by directing a laser beam toward the semiconductor die. The laser beam may volatize the flux and make an electrical connection between the bump and the circuit pattern. A jig plate may be placed on the semiconductor die when the laser beam is directed toward the semiconductor die. Warpage may be reduced during heating or cooling of the semiconductor die by applying pressure to the jig plate. Jig bars may extend outward from the jig plate and may be in contact with the circuit board during the application of pressure to the jig plate. The jig plate may comprise one or more of: silicon, silicon carbide, and glass. | 2016-02-18 |
20160049382 | METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE AND WIRE BONDING APPARATUS FOR PERFORMING THE SAME - In a method of manufacturing a semiconductor package, a first semiconductor chip is adhered to a package substrate. An end portion of a wire is bonded to a first bonding pad of the first semiconductor chip by using a capillary. An operating voltage of the first semiconductor chip is applied to the first bonding pad through the wire to detect a leakage current. A second end portion of the wire is bonded to the first connection pad by using the capillary, according to a result of the detection. | 2016-02-18 |
20160049383 | DEVICE AND METHOD FOR AN INTEGRATED ULTRA-HIGH-DENSITY DEVICE - A device and method for an integrated device includes a first redistribution layer comprising one or more first conductors, one or more first dies mounted to a first surface of the first redistribution layer and electrically coupled to the first conductors, one or more first posts having first ends attached to the first dies and second ends opposite the first ends, one or more second posts having third ends attached to the first surface of the first redistribution layer and fourth ends opposite the third ends, and a second redistribution layer comprising one or more second conductors, the second redistribution layer being attached to the second ends of the first posts and to the fourth ends of the second posts. In some embodiments, the integrated device further includes a heat spreader mounted to a second surface of the first redistribution layer. The second surface is opposite the first surface. | 2016-02-18 |
20160049384 | BUFFER LAYER(S) ON A STACKED STRUCTURE HAVING A VIA - A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer. | 2016-02-18 |
20160049385 | PACKAGES AND METHODS OF MANUFACTURE THEREOF - Packages and methods of manufacture thereof are described. In an embodiment, a package may include a first chip package and a die structure disposed over the first chip package. In an embodiment, the first chip package may include: a molding compound; a first die within the molding compound; a first via structure and a second via structure within the molding compound at opposite lateral portions of the first die, wherein the first and second via structures extend between an active surface of the first die and a first surface of the molding compound; and a second die within the molding compound, the second die disposed at the active surface of the first die and between the first via structure and the second via structure. | 2016-02-18 |
20160049386 | SELF-ORGANIZING NETWORK WITH CHIP PACKAGE HAVING MULTIPLE INTERCONNECTION CONFIGURATIONS - In general, embodiments of the present invention provide a chip package with multiple TSV configurations. Specifically, the chip package typically includes a backend layer (e.g., metal interconnect layer); a substrate coupled to the backend layer; a set (at least one) of backend side interconnects extending (e.g., angularly) from a side surface of the backend layer to a bottom surface of the backend layer; a set of optional vertical TSVs extending from a top surface of the backend layer through the substrate; and a network organizer positioned in the substrate organizer for handling communications made using the set of backend side interconnects and the set of vertical TSVs. A set of connections (e.g., controlled collapse chip connections (C4s) can be positioned adjacent to any of the vias to provide connectively to other hardware elements such as additional chip packages, buses, etc. Among other things, the use of backend side interconnects allows maximum surface area of the chip package to be utilized and provides increased reliability. These advantages are especially realized when used in conjunction with vertical TSVs. | 2016-02-18 |
20160049387 | HIGH VOLTAGE SOLID-STATE TRANSDUCERS AND SOLID-STATE TRANSDUCER ARRAYS HAVING ELECTRICAL CROSS-CONNECTIONS AND ASSOCIATED SYSTEMS AND METHODS - Solid-state transducer (“SST”) dies and SST arrays having electrical cross-connections are disclosed herein. An array of SST dies in accordance with a particular embodiment can include a first terminal, a second terminal and a plurality of SST dies coupled between the first and second terminals with at least a pair of the SST dies being coupled in parallel. The plurality of SST dies can individually include a plurality of junctions coupled in series with an interconnection between each individual junction. Additionally, the individual SST dies can have a cross-connection contact coupled to the interconnection. In one embodiment, the array can further include a cross-connection between the cross-connection contacts on the pair of the SST dies. | 2016-02-18 |
20160049388 | LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A light-emitting device may comprise a substrate, an electric wire fixed to the substrate, and a plurality of light-emitting diodes mounted to the electric wire. According to one embodiment, each of the plurality of light-emitting diodes is an LED chip, and the light-emitting diodes on the substrate are sealed individually or collectively by one or more sealing members. According to another embodiment, the substrate has a plurality of through holes, wherein a plurality of portions of the electric wire provided on a rear surface side of the substrate communicates with a front surface side of the substrate at the plurality of through holes of the substrate, and wherein the plurality of light-emitting diodes is respectively mounted to the respective portions of the electric wire that communicate with the front surface side of the substrate. Other embodiments relate to methods of manufacturing a light-emitting device. | 2016-02-18 |
20160049389 | 3DIC Package and Methods of Forming the Same - A package includes a first molding material, a first device die molded in the molding material, a Through Via (TV) penetrating through the first molding material, and a redistribution line over the first molding material. The redistribution line is electrically connected to the TV. A second device die is over and bonded to the first device die through flip-chip bonding. A second molding material molds the second device die therein. | 2016-02-18 |
20160049390 | Multiple bond via arrays of different wire heights on a same substrate - An apparatus relating generally to a substrate is disclosed. In such an apparatus, a first bond via array has first wires extending from a surface of the substrate. A second bond via array has second wires extending from the surface of the substrate. The first bond via array is disposed at least partially within the second bond via array. The first wires of the first bond via array are of a first height. The second wires of the second bond via array are of a second height greater than the first height for coupling of at least one die to the first bond via array at least partially disposed within the second bond via array. | 2016-02-18 |
20160049391 | VERTICAL NANOWIRE TRANSISTOR FOR INPUT/OUTPUT STRUCTURE - An electrostatic discharge (ESD) protection circuit includes an input terminal, a transistor, and an output terminal. The input terminal is configured to receive an input signal. The transistor includes a first source/drain region, a second source/drain region, and a drift region that has a resistance in series between the first and second source/drain regions and that is configured to attenuate an ESD voltage in the input signal. The output terminal is connected to the second source/drain region. | 2016-02-18 |
20160049392 | PLANAR SRFET USING NO ADDITIONAL MASKS AND LAYOUT METHOD - A semiconductor power device is supported on a semiconductor substrate of a first conductivity type with a bottom layer functioning as a bottom electrode and an epitaxial layer overlying the bottom layer with a same conductivity type as the bottom layer. The semiconductor power device includes a plurality of FET cells and each cell further includes a body region of a second conductivity type extending from a top surface into the epitaxial layer. The body region encompasses a heavy body dopant region of second conductivity type. An insulated gate is disposed on the top surface of the epitaxial layer, overlapping a first portion of the body region. A barrier control layer is disposed on the top surface of the epitaxial layer next to the body region away from the insulated gate. A conductive layer overlies the top surface of the epitaxial layer covering a second portion of the body region and the heavy body dopant region extending over the barrier control layer forming a Schottky junction diode. | 2016-02-18 |
20160049393 | CAPACITOR STRUCTURE IN AN INTEGRATED CIRCUIT - In an example, a capacitor in an integrated circuit (IC), includes: a first finger capacitor formed in at least one layer of the IC having a first bus and a second bus; a second finger capacitor formed in the at least one layer of the IC having a first bus and a second bus, where a longitudinal edge of the second bus of the second finger capacitor is adjacent a longitudinal edge of the first bus of the first finger capacitor and separated by a dielectric gap; and a first metal segment formed on a first layer above the at least one layer, the first metal segment being electrically coupled to the first bus of the first finger capacitor and increasing a width and a height of the first bus of the first finger capacitor. | 2016-02-18 |
20160049394 | SEMICONDUCTOR DEVICE - A semiconductor device includes a transistor formed on a substrate and including a gate electrode and a source/drain, an interlayer insulating layer covering the transistor, a first contact hole formed in the interlayer insulating layer to expose a part of the transistor, a first barrier metal conformally formed on an inner surface of the first contact hole, a first conductive layer formed on the first barrier metal to fill the first contact hole, a second contact hole formed on the first conductive layer in the interlayer insulating layer and having a larger width than the first contact hole, a second barrier metal conformally formed on an inner surface of the second contact hole, and a second conductive layer formed on the second barrier metal to fill the second contact hole, wherein the second barrier metal is formed between the first conductive layer and the second conductive layer. | 2016-02-18 |
20160049395 | SEMICONDUCTOR DEVICE - An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured. | 2016-02-18 |
20160049396 | Systems and Methods for Fabricating Semiconductor Devices at Different Levels - Systems and methods are provided for fabricating semiconductor device structures on a substrate. For example, a substrate including a first region and a second region is provided. One or more first semiconductor device structures are formed on the first region. One or more semiconductor fins are formed on the second region. One or more second semiconductor device structures are formed on the semiconductor fins. A top surface of the semiconductor fins is higher than a top surface of the first semiconductor device structures. | 2016-02-18 |
20160049397 | TRANSISTOR, INTEGRATED CIRCUIT AND METHOD OF FABRICATING THE SAME - A transistor, an integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the transistor includes a source electrode, at least one semiconductor channel, a gate electrode, a drain electrode, and a drain pad. The source electrode is disposed in a substrate. The semiconductor channel extends substantially perpendicular to the source electrode. The gate electrode surrounds the semiconductor channel. The drain electrode is disposed on top of the semiconductor channel. The drain pad is disposed on the drain electrode, wherein the drain pad comprises multiple conductive layers. | 2016-02-18 |
20160049398 | SEMICONDUCTOR DEVICE - A semiconductor device including a substrate including an NMOS region and a PMOS region; first and second gate dielectrics on the NMOS and PMOS regions of the substrate and including a high-k dielectric material; a first gate structure on the first gate dielectric and including a sequentially stacked first n-type metal layer pattern and first electrode layer pattern; a second gate structure on the second gate dielectric and including a sequentially stacked p-type metal layer pattern, second n-type metal layer pattern, and second electrode layer pattern; first and second spacers on sidewalls of the first and second gate structures; a first offset pattern between the first gate structure and the first spacer; and a second offset pattern between the second gate structure and the second spacer, the second offset pattern being on the sidewalls of the second gate structure excluding sidewalls of the p-type metal layer pattern. | 2016-02-18 |
20160049399 | GATE STRUCTURES FOR SEMICONDUCTOR DEVICES WITH A CONDUCTIVE ETCH STOP LAYER - One illustrative gate structure of a transistor device disclosed herein includes a high-k gate insulation layer and a work function metal layer positioned on the high-k gate insulation layer. The device further includes a first bulk metal layer positioned on the work function metal layer. The device further includes a second bulk metal layer. The first and second bulk metal layers have upper surfaces that are at substantially the same height level, and the first and second bulk metal layers are made of substantially the same material. The device further includes a conductive etch stop layer between the first and second bulk metal layers. | 2016-02-18 |
20160049400 | THRESHOLD VOLTAGE CONTROL FOR MIXED-TYPE NON-PLANAR SEMICONDUCTOR DEVICES - A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal. | 2016-02-18 |
20160049401 | HYBRID CONTACTS FOR COMMONLY FABRICATED SEMICONDUCTOR DEVICES USING SAME METAL - A non-planar semiconductor structure, for example, a dual FinFET structure, includes a n-type semiconductor device and a p-type semiconductor device. Metal-insulator-semiconductor (MIS) contacts provide electrical connection to the n-type device, and metal-semiconductor (MS) contacts provide electrical connection to the p-type device. The metal of both MIS and MS contacts is a same n-type work function metal. In one example, the semiconductor of the MIS contact includes epitaxial silicon germanium with a relatively low percentage of germanium, the insulator of the MIS contact includes titanium dioxide, the semiconductor for the MS contact includes silicon germanium with a relatively high percentage of germanium or pure germanium, and the metal for both contacts includes a n-type work function metal. | 2016-02-18 |
20160049402 | SEMICONDUCTOR DEVICE HAVING FINS WITH IN-SITU DOPED, PUNCH-THROUGH STOPPER LAYER AND RELATED METHODS - A method for making a semiconductor device may include forming first and second semiconductor regions laterally adjacent one another and each comprising a first semiconductor material. The method may further include forming an in-situ doped, punch-through stopper layer above the second semiconductor region comprising the first semiconductor material and a first dopant, and forming a semiconductor buffer layer above the punch-through stopper layer, where the punch-through stopper layer includes the first semiconductor material. The method may also include forming a third semiconductor region above the semiconductor buffer layer, where the third semiconductor region includes a second semiconductor material different than the first semiconductor material. In addition, at least one first fin may be formed from the first semiconductor region, and at least one second fin may be formed from the second semiconductor region, the punch-through stopper layer, the semiconductor buffer layer, and the third semiconductor region. | 2016-02-18 |
20160049403 | CMOS COMPATIBLE MEMORY CELLS - A memory cell and a process for production thereof, the memory cell having a CMOS substrate having two adjacent wells of opposite conductivity types, having trench isolation between the wells, wherein one of the wells is connected to a ground voltage level and the other one to a constant voltage level; a shallow lightly doped n layer in a first one of the wells; a shallow lightly doped p layer in a second one of the wells; at least a first and second deep heavily doped p regions in the first well; at least a first and second deep heavily doped n regions in the second well; and a conductor to connect the first and second deep p regions, the shallow n region, the first and second deep n regions and the shallow p region to the same input voltage level relative to the ground voltage level. | 2016-02-18 |
20160049404 | Array Of Gated Devices And Methods Of Forming An Array Of Gated Devices - An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed. | 2016-02-18 |
20160049405 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A conventional DRAM needs to be refreshed at an interval of several tens of milliseconds to hold data, which results in large power consumption. In addition, a transistor therein is frequently turned on and off; thus, deterioration of the transistor is also a problem. These problems become significant as the memory capacity increases and transistor miniaturization advances. A transistor is provided which includes a wide-gap semiconductor and has a trench structure including a trench for a gate electrode and a trench for element isolation. Even when the distance between a source electrode and a drain electrode is decreased, the occurrence of a short-channel effect can be suppressed by setting the depth of the trench for the gate electrode as appropriate. | 2016-02-18 |
20160049406 | SEMICONDUCTOR DEVICES AND SYSTEMS INCLUDING MEMORY CELLS AND RELATED METHODS OF FABRICATION - A memory cell is disclosed. The memory cell includes a transistor and a capacitor. The transistor includes a source region, a drain region, and a channel region including an indium gallium zinc oxide (IGZO, which is also known in the art as GIZO) material. The capacitor is in operative communication with the transistor, and the capacitor includes a top capacitor electrode and a bottom capacitor electrode. Also disclosed is a semiconductor device including a dynamic random access memory (DRAM) array of DRAM cells. Also disclosed is a system including a memory array of DRAM cells and methods for forming the disclosed memory cells and arrays of cells. | 2016-02-18 |
20160049407 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a device isolation pattern on a substrate to define active patterns, a gate electrode crossing the active patterns, first and second impurity regions in each of the active patterns and on both sides of the gate electrode, a bit line crossing the gate electrode, a first contact electrically connecting the first impurity region to the bit line, and a second contact electrically connected to the second impurity region. The second contact includes a vertically-extended portion covering an upper side surface of the second impurity region. | 2016-02-18 |
20160049408 | SEMICONDUCTOR DEVICES HAVING BIT LINE STRUCTURES DISPOSED IN TRENCHES - Semiconductor devices are provided. The semiconductor device includes a bit line contact plug and a storage node contact plug electrically connected to an active region of a substrate. A bit line structure is disposed on the bit line contact plug to extend in a first direction. The bit line structure is disposed in a trench pattern that intrudes into a side of the storage node contact plug. Related methods and systems are also provided. | 2016-02-18 |
20160049409 | SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a plurality of first conductive structures formed over a substrate, second conductive structures each formed between neighboring first conductive structures of the first conductive structures, air gaps each formed between the second conductive structures and the neighboring first conductive structures thereof, third conductive structures each capping a portion of the air gaps, and capping structures each capping the other portion of the air gaps. | 2016-02-18 |
20160049410 | SRAM WELL-TIE WITH AN UNINTERRUPTED GRATED FIRST POLY AND FIRST CONTACT PATTERNS IN A BIT CELL ARRAY - An integrated circuit containing an SRAM may be formed using one or more periodic photolithographic patterns for elements of the integrated circuit such as gates and contacts, which have alternating line and space configurations in SRAM cells. Strap rows of the SRAM containing well ties and/or substrate taps which have SRAM cells on two opposite sides are configured so that the alternating line and space configurations are continuous across the regions containing the well ties and substrate taps. | 2016-02-18 |
20160049411 | METHOD FOR PROCESSING A CARRIER, A CARRIER, AND A SPLIT GATE FIELD EFFECT TRANSISTOR STRUCTURE - According to various embodiments, a method for processing a carrier may include: doping a carrier with fluorine such that a first surface region of the carrier is fluorine doped and a second surface region of the carrier is at least one of free from the fluorine doping or less fluorine doped than the first surface region; and oxidizing the carrier to grow a first gate oxide layer from the first surface region of the carrier with a first thickness and simultaneously from the second surface region of the carrier with a second thickness different from the first thickness. | 2016-02-18 |
20160049412 | Apparatus for High Speed ROM Cells - An apparatus comprises a plurality of memory cells in rows and columns, a first word line electrically coupled to a first group of memory cells through a first word line strap structure comprising a first gate contact, a first-level via, a first metal line and a second-level via and a second word line electrically coupled to a second group of memory cells through a second word line strap structure, wherein the second word line strap structure and the first word line strap structure are separated by at least two memory cells. | 2016-02-18 |
20160049413 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device is disclosed. The semiconductor device includes: a substrate; a floating gate on the substrate; a first silicon oxide layer between the floating gate and the substrate; a first tunnel oxide layer and a second tunnel oxide layer adjacent to two sides of the first silicon oxide layer; and a control gate on the floating gate. Preferably, the thickness of the first tunnel oxide layer and the second tunnel oxide layer is less than the thickness of the first silicon oxide layer. | 2016-02-18 |
20160049414 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to an embodiment, a nonvolatile semiconductor memory device comprises: a semiconductor layer; a first gate insulating film; a plurality of floating gate electrodes; a second gate insulating film; a plurality of control gate electrodes; and an upper insulating film. The semiconductor layer is provided on a substrate and extends in a first direction. The floating gate electrode is formed on the semiconductor layer via the first gate insulating film. The control gate electrode faces the upper surface of the floating gate electrode via the second gate insulating film. Moreover, the control gate electrode extends in a second direction intersecting the first direction. The upper insulating film is formed on an upper portion of the plurality of control gate electrodes. Moreover, a height of an upper surface of the upper insulating film changes along the second direction. | 2016-02-18 |
20160049415 | SEMICONDUCTOR DEVICE - In a memory cell array region and a source contact region defined in a surface of a semiconductor substrate, a memory cell transistor including a floating gate electrode and a control gate electrode is formed. In a gate contact region, a dummy floating gate electrode is arranged to partially be superimposed on a dummy element formation region in a two-dimensional view. In a first interlayer insulating film and a second interlayer insulating film covering the memory cell transistor, a contact plug is formed to penetrate the first interlayer insulating film and a via is formed to penetrate a second interlayer insulating film. | 2016-02-18 |
20160049416 | INTEGRATION OF SEMICONDUCTOR MEMORY CELLS AND LOGIC CELLS - A polysilicon gate electrode is formed in a memory cell area, and a dummy polysilicon gate electrode is formed in a logic cell area of a silicon substrate. The dummy polysilicon gate electrode is removed and a gate insulation film and a metal gate electrode having a recess portion are formed. Further, contact holes are formed on source regions and drain regions of the memory cell area and the logic cell area. The recess portion of the metal gate electrode and the contact holes are filled with a wiring metal, substantially simultaneously, and thereafter the wiring metal is planarized by polishing. | 2016-02-18 |
20160049417 | FLOATING GATE MEMORY CELLS IN VERTICAL MEMORY - Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion. | 2016-02-18 |
20160049418 | MEMORY CELL HAVING ISOLATED CHARGE SITES AND METHOD OF FABRICATING SAME - Memory cells having isolated charge sites and methods of fabricating memory cells having isolated charge sites are described. In an example, a nonvolatile charge trap memory device includes a substrate having a channel region, a source region and a drain region. A gate stack is disposed above the substrate, over the channel region. The gate stack includes a tunnel dielectric layer disposed above the channel region, a first charge-trapping region and a second charge-trapping region. The regions are disposed above the tunnel dielectric layer and separated by a distance. The gate stack also includes an isolating dielectric layer disposed above the tunnel dielectric layer and between the first charge-trapping region and the second charge-trapping region. A gate dielectric layer is disposed above the first charge-trapping region, the second charge-trapping region and the isolating dielectric layer. A gate electrode is disposed above the gate dielectric layer. | 2016-02-18 |
20160049419 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including gate structures provided on a substrate, a separation insulating layer interposed between the gate structures, and a plurality of cell pillars connected to the substrate through each gate structure. Each gate structure may include horizontal electrodes vertically stacked on the substrate, and an interval between adjacent ones of the cell pillars is non-uniform. | 2016-02-18 |
20160049420 | COMPOSITE SPACER FOR SILICON NANOCRYSTAL MEMORY STORAGE - Some embodiments relate to a memory device comprising a charge-trapping layer disposed between a control gate and a select gate. A capping structure is disposed over an upper surface of the control gate, and a composite spacer is disposed on a source-facing sidewall surface of the control gate. The capping structure and the composite spacer prevent damage to the control gate during one more etch processes used for contact formation to the memory device. To further limit or prevent the select gate sidewall etching, some embodiments provide for an additional liner oxide layer disposed along the drain-facing sidewall surface of the select gate. The liner oxide layer is configured as an etch stop layer to prevent etching of the select gate during the one or more etch processes. As a result, the one or more etch processes leave the control gate and select gate substantially intact. | 2016-02-18 |
20160049421 | THREE DIMENSIONAL NAND DEVICE HAVING DUMMY MEMORY HOLES AND METHOD OF MAKING THEREOF - A monolithic three dimensional NAND string includes a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate, a memory opening extending substantially perpendicular to the major surface of the substrate and filled with a memory opening material including a memory film, and a dummy opening extending substantially perpendicular to the major surface of the substrate and filled with a dummy channel material which is different from the memory opening material. The dummy channel material has a higher Young's modulus than the memory opening material to offset warpage of the substrate due to the one of compressive and tensile stress imposed by the plurality of control gate electrodes on the substrate. | 2016-02-18 |
20160049422 | SEMICONDUCTOR DEVICE - A semiconductor device may include an insulating layer provided in one body on a substrate, a first gate electrode and a second gate electrode disposed on the insulating layer, the first and second gate electrodes extending in a first direction parallel to a top surface of the substrate, a first channel structure penetrating the first gate electrode and the insulating layer so as to be connected to the substrate, a second channel structure penetrating the second gate electrode and the insulating layer so as to be connected to the substrate, and a contact penetrating the insulating layer between the first gate electrode and the second gate electrode. The contact may be connected to a common source region formed in the substrate, and the common source region may have a first conductivity type. Further, the first gate electrode and the second gate electrode may be spaced apart from each other in a second direction at the same level from the substrate, wherein the second direction intersects the first direction and is parallel to the top surface of the substrate. | 2016-02-18 |
20160049423 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A three-dimensional semiconductor device may include a substrate including a cell array region, a word line contact region, and a peripheral circuit region, gate electrodes stacked on the substrate to extend from the cell array region to the word line contact region, a channel hole penetrating the gate electrodes on the cell array region and exposing an active region of the substrate, a dummy hole penetrating the gate electrodes on the word line contact region and exposing a device isolation layer provided on the substrate, and a semiconductor pattern provided in the channel hole but not in the dummy hole. | 2016-02-18 |
20160049424 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY DEVICE - An array substrate, a manufacturing method of the array substrate and a display device including the array substrate are disclosed. The array substrate includes a substrate ( | 2016-02-18 |
20160049425 | ARRAY SUBSTRATE AND FABRICATION METHOD THEREOF, AND DISPLAY DEVICE - An array substrate and a fabrication method thereof, and a display device are provided. The array substrate comprises a gate line and a data line intersecting with each other. The data line and the gate line are formed in a same layer on a substrate, the data line is disconnected in a region of the gate line. A connection pattern is formed in the region of the gate line, the connection pattern is insulated from the gate line, and ends of the data line located on both sides of the gate line are electrically connected by the connection pattern. | 2016-02-18 |
20160049426 | ORGANIC LIGHTING EMITTING DISPLAY DEVICE INCLUDING LIGHT ABSORBING LAYER AND METHOD FOR MANUFACTURING SAME - Provided is a display device including: a plurality of pixels where a plurality of gate lines cross a plurality of data lines, respectively, each of the pixels including a thin film transistor (TFT) region and a display region; a TFT formed in the TFT region; light emitting elements formed in the display region for displaying images based on signals from the TFT; a metallic layer disposed in the TFT region for electrical connection of the TFT; and a light absorbing layer disposed on the metallic layer and configured to absorb at least part of light propagating toward the metallic layer. | 2016-02-18 |
20160049427 | INTEGRATED CIRCUITS WITH SELF ALIGNED CONTACT STRUCTURES FOR IMPROVED WINDOWS AND FABRICATION METHODS - Devices and methods for forming semiconductor devices with self aligned contacts for improved process windows are provided. One method includes, for instance: obtaining a wafer with at least two gates, forming partial spacers adjacent to the at least two gates, and forming at least one contact on the wafer. One intermediate semiconductor device includes, for instance: a wafer with an isolation region, at least two gates disposed on the isolation region, at least one source region disposed on the isolation region, at least one drain region disposed on the isolation region, and at least one contact positioned between the at least two gates, wherein a first portion of the at least one contact engages the at least one source region or the at least one drain region and a second portion of the at least one contact extends above a top surface of the at least two gates. | 2016-02-18 |
20160049428 | SEMICONDUCTOR DEVICE - A semiconductor device having a high aperture ratio and including a capacitor capable of increasing the charge capacity is provided. A semiconductor device includes a transistor over a substrate, a first light-transmitting conductive film over the substrate, an oxide insulating film covering the transistor and having an opening over the first light-transmitting conductive film, a nitride insulating film over the oxide insulating film and in contact with the first light-transmitting conductive film in the opening, a second light-transmitting conductive film connected to the transistor and having a depressed portion in the opening, and an organic resin film with which the depressed portion of the second light-transmitting conductive film is filled. | 2016-02-18 |
20160049429 | GLOBAL SHUTTER IMAGE SENSOR, AND IMAGE PROCESSING SYSTEM HAVING THE SAME - A global shutter image sensor according to an exemplary embodiment of the present inventive concepts includes a semiconductor substrate including a first surface and a second surface, a photo-electric conversion region formed in the semiconductor substrate, a storage diode formed in a vicinity of the photo-electric conversion region in the semiconductor substrate, a drain region formed above the photo-electric conversion region in the semiconductor substrate, a floating diffusion region formed above the storage diode in the semiconductor substrate, an overflow gate transferring first charges from the photo-electric conversion region to the drain region, a storage gate transferring second charges from the photo-electric conversion region to the storage diode, and a transfer gate transferring the second charges from the storage diode to the floating diffusion region. The overflow gate, the photo-electric conversion region, the storage gate, the storage diode, the transfer gate, and the floating diffusion region are formed in a row. | 2016-02-18 |
20160049430 | IMAGING ELEMENT AND IMAGING DEVICE - An imaging element according to the present disclosure includes: a first pixel and a second pixel each including a light receiving section and a light condensing section, in which the light receiving section includes a photoelectric conversion element, and the light condensing section is configured to allow entering light to be condensed toward the light receiving section; a trench provided between the first pixel and the second pixel; a first light shielding film embedded in the trench; and a second light shielding film provided on part of a light receiving surface of the light receiving section of the second pixel, in which the second light shielding film is continuous with the first light shielding film. | 2016-02-18 |
20160049431 | RADIATION IMAGING DEVICE WITH METAL-INSULATOR-SEMICONDUCTOR PHOTODETECTOR AND THIN FILM TRANSISTOR - A photosensor pixel includes a thin film transistor (TFT) and a metal-insulator-semiconductor (MIS) photodetector. The TFT includes a gate, a gate insulator layer, a semiconductor layer forming a channel region, a drain, and a source. The MIS photodetector includes a transparent conductor layer, a semiconductor layer including a photosensitive semiconductor, and an insulator layer between the transparent conductor layer and the semiconductor layer. The semiconductor layer of the MIS photodetector is connected to the source or the drain of the TFT, and the thickness of the insulator layer of the MIS photodetector is less than the thickness of the gate insulator layer of the TFT. | 2016-02-18 |
20160049432 | SOLID-STATE IMAGE PICKUP DEVICE - A solid-state image pickup device has a first substrate and a second substrate in which circuit elements constituting pixels are arranged. The pixel includes: a pixel section that includes a photoelectric conversion element; a ground potential controller that switches a potential to which a circuit element included in the pixel section is grounded; and a reading section that outputs a signal corresponding to the signal charge as a pixel signal output by the pixel. The pixel section includes: the photoelectric conversion element; an amplification transistor that outputs an amplification signal amplified according to the signal charge generated by the photoelectric conversion element; and a switch circuit that switches a ground of the amplification transistor according to a first output mode and a second output mode. The ground potential controller supplies a first potential in the first output mode and supplies a second potential in the second output mode. | 2016-02-18 |
20160049433 | SOLID-STATE IMAGING DEVICE, SOLID-STATE IMAGING DEVICE MANUFACTURING METHOD, ELECTRONIC DEVICE, AND LENS ARRAY - A solid-state imaging device includes: multiple micro lenses, which are disposed in each of a first direction and a second direction orthogonal to the first direction, focus the incident light into the light-receiving surface; with the multiple micro lenses of which the planar shape is a shape including a portion divided by a side extending in the first direction and a side extending in the second direction being disposed arrayed mutually adjacent to each of the first direction and the second direction; and with the multiple micro lenses being formed so that the depth of a groove between micro lenses arrayed in a third direction is deeper than the depth of a groove between micro lenses arrayed in the first direction, and also the curvature of the lens surface in the third direction is higher than the curvature of the lens surface in the first direction. | 2016-02-18 |
20160049434 | DIGITAL RADIATION SENSOR PACKAGE - A radiation sensing apparatus includes, in a vertically stacked configuration: a radiation sensor chip, an integrated circuit chip beneath the radiation sensor chip, and an optical element above the radiation sensor chip. The radiation sensor chip has a radiation sensing element and an electrically-conductive contact coupled to the radiation sensing element and exposed at a lower surface. The integrated circuit chip has an integrated circuit and an electrical conductor coupled to the integrated circuit and exposed at an upper surface. The electrically conductive contact at the lower surface of the radiation sensor chip is physically and electrically coupled to the electrical conductor at the upper surface of the integrated circuit chip. The optical element is configured to pass incident radiation at a wavelength that the radiation sensing element is configured to sense. | 2016-02-18 |
20160049435 | WAFER ON WAFER STACK METHOD OF FORMING AND METHOD OF USING THE SAME - A wafer on wafer (WOW) stack includes a first wafer having dies of a first type. The WOW stack further includes a second wafer bonded to the first wafer. The second wafer has dies of a second type. An integer number of dies of the second type are bonded to a corresponding die of the first type. A total area of the dies of the second type bonded to the corresponding die of the first type is less than or equal to an area of the corresponding die of the first type. A functionality of the dies of the first type is different from a functionality of the dies of the second type. | 2016-02-18 |
20160049436 | CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing chip package includes providing a semiconductor substrate having at least a photo diode and an interconnection layer. The interconnection layer is disposed on an upper surface of the semiconductor substrate and above the photo diode and electrically connected to the photo diode. At least a redistribution circuit is formed on the interconnection layer. The redistribution circuit is electrically connected to the interconnection layer. A packaging layer is formed on the redistribution circuit. Subsequently, a carrier substrate is attached to the packaging layer. A colour filter is formed on a lower surface of the semiconductor substrate. A micro-lens module is formed under the colour filter. The carrier substrate is removed. | 2016-02-18 |
20160049437 | SOLID-STATE IMAGING DEVICE - A MOS solid-state imaging device is provided in which withstand voltage and 1/f noise of a MOS transistor are improved. In the MOS solid-state imaging device whose unit pixel has at least a photoelectric converting portion and a plurality of field effect transistors, the thickness of gate insulating film in a part of the field effect transistors is different from the thickness of gate insulating film in the other field effect transistors among the plurality of the field effect transistors. | 2016-02-18 |
20160049438 | IMAGING DEVICE AND IMAGING UNIT - An imaging device having a first surface on which light is incident and a second surface on an opposite side of the first surface, includes a photoelectric conversion section including semiconductors having a same conductivity type, in which an impurity concentration on the second surface side is higher than an impurity concentration on the first surface side. | 2016-02-18 |
20160049439 | IMAGE PICKUP DEVICE AND IMAGE PICKUP APPARATUS - An image pickup device according to the present disclosure includes a first pixel and a second pixel each including a photodetection section and a light condensing section, the photodetection section including a photoelectric conversion element, the light condensing section condensing incident light toward the photodetection section, the first pixel and the second pixel being adjacent to each other and each having a step part on a photodetection surface of the photodetection section, in which at least a part of a wall surface of the step part is covered with a first light shielding section. | 2016-02-18 |
20160049440 | IMAGE PICKUP UNIT AND ELECTRONIC APPARATUS - A solid-state image pickup unit includes substrate; a red pixel including a red charge storage section; a blue pixel including a blue charge storage section; and a green pixel including a plurality of green charge storage sections, the red charge storage section and the blue charge storage section being provided in the substrate. Then, the plurality of green charge storage sections are arranged in the substrate along a thickness direction of the substrate. | 2016-02-18 |
20160049441 | FLEXIBLE APS X-RAY IMAGER WITH MOTFT PIXEL READOUT AND A PIN DIODE SENSING ELEMENT - A method of fabricating an X-ray imager including the steps of forming an etch stop layer on a glass substrate and depositing a stack of semiconductor layers on the etch stop layer to form a sensor plane. Separating the stack into an array of PIN photodiodes. Depositing a layer of insulating material on the array to form a planarized surface and forming vias through the insulating layer into communication with an upper surface of each photodiode and forming metal contacts on the planarized surface through the vias in contact with each photodiode. Fabricating an array of MOTFTs in an active pixel sensor configuration backplane on the planarized surface and in electrical communication with the contacts, to provide a sensor plane/MOTFT backplane interconnected combination. Attaching a flexible support carrier to the MOTFT backplane and removing the glass substrate. A scintillator is then laminated on the array of photodiodes. | 2016-02-18 |
20160049442 | Light-Emitting Structure - A light-emitting structure, comprising a substrate; a first unit and a second unit, separately formed on the substrate; a trench between the first unit and the second unit; and an electrical connection, electrically connecting the first unit and the second unit and comprising a bridging portion and a joining portion extending from the bridging portion, wherein the bridging portion is wider than the joining portion and the bridging portion is configured to cover the trench, and the joining portion is configured to cover first unit and the second unit. | 2016-02-18 |
20160049443 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A display device includes: a substrate; a pixel defining layer defining a pixel region on the substrate; a first electrode on the pixel region; a light emitting layer on the first electrode; a second electrode on the light emitting layer; a thin film encapsulation layer on the second electrode; a metal pattern on the thin film encapsulation layer and overlapping the pixel defining layer; and a multi-layer thin film layer on the metal pattern and the thin film encapsulation layer. | 2016-02-18 |
20160049444 | ARRAY-TYPE LIGHT-EMITTING DEVICE AND APPARATUS THEREOF - The application discloses an array-type light-emitting device comprising a substrate, a semiconductor light-emitting array formed on the substrate and emitting a first light with a first spectrum, wherein the semiconductor light-emitting array comprises a first light-emitting unit and a second light-emitting units, a first wavelength conversion layer formed on the first light-emitting unit for converting the first light into a third light with a third spectrum, and a circuit layer connecting the first light-emitting unit and the second light-emitting unit in a connection form to make the first light-emitting and the second light-emitting unit light alternately in accordance with a predetermined clock when driving by a power supply. | 2016-02-18 |
20160049445 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a semiconductor substrate including a plane portion expanding in a first direction and a second direction perpendicular to the first direction, and a pillar portion formed on an upper surface of the plane portion and extending in a stacking direction, a first gate electrode formed on a first gate insulating layer on a lower side surface of the pillar portion, and extending in the first direction, a second gate electrode formed on a second gate insulating layer on an upper side surface of the pillar portion, and extending in the second direction, a variable-resistance element formed on an upper surface of the pillar portion, and an interconnection formed on an upper surface of the variable-resistance element. | 2016-02-18 |
20160049446 | TRANSISTOR, RESISTANCE VARIABLE MEMORY DEVICE INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOF - A resistance variable memory device including a vertical transistor includes an active pillar including a channel region, a source formed in one end of the channel region, and a lightly doped drain (LDD) region and a drain formed in the other end of the channel region, a first gate electrode formed to surround a periphery of the LDD region and having a first work function, and a second gate electrode formed to be connected to the first gate electrode and to surround the channel region and having a second work function that is higher than the first work function. | 2016-02-18 |
20160049447 | RESISTIVE MEMORY DEVICE AND METHOD OF OPERATING RESISTIVE MEMORY DEVICE - A resistive memory device includes a plurality of memory cell pillars arranged in a line in one direction and each having a memory layer and a top electrode layer connected to the memory layer, a top conductive line having a plurality of protrusions extending downwardly and between which pockets in the bottom of the top conductive line are defined, and a plurality of insulating pillars. The protrusions of the top conductive line face and are electrically connected to the memory cell pillars, respectively, so as to be electrically connected to the memory layer through the top electrode layer of the memory cell pillar. The insulating pillars extend from insulating spaces, between side wall surfaces of the memory layers and top electrode layers of the memory cell pillars, into the pockets in the bottom of the top conductive line. | 2016-02-18 |
20160049448 | IMAGE SENSOR AND ELECTRONIC DEVICE INCLUDING THE SAME - Example embodiments relate to an image sensor that includes a semiconductor substrate integrated with at least one photo-sensing device, an impurity-doped first light-transmitting electrode present in the semiconductor substrate, an organic photoelectric conversion layer positioned on one side of the semiconductor substrate and absorbing light in a different wavelength from the wavelength sensed by the photo-sensing device, and a second light-transmitting electrode positioned on one side of the organic photoelectric conversion layer, and an electronic device including the same. | 2016-02-18 |
20160049449 | IMAGE SENSOR HAVING LIGHT GUIDE MEMBERS - Image sensors include a color photo-sensing photoelectric conversion device, a first color filter and a second color filter disposed under the color photo-sensing photoelectric conversion device, a first photodiode and a second photodiode disposed under the first color filter and the second color filter, respectively, a first light guide member disposed between the first color filter and the first photodiode, and a second light guide member disposed between the second color filter and the second photodiode. | 2016-02-18 |
20160049450 | DONOR MASK, METHOD OF MANUFACTURING ORGANIC LIGHT-EMITTING DISPLAY APPARATUS BY USING THE SAME, AND ORGANIC LIGHT-EMITTING DISPLAY APPARATUS - A donor mask and a method of manufacturing an organic light-emitting display apparatus by using the donor mask. The method includes transferring a portion corresponding to a through hole of a transferring layer deposited on a light-to-heat conversion layer of the donor mask onto at least a portion of pixel electrodes on a substrate. | 2016-02-18 |
20160049451 | THIN FILM TRANSISTOR, AND THIN FILM TRANSISTOR ARRAY PANEL AND ORGANIC LIGHT EMITTING DIODE DISPLAY INCLUDING THE SAME - A thin film transistor includes a semiconductor which is disposed on a substrate and includes a source region, a drain region and a channel region, a gate insulating layer disposed on the semiconductor, a gate electrode disposed on the gate insulating layer, an interlayer insulating layer disposed on the gate electrode, contact holes defined in the interlayer insulating layer, the contact holes respectively exposing the source region and the drain region of the semiconductor, and a source electrode and a drain electrode which are disposed on the interlayer insulating layer and respectively contact the source region and the drain region through the contact holes, where at least one of the contact holes exposing the source region and the drain region obliquely traverses the semiconductor. | 2016-02-18 |
20160049452 | LIGHT-EMITTING DEVICE - There is provided an EL light-emitting device with less uneven brightness. When a drain current of a plurality of current controlling TFTs is Id, a mobility is μ, a gate capacitance per unit area is Co, a maximum gate voltage is Vgs | 2016-02-18 |
20160049453 | OLED ARRAY SUBSTRATE, MANUFACTURING METHOD OF THE SAME, DISPLAY PANEL, AND DISPLAY DEVICE - The present invention provides an OLED array substrate, a manufacturing method of the same, a display panel, and a display device, and relates to the field of active matrix organic light-emitting diode (AMOLED) display technology. The present invention can solve the problem that turn-on and turn-off of a switching thin film transistor and grayscale control cannot be performed effectively because the switching thin film transistor and a driving thin film transistor are manufactured as thin film transistors having same performance parameters in an existing OLED array substrate. The OLED array substrate according to the present invention includes a switching thin film transistor and a driving thin film transistor, wherein, an S factor of the switching thin film transistor is less than that of the driving thin film transistor. | 2016-02-18 |
20160049454 | Organic Light Emitting Display Panel - An organic light emitting display panel is provided that comprises a substrate comprising an emission area and a non-emission area; a black matrix disposed on the non-emission area and comprising at least one open area that exposes at least a portion of a pattern formed on the substrate, wherein the pattern or the exposed portion of the pattern comprises a multi-layer structure comprising a conductive layer and at least one low reflective layer. | 2016-02-18 |
20160049455 | Organic Electroluminescence Display - An organic electroluminescence display includes a plurality of scan lines, a plurality of data lines, at least one first pixel circuit, and at least one second pixel circuit. The scan lines and the data lines cross. Each of the first and second pixel circuits is electrically connected to one of the scan lines and one of the data lines. The first pixel circuit includes at least one first driving transistor having a first channel in a first channel direction. The second pixel circuit includes at least one second driving transistor having a second channel in a second channel direction. The second channel direction is different from that of the first channel direction. | 2016-02-18 |
20160049456 | DISPLAY APPARATUS AND ELECTRONIC APPARATUS - Disclosed herein is a display apparatus, including: a plurality of subpixels disposed adjacent each other and forming one pixel which forms a unit for formation of a color image; the plurality of subpixels including a first subpixel which emits light of the shortest wavelength and a second subpixel disposed adjacent the first subpixel; the second subpixel having a light blocking member disposed between the second subpixel and the first subpixel and having a width greater than a channel length or a channel width of a transistor which forms the second subpixel. | 2016-02-18 |
20160049457 | METHOD OF MANUFACTURING DISPLAY APPARATUS - A display apparatus includes a plurality of pixels, a signal transmission line, a pad and a buffer. The pixels display an image. The signal transmission line is electrically connected to at least one of the pixels to transmit a signal. The pad is electrically connected to the signal transmission line. The pad has greater width than the signal transmission line. The buffer is disposed between the signal transmission line and the pad. A first end of the buffer adjacent to the pad is wider than a second end of the buffer adjacent to the signal transmission line. | 2016-02-18 |
20160049458 | FISHBONE LC COMPONENT AND METHOD OF MAKING THE SAME - A semiconductor structure according to some examples may include an LC component for use in PMIC applications. The semiconductor structure may have a first conductive coil mounted on an upper surface of a substrate, the first conductive coil surrounding a magnetic core; an output located on a surface of the first conductive coil and coupled to the coil; a dielectric layer located on a surface of the output; and an upper conductive element located on a surface of the dielectric layer, wherein the upper conductive element, the dielectric layer, and the output form a capacitor; and the first conductive coil and the magnetic core form an inductor. The semiconductor structure may also include a second conductive coil located in a same horizontal plane as the first conductive coil, the second conductive coil surrounding a magnetic core where the first conductive coil and the second conductive coil form a fishbone pattern. | 2016-02-18 |
20160049459 | INTEGRATED CIRCUIT COMPRISING AT LEAST AN INTEGRATED ANTENNA - An integrated circuit on a substrate including at least one peripheral portion that surrounds an active area and is realized close to at least one scribe line providing separation with other integrated circuits realized on a same wafer. The integrated circuit includes at least one conductive structure that extends in its peripheral portion on different planes starting from the substrate and realizes an integrated antenna for the circuit. | 2016-02-18 |
20160049460 | Semiconductor Devices Having a Supporter and Methods of Fabricating the Same - Provided are semiconductor devices and methods of fabricating the same. The semiconductor devices include an interlayer insulating layer on a semiconductor substrate, contact pads on the semiconductor substrate and penetrating the interlayer insulating layer, a stopping insulating layer on the interlayer insulating layer, storage electrodes on the contact pads, upper supporters between upper parts of the storage electrodes, side supporters between the storage electrodes and the upper supporters, a capacitor dielectric layer on the storage electrodes, the side supporters, and the upper supporters, and a plate electrode on the capacitor dielectric layer. | 2016-02-18 |
20160049461 | METAL-INSULATOR-METAL (MIM) CAPACITOR - There is disclosed a metal-insulator-metal, MIM, capacitor. The MIM capacitor comprises a MIM stack formed within an interconnect metal layer. The interconnect metal layer is utilised as an electrical connection to a metal layer of the MIM stack. | 2016-02-18 |
20160049462 | SEMICONDUCTOR CAPACITOR STRUCTURE FOR HIGH VOLTAGE SUSTAIN - The present invention provides a semiconductor capacitor structure. The semiconductor capacitor structure comprises a first metal layer, a second metal layer and a first dielectric layer. The first metal layer is arranged to be a part of a first electrode of the semiconductor capacitor structure, and the first metal layer comprises a first portion and a second portion. The first portion is formed to have a first pattern, and the second portion is connected to the first portion. The second metal layer is arranged to be a part of a second electrode of the semiconductor capacitor structure, and the first dielectric layer is formed between the first metal layer and the second metal layer. | 2016-02-18 |
20160049463 | Semiconductor Device with a Shielding Structure - A semiconductor device has a semiconductor body including opposing bottom and top sides, a surface surrounding the semiconductor body, an active semiconductor region formed in the semiconductor body, an edge region surrounding the active semiconductor region, a first semiconductor zone of a first conduction type formed in the edge region, an edge termination structure formed in the edge region at the top side, and a shielding structure arranged on that side of the edge termination structure facing away from the bottom side. The shielding structure has a number of N1≧2 first segments and a number of N2≧1 second segments. Each of the first segments is electrically connected to each of the other first segments and to each of the second segments, and each of the second segments has an electric resistivity higher than an electric resistivity of each of the first segments. | 2016-02-18 |
20160049464 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - Some embodiments of the present disclosure provide a semiconductor device including a substrate and a gate structure on the substrate. A first well region of a first conductivity type is in the substrate, close to a first sidewall of the gate structure. A second well region of a second conductivity type is also in the substrate close to the second sidewall of the gate structure. A conductive region is disposed in the second well region. The conductive region can be an epitaxy region. A chemical composition inside the second well region between the conductive region and the gate structure is essentially homogeneous as a chemical composition throughout the second well region. | 2016-02-18 |