08th week of 2009 patent applcation highlights part 12 |
Patent application number | Title | Published |
20090045406 | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE - A semiconductor device which can realize a diode function is provided with a manufacturing process of a polysilicon thin film transistor and without adding a dedicated process. A semiconductor device is provided having a semiconductor layer comprising a low-concentration p-type polysilicon region formed over a substrate, the semiconductor device comprising a high-concentration p-type polysilicon region and a high-concentration n-type polysilicon region which are formed over the substrate on both sides of the low-concentration p-type polysilicon region, an insulating film which is formed over the high-concentration p-type polysilicon region, the low-concentration p-type polysilicon region, and the high-concentration n-type polysilicon region, and a control electrode which is formed over the insulating film and over the low-concentration p-type polysilicon region, wherein the control electrode is electrically connected to one of the high-concentration p-type polysilicon region and the high-concentration n-type polysilicon region. | 2009-02-19 |
20090045407 | SOLID-STATE IMAGING DEVICE - Realized is a solid-state imaging device capable of achieving both a finer pixel size and high light receiving efficiency with an excellent image characteristic. A high concentration p-well layer ( | 2009-02-19 |
20090045408 | Display device - A display device includes a display panel which forms a plurality of sub pixels on a substrate thereof, and a drive circuit which is configured to drive the plurality of sub pixels, wherein the drive circuit has a thin film transistor formed on the substrate, and the thin film transistor has a semiconductor layer made of poly-silicon. The thin film transistor includes: a source electrode, a semiconductor layer and a drain electrode which are formed on the substrate; a gate insulation film which is formed on the source electrode, the semiconductor layer and the drain electrode; a gate electrode which is formed on the gate insulation film and above the semiconductor layer; an insulation film which is formed on the gate electrode; and a metal layer which is formed on the insulation film in a state that the metal layer covers at least a portion of the gate electrode. | 2009-02-19 |
20090045409 | Display device - A display device including both an n-channel thin film transistor and a p-channel thin film transistor each having excellent electric characteristics and high reliability is demonstrated, and a method for manufacturing thereof is also provided. The display device includes an inverted-staggered p-channel thin film transistor and an inverted-staggered n-channel thin film transistor in which a gate insulating film, a microcrystalline semiconductor film, and an amorphous semiconductor film are sequentially stacked over a gate electrode. The microcrystalline semiconductor film contains oxygen at a concentration of 1×10 | 2009-02-19 |
20090045410 | GaN SUBSTRATE AND SEMICONDUCTOR DEVICE PREPARED BY USING METHOD AND APPARATUS OF POLISHING GaN SUBSTRATE - In a polishing method of a GaN substrate according to this invention, first, while supplying a polishing solution | 2009-02-19 |
20090045411 | Forming Embedded Dielectric Layers Adjacent to Sidewalls of Shallow Trench Isolation Regions - A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate; an insulating region extending from substantially a top surface of the semiconductor substrate into the semiconductor substrate; an embedded dielectric spacer adjacent the insulating region, wherein a bottom of the embedded dielectric spacer adjoins the semiconductor substrate; and a semiconductor material adjoining a top edge and extending on a sidewall of the embedded dielectric spacer. | 2009-02-19 |
20090045412 | Method for production of silicon carbide layer, gallium nitride semiconductor device and silicon substrate - A method for producing a silicon carbide layer on a surface of a silicon substrate includes the step of irradiating the surface of the silicon substrate heated in a high vacuum at a temperature in a range of from 500° C. to 1050° C. with a hydrocarbon-based gas as well as an electron beam to form a cubic silicon carbide layer on the silicon substrate surface. | 2009-02-19 |
20090045413 | Silicon Carbide Bipolar Semiconductor Device - In a SiC bipolar semiconductor device with a mesa structure having a SiC drift layer of a first conductive type and a SiC carrier injection layer of a second conductive type that are SiC epitaxial layers grown from a surface of a SiC single crystal substrate, the formation of stacking faults and the expansion of the area thereof are prevented and thereby the increase in forward voltage is prevented. Further, a characteristic of withstand voltage in a reverse biasing is improved. An forward-operation degradation preventing layer is formed on a mesa wall or on a mesa wall and a mesa periphery to separate spatially the surface of the mesa wall from a pn-junction interface. In one embodiment, the forward-operation degradation preventing layer is composed of a silicon carbide low resistance layer of a second conductive type that is equipotential during the application of a reverse voltage. In another embodiment, the forward-operation degradation preventing layer is composed of a silicon carbide conductive layer of a second conductive type, and a metal layer that is equipotential during the application of a reverse voltage is formed on a surface of the silicon carbide conductive layer. In still another embodiment, the forward-operation degradation preventing layer is composed of a high resistance amorphous layer. | 2009-02-19 |
20090045414 | SILICON CARBIDE SEMICONDUCTOR ELEMENT, METHOD OF MANUFACTURING THE SAME, AND SILICON CARBIDE DEVICE - A silicon carbide semiconductor element and a manufacturing method thereof are disclosed in which a low contact resistance is attained between an electrode film and a wiring conductor element, and the wiring conductor element is hardly detached from the electrode film. In the method, a nickel film and a nickel oxide film are laminated in this order on a surface of an n-type silicon carbide substrate or an n-type silicon carbide region of a silicon carbide substrate, followed by a heat treatment under a non-oxidizing condition. The heat treatment transforms a portion of the nickel film into a nickel silicide film. Then, the nickel oxide film is removed with hydrochloric acid solution, and subsequently, a nickel aluminum film and an aluminum film are laminated in this order on a surface of the nickel silicide film. | 2009-02-19 |
20090045415 | BACKSIDE-ILLUMINATED IMAGING DEVICE - A backside-illuminated imaging device is provided and includes: a plurality of charge accumulating areas in the semiconductor substrate which accumulate the electric charges; and a plurality of filters above a backside surface of the semiconductor substrate corresponding to the respective charge accumulating areas. The plurality of filters includes different color filters which transmit different color components of the light from one another and luminance filters each having a spectral characteristic correlated with a luminance component of the light, the plurality of charge accumulating areas includes first charge accumulating areas corresponding to the respective color filters, and second charge accumulating areas corresponding to the respective luminance filters, and the second charge accumulating areas includes a third charge accumulating area having a size larger than those of the first accumulating areas. | 2009-02-19 |
20090045416 | Optical Element Coupled to Low Profile Side Emitting LED - A low profile, side-emitting LED with one or more optical elements, such as a reflector or lens, optically coupled to each light emitting sidewall is described. In one embodiment, a reflector is used to redirect the light emitted from each sidewall to a forward direction, e.g., in a flash configuration. In another embodiment, a lens is used to collimate the side emitted light in the horizontal plane, e.g., for backlighting. Each entrance surface of the lens is positioned so that the bottom edge is at or below the bottom of the light emitting sidewall so that the base of the lens does not block light that is emitted by the LED. | 2009-02-19 |
20090045417 | LIGHT EMITTING SEMICONDUCTOR DEVICE - A light emitting semiconductor device is provided, wherein the light emitting semiconductor device comprises a substrate, a plurality of flip chips, a heat conductive board and an insulating board. These flip chips are electrically connected on the substrate. The heat conductive board has a protruding portion used to support the substrate. The insulating board has a plurality of connecting pads and an opening, wherein the protruding portion is sheathed in the opening, so as to expose the substrate. The exposed substrate is then electrically connected to the connecting pads. | 2009-02-19 |
20090045418 | Light emitting diode (LED) with longitudinal package structure - The present invention provides erected LED package structure, which includes: a carrier substrate having a first surface, a second surface and a plurality of through holes passed through the first surface and the second surface of the carrier substrate, and the conductive material filled with each of the through holes; a LED having a semiconductor layer capable of the light emitting and an N electrode and a P electrode formed on the two sides of the semiconductor layer thereon; a first transparent carrier substrate having a metal layer thereon, in which the metal layer electrically connected to the N electrode of the LED and to the conductive material which is formed on the first surface of the carrier substrate; a second transparent carrier substrate having another metal layer thereon, in which another metal layer electrically connected to the P electrode of the LED and to another conductive material which is formed on the first surface of the carrier substrate; and a plurality of connecting elements electrically connected to the plurality of conductive material which is formed on the second surface of the carrier substrate. | 2009-02-19 |
20090045419 | Semiconductor light-emitting device with high light-extraction efficiency and method for fabricating the same - The invention discloses a semiconductor light-emitting device and a method of fabricating the same. The semiconductor light-emitting device according to the invention includes a substrate, a first semiconductor material layer, a multi-layer structure and an ohmic electrode structure. The substrate has a first upper surface and a plurality of recesses formed on the first upper surface. The first semiconductor material layer is formed on the first upper surface of the substrate and has a second upper surface. The multi-layer structure is formed on the second upper surface of the first semiconductor material layer and includes a light-emitting region. The ohmic electrode structure is formed on the multi-layer structure. In particular, the first semiconductor material layer has a refractive index different from those of the substrate and a bottom-most layer of the multi-layer structure. | 2009-02-19 |
20090045420 | Backlight Including Side-Emitting Semiconductor Light Emitting Devices - Individual side-emitting LEDs are separately positioned in a waveguide, or mounted together on a flexible mount then positioned together in a waveguide. As a result, the gap between each LED and the waveguide can be small, which may improve coupling of light from the LED into the waveguide. Since the LEDs are separately connected to the waveguide, or mounted on a flexible mount, stress to individual LEDs resulting from changes in the shape of the waveguide is reduced. | 2009-02-19 |
20090045421 | Surface mount type light emitting diode package device - The invention discloses a surface mount type light emitting diode (LED) package device, which has a cup-shaped structure and comprises a specific lens bulged out over the cup opening. The lens is an aspheric lens having a specific curved surface not fully symmetric with respect to its central point, while it exhibits a similarly symmetric curved surface with respect to a bisector line or a diagonal line passing through the central point. The LED package device according to the present invention may have a wider view angle. | 2009-02-19 |
20090045422 | MEMBER FOR SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SUCH MEMBER, AND SEMICONDUCTOR LIGHT EMITTING DEVICE USING SUCH MEMBER - To provide novel semiconductor light-emitting device member superior in transparency, light resistance, and heat resistance and capable of sealing semiconductor light-emitting device and holding phosphor without generating cracks or peelings even after use for a long time, the member meets the following requirements: (1) comprising functional group forming hydrogen bond with hydroxyl group or oxygen in a metalloxane bond, on the surface of ceramic or metal, (2) maintenance rate of transmittance at 400 nm wavelength before and after left at 200° C. for 500 hours is between 80% to 110%, (3) no change is observed by visual inspection after irradiated with light having 380 nm to 500 nm wavelength, whose center wavelength is between 400 nm and 450 nm both inclusive, for 24 hours with 4500 W/m | 2009-02-19 |
20090045423 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - An object of the present invention is to provide a light-emitting device with a high output and a high efficiency by improving the efficiency for utilizing light emitted from a semiconductor light-emitting element. | 2009-02-19 |
20090045424 | SILICONE BASED CIRCUIT BOARD INDICATOR LED LENS - The present invention relates generally to a light transmitting device. In one embodiment, the light transmitting device includes a light emitting diode (LED) chip, a surface mounting device and a lens comprising a silicone based material, wherein a portion of the lens achieves a total internal reflection of a light emitted by the LED chip. | 2009-02-19 |
20090045425 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor light emitting device includes: a support substrate; a metal layer provided on the support substrate; a semiconductor layer provided on the metal layer and including a light emitting layer; a contact layer containing a semiconductor, selectively provided between the semiconductor layer and the metal layer, and being in contact with the semiconductor layer and the metal layer; and an insulating film provided between the semiconductor layer and the metal layer at a position not overlapping the contact layer. | 2009-02-19 |
20090045426 | Semiconductor chip and method for producing a semiconductor chip - A semiconductor chip ( | 2009-02-19 |
20090045427 | Photonic Crystal Light Emitting Device - A photonic crystal structure is formed in an n-type region of a III-nitride semiconductor structure including an active region sandwiched between an n-type region and a p-type region. A reflector is formed on a surface of the p-type region opposite the active region. In some embodiments, the growth substrate on which the n-type region, active region, and p-type region are grown is removed, in order to facilitate forming the photonic crystal in an n-type region of the device, and to facilitate forming the reflector on a surface of the p-type region underlying the photonic crystal. The photonic crystal and reflector form a resonant cavity, which may allow control of light emitted by the active region. | 2009-02-19 |
20090045428 | POLARLESS SURFACE MOUNTING LIGHT EMITTING DIODE - A polarless surface mounting light emitting diode comprises a substrate having; an upper surface of the substrate being etched with four independent metal thin film block; an lower surface of the substrate being formed with two independent metal thin film block; two ends of the substrate being formed with electroplating through holes; a plurality of metal thin films adhered upon the upper and lower surfaces of the substrate; at least one light emitting assembly, each light emitting assembly being formed by the chip resistor and the chip light emitting diode; and a package layer. The connection of the polarless surface mounting light emitting diode of the present invention is not limited by the polarity. Any end of the polarless surface mounting light emitting diode can be connected to positive electrode or negative electrode. | 2009-02-19 |
20090045429 | Diode structure and memory device including the same - Provided are a diode structure and a memory device including the same. The diode structure includes: a first electrode; a p-type Cu oxide layer formed on the first electrode; an n-type InZn oxide layer formed on the p-type Cu oxide layer; and a second electrode formed on the n-type InZn oxide. | 2009-02-19 |
20090045430 | LIGHT EMITTING ELEMENT - A heat radiation structure of a light emitting element has leads, each lead having a plurality of leg sections, and a light emitting chip mounted on any one of the leads. The present invention can provide a high-efficiency light emitting element, in which a thermal load is reduced by widening a connecting section through which a lead and a chip seating section of the light emitting element are connected, and the heat generated from a heat source can be more rapidly radiated to the outside. Further, the present invention can also provide a high-efficiency light emitting element, in which heat radiation fins are formed between a stopper and a molding portion of a lead of the light emitting element so that natural convection can occur between the heat radiation fins, and an area in which heat radiation can occur is widened to maximize a heat radiation effect. | 2009-02-19 |
20090045431 | SEMICONDUCTOR LIGHT-EMITTING DEVICE HAVING A CURRENT-BLOCKING LAYER FORMED BETWEEN A SEMICONDUCTOR MULTILAYER FILM AND A METAL FILM AND LOCATED AT THE PERIPHERY., METHOD FOR FABRICATING THE SAME AND METHOD FOR BONDING THE SAME - A light-emitting device includes an element structure including at least two semiconductor layers having mutually different conductivity types. A transparent p-side electrode of ITO is formed on the element structure. A bonding pad is formed on a region of the p-side electrode. An n-side electrode made of Ti/Au is formed on the surface of the element structure opposite to the p-side electrode. A metal film made of gold plating with a thickness of about 50 μm is formed, using an Au layer in the n-side electrode as an underlying layer. | 2009-02-19 |
20090045432 | Circuit board for light emitting device package and light emitting unit using the same - A circuit board for a light emitting device and a light emitting unit using the same, which are capable of achieving an enhancement in light emission efficiency and an enhancement in reliability, are disclosed. The disclosed circuit board includes a substrate having a first surface and a second surface, at least one pair of conductive lines formed on the first surface of the substrate, and electrically connected to a light emitting device package, and a heat transfer member formed in a region where the light emitting device package is coupled to the circuit board, such that the heat transfer member connects the first and second surfaces of the substrate. | 2009-02-19 |
20090045433 | NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE AND PRODUCTION METHOD THEREOF - The present invention provides a nitride semiconductor light emitting device, which comprises positive and negative electrodes with high adhesion, can output high power, and does not generate heat; specifically, the present invention provides a nitride semiconductor light emitting device comprising at least an ohmic contact layer, a p-type nitride semiconductor layer, a nitride semiconductor light emitting layer, and an n-type nitride semiconductor layer, which are laminated on a plate layer, wherein a plate adhesion layer is formed between the ohmic contact layer and the plate layer, and the plate adhesion layer is made of an alloy comprising 50% by mass or greater of a same component as a main component of an alloy contained in the plate layer. | 2009-02-19 |
20090045434 | GALLIUM NITRIDE-BASED COMPOUND SEMICONDUCTOR LIGHT-EMITTING DEVICE - A gallium nitride-based compound semiconductor light-emitting device including a positive electrode having openings, which is excellent in light extraction efficiency. The gallium nitride-based compound semiconductor light-emitting device includes a substrate; an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer, the layers being formed of a gallium nitride-based compound semiconductor and being stacked in this order on the substrate; a positive electrode which is provided so as to contact the p-type semiconductor layer; and a negative electrode which is provided so as to contact the n-type semiconductor layer, where the positive electrode is a positive electrode having openings, and at least a portion of the surface of the p-type semiconductor layer corresponding to the openings are roughened surface derived from spherical particulates. | 2009-02-19 |
20090045435 | Stamp having nanoscale structure and applications therefore in light-emitting device - A stamp having a nanoscale structure and a manufacturing method thereof are disclosed. The stamp includes a substrate, a buffer layer, and a nanoscale stamp layer. The method comprises forming a buffer layer on the substrate, and forming a stamp layer having a nanoscale structure on the buffer layer. | 2009-02-19 |
20090045436 | LOCALIZED TRIGGER ESD PROTECTION DEVICE - The present invention provides an ESD device to reduce the total triggering current without increasing the overshoot voltage. This is achieved by localizing the triggering current, such that the local current density remains high enough to trigger the ESD device. This localized triggering provides a fast and efficient triggering of the ESD device. | 2009-02-19 |
20090045437 | METHOD AND APPARATUS FOR FORMING A SEMI-INSULATING TRANSITION INTERFACE - The disclosure relates to a method for forming an intermediate lattice transition buffer layer. The method includes: (a) depositing a first graded InAlAs layer on a substrate at a first constant temperature, the first graded InAlAs layer having an In/AI composition ratio which increases across the buffer layer from a first level to a second level; (b) annealing at least the first graded InAlAs layer; (c) depositing the second graded InAlAs layer on the first graded InAlAs layer at the first constant temperature, the second graded InAlAs layer having an In/Al composition ratio which increases across the buffer layer from the second level to a third level; and (d) annealing at least the second graded InAlAs layer; the buffer layer being formed under Groups III/V overpressure. | 2009-02-19 |
20090045438 | FIELD EFFECT TRANSISTOR, AND MULTILAYERED EPITAXIAL FILM FOR USE IN PREPARATION OF FIELD EFFECT TRANSISTOR - In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer). To gate length Lg of a FET to be prepared, a sum a of layer thicknesses of an electron supply layer and a channel layer is selected so as to fulfill Lg/a≧5, and in such a case, the layer thickness of the channel layer is selected in a range of not exceeding 5 times (about 500 Å) as long as a de Broglie wavelength of two-dimensional electron gas accumulated in the channel layer in room temperature. | 2009-02-19 |
20090045439 | Heterojunction field effect transistor and manufacturing method thereof - A heterojunction field effect transistor includes a laminated body. The laminated body includes a channel layer of GaN, an electron supply layer of AlN or Al | 2009-02-19 |
20090045440 | METHOD OF FORMING AN MOS TRANSISTOR AND STRUCTURE THEREFOR - In one embodiment, an MOS transistor is formed with trench gates. The gate structure of the trench gates generally has a first insulator that has a first thickness in one region of the gate and a second thickness in a second region of the gate. | 2009-02-19 |
20090045441 | CMOS image sensor package - A CMOS image sensor package is disclosed. The CMOS image sensor package includes: a substrate, on which a pre-designed circuit pattern is formed, and in which a cavity is formed; a pixel array sensor, which is electrically connected with the circuit pattern and stacked on one side of the substrate; and a control chip, which is electrically connected with the circuit pattern and held within the cavity. According to certain aspects of the invention, the CMOS image sensor chip can be separated into the pixel array sensor and the control chip, with the control chip and passive components embedded in cavities formed in the substrate, so that the size of the chip mounted on the substrate may be reduced, and consequently the overall size of the CMOS image sensor package may be reduced. | 2009-02-19 |
20090045442 | SOLID STATE IMAGING DEVICE AND METHOD FOR FABRICATING THE SAME - A first oxide film ( | 2009-02-19 |
20090045443 | SPLIT TRUNK PIXEL LAYOUT - A pixel array architecture having multiple pixel cells arranged in a split trunk pixel layout and sharing common pixel cell components. The array architecture increases the fill factor, and in turn, the quantum efficiency of the pixel cells. The common pixel cell components may be shared by a number of pixels in the array, and may include several components that are associated with the storage and readout of a signal from the pixel cells. | 2009-02-19 |
20090045444 | INTEGRATED DEVICE AND CIRCUIT SYSTEM - An integrated circuit, comprising a substrate stack, comprising a first substrate and a second substrate, the first substrate comprising a first contact field on a side face of the substrate stack and the second substrate comprising a second contact field on the side face; a side substrate, comprising a first contact pad and a second contact pad, the first contact pad being coupled to the second contact pad; first connection, connecting the first contact field and the first contact pad; and a second connection, connecting the second contact field and the second contact pad. | 2009-02-19 |
20090045445 | CAPACITOR STRUCTURE USED FOR FLASH MEMORY - A method of forming a capacitor for use as a charge pump with flash memory, comprising: (a) concurrently forming polysilicon gates on a semiconductor body in a core region and a polysilicon middle capacitor plate in a peripheral region, (b) forming a first dielectric layer over the polysilicon gates and the middle capacitor plate, (c) planarizing the first dielectric layer to expose a top portion of the polysilicon gates and a top portion of the middle capacitor plate, (d) forming a second dielectric layer over the top portion of the middle capacitor layer, (e) concurrently forming patterning a second polysilicon layer in the core region and a third capacitor plate in the periphery region and (f) connecting the third capacitor plate to the source/drain well. | 2009-02-19 |
20090045446 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device having a first active semiconductor component and a second active semiconductor component, the electrical connections of which are routed out of the semiconductor components in the form of connecting legs is disclosed. In one embodiment, the first semiconductor component is at least partially electrically connected to the second semiconductor component by means of a plug-in connection. The plug-in connection is realized by virtue of the connecting legs of the second semiconductor component engaging in the electrical connections of the first semiconductor component. | 2009-02-19 |
20090045447 | COMPLEX OXIDE NANODOTS - Methods and devices are disclosed, such as those involving forming a charge trap for, e.g., a memory device, which can include flash memory cells. A substrate is exposed to temporally-separated pulses of a titanium source material, a strontium source material, and an oxygen source material capable of forming an oxide with the titanium source material and the strontium source material to form the charge trapping layer on the substrate. | 2009-02-19 |
20090045448 | Non-volatile memory device and methods of forming the same - Example embodiments provide a non-volatile memory device and methods of forming the same. The non-volatile memory device may define an active region in a semiconductor substrate, and may include a device isolation layer extending in a first direction, bit lines in the semiconductor substrate, the bit lines extending in a second direction which intersects the first direction; word lines extending in the first direction and covering the active region; and charge storage patterns between the word lines and active region, wherein the charge storage patterns may be in pairs on both edges of the bit lines, and a pair of charge storage patterns may be spaced apart from each other by the word lines. | 2009-02-19 |
20090045449 | FINNED MEMORY CELLS - For an embodiment, a memory array has a plurality fins protruding from a substrate. A tunnel dielectric layer overlies the fins. A plurality floating gates overlie the tunnel dielectric layer, and the floating gates correspond one-to-one with the fins protruding from the substrate. An intergate dielectric layer overlies the floating gates. A control gate layer overlies the intergate dielectric layer. Each fin includes an upper surface rounded by isotropic etching. | 2009-02-19 |
20090045450 | Non-volatile memory device and method of fabricating the same - Provided are a non-volatile memory device, which may have higher integration density, improved or optimal structure, and/or reduce or minimize interference between adjacent cells without using an SOI substrate, and a method of fabricating the non-volatile memory device. The non-volatile memory device may include: a semiconductor substrate comprising a body, and a pair of fins protruding from the body; a buried insulating layer filling between the pair of fins; a pair of floating gate electrodes on outer surfaces of the pair of fins to a height greater than that of the pair of fins; and a control gate electrode on the pair of floating gate electrodes. | 2009-02-19 |
20090045451 | Semiconductor device and method of manufacturing the same - A method of manufacturing a semiconductor device that comprises the steps of: removing a second insulating film on a contact region of a first conductor; forming a second conductive film on the second insulating film; removing the second conductive film on the contact region of the first conductor to make the second conductive film into a second conductor; forming an interlayer insulating film (a third insulating film) covering the second conductor; forming a first hole in the interlayer insulating film on the contact region; and forming a conductive plug, which is electrically connected with the contact region, in the first hole. | 2009-02-19 |
20090045452 | Structure and Method of Sub-Gate NAND Memory with Bandgap Engineered SONOS Devices - A bandgap engineered SONOS device structure for design with various AND architectures. The BE-SONOS device structure comprises a spacer oxide disposed between a control gate overlaying an oxide-nitride-oxide-nitride-oxide stack and a sub-gate overlaying a gate oxide. In one example, a BE-SONOS sub-gate-AND array architecture has multiple strings of SONONOS devices with sub-gate lines and diffusion bit lines. In another example, a BE-SONOS sub-gate-AND architecture has multiple strings of SONONOS devices with sub-gate lines, relying on the sub-gate lines that create inversions to substitute for the diffusion bit lines. | 2009-02-19 |
20090045453 | NONVOLATILE MEMORY DEVICES INCLUDING GATE CONDUCTIVE LAYERS HAVING PEROVSKITE STRUCTURE AND METHODS OF FABRICATING THE SAME - A nonvolatile memory device includes a tunneling insulating layer on a semiconductor layer. A charge storage layer is on the tunneling insulating layer. A blocking insulating layer having a Perovskite structure is on the charge storage layer. A gate conductive layer having a Perovskite structure is on the blocking insulating layer. | 2009-02-19 |
20090045454 | Semiconductor non-volatile memory cell, method of producing the same, semiconductor non-volatile memory having the semiconductor non-volatile memory cell, and method of producing the same - A semiconductor non-volatile memory cell includes an Si (silicon) layer containing substrate including an activation region having a ridge portion; an element separation region embedded in both sides of the activation region; a gate electrode with a gate insulation film inbetween formed over the ridge portion for covering a part of both side surfaces of the ridge portion and an upper surface of the element separation region; a channel forming region formed in a surface layer region of the ridge portion; an extension region formed on both sides of the channel forming region in the longitudinal direction; and an electric charge accumulation layer capable of accumulating electric charges and a sidewall formed on the extension region and one or both of side surfaces of the gate electrode facing with each other in the longitudinal direction. | 2009-02-19 |
20090045455 | Nonvolatile memory device and method of fabricating the same - Example embodiments relate to nonvolatile semiconductor memory devices using an electric charge storing layer as a storage node and fabrication methods thereof. An electric charge trap type nonvolatile memory device may include a tunneling film, an electric charge storing layer, a blocking insulation film, and a gate electrode. The blocking insulation film may be an aluminum oxide having an energy band gap larger than that of a γ-phase aluminum oxide film. An α-phase crystalline aluminum oxide film as a blocking insulation film may have an energy band gap of about 7.0 eV or more along with fewer defects. The crystalline aluminum oxide film may be formed by providing a source film (e.g., AlF | 2009-02-19 |
20090045456 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device is provided. The method includes forming a gate structure on a substrate. The gate structure includes a patterned gate dielectric layer, a patterned gate conductor layer, a cap layer and a spacer. Next, a first and a second recesses are formed in the substrate on the two sides of the gate structure. Thereafter, a protection layer is formed on the bottom surfaces of the first and the second recesses, and then a etching process is performed to laterally enlarge first and the second recesses towards the direction of the gate structure. Thereafter, a material layer is respectively formed in the first recess and the second recess. Afterward, two source/drain contact regions are respectively formed in the material layers of the first recess and the second recess. | 2009-02-19 |
20090045457 | Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (TVS) - A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate including a low-side steering diode, a high-side steering diode integrated with a main Zener diode for suppressing a transient voltage. The low-side steering diode and the high-side steering diode integrated with the Zener diode are disposed in the semiconductor substrate and each constituting a vertical PN junction as vertical diodes in the semiconductor substrate whereby reducing a lateral area occupied by the TVS device. In an exemplary embodiment, the high-side steering diode and the Zener diode are vertically overlapped with each other for further reducing lateral areas occupied by the TVS device. | 2009-02-19 |
20090045458 | MOS TRANSISTORS FOR THIN SOI INTEGRATION AND METHODS FOR FABRICATING THE SAME - MOS transistors for thin SOI integration and methods for fabricating such MOS transistors are provided. One exemplary method includes the steps of providing a silicon layer overlying a buried insulating layer and epitaxially growing a silicon-comprising material layer overlying the silicon layer. A trench is etched within the silicon-comprising material layer and exposing the silicon layer. An MOS transistor gate stack is formed within the trench. The MOS transistor gate stack comprises a gate insulator and a gate electrode. Ions of a conductivity-determining type are implanted within the silicon-comprising material layer using the gate stack as an implantation mask. | 2009-02-19 |
20090045459 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to an aspect of an embodiment, a semiconductor device has a semiconductor substrate, a gate insulating film on the semiconductor substrate, a gate electrode formed on the gate insulating film, an impurity diffusion region formed in an area of the semiconductor substrate adjacent to the gate electrode to a first depth to the semiconductor substrate, the impurity diffusion region containing impurity, an inert substance containing region formed in the area of the semiconductor substrate to a second depth deeper than the first depth, the inert substance containing region containing an inert substance, and a diffusion suppressing region formed in the area of the semiconductor substrate to a third depth deeper than the second depth, the diffusion suppressing region containing a diffusion suppressing substance suppressing diffusion of the impurity. | 2009-02-19 |
20090045460 | MOSFET FOR HIGH VOLTAGE APPLICATIONS AND A METHOD OF FABRICATING SAME - A PMOS device comprises a semiconductor-on-insulator (SOI) substrate having a layer of insulating material over which is provided an active layer of n-type semiconductor material. | 2009-02-19 |
20090045461 | Active Device on a Cleaved Silicon Substrate - A hydrogen (H) exfoliation gettering method is provided for attaching fabricated circuits to receiver substrates. The method comprises: providing a Si substrate; forming a Si active layer overlying the substrate with circuit source/drain (S/D) regions; implanting a p-dopant into the S/D regions; forming gettering regions underling the S/D regions; implanting H in the Si substrate, forming a cleaving plane (peak concentration (Rp) H layer) in the Si substrate about as deep as the gettering regions; bonding the circuit to a receiver substrate; cleaving the Si substrate along the cleaving plane; and binding the implanted H underlying the S/D regions with p-dopant in the gettering regions, as a result of post-bond annealing. | 2009-02-19 |
20090045462 | ULTRATHIN SOI CMOS DEVICES EMPLOYING DIFFERENTIAL STI LINERS - An oxynitride pad layer and a masking layer are formed on an ultrathin semiconductor-on-insulator substrate containing a top semiconductor layer comprising silicon. A first portion of a shallow trench is patterned in a top semiconductor layer by lithographic masking of an NFET region and an etch, in which exposed portions of the buried insulator layer is recessed and the top semiconductor layer is undercut. A thick thermal silicon oxide liner is formed on the exposed sidewalls and bottom peripheral surfaces of a PFET active area to apply a high laterally compressive stress. A second portion of the shallow trench is formed by lithographic masking of a PFET region including the PFET active area. A thin thermal silicon oxide or no thermal silicon oxide is formed on exposed sidewalls of the NFET active area, which is subjected to a low lateral compressive stress or no lateral compressive stress. | 2009-02-19 |
20090045463 | ACTIVE DEVICE ARRAY SUBSTRATE - An active device array substrate including a substrate, a plurality of pixel units, a plurality of driving lines, a plurality of common lines, an electrostatic discharge (ESD) protection circuit, and a plurality of switch elements is provided. The substrate has a display region and a peripheral region adjacent to the display region. The pixel units are arranged as an array in the display region of the substrate. The driving lines are disposed in the display region and the peripheral region and are electrically connected to the pixel units. The common lines are disposed in the display region and are extended into the peripheral region. The ESD protection circuit is disposed in the peripheral region of the substrate. The switch elements are disposed in the peripheral region, wherein each of the switch elements is electrically connected between one of the common lines and the ESD protection circuit. | 2009-02-19 |
20090045464 | ESD protection for high voltage applications - An ESD device includes a low doped well connected to a first contact and a diffusion area connected to a second contact. A substrate between the low doped well and the diffusion area has a dopant polarity that is opposite a dopant polarity of the low doped well and the diffusion area. A distance between the low doped well and the diffusion area determines a triggering voltage of the ESD device. A depletion region is formed between the low doped well and the substrate when a reverse bias voltage is applied to the ESD device. A current discharging path is formed between the first contact and the second contact when the depletion region comes in to contact with the diffusion area. The substrate is biased by a connection to the second contact. Alternatively, an additional diffusion area with the same dopant polarity, connected to a third contact, biases the substrate. | 2009-02-19 |
20090045465 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device can prevent exposure of an inner wall of a recess pattern caused by misalignment between masks. A gate electrode is formed inside the recess pattern so that only a gate hard mask layer is exposed above a substrate surface. Since the gate electrode is not exposed above the substrate, it is possible to prevent SAC failure and decrease an aspect ratio of a gate pattern to increase an open margin of a contact hole. Thus, a semiconductor device having a recess channel gate structure which exhibits a superior refresh property is fabricated. | 2009-02-19 |
20090045466 | SEMICONDUCTOR DEVICE - There are accomplished nMOSFET and pMOSFET both having high mobility, by optimizing stress and location of a film existing around a gate electrode such that high stress acts on a channel. In nMOSFET, a first film having compressive stress is formed on a gate electrode, and a second film having tensile stress is formed covering a gate electrode, a sidewall spacer of a gate electrode, and source/drain regions therewith. In pMOSFET, a film having tensile stress is formed on the gate electrode in place of the first film, and a film having compressive stress is formed in place of the second film. | 2009-02-19 |
20090045467 | BIPOLAR TRANSISTOR FINFET TECHNOLOGY - This document discusses, among other things, apparatus having at least one CMOS transistor overlying a substrate; and at least one finned bipolar transistor overlying the substrate and methods for making the apparatus. | 2009-02-19 |
20090045468 | TRENCH ISOLATION AND METHOD OF FABRICATING TRENCH ISOLATION - Trench isolation structure and method of forming trench isolation structures. The structures includes a trench in a silicon region of a substrate, the trench extending from a top surface of the substrate into the silicon region; an ion implantation stopping layer over sidewalls of the trench; a dielectric fill material filling remaining space in the trench, the dielectric fill material not including any materials found in the stopping layer; an N-type dopant species in a first region of the silicon region on a first side of the trench; the N-type dopant species in a first region of the dielectric material adjacent to the first side of the trench; a P-type dopant species in a second region of the silicon region on a second side of the trench; and the P-type dopant species in a second region of the dielectric material adjacent to the second side of the trench. | 2009-02-19 |
20090045469 | Semiconductor Device and Manufacturing Method Thereof - A semiconductor device including a silicon substrate; a gate insulating film on the silicon substrate; a gate electrode on the gate insulating film; and source/drain regions formed in the substrate on both sides of the gate electrode, wherein the gate electrode includes a first silicide layered region formed of a silicide of a metal M | 2009-02-19 |
20090045470 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - Provided is a technology capable of suppressing a reduction in electron mobility in a channel region formed in a strained silicon layer. A p type strained silicon layer is formed over a p type silicon-germanium layer formed over a semiconductor substrate. The p type strained layer has a thickness adjusted to be thicker than the critical film thickness at which no misfit dislocation occurs. Accordingly, misfit dislocations occur in the vicinity of the interface between the p type strained silicon layer and p type silicon-germanium layer. At a position which is below the end of a gate electrode and at which misfit dislocations occur, the impurity concentration of the n type strained silicon layer and n type silicon-germanium layer is 1×10 | 2009-02-19 |
20090045471 | Semiconductor device fabricated by selective epitaxial growth method - A semiconductor device in which selectivity in epitaxial growth is improved. There is provided a semiconductor device comprising a gate electrode formed over an Si substrate, which is a semiconductor substrate, with a gate insulating film therebetween and an insulating layer formed over sides of the gate electrode and containing a halogen element. With this semiconductor device, a silicon nitride film which contains the halogen element is formed over the sides of the gate electrode when an SiGe layer is formed over the Si substrate. Therefore, the SiGe layer epitaxial-grows over the Si substrate with high selectivity. As a result, an OFF-state leakage current which flows between, for example, the gate electrode and source/drain regions is suppressed and a manufacturing process suitable for actual mass production is established. | 2009-02-19 |
20090045472 | Methodology for Reducing Post Burn-In Vmin Drift - A semiconductor device includes source/drain regions formed in a substrate and having a concentration of nitrogen of at least about 5E18 cm | 2009-02-19 |
20090045473 | Devices having horizontally-disposed nanofabric articles and methods of making the same - New devices having horizontally-disposed nanofabric articles and methods of making same are described. A discrete electro-mechanical device includes a structure having an electrically-conductive trace. A defined patch of nanotube fabric is disposed in spaced relation to the trace; and the defined patch of nanotube fabric is electromechanically deflectable between a first and second state. In the first state, the nanotube article is in spaced relation relative to the trace, and in the second state the nanotube article is in contact with the trace. A low resistance signal path is in electrical communication with the defined patch of nanofabric. Under certain embodiments, the structure includes a defined gap into which the electrically conductive trace is disposed. The defined gap has a defined width, and the defined patch of nanotube fabric spans the gap and has a longitudinal extent that is slightly longer than the defined width of the gap. | 2009-02-19 |
20090045474 | MEMS sensor and production method of MEMS sensor - The MEMS sensor includes a substrate, a lower thin film, opposed to a surface of the substrate at an interval, having a plurality of lower through-holes formed to pass through the lower thin film in the thickness direction thereof, an upper thin film, opposed to the lower thin film at an interval on the side opposite to the substrate, having a plurality of upper through-holes formed to pass through the upper thin film in the thickness direction thereof, and a plurality of protrusions irregularly provided on a region of the surface of the substrate opposed to the lower thin film. | 2009-02-19 |
20090045475 | DOUBLE SIDED INTEGRATED PROCESSING AND SENSING CHIP - A high density integrated processing and sensing chip includes an integrated signal processing circuit formed on one side of a substrate and a magnetic sensor element formed on an opposing side of the substrate. In one embodiment, the integrated signal processing circuit and the magnetic sensor are able to electrically connected to one another through vias or through metallic trace elements provided by a package frame. | 2009-02-19 |
20090045476 | IMAGE SENSOR PACKAGE AND METHOD FOR FORMING THE SAME - An image sensor package is provided including a substrate; a sensor chip; a plurality of bond wires for connecting the sensor chip to the substrate at predetermined locations; a sensor housing on the substrate for substantially encompassing the sensor chip, the sensor housing having a through-hole cavity defining an optical glass (IR filter) seat, the sensor housing defining an upper surface and an edge surface thereof; an optical glass (IR filter) on the optical glass (IR filter) seat; an encapsulation material for substantially encapsulating the upper surface and edge surface of the sensor housing, a corresponding surface of the substrate adjacent the edge surface of the sensor housing, and the side edge of the optical glass (IR filter); wherein the sensor housing is provided with a gas-exit allowing possible high temperature gas to exit; the encapsulation material forms an upper surface which is substantially aligned with a top surface of the optical glass (IR filter); the encapsulation material forms an upper surface which is lower than a top surface of the optical glass (IR filter); the sensor housing defines a profile shape, the profile shape has at least a step-wise configuration for facilitating and accommodating flowing of the encapsulation material; the sensor housing has a bottom surface adhered to the substrate by an adhesive; and a slot is provided on the bottom surface of the sensor housing for accommodating the adhesive. | 2009-02-19 |
20090045477 | Solid-State Imager Having Anti-Reflection Film, Display, and Its Manufacturing Method - Solid-state image sensors are disclosed that include an optical unit which separates incident light into a plurality of color elements, an optical receiving unit which converts each of the color elements separated by the optical unit to an electrical signal and an anti-reflection film having a high-refractive-index layer with a refractive index of 1.7 or higher and a low-refractive-index layer with a refractive index of less than 1.7. The anti-reflection film is between the optical unit for each of color elements and the optical receiving unit, on a semiconductor substrate. Each of the high-refractive-index layer and the low-refractive-index layer corresponds to at least one color element of the plurality of color elements and includes two or more layers. With such sensors it is possible to suppress the variation in sensitivity for each color. | 2009-02-19 |
20090045478 | CMOS image sensor package structure - The present invention provides a complementary metal oxide semiconductor (CMOS) sensor package structure that includes a carrier substrate having a top surface and a bottom surface; a metal layer placed on the top surface of the carrier substrate and exposed a portion of the top surface of the metal layer; the plurality of CMOS chips having an active surface thereon formed on a portion of the top surface of the metal layer, and being exposed a portion of the active surface; a plurality of connecting elements formed on the bottom surface of the plurality of CMOS chips and a portion of the top surface of the metal layer; a molding material covers a portion of the top surface of the carrier substrate, a plurality of the connecting elements and the bottom surface of each of the plurality of CMOS chips and a plurality of the conductive elements formed on the top of the plurality of connecting elements on the metal layer. | 2009-02-19 |
20090045479 | Image sensor with vertical drain structures - An image sensor includes an array of photo-detectors, a plurality of conductive line regions, and a conductive junction region. The array of photo-detectors is formed in a semiconductor substrate. Each conductive line region is formed under a respective line of photo-detectors along a first direction in the substrate. The conductive junction region is formed between the array of photo-detectors and the plurality of conductive line regions in the substrate. The conductive line regions and the conductive junction region form vertical drain structures for the photo-detectors. | 2009-02-19 |
20090045480 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a plurality of circuit cells on a semiconductor chip. The plurality of circuit cells are formed along a first chip side of the semiconductor chip. Each of the plurality of circuit cells has a pad. The semiconductor integrated circuit further includes a high voltage potential interconnect formed over the plurality of circuit cells. The high voltage potential interconnect has a width expanding in a length direction from a center portion to end portions of the high voltage potential interconnect. | 2009-02-19 |
20090045481 | SEMICONDUCTOR DEVICE HAVING BREAKDOWN VOLTAGE MAINTAINING STRUCTURE AND ITS MANUFACTURING METHOD - A semiconductor device has an active portion having at least one well region in a semiconductor layer, and a breakdown voltage maintaining structure surrounding the active portion. The maintaining structure includes a conductor layer over each of a plurality of guard rings with an insulating film interposed in between and connected to the respective guard ring. An inner side end portion of each conductor layer projects over the immediate adjacent inner side guard ring. The impurity concentration of the guard rings is set between the impurity concentrations of the semiconductor layer and the well regions. A field plate can extend over the innermost conductor layer with the insulating film interposed in between. The field plate is in contact with the outermost well region and is in contact with the first conductor layer. The outer side end of the field plate extends outwardly beyond an outer side end of the innermost conductor layer. With these arrangements, the guard rings can be shortened and the chip size can be reduced. Furthermore, the device can be made less susceptible to external charge. | 2009-02-19 |
20090045482 | Shallow Trench Isolation with Improved Structure and Method of Forming - A shallow trench isolation (STI) structure has a top portion tapering in width from wide to narrow in a direction from a substrate surface, from a first width at a top of the first portion to a second width at a bottom of the first portion. The STI structure also includes a bottom portion below the top portion, which expands from the bottom of the top portion to a substantially widened lateral distance having a third width. The third width is, in general, substantially larger than the second width. The inventive STI structure can provide desired isolation characteristics with a significantly reduced aspect ratio, thus suitable for device isolations in advanced processing technology. | 2009-02-19 |
20090045483 | Semiconductor devices having trench isolation regions and methods of manufacturing semiconductor devices having trench isolation regions - A semiconductor device may include a semiconductor substrate, trench region, buffer pattern, gap fill layer, and transistor. The trench region may be provided in the semiconductor substrate to define an active region. The buffer pattern and gap fill layer may be provided in the trench region. The buffer pattern and gap fill layer may fill the trench region. The gap fill layer may be densified by the buffer pattern. The transistor may be provided in the active region. A method of manufacturing a semiconductor device may include: forming a trench region in a semiconductor substrate; forming a buffer layer on an inner wall of the first trench region; forming a gap fill layer, filling the trench region; performing a thermal process to react the impurity with the oxygen, forming a buffer pattern; and forming a transistor in the active region. | 2009-02-19 |
20090045484 | METHODS AND SYSTEMS INVOLVING ELECTRICALLY REPROGRAMMABLE FUSES - An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire. | 2009-02-19 |
20090045485 | CAPACITOR, METHOD OF MANUFACTURING CAPACITOR, CAPACITOR MANUFACTURING APPARATUS, AND SEMICONDUCTOR MEMORY DEVICE - The present invention provides a capacitor including: an under electrode; an upper electrode; and a dielectric film which is provided between the under electrode and the upper electrode, wherein at least a portion of the dielectric film is composed of an aluminum oxide film deposited by an atomic layer deposition method and a titanium oxide film deposited by the atomic layer deposition method. An aluminum composition ratio x and a titanium composition ratio y in the dielectric film preferably comply with 7≦[x/(x+y)]×100≦35. | 2009-02-19 |
20090045486 | Method of manufacturing nitride semiconductor device - A method of manufacturing a nitride semiconductor device includes the steps of: forming a mask of a pattern selectively covering a cutting line on a first major surface of a substrate; forming group III nitride semiconductor layers exposing the mask provided on the cutting line by selectively growing a group III nitride semiconductor from exposed portions of the first major surface of the substrate; forming a division guide groove on the substrate along the cutting line; and dividing the substrate along the division guide groove. The step of forming the division guide groove may be a step of forming the division guide groove by laser processing. | 2009-02-19 |
20090045487 | SEMICONDUCTOR CHIP, METHOD OF FABRICATING THE SAME AND STACKED PACKAGE HAVING THE SAME - A semiconductor chip, a method of fabricating the same and a stacked package having the same are disclosed. The semiconductor chip includes a wafer, a semiconductor device disposed on the wafer, an insulating layer covering the semiconductor device and disposed on the wafer, a deep via formed to penetrate the wafer and the insulating layer, and a heat dissipation member spaced at a predetermined interval from the deep via and penetrating at least a portion of the insulating layer for dissipating heat generated by the deep via. | 2009-02-19 |
20090045488 | Magnetic shielding package structure of a magnetic memory device - This invention provides a magnetic shielding package structure of a magnetic memory device, in which at least a magnetic memory device is embedded between a magnetic shielding substrate and a magnetic shielding layer. A plurality of through vias is formed in the magnetic shielding substrate or the magnetic shielding layer, and a plurality of conductive contacts passes through the through vias such that electrical connection between the magnetic memory device and the external is established. | 2009-02-19 |
20090045489 | MICROELECTRONIC DIE PACKAGES WITH LEADFRAMES, INCLUDING LEADFRAME-BASED INTERPOSER FOR STACKED DIE PACKAGES, AND ASSOCIATED SYSTEMS AND METHODS - Microelectronic die packages, stacked systems of die packages, and methods of manufacturing thereof are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes stacking a first die package having a first dielectric casing on top of a second die package having a second dielectric casing, aligning first metal leads at a lateral surface of the first casing with second metal leads at a second lateral surface of the second casing, and forming metal solder connectors that couple individual first leads to individual second leads. In another embodiment, the method of manufacturing the microelectronic device may further include forming the connectors by applying metal solder to a portion of the first lateral surface, to a portion of the second lateral surface, and across a gap between the first die package and the second die package so that the connectors are formed by the metal solder wetting to the individual first leads and the individual second leads. | 2009-02-19 |
20090045490 | POWER SEMICONDUCTOR MODULE - Included are a semiconductor package, a first bus bar, a second bus bar and a soldering control unit. The semiconductor package includes a power semiconductor element, a first electrode plate and a second electrode plate. The first bus bar is a conductive member which is soldered onto the main surface of the first electrode plate through a first solder member. The second bus bar is a conductive member which is soldered onto the main surface of the second electrode plate through a second solder member. The soldering control unit is provided on each of the main surface of the first bus bar to which the first electrode plate is soldered and the main surface of the second bus bar to which the second electrode plate is soldered, and controls the solder joint thickness. | 2009-02-19 |
20090045491 | SEMICONDUCTOR PACKAGE STRUCTURE AND LEADFRAME THEREOF - A semiconductor package structure including a chip and a leadframe unit is provided. The chip has an active surface and a plurality of recesses disposed thereon. The leadframe unit has at least one packaging area in which the chip is disposed. The packaging area has a plurality of leads on the peripheral portion thereof, wherein each of the leads has a first end fastened on the peripheral portion of the packaging area and a second end extending inward to the active surface of the chip. The leads have a plurality of protrusions, which are capable of being contained by the recesses, located on the second ends to electrically connect the chip and the leadframe unit. | 2009-02-19 |
20090045492 | LEAD FRAME, SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE LEAD FRAME, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A lead frame is provided which can prevent a short circuit between wires and the ends of adjacent leads, the short circuit being caused by wire sweep during the injection of molding resin, in a configuration where the electrodes of a semiconductor chip and the leads disposed around the semiconductor chip. The lead having sides substantially perpendicular to the direction of a resin flow has an end whose upstream side relative to the resin flow is constricted. | 2009-02-19 |
20090045493 | SEMICONDUCTOR COMPONENT AND METHOD OF PRODUCING - A semiconductor component and method for producing. The semiconductor component includes a semiconductor device and a leadframe. A package layout is defined and the orientation of electrically conductive members with respect to the semiconductor device and inner contact areas of the leadframe is altered so as to maximize the interfacial bonding area. The constraints of the standard package dimensions and the component assembly method are taken into account. | 2009-02-19 |
20090045494 | METHOD FOR MANUFACTURING A MICROELECTRONIC PACKAGE - The invention relates to a method of packaging an electronic microsystem ( | 2009-02-19 |
20090045495 | SEMICONDUCTOR DEVICE WITH SIDE TERMINALS - Side terminals | 2009-02-19 |
20090045496 | STACKED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING STACKED MICROELECTRONIC DEVICES - Stacked microelectronic devices and methods of manufacturing stacked microelectronic devices are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes forming a plurality of electrically isolated, multi-tiered metal spacers on a front side of a first microelectronic die, and attaching a back-side surface of a second microelectronic die to individual metal spacers. In another embodiment, the method of manufacturing the microelectronic device may further include forming top-tier spacer elements on front-side wire bonds of the first die. | 2009-02-19 |
20090045497 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a wiring board having connection pads thereon and a semiconductor chip mounted on the wiring board. The wiring board and the semiconductor chip are covered with a sealing portion. Conductive members are extended upward from the connection pads and are exposed from the sealing portion. Rewiring lines are connected to the exposed conductive members. Land portions are arranged on the sealing portion and are electrically connected to the conductive members through the rewiring lines. | 2009-02-19 |
20090045498 | Partitioning of electronic packages - Partitioning electronic sensor packages is provided. The electronic sensor package includes an electronic component, a sensor device, and electrical connections between the electronic component and the sensor device. A dam is written in the electronic sensor package to partition the package into two or more sections, where the sensor device is situated at least partially in one section and the electronic component is situated at least partially in another section. The partitioning of the dam allows the two sections to be filled with different fill materials. For example, the section with the sensor device can be filled with a soft gel-like material to provide some moisture protection to the sensor device without causing detrimental stresses to the sensor device, whilst the section with the electronic component can be filled with a highly moisture protective epoxy. | 2009-02-19 |
20090045499 | Semiconductor package having a plurality input/output members - A semiconductor package has a first substrate having a plurality of electrically conductive patterns formed thereon. A first semiconductor die is coupled to the plurality of conductive patterns. A second semiconductor die is coupled to the first semiconductor die by a die attach material. A third semiconductor die is coupled to the second semiconductor die by a die attach material. A second substrate having a plurality of electrically conductive patterns formed thereon is coupled to the third semiconductor die. A plurality of contacts is coupled to a bottom surface of the first substrate. A connector jack is coupled to the second substrate. A plurality of leads is coupled to the second semiconductor die by conductive wires. | 2009-02-19 |
20090045500 | Power semiconductor module with a connected substrate carrier and production method therefor - A power semiconductor module includes a housing, a substrate carrier with a circuit thereon and electrical connection elements extending therefrom. The carrier has a cutout between its inner surface (facing the interior of the module) and its outer surface. The cutout is smaller at the inner surface than at the outer surface. The housing has an extension that reaches into the cutout and may be deformed to form a riveted connection. The method comprises: forming a housing with at least one extension which extends towards the exterior of the module, wherein the extension projects through the cutout and beyond the outer surface of the carrier; and deforming the end of the extension so that it widens and forms a riveted connection and at the same time lies below the outer surface of the carrier. | 2009-02-19 |
20090045501 | STRUCTURE ON CHIP PACKAGE TO SUBSTANTIALLY MATCH STIFFNESS OF CHIP - Chip packages and a related method are disclosed that provide a structure on a side opposite a chip on a carrier of a chip package to substantially match a stiffness of the chip. In one embodiment, a chip package includes a chip coupled to a carrier; and a structure on a side opposite the chip on the carrier, the structure having a first stiffness to substantially match a second stiffness of the chip. | 2009-02-19 |
20090045502 | CHIP SCALE PACKAGE WITH THROUGH-VIAS THAT ARE SELECTIVELY ISOLATED OR CONNECTED TO THE SUBSTRATE - A semiconductor chip scale package formed with through-vias, which can be either isolated or electrically connected to a substrate, and a method of producing the semiconductor chip scale package with through-vias, which can be isolated or electrically connected to the substrate. | 2009-02-19 |
20090045503 | Multidirectional Semiconductor Device Package Thermal Enhancement Systems and Methods - The invention provides thermally-enhanced semiconductor device package systems and associated methods for reducing thermal resistance for improved heat egress. In one disclosed embodiment of the invention, a semiconductor device package system includes a packaged semiconductor device having operable contacts for external electrical coupling. The packaged device has an exposed surface, and a heat spreader is affixed to the exposed device surface. The heat spreader includes a portion extending in a configuration coplanar with the device contacts. In another example of a preferred embodiment of the invention, a semiconductor device package system includes an external heat sink affixed to a heat spreader, the heat spreader having a portion extending in a configuration coplanar with the device contacts. According to exemplary systems and methods of the invention package systems are provided with a heat spreader so configured that the junction-to-board thermal resistance and junction-to-case thermal resistance are both reduced. | 2009-02-19 |
20090045504 | SEMICONDUCTOR PACKAGE THROUGH-ELECTRODE SUITABLE FOR A STACKED SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor package including a through-electrode for stacked a semiconductor package and a semiconductor package having the same is disclosed. The semiconductor package through-electrode includes a first electrode having a recessed portion formed therein to pass through a semiconductor chip. A second electrode is disposed within the recess of the first electrode. The first electrode of the semiconductor package through-electrode includes a first metal having a first hardness, and a second electrode comprises a second metal having a second hardness lower than the first hardness. The through-electrode passes through the semiconductor chip body and may be formed with the first metal having the first hardness and/or a first melting point and the second metal having the second hardness and/or a second melting point which are lower than the first hardness and/or the first melting point. This through-electrode allows a plurality of semiconductor packages to be easily stacked. | 2009-02-19 |
20090045505 | Electronic device with package module - A package module is provided. The package module comprises a substrate having a surface comprising a die region. A die is disposed in the die region of the surface on the substrate. A flexible heat spreader conformally covers the surface of the substrate and the die. The invention also discloses an electronic device with the package module. | 2009-02-19 |