08th week of 2015 patent applcation highlights part 53 |
Patent application number | Title | Published |
20150052299 | APPARATUSES AND METHODS FOR PROVIDING DATA TO A CONFIGURABLE STORAGE AREA - Apparatuses and methods for providing data to a configurable storage area are disclosed herein. An example apparatus may include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command. | 2015-02-19 |
20150052300 | DATA STORAGE MANAGEMENT - A method of managing a plurality of storage devices. The method comprises at a first device connected to the plurality of storage devices via a switch, receiving an indication of a plurality of logical disks, each logical disk being provided by a respective one of the plurality of storage devices. Each logical disk comprises a plurality of logical blocks. Data representing a virtual disk is generated, the virtual disk comprising a plurality of virtual blocks, each virtual block being provided by a logical block. Access is provided to the virtual disk to a second device different to the first device. A first virtual block is selected, the first virtual block being provided by a first logical block, and a re-mapping operation is performed after which the first virtual block is provided by a second logical block different to the first logical block. | 2015-02-19 |
20150052301 | MIRRORING MULTIPLE WRITEABLE STORAGE ARRAYS - Systems, methods, and computer program products for mirroring dual writeable storage arrays are provided. Various embodiments provide configurations including two or more mirrored storage arrays that are each capable of being written to by different hosts. When commands to write data to corresponding mirrored data blocks within the respective storage arrays are received from different hosts at substantially the same time, write priority for writing data to the mirrored data blocks is given to one of the storage arrays based on a predetermined criterion or multiple predetermined criteria. | 2015-02-19 |
20150052302 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - The disclosed technology provides an electronic device and a fabrication method thereof, in which an etching margin in formation of a variable resistance element is secured and process difficulty is reduced. An electronic device according to an implementation includes a semiconductor memory, the semiconductor memory including: a variable resistance element including a stack of a first magnetic layer, a tunnel barrier layer and a second magnetic layer; a contact plug coupling a top of the variable resistance element and including a magnetism correcting layer; and a conductive line coupled to the variable resistance element through the contact plug including the magnetism correcting layer. | 2015-02-19 |
20150052303 | SYSTEMS AND METHODS FOR ACQUIRING DATA FOR LOADS AT DIFFERENT ACCESS TIMES FROM HIERARCHICAL SOURCES USING A LOAD QUEUE AS A TEMPORARY STORAGE BUFFER AND COMPLETING THE LOAD EARLY - A method for acquiring cache line data associated with a load from respective hierarchical cache data storage components. As a part of the method, a store queue is accessed for one or more portions of a cache line associated with a load, and, if the one or more portions of the cache line is held in the store queue, the one or more portions of the cache line is stored in a load queue location associated with the load. The load is completed if the one or more portions of the cache line stored in the load queue location includes all portions of the cache line associated with the load. | 2015-02-19 |
20150052304 | SYSTEMS AND METHODS FOR READ REQUEST BYPASSING A LAST LEVEL CACHE THAT INTERFACES WITH AN EXTERNAL FABRIC - Methods for read request bypassing a last level cache which interfaces with an external fabric are disclosed. A method includes identifying a read request for a read transaction, generating a phantom read transaction identifier for the read transaction and forwarding the read transaction with the phantom read transaction identifier beyond a last level cache before detection of a hit or miss with respect to the read transaction. The phantom read transaction identifier acts as a pointer to a real read transaction identifier. | 2015-02-19 |
20150052305 | ARITHMETIC PROCESSING DEVICE, ARITHMETIC PROCESSING METHOD AND ARITHMETIC PROCESSING SYSTEM - An arithmetic processing device includes: a cache memory configured to store data; and a circuitry configured to: execute access instructions including a first access instruction and a second access instruction; and request, in a case where a first access to the cache memory based on the first access instruction has been completed and the first access instruction is a serializing instruction, a re-execution of the second access instruction subsequent to the serializing instruction when a second access to the cache memory based on the second instruction has been completed. | 2015-02-19 |
20150052306 | PROCESSOR AND CONTROL METHOD OF PROCESSOR - Lock information indicating that an address is locked and a lock address are held for each thread, and in a case where the execution of a CAS instruction is requested, a primary cache controller which receives a request from an instruction controlling unit which requests processing according to an instruction in each thread executes a plurality of pieces of processing included in the CAS instruction when an access target address of the CAS instruction is different from the lock address of a thread whose lock information is held, and prohibits the execution of store processing of a thread whose lock information is not held, to a cache memory when the lock information of any thread out of the plural threads is held. | 2015-02-19 |
20150052307 | PROCESSOR AND CONTROL METHOD OF PROCESSOR - When a primary cache controller of a core unit arbitrates and issues a non-cache write request in a thread “0” (zero) and a non-cache read request in a thread 1 from an instruction controller, and when the non-cache requests being arbitration objects are in issuable states by obtaining a response for a preceding non-cache write request after an issuance of the preceding non-cache write request in the thread-0 (zero) which precedes to the non-cache write request in the thread-0 (zero) being the arbitration object, the non-cache read request in the thread-1 is given priority to be issued so that the non-cache read request whose priority is low is not continued to be waited. | 2015-02-19 |
20150052308 | PRIORITIZED CONFLICT HANDLING IN A SYSTEM - A controller has a cache to store data associated with an address that is subject to conflict resolution. A conflict resolution queue stores information relating to plural transactions, and logic reprioritizes the plural transactions in the conflict resolution queue to change a priority of a first type of transaction with respect to a priority of second type of transaction. | 2015-02-19 |
20150052309 | COMBINING ASSOCIATIVITY AND CUCKOO HASHING - Addition, search, and performance of other allied activities relating to keys are performed in a hardware hash table. Further, high performance and efficient design may be provided for a hash table applicable to CPU caches and cache coherence directories. Set-associative tables and cuckoo hashing are combined for construction of a directory table of a directory based cache coherence controller. A method may allow configuration of C cuckoo ways, where C is an integer greater than or equal to 2, wherein each cuckoo way C | 2015-02-19 |
20150052310 | CACHE DEVICE AND CONTROL METHOD THEREOF - A cache device may include a first cache including a first set and a plurality of ways corresponding to the first set, and a second cache including a second set and a plurality of ways corresponding to the second set. The second set is related with the first set depending on a vacancy of the ways of the first set. | 2015-02-19 |
20150052311 | MANAGEMENT OF TRANSACTIONAL MEMORY ACCESS REQUESTS BY A CACHE MEMORY - In a data processing system having a processor core and a shared memory system including a cache memory that supports the processor core, a transactional memory access request is issued by the processor core in response to execution of a memory access instruction in a memory transaction undergoing execution by the processor core. In response to receiving the transactional memory access request, dispatch logic of the cache memory evaluates the transactional memory access request for dispatch, where the evaluation includes determining whether the memory transaction has a failing transaction state. In response to determining the memory transaction has a failing transaction state, the dispatch logic refrains from dispatching the memory access request for service by the cache memory and refrains from updating at least replacement order information of the cache memory in response to the transactional memory access request. | 2015-02-19 |
20150052312 | PROTECTING THE FOOTPRINT OF MEMORY TRANSACTIONS FROM VICTIMIZATION - A processing unit includes a processor core and a cache memory. Entries in the cache memory are grouped in multiple congruence classes. The cache memory includes tracking logic that tracks a transaction footprint including cache line(s) accessed by transactional memory access request(s) of a memory transaction. The cache memory, responsive to receiving a memory access request that specifies a target cache line having a target address that maps to a congruence class, forms a working set of ways in the congruence class containing cache line(s) within the transaction footprint and updates a replacement order of the cache lines in the congruence class. Based on membership of the at least one cache line in the working set, the update promotes at least one cache line that is not the target cache line to a replacement order position in which the at least one cache line is less likely to be replaced. | 2015-02-19 |
20150052313 | PROTECTING THE FOOTPRINT OF MEMORY TRANSACTIONS FROM VICTIMIZATION - A processing unit includes a processor core and a cache memory. Entries in the cache memory are grouped in multiple congruence classes. The cache memory includes tracking logic that tracks a transaction footprint including cache line(s) accessed by transactional memory access request(s) of a memory transaction. The cache memory, responsive to receiving a memory access request that specifies a target cache line having a target address that maps to a congruence class, forms a working set of ways in the congruence class containing cache line(s) within the transaction footprint and updates a replacement order of the cache lines in the congruence class. Based on membership of the at least one cache line in the working set, the update promotes at least one cache line that is not the target cache line to a replacement order position in which the at least one cache line is less likely to be replaced. | 2015-02-19 |
20150052314 | CACHE MEMORY CONTROL PROGRAM, PROCESSOR INCORPORATING CACHE MEMORY, AND CACHE MEMORY CONTROL METHOD - A cache memory control procedure has: cache area allocating including allocating, in response to an acquisition request, and according to an effective cache usage degree that is based on a memory access frequency and a difference between a cache hit rate in a case where the dedicated cache area is allocated and a cache hit rate in a case where a shared cache area in the cache memory is allocated, the dedicated cache area for a higher effective cache usage degree and the shared cache area for a lower effective cache usage degree; and releasing the dedicated cache area which is allocated, in response to a release request which is issued during execution of a process by the processor and requests the release of the allocated dedicated cache area. | 2015-02-19 |
20150052315 | MANAGEMENT OF TRANSACTIONAL MEMORY ACCESS REQUESTS BY A CACHE MEMORY - In a data processing system having a processor core and a shared memory system including a cache memory that supports the processor core, a transactional memory access request is issued by the processor core in response to execution of a memory access instruction in a memory transaction undergoing execution by the processor core. In response to receiving the transactional memory access request, dispatch logic of the cache memory evaluates the transactional memory access request for dispatch, where the evaluation includes determining whether the memory transaction has a failing transaction state. In response to determining the memory transaction has a failing transaction state, the dispatch logic refrains from dispatching the memory access request for service by the cache memory and refrains from updating at least replacement order information of the cache memory in response to the transactional memory access request. | 2015-02-19 |
20150052316 | CENTRALIZED MEMORY ALLOCATION WITH WRITE POINTER DRIFT CORRECTION - A system for writing data includes a memory, at least one memory controller and control logic. The memory stores data units. The memory controller receives a write request associated with a data unit and stores the data unit in the memory. The memory controller also transmits a reply that includes an address where the data unit is stored. The control logic receives the reply and determines whether the address in the reply differs from an address included in replies associated with other memory controllers by a threshold amount. When this occurs, the control logic performs a corrective action to bring an address associated with the memory controller back within a defined range. | 2015-02-19 |
20150052317 | SYSTEMS, DEVICES, MEMORY CONTROLLERS, AND METHODS FOR MEMORY INITIALIZATION - Systems, devices, memory controllers, and methods for initializing memory are described. Initializing memory can include configuring memory devices in parallel. The memory devices can receive a shared enable signal. A unique volume address can be assigned to each of the memory devices. | 2015-02-19 |
20150052318 | MEMORY APPARATUSES, COMPUTER SYSTEMS AND METHODS FOR ORDERING MEMORY RESPONSES - Memory apparatuses that may be used for receiving commands and ordering memory responses are provided. One such memory apparatus includes response logic that is coupled to a plurality of memory units by a plurality of channels and may be configured to receiving a plurality of memory responses from the plurality of memory units. Ordering logic may be coupled to the response logic and be configured to cause the plurality of memory responses in the response logic to be provided in an order based, at least in part, on a system protocol. For example, the ordering logic may enforce bus protocol rules on the plurality of memory responses stored in the response logic to ensure that responses are provided from the memory apparatus in a correct order. | 2015-02-19 |
20150052319 | MEMORY MANAGEMENT METHODS AND SYSTEMS FOR PAGE-OUT MECHANISM - Memory management methods and systems for page-out mechanism are provided. A page-out mechanism is performed via an OS (Operating System) based on a parameter of the page-out mechanism, wherein the page-out mechanism moves data from a memory to a storage unit. A usage of a page-out partition in the storage unit is monitored. The parameter of the page-out mechanism is dynamically set according to the usage of the page-out partition, wherein when the usage is increased, the parameter of the page-out mechanism is decreased, and when the usage is decreased, the parameter of the page-out mechanism is increased. | 2015-02-19 |
20150052320 | REDUCING DATA BACKUP TIME DURING INCREMENTAL SNAPSHOTS - Machines, systems and methods for performing intermediate data backups, the method comprising monitoring data updates to one or more data blocks in at least a target data storage medium, wherein the target data storage medium is subject to an incremental data backup routine at prescheduled time intervals; in response to determining that said at least one or more data blocks is updated prior to a prescheduled time interval for the incremental data backup routine, performing one or more intermediate data backups to store data from the updated data blocks to at least one backup data storage medium; and in response to determining that said at least one or more data blocks is updated prior to the prescheduled time interval for the incremental data backup routine but after the last of the intermediate data backups, copying data on one or more updated data blocks after the last of the intermediate data backups to the backup data storage medium. | 2015-02-19 |
20150052321 | MINIMALLY DISRUPTIVE VIRTUAL MACHINE SNAPSHOTS - Aspects of the present invention provide a solution for creating a snapshot of a virtual server. In an embodiment, a first write storage is created in response to a snapshot request. For each write from the virtual server to primary storage that is the first write of that particular data block since the snapshot request, the data that resided in the data block previous to the write is copied from the primary storage to the first write storage. | 2015-02-19 |
20150052322 | SYSTEMS AND METHODS FOR MEMORY DEDUPLICATION BY ORIGIN HOST IN VIRTUAL MACHINE LIVE MIGRATION - Systems and methods for memory de-duplication in a virtual machine undergoing live migration. An example method may comprise: determining a first identifier identifying a first physical memory range, the first physical memory range mapped to a first virtual memory range in a virtual address space of a first virtual machine undergoing live migration from a origin host computer system to a destination host computer system; determining a second identifier identifying a second physical memory range, the second physical memory range mapped to a second virtual memory range in a virtual address space of a second virtual machine undergoing live migration from the origin host computer system to the destination host computer system; determining that the first identifier and the second identifier identify the same physical memory range; and notifying the destination host computer system that the first virtual memory range and the second virtual memory range have identical contents. | 2015-02-19 |
20150052323 | SYSTEMS AND METHODS FOR MEMORY DEDUPLICATION BY DESTINATION HOST IN VIRTUAL MACHINE LIVE MIGRATION - Systems and methods for memory de-duplication in a virtual machine undergoing live migration. An example method may comprise: receiving, by a hypervisor executing on a destination host computer system, a first virtual address and a corresponding physical memory range identifier, the physical memory range identifier identifying a first physical memory range on an origin host computer system, the first virtual address identifying a first virtual memory range mapped to the first physical memory range in a virtual address space of a first virtual machine undergoing live migration from the origin host computer system to the destination host computer system; identifying a second virtual address corresponding to the physical memory range identifier, the second virtual address identifying a second virtual memory range in a virtual address space of a second virtual machine undergoing live migration from the origin host computer system to the destination host computer system; identifying a destination physical address corresponding to the second virtual address, the destination physical address identifying a second physical memory range on the destination host computer system; and mapping, on the destination host computer system, the first virtual address to the destination physical address. | 2015-02-19 |
20150052324 | AUTOMATED MIGRATION TO A NEW COPY SERVICES TARGET STORAGE SYSTEM TO MANAGE MULTIPLE RELATIONSHIPS SIMULTANEOUSLY WHILE MAINTAINING DISASTER RECOVERY CONSISTENCY - A method according to one embodiment includes receiving instruction to change from an original target storage subsystem in a disaster recovery configuration-to a new target storage subsystem. Second copy services relationships are created between one or more new target volumes on the new target storage subsystem and one or more source volumes on a source storage subsystem using multi-target functionality. Existing first copy services relationships between the source storage subsystem and the original target storage subsystem are terminated after all of the second copy services relationships are full duplex. | 2015-02-19 |
20150052325 | DATA PROCESSING SYSTEMS - A data processing system includes a host processor and a graphics processing unit operable to process data under the control of an operating system executing on the host processor. The graphics processing unit can be switched between a normal mode of operation in which the it has read and write access to data that is stored in non-protected memory regions | 2015-02-19 |
20150052326 | USER-CONTROLLED PAGING - A request is received to load a first page into main memory with the main memory containing a plurality of page frames. It is determined that none of the plurality of page frames is an empty page frame. User input is referenced to determine a target memory resource consumer. A second page is selected which is loaded in a first page frame. The second page is associated with the target memory resource consumer. The second page is moved from the main memory to a secondary storage device. The first page is loaded into the first page frame. | 2015-02-19 |
20150052327 | DYNAMIC MEMORY RELOCATION - For dynamic memory relocation, a tracking module tracks accesses to a plurality of memory devices. Each of the plurality of memory devices is in communication with one memory controller of a plurality of memory controllers embedded in a computing device comprising a plurality of nodes. A migration module migrates first data from a first memory device in communication with a first memory controller to a second memory device in communication with a second memory controller. | 2015-02-19 |
20150052328 | USER-CONTROLLED PAGING - A request is received to load a first page into main memory with the main memory containing a plurality of page frames. It is determined that none of the plurality of page frames is an empty page frame. User input is referenced to determine a target memory resource consumer. A second page is selected which is loaded in a first page frame. The second page is associated with the target memory resource consumer. The second page is moved from the main memory to a secondary storage device. The first page is loaded into the first page frame. | 2015-02-19 |
20150052329 | MEMORY CONTROL DEVICE, HOST COMPUTER, INFORMATION PROCESSING SYSTEM AND METHOD OF CONTROLLING MEMORY CONTROL DEVICE - A memory control device includes an address translation information holding portion that holds a portion of entries that are selected from address translation information containing a plurality of entries that associate a logical address with a physical address of a memory device; an address translation information acquisition unit that, when the entry containing the logical address specified by a host computer is not held in the address translation information holding portion, acquires the entry that is not held from the host computer and causes the address translation information holding portion to hold the entry; an address translation unit that translates the specified logical address into the physical address on the basis of the entries that are held in the address translation information holding portion; and a data transfer unit that executes a data transfer process in which transfer data is transferred using the translated physical address. | 2015-02-19 |
20150052330 | VECTOR ARITHMETIC REDUCTION - In a particular embodiment, a method includes executing a vector instruction at a processor. The vector instruction includes a vector input that includes a plurality of elements. Executing the vector instruction includes providing a first element of the plurality of elements as a first output. Executing the vector instruction further includes performing an arithmetic operation on the first element and a second element of the plurality of elements to provide a second output. Executing the vector instruction further includes storing the first output and the second output in an output vector. | 2015-02-19 |
20150052331 | Efficient Directed Acyclic Graph Pattern Matching To Enable Code Partitioning and Execution On Heterogeneous Processor Cores - Methods, devices, and systems for automatically determining how an application program may be partitioned and offloaded for execution by a general purpose applications processor and an auxiliary processor (e.g., a DSP, GPU, etc.) within a mobile device. The mobile device may determine the portions of the application code that are best suited for execution on the auxiliary processor based on pattern-matching of directed acyclic graphs (DAGS). In particular, the mobile device may identify one or more patterns in the code, particularly in a data flow graph of the code, comparing each identified code pattern to predefined graph patterns known to have a certain benefit when executed on the auxiliary processor (e.g., a DSP). The mobile device may determine the costs and/or benefits of executing the potions of code on the auxiliary processor, and may offload portions that have low costs and/or high benefits related to the auxiliary processor. | 2015-02-19 |
20150052332 | MICROPROCESSOR INTEGRATED CONFIGURATION CONTROLLER FOR CONFIGURABLE MATH HARDWARE ACCELERATORS - A microprocessor circuit may include a software programmable microprocessor core and a data memory accessible via a data memory bus. The data memory may include sets of configuration data structured according to respective predetermined data structure specifications for configurable math hardware accelerators, and sets of input data for configurable math hardware accelerators, each configured to apply a predetermined signal processing function to the set of input data according to received configuration data. A configuration controller is coupled to the data memory via the data memory bus and to the configurable math hardware accelerators. The configuration controller may fetch the configuration data for each math hardware accelerator from the data memory and translate the configuration data. The configuration controller may transmit each set of configuration data to the corresponding configurable math hardware accelerator and write the configuration data to configuration registers of the math hardware accelerator. | 2015-02-19 |
20150052333 | Systems, Apparatuses, and Methods for Stride Pattern Gathering of Data Elements and Stride Pattern Scattering of Data Elements - Embodiments of systems, apparatuses, and methods for performing gather and scatter stride instruction in a computer processor are described. In some embodiments, the execution of a gather stride instruction causes a conditionally storage of strided data elements from memory into the destination register according to at least some of bit values of a writemask. | 2015-02-19 |
20150052334 | ARITHMETIC PROCESSING DEVICE AND CONTROL METHOD OF ARITHMETIC PROCESSING DEVICE - An arithmetic processing device includes: a first instruction execution unit configured to include plural staging latches and execute a first instruction by a pipeline operation requiring only a single clock for transition of data between first plural staging latches including a staging latch at a final stage from among the plural staging latches, and a multi-cycle operation requiring plural clocks for transition of data between second plural staging latches positioning at a previous stage side than the first plural staging latches from among the plural staging latches; a second instruction execution unit configured to execute a second instruction; and an instruction control unit configured to input the first instruction and the second instruction, issue the first instruction to the first instruction execution unit and issue the second instruction to the second instruction execution unit such that the execution of the first instruction and the second instruction are partly overlapped. | 2015-02-19 |
20150052335 | INTERPOLATION IMPLEMENTATION - Techniques are disclosed relating to floating-point operations in computer processors. In one embodiment, an apparatus includes a floating-point unit and circuitry configured to receive an initial value X for a floating-point operation. In this embodiment, X is between 0 and 1.0 inclusive. In this embodiment, the circuitry is configured to generate first and second floating-point values based on an exponent of X that sum to 1. In this embodiment, the floating-point unit is configured to perform an operation using the first and second floating-point values. The apparatus may reduce drift, in this embodiment, when a floating-point representation of X does not guarantee that the sum of X and (1−X) is 1. The apparatus may be configured to perform blending and/or interpolation operations using the first and second floating-point values. | 2015-02-19 |
20150052336 | SELECTIVELY CONTROLLING INSTRUCTION EXECUTION IN TRANSACTIONAL PROCESSING - Execution of instructions in a transactional environment is selectively controlled. A TRANSACTION BEGIN instruction initiates a transaction and includes controls that selectively indicate whether certain types of instructions are permitted to execute within the transaction. The controls include one or more of an allow access register modification control and an allow floating point operation control. | 2015-02-19 |
20150052337 | SELECTIVELY CONTROLLING INSTRUCTION EXECUTION IN TRANSACTIONAL PROCESSING - Execution of instructions in a transactional environment is selectively controlled. A TRANSACTION BEGIN instruction initiates a transaction and includes controls that selectively indicate whether certain types of instructions are permitted to execute within the transaction. The controls include one or more of an allow access register modification control and an allow floating point operation control. | 2015-02-19 |
20150052338 | ARITHMETIC PROCESSING DEVICE AND CONTROL METHOD OF ARITHMETIC PROCESSING DEVICE - An arithmetic processing device includes: first prediction units which output branch prediction information of a fetched conditional branch instruction based on past branch history information of conditional branch instructions; a second prediction unit which stores a branch taken consecutive number of times and a branch not-taken consecutive number of times to a pattern information storage unit, and outputs branch prediction information of a fetched conditional branch instruction based on the past branch taken consecutive number of times or branch not-taken consecutive number of times stored; selecting units which selectively output the branch prediction information output from the first prediction units or the second prediction unit; and a selector which outputs a next instruction address of the conditional branch instruction or a branch target address of the conditional branch instruction to an instruction fetch unit in accordance with the branch prediction information output by the selecting units. | 2015-02-19 |
20150052339 | PROCESSOR AND CONTROL METHOD OF PROCESSOR - When predicting that branch is established as a result of performing branch prediction of a branch instruction based on pieces of branch information on branch instructions included in entries read from branch histories stored in a storing unit which stores, in each way, the branch history including a first index being part of an instruction address and a second index being a value obtained by an arithmetic operation using part of the instruction address, a branch predicting unit outputs a predicted branch destination address, and when a prediction failure of the predicted branch destination address obtained is detected, a branch history updating unit sets updated information of the branch information to update the branch history, and when the prediction failure is detected and the updated information is set in the branch information, registers the branch information in the branch history stored in the storing unit, by using the second index. | 2015-02-19 |
20150052340 | TASK EXECUTION DETERMINISM IMPROVEMENT FOR AN EVENT-DRIVEN PROCESSOR - Embodiments of a method for operating an event-driven processor and an event-driven processor are described. In one embodiment, a method for operating an event-driven processor involves configuring a heartbeat timer of the event-driven processor and handling an event using the event-driven processor based on the heartbeat timer. Using a heartbeat timer built into the event-driven processor, the task execution determinism of the event-driven processor is improved and the power consumption of the event-driven processor is reduced. Other embodiments are also described. | 2015-02-19 |
20150052341 | INFORMATION PROCESSING APPARATUS ENABLING HIGH-SPEED START-UP, CONTROL METHOD THEREFOR, AND STORAGE MEDIUM STORING CONTROL PROGRAM THEREFOR - An information processing apparatus that can execute a start-up process properly, even when electric power is cut off without performing a normal power turn-OFF process. A first storage unit stores a program. A second storage unit continues holding information even when a power supply stops. A third storage unit stores information showing a power-OFF-timing state of the information processing apparatus. A control unit determines whether the information showing the power-OFF-timing state obtained from the third storage unit needs read-out of a program at a power ON timing of the information processing apparatus, performs a start-up process after reading and developing the program from the first storage unit to the second storage unit when the read-out of the program is needed, and performs the start-up process without reading and developing the program from the first storage unit to the second storage unit when the read-out of the program is not needed. | 2015-02-19 |
20150052342 | METHOD OF IDENTIFYING SECURITY AND ELECTRONIC DEVICE THEREOF - An apparatus and a method for identifying security of an electronic device are provided. The method includes identifying a security state of a system binary loaded to a memory of the electronic device based on booting of the electronic device in a second operating system of the electronic device, and sending security state information to a first operating system in the second operating system based on a request from the first operating system of the electronic device. | 2015-02-19 |
20150052343 | METHOD AND SYSTEM FOR PROVIDING HYBRID-SHUTDOWN AND FAST STARTUP PROCESSES - In an example, in a method for providing a shutdown process for a computer system including an operating system (OS), basic input/output system (BIOS) firmware may capture a request from the OS to hardware of the computer system to enter into a hibernate state. In addition, the BIOS firmware may determine whether a hybrid-shutdown process is in process and in response to a determination that the hybrid-shutdown process is in process, may turn off the computer system instead of entering the computer system into the hibernate state. | 2015-02-19 |
20150052344 | DATA PROCESSING APPARATUS, DATA PROCESSING METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM - Provided is a data processing apparatus including a reconfigurable circuit that has a dynamically-reconfigurable circuit configuration to execute data processing with the reconfigured circuit configuration, a loading processor that loads reconfiguration data to a reconfiguration memory based on set loading information, a reconfiguration processor that reconfigures the circuit configuration with the reconfiguration data loaded to the reconfiguration memory in response to a request from the reconfigurable circuit, and a controller that executes a process of setting the loading information with respect to the loading processor while inhibiting the reconfiguration by invalidating the request, and validates the request after terminating the setting process to permit the reconfiguration. | 2015-02-19 |
20150052345 | SELECTIVELY PERFORMING MAN IN THE MIDDLE DECRYPTION - A HTTP request addressed to a first resource on a second device outside the network is received from a first device within the network. The HTTP request is redirected to a third device within the network. A first encrypted connection is established between the first device and the third device, and a second encrypted connection between the third device and the second device. The third device retrieves the first resource from the second device. The first resource is modified to change pointers within the first resource to point to location in a domain associated with the third device within the network. The third device serves, to the first device, the second resource. | 2015-02-19 |
20150052346 | Privacy-Protective Data Transfer and Storage - A method is performed at a computer system having one or more processors and memory storing one or more programs executed by the one or more processors. The method includes receiving a first data transmission from a first client system, where the first data transmission including a first document, the first document having one or more portions that are marked as private; encrypting the marked portions of the first document using a key; and sending a second data transmission to a destination system, where the second data transmission includes a second document, the second document including the encrypted marked portions of the first document and a remainder of the first document that is not marked as private. The key is unavailable to the destination system. The second document is stored at the destination system. | 2015-02-19 |
20150052347 | FILE-BASED APPLICATION PROGRAMMING INTERFACE PROVIDING SELECTABLE SECURITY FEATURES - A data communication security system is disclosed that includes a network interface including a first security module implementing a first security architecture, and a second security module implementing a second security architecture different from the first security architecture. The network interface further includes a file-based application programming interface defining a plurality of attributes of the network interface and including at least one attribute associated with data security managed by one of the first and second security modules. The file-based application programming interface includes at least one attribute from among the plurality of attributes that is associated with selecting between the first or second security modules. | 2015-02-19 |
20150052348 | SESSION LAYER DATA SECURITY - A first application at a first device selects one of multiple encapsulation format types based on a cost or bandwidth associated with a network, or associated with a link of the network, connected between the first application at the first device and a second application at a second device. The first application receives, at the first application from Open Systems Interconnection (OSI) layers above an OSI session layer, payload data associated with a session, and generates one or more session layer encapsulated blocks of the payload data using the selected one of the multiple encapsulated format types. The first application encrypts the payload data, and other data of the one or more session layer encapsulated blocks, and passes the encrypted session layer encapsulated block to OSI layers below the session layer for sending to the second application at the second device. | 2015-02-19 |
20150052349 | Splicing into an active TLS session without a certificate or private key - An origin server selectively enables an intermediary (e.g., an edge server) to shunt into and out of an active TLS session that is on-going between a client and the origin server. The technique allows for selective pieces of a data stream to be delegated from an origin to the edge server for the transmission (by the edge server) of authentic cached content, but without the edge server having the ability to obtain control of the entire stream or to decrypt arbitrary data after that point. The technique enables an origin to authorize the edge server to inject cached data at certain points in a TLS session, as well as to mathematically and cryptographically revoke any further access to the stream until the origin deems appropriate. | 2015-02-19 |
20150052350 | SYSTEM AND METHOD FOR AUTHENTICATING A USER - A method for a user authentication implementing a first server connected to a public network, and a second server connected to the first server but not connected to the public network, this method comprising a step of enrolment comprising: receiving by the first server an reference identifier and of a reference password, and transmitting this information to the second server, loading a security parameter by the second server, and calculating a first cryptogram by a one-way function Hash on the reference identifier, the reference password, and the security parameter, encrypting at least the reference identifier and the password by using an asymmetrical encryption method, and storing the encrypted data by the second server, returning the first cryptogram to the first server and storing said cryptogram by the first server, and a verification step of an user comprising: receiving by the first server of the current identifier and of the current password, and transmission of said information to the second server, calculating a second cryptogram by the one-way function Hash on the current identifier, the current password, and the security parameter by the second server, returning the second cryptogram to the first server and verification that the first cryptogram is included in the database, if not, generating an error message. | 2015-02-19 |
20150052351 | Secure installation of encryption enabling software onto electronic devices - A process/method is provided, which authenticates electronic devices allowing the installation and utilization of encryption enabling software capable of facilitating a public key infrastructure in combination with electronic devices without need for such encryption enabling software capable of facilitating a public key infrastructure to be installed at the same time as manufacture of the electronic device. The disclosed process/method may then provide a system for monitoring various metrics and statuses of the electronic devices through the manufacturing chain, distribution chain and product lifecycle. The process/method can be utilized to create electronic devices secured with encryption enabling software capable of facilitating a public key infrastructure, free from the security risks inherent with the current method of installing encryption enabling software onto electronic devices, which will render such secured electronic devices suitable for tasks requiring such enhanced security or encryption. Moreover, electronic devices utilizing the disclosed process/method to install encryption enabling software capable of facilitating a public key infrastructure will be enabled to benefit from and facilitate public key infrastructure functionality, including, but not limited to, the renew encryption enabling software on a defined renewal interval. | 2015-02-19 |
20150052352 | CERTIFICATING VEHICLE PUBLIC KEY WITH VEHICLE ATTRIBUTES - A method for providing secure connection between vehicles over channels of a wireless communication network, according to which, a first unique pair of digitally signed public key and private key is provided to each vehicle, along with additional vehicle-related data including a visually static collection of attributes of the vehicle. A unique certificate number is generated for each vehicle and monolithic data consisting of the public key, the certificate number and the attributes is signed by a trusted certificate generating authority. Prior to wireless communication between a first vehicle and a second vehicle, a verification step is performed during which the first vehicle sends its unique certificate number to a second vehicle over a communication channel; the second vehicle verifies the authenticity of received unique certificate number of the first vehicle and attributes by a camera that captures attributes which are visible, using image processing means. If the attributes are verified successfully, the second vehicle sends its unique certificate number to the first vehicle over a communication channel, along with a secret session key, which is valid for the current session only. Then the first vehicle verifies the authenticity of received unique certificate number of the second vehicle and attributes by a camera that captures attributes of the second vehicle which are visible, using signal processing means and both vehicles are allowed to securely exchange message or data using the secret session key. | 2015-02-19 |
20150052353 | System and Method For Synchronizing An Encrypted File With A Remote Storage - A method and system for synchronizing an encrypted file with a remote storage is disclosed. According to one embodiment, a computer-implemented method comprises providing a user with a user application and an encryption key in a portable memory device. The user runs the user application to securely access to a storage on a cloud storage system. A file is encrypted with the encryption key stored in the portable memory device and synchronized with the cloud storage system. | 2015-02-19 |
20150052354 | DISTRIBUTED FRAGMENTS FILE SYSTEM - The present invention relates to a distributed storage scheme, the distributed storage scheme, every file is encrypted, interleaved and fragmented, and the various fragments are stored on different constituent physical file systems. | 2015-02-19 |
20150052355 | Method of Transmission of Encrypted Documents From An Email Application - The application discloses an improved method of transmitting encrypted emails by prompting the user to select at least one attachment for attaching with the email, prompting the user to select an encryption option from among several encryption options, causing an application to encrypt the selected attachment using the selected encryption option while retaining the original format of the attachments, attaching the encrypted attachment to the email, transmitting the email containing the encrypted attachment to at least one recipient address using the email application, and transmitting a second email containing at least one password to the recipient address using the email application. | 2015-02-19 |
20150052356 | INFORMATION PROCESSING APPARATUS AND METHOD - An information processing apparatus, including a plurality of information processing elements, includes a transmission unit, provided in a first information processing element newly connected to the information processing apparatus, that transmits identification information of the first information processing element to a second information processing element among the plurality of information processing elements; a first control unit, provided in the second information processing element, that assigns address information to identification information of the first information processing element, generates element information including address information corresponding to identification information of the first information processing element and each of already implemented information processing elements, and returns the element information to the first information processing element; and a second control unit, provided in the first information processing element, that performs communication with an already implemented information processing element by using address information included in the element information received from the second information processing element. | 2015-02-19 |
20150052357 | METHOD AND NETWORK NODE DEVICE FOR CONTROLLING THE RUN OF TECHNOLOGY SPECIFIC PUSH-BUTTON CONFIGURATION SESSIONS WITHIN A HETEROGENEOUS OR HOMOGENOUS WIRELESS NETWORK AND HETEROGENEOUS OR HOMOGENOUS WIRELESS NETWORK - A method and network node device control the run of technology specific Push-Button Configuration sessions within a heterogeneous or homogeneous wireless network as well as a heterogeneous or homogeneous wireless network detecting a session overlap within the network. The session is related to a configuration session (bootstrapping session, setup session) that establishes a security configuration for encrypted communication over a wireless link it is proposed an enhanced mechanism for controlling the run of technology specific Push Button Configuration sessions within a heterogeneous or homogeneous wireless network and a plurality of network node devices interconnected to each other via at least one interface and/or over multiple hops and authenticated or unauthenticated for the network by using a piece of information, e.g. a “Configuration Setup Session Identifier (CSSID),” for identifying a technology specific Push Button Configuration setup session. | 2015-02-19 |
20150052358 | KEY GENERATION AND BROADCASTING - Embodiments provide techniques generating and managing encryption keys within a computing infrastructure. Embodiments provide a key publisher that generates and maintains key pairs in a list at a configurable interval. In addition, the key publisher publishes the list to other components within the computing infrastructure. Embodiments also provide a key consumer that downloads the list of encrypted key pairs and maintains an active window of keys to can be accepted from client devices that communicate sensitive data to the computing infrastructure. If the key consumer receives a key from a client device that is outside of the active window yet that corresponds to a future key pair in the list, the key consumer advances the active window towards the future key pair. | 2015-02-19 |
20150052359 | METHOD FOR ASYNCHRONOUSLY PROVISIONING KEYS FROM ONE SECURE DEVICE TO ANOTHER - The present invention relates to a method to securely and asynchronously provisioning keys from one source secure device to a target secure device through a key provisioning server for which the keys to be provisioned through the method remain unknown. | 2015-02-19 |
20150052360 | METHOD AND SYSTEM FOR PROVIDING ENHANCED DATA ENCRYPTION PROTOCOLS IN A MOBILE SATELLITE COMMUNICATIONS SYSTEM - An approach for improved security protocols in a mobile satellite system is provided. A remote terminal performs a key establishment function, including determination of a first encryption key for encrypting data for transmission over the satellite communications channels, and determination of an authentication key for authenticating entities communicating over the communications channels. The remote terminal receives a security mode command including a key indicator, and determines a second encryption key for enhanced session data security over communications channels. The second encryption key is determined based on the key indicator and a key generation algorithm. The remote terminal further determines a key indicator response and transmits a security mode complete command including the key indicator response to a satellite base station subsystem (SBSS). The key indicator response is constructed for the SBSS to determine the second encryption key based on the key indicator response and a key generation algorithm. | 2015-02-19 |
20150052361 | METHOD FOR SETTING UP AN ENCRYPTED CONNECTION BETWEEN TWO COMMUNICATION APPLIANCES FOLLOWING PRIOR KEY INTERCHANGE VIA A SHORTHAUL CONNECTION - In order to set up an encrypted communication link between two mobile appliances, it is proposed that the identification data and keys that are required therefor be interchanged in a one-off identification step and that, as part of the setup of the actual communication link, an unencrypted connection first of all be set up for reciprocal identification and then a connection encrypted with the initial interchanged keys be set up. | 2015-02-19 |
20150052362 | COMPUTERIZED SYSTEM AND METHOD FOR DEPLOYMENT OF MANAGEMENT TUNNELS - Methods and systems for deploying management tunnels between managed and managing devices are provided. According to one embodiment, network devices, including a peer managed devices, a management device and a trusted peer managed device are deployed within a network. The network devices are pre-configured to form a web of trust by storing within each network device (i) a digital certificate signed by a manufacturer or a distributor and (ii) a unique identifier. The peer managed device establishes a management tunnel with the management device based on an address received from an external source. Prior to allowing the management device to use the management tunnel to perform management functionality, the peer managed device verifies credentials of the managed device by causing its unique identifier to be confirmed with reference to a pre-configured identifier of an authorized management device stored within the peer managed device. | 2015-02-19 |
20150052363 | SYSTEM AND METHOD FOR PROCESS RESOLUTION AND COMPOSITION IN ACTOR SYSTEMS - The various embodiments herein provide an actor oriented system and a method for providing communication between a plurality of processes in the actor system. The system uses actor model as the basis for a large scale process distribution. The system abstracts the plurality of processes and adopts a method of process composition and resolution. The method provides binding of different processes in the system to create a multi-functional distributed application. | 2015-02-19 |
20150052364 | Increasing Security in Inter-Chip Communication - An apparatus for increasing security in inter-chip communication includes a sending control module, a communication bus, and a receiving control module. The communication bus is coupled between the sending control module and the receiving control module. The sending control module operates to send data on the communication bus, disable the communication bus when threats are detected, or both. | 2015-02-19 |
20150052365 | Network Managed Antivirus Appliance - Data can be scanned using a network managed appliance. The network managed appliance may integrate commercial hardware elements connected through a basic or simplified operating system environment expressly developed for the appliance, thus being more malware resistant and less vulnerable to attacks from the scanned data or other sources. The network managed appliance may be a self-contained apparatus with an integrated chassis, designed and configured as “single-purpose” device. Such appliances may be connected to an appliance management network including central management servers in communication with appliances in remote locations. The central management servers may ensure that scanning software and the definitions lists for each of the appliances are current and match an enterprise-approved configuration. | 2015-02-19 |
20150052366 | EFFICIENT DATA REHYDRATION - A system for an efficient data rehydration comprises a server, one or more reader device managers, a writer device manager, and a verifier. The server is for receiving a restore list comprising a plurality of storage locations and lengths for performing a data rehydration. The one or more reader device managers is for reading a data set indicated by the restore list by reading the plurality of storage locations for the lengths from one or more storage nodes. The plurality of storage locations and lengths indicate chunks from a client system stored as part of a full or as an incremental backup session on a storage device attached to a storage node. The writer device manager is for transferring the data set to a save node. A verifier is for verifying transfer of the data set. | 2015-02-19 |
20150052367 | APPARATUS AND METHOD FOR PROVIDING HARDWARE SECURITY - A technique to provide a hardware security module that provides a secure boundary for retention of a secure key within the secure boundary and prevention of unauthorized accesses from external sources outside of the secure boundary to obtain the secure key. The hardware security module includes a security processor to unwrap and authenticate a secure key within the secure boundary to decrypt or encrypt data and to provide data through a single interface that communicates with external sources, so that all data transfers between the secure boundary, formed by the hardware security module, and external sources are transferred only through the interface. The hardware security module ensures no unwrapped key leaves the secure boundary established by the hardware security module. | 2015-02-19 |
20150052368 | DIFFERENTIAL POWER ANALYSIS - RESISTANT CRYPTOGRAPHIC PROCESSING - Information leaked from smart cards and other tamper resistant cryptographic devices can be statistically analyzed to determine keys or other secret data. A data collection and analysis system is configured with an analog-to-digital converter connected to measure the device's consumption of electrical power, or some other property of the target device, that varies during the device's processing. As the target device performs cryptographic operations, data from the A/D converter are recorded for each cryptographic operation. The stored data are then processed using statistical analysis, yielding the entire key, or partial information about the key that can be used to accelerate a brute force search or other attack. | 2015-02-19 |
20150052369 | Local Keying for Self-Encrypting Drives (SED) - A method and system self encrypts a disk storage device. Given a plurality of data storage devices, the system establishes an encryption key for the plurality of data storage devices. The system locally stores the encryption key in a piecewise manner throughout the plurality of data storage devices such that the encryption key is rendered undeterminable with less than a threshold subset of the plurality of data storage devices. This results in the plurality of data storage devices being self encrypting. Upon an increase or decrease in the plurality, the system resplits the encryption key and locally stores the resulting pieces throughout the changed (increased/decreased) plurality of data storage devices. This renders the encryption key undeterminable with less than a new or revised threshold each time the plurality is changed. | 2015-02-19 |
20150052370 | Cascaded Data Encryption Dependent on Attributes of Physical Memory - Apparatus and method for providing data security through cascaded encryption. In accordance with various embodiments, input data are encrypted in relation to a first auxiliary data value to provide first level ciphertext. The first level ciphertext are encrypted using a second auxiliary data value associated with a selected physical location in a memory to produce second level ciphertext, which are thereafter stored to the selected physical location. In some embodiments, migration of the stored data to a new target location comprises partial decryption and re-encryption of the data using a third auxiliary data value associated with a new target physical location to produce third level ciphertext, and the storage of the third level ciphertext to the new target physical location. | 2015-02-19 |
20150052371 | MULTI-VENDOR POWER DISTRIBUTION UNIT SUPPORT IN RACK MANAGEMENT SOFTWARE - A PDU management system for automatically configure, manage and monitor managed power distribution units (PDUs) includes: (a) a user interface module configured to allow an operator to enter management information of the managed PDUs, (b) a database configured to store management information of the managed PDUs, (c) a power management communication interface configured to facilitate the communication between the PDU management system and the managed PDUs through a communication link, (d) a PDU power management module configured to construct, manage, and monitor the managed PDUs, (e) a PDU discovery module configured to discover all managed PDUs according to the information entered by the operator through the user interface module, (f) a PDU loader to load the management information of the managed PDUs to the database, the PDU discovery module and the PDU power management module. | 2015-02-19 |
20150052372 | COMPUTING SYSTEM WITH RESOURCE MANAGEMENT MECHANISM AND METHOD OF OPERATION THEREOF - A computing system includes: a storage interface configured to access an application code including a target code; a control unit, coupled to the storage interface, configured to: identify a consumption model corresponding to the target code, calculate a consumption estimate for the target code based on the consumption model, and generate a code-power analysis output based on the consumption estimate. | 2015-02-19 |
20150052373 | Keep Alive Management - Keep alive management techniques are described. In one or more implementations, a keep alive interval is calculated by an operating system of the computing device. The keep alive interval is used to maintain one or more notification channels between one or more applications of the computing device and a network. | 2015-02-19 |
20150052374 | DATA STORAGE DEVICE AND DATA PROCESSING SYSTEM INCLUDING THE SAME - A data processing system includes a host device; and a data storage device including an interface unit which is configured to interface with the host device, and configured to store data provided from the host device or provide data to the host device, in response to a request from the host device, wherein the data storage device is configured to interrupt power supply to the interface unit while the host device operates in a power saving mode. | 2015-02-19 |
20150052375 | INFORMATION PROCESSING METHOD AND ELECTRONIC DEVICE - The present invention discloses information processing methods, apparatuses and electronic devices. The method comprises: determining sensor units that will normally operate in the low power consumption state based on the i-th usage mode; generating, in response to obtaining an input operation for generating a wake-up instruction via the sensor units, the wake-up instruction; and switching the electronic device from the low power consumption state to the normal operation state in response to the wake-up instruction. With the present invention, sensor units that will normally operate in the low power consumption state are determined based on the i-th usage mode of the electronic device. A wake-up instruction is generated in response to obtaining an input operation via the sensor units. The electronic device is switched from the low power consumption state to the normal operation state in response to the wake-up instruction. The present invention solves the problem that it is difficult to operate an power-on/off button of an electronic device in complicated scenarios and achieves the effect of determining, based on the usage mode of the electronic device, a switching trigger scheme most suitable for the usage mode. | 2015-02-19 |
20150052376 | SYSTEM AND METHOD FOR CONSERVING POWER IN A MEDICAL DEVICE - A system and method for conservation of battery power in a portable medical device is provided. In one example, a processor arrangement that includes a plurality of processors is implemented. At least one of these processors is configured to execute the critical functions of the medical device, while one or more other processors assume a reduced service level, thereby drawing significantly less power. According to this arrangement, the medical device conserves energy by drawing the additional electrical power needed to activate the additional processing power only when needed. | 2015-02-19 |
20150052377 | Method And Apparatus For A Zero Voltage Processor - Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory. | 2015-02-19 |
20150052378 | CONNECTING INTERFACE UNIT AND MEMORY STORAGE DEVICE - A connecting interface unit and a memory storage device without a crystal oscillator are provided and include a frequency detector, a phase detector, an oscillator, a sampling circuit and a transmitter circuit. The frequency detector and the phase detector respectively detect frequency difference and phase difference between an input signal from a host system and a reference signal to generate a frequency signal and a phase signal. The frequency signal and the phase signal that have passed through a filter are transmitted to the oscillator to generate the reference signal for generating a clock signal. The sampling circuit generates an input data signal according to the reference signal. The transmitter circuit modulates an output data signal according to the clock signal to generate and transmit an output signal to the host system. Accordingly, the connecting interface unit conforms to the specification of a transmission stand. | 2015-02-19 |
20150052379 | SPREAD SPECTRUM CLOCK GENERATION CIRCUIT, CLOCK TRANSFER CIRCUIT, INTEGRATED CIRCUIT, AND IMAGE READING APPARATUS - A spread spectrum clock generation circuit includes a generation unit configured to generate and output a spread spectrum clock based on an input reference clock, a monitoring unit configured to monitor a difference between the number of pulses of a reference clock input to the generation unit after a reference time and the number of pulses of a spread spectrum clock output from the generation unit after the reference time, and a control unit configured to control a frequency of a spread spectrum clock to be generated by the generation unit so as to make the difference fall within a predetermined range. | 2015-02-19 |
20150052380 | METASTABILITY PREDICTION AND AVOIDANCE IN MEMORY ARBITRATION CIRCUITRY - An integrated circuit with hazard prediction and prevention circuitry is provided. The hazard prediction circuitry may predict a future hazard condition between two periodic signals, and the hazard prevention circuitry may selectively delay at least one of the two periodic signals to avoid the predicted hazard condition. Single-port memory cells may provide multiport memory functionality using an arbitration circuit that includes the hazard prediction and prevention circuitry and receives memory access requests from at least two request generators. The arbitration circuit may operate in synchronous mode and perform port selection based on a predetermined logic table. The arbitration circuit may also operate in asynchronous mode and execute a memory access request as soon as it is received by the arbitration circuit. Metastability caused by receiving memory access requests at the same time from at least two request generators may be avoided with the hazard prediction and prevention circuitry. | 2015-02-19 |
20150052381 | ELECTRONIC DEVICE AND METHOD FOR DETECTING FIRMWARE OF BMC - In a method of detecting firmware using a first electronic device, the first electronic device comprises a first baseboard management controller (BMC). The first electronic device receives a first message of requiring the first electronic device from a host computer, to detect whether firmware of a second BMC of a second electronic device runs in a normal state. The electronic device sends a second message of requiring the second BMC to obtain whether firmware of the second BMC runs in the normal state. Once the second BMC dose not response to the second message in a first predetermined time period, the electronic device recovers the firmware of the second BMC using firmware of the first BMC. | 2015-02-19 |
20150052382 | FAILOVER METHODS AND SYSTEMS FOR A VIRTUAL MACHINE ENVIRONMENT - A storage provider executing a plurality of Web servers is provided for receiving a request from a management console managing a plurality of virtual machines. The management console uses a same address to send the request, regardless of which Web server is selected to process the request. The selected Web server re-sends the request to a second storage provider node instance, when a first storage provider node instance fails to process the request, where the first and the second storage provide node instances are executed by the storage provider as virtual machines for providing failover in processing requests. | 2015-02-19 |
20150052383 | MANAGING DATABASE NODES - A method for managing database nodes includes determining that a data segment is on a failed node. The data segment is referenced by an operation of a query plan. The method includes selecting a victim node based on a segmentation ring, a buddy node for the data segment, a plurality of remaining operational nodes, and a predetermined selection parameter. The method includes generating a query plan such that the victim node performs double duty for operations accessing the data segment from a buddy projection on the victim node, and operations accessing a data segment for a primary projection of the victim node. | 2015-02-19 |
20150052384 | INFORMATION PROCESSING SYSTEM, CONTROL METHOD OF INFORMATION PROCESSING SYSTEM, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM - The information processing system includes a first management device, a second management device coupled to the first management device, and a first information processing device coupled to the second management device, wherein the second management device receives, from the first information processing device, a notification indicating that an operation state of the first information processing device is changed from a first state to a second state, and the second management device transmits the notification to the first management device after a first time period is collapsed after receiving the notification, the first time period being defined based on the second state. | 2015-02-19 |
20150052385 | IMPLEMENTING ENHANCED DATA CACHING AND TAKEOVER OF NON-OWNED STORAGE DEVICES IN DUAL STORAGE DEVICE CONTROLLER CONFIGURATION WITH DATA IN WRITE CACHE - A method, system and computer program product are provided for implementing enhanced data caching and takeover of non-owned storage devices in a computer system. Each of a first controller and a second controller has a cache memory. During normal run-time, each storage device controller validates cached write data after it is written to its cache memory by reading the write data from its cache memory. If any error is detected on the read, then unit check failed storage device controller, which results in a reset of the failed storage device controller. When a storage device controller detects its dual partner controller fails, the surviving storage device controller queues host read/write operations for its storage devices already owned, and tests a cache mirrored copy from its cache memory of the failed first storage device controller before takeover of the failed controller's storage devices. | 2015-02-19 |
20150052386 | TECHNIQUE FOR REPAIRING MEMORY MODULES IN DIFFERENT POWER REGIONS - A reshift unit within a computer system is configured to store repair information associated with random-access memory (RAM) modules that reside in different power regions. When one or more RAM modules in a given power region need to be repaired, the reshift unit identifies a portion of the repair information that is relevant to those RAM modules. The reshift unit then transmits that portion to the RAM modules, thereby repairing those RAM modules. Accordingly, RAM modules in a given power region can be repaired independently of RAM modules in other power regions. Advantageously, RAM modules can be repaired between cold boots without implementing the slow repair procedure performed by the fuse block during cold boot. | 2015-02-19 |
20150052387 | SYSTEMS AND METHODS UTILIZING A FLEXIBLE READ REFERENCE FOR A DYNAMIC READ WINDOW - A memory system having a flexible read reference is disclosed. The system includes a memory partition, a failcount component, and a controller. The memory partition includes a plurality of memory cells. The failcount component is configured to generate failcounts in response to read operations of the memory partition. The controller is configured to calibrate a reference value for the memory partition by utilizing the failcounts. | 2015-02-19 |
20150052388 | ENCRYPTING DATA FOR STORAGE IN A DISPERSED STORAGE NETWORK - A method begins by a dispersed storage (DS) processing module encrypting a plurality of data segments of the data using a plurality of encryption keys to produce a plurality of encrypted data segments and generating a plurality of deterministic values from the plurality of encrypted data segments. The method continues with the DS processing module establishing a data intermingling pattern and generating a plurality of masked keys by selecting one or more of the plurality of deterministic values in accordance with the data intermingling pattern and performing a masking function on the plurality of encryption keys and the selected one or more of the plurality of deterministic values. The method continues with the DS processing module appending the plurality of masked keys to the plurality of encrypted data segments to produce a plurality of secure data packages and outputting the plurality of secure data packages. | 2015-02-19 |
20150052389 | MANAGEABILITY REDUNDANCY FOR MICRO SERVER AND CLUSTERED SYSTEM-ON-A-CHIP DEPLOYMENTS - Technologies for providing manageability redundancy for micro server and clustered System-on-a-Chip (SoC) deployments are presented. A configurable multi-processor apparatus may include multiple integrated circuit (IC) blocks where each IC block includes a task block to perform one or more assignable task functions and a management block to perform management functions with respect to the corresponding IC block. Each task block and each management block may include one or more instruction processors and corresponding memory. Each IC block may be controllable to perform a function of one or more other IC blocks. The IC blocks may communicate with each other via a management communication infrastructure that may include a communication path from each of the management blocks to each of the other management blocks. Via the management communication infrastructure, the management blocks may bridge communication paths between pairs of management blocks. | 2015-02-19 |
20150052390 | Apparatus and Method for Microprocessor File System Protection - A system for providing protection to a processor system from the problems associated with power failures in the middle of processor operations is described. On detection of a power failure in the main power source, the processor power is maintained by means of a short-term secondary power source. Either immediately or after a momentary pause to override glitches, if power remains off the processor is notified that power will soon be removed and that an orderly shutdown is to take place. Once the protected system has completed its orderly shutdown, or after a length of time indicating that the orderly shutdown is improbable, power is removed from the system for a defined period and the system removes power from the protected processor system for at least a defined period of time, providing an assured hard restart. When external power is restored a normal running state is resumed after any power up sequencing. The orderly shutdown and hard reset can take place by command from the protected processor or system. A state machine is used to sequence the states in this process and control the transitions between states. | 2015-02-19 |
20150052391 | AUTOMATED MONITORING OF SERVER CONTROL AUTOMATION COMPONENTS - Systems and methods for automated monitoring of automated server control components are provided. Embodiments may include transmitting a request for state information associated with a component of the automated server control system. At least one of a reception of the state information for the component and a threshold time period without reception of the state information for the component may be detected. Some embodiments may include determining if the received state information for the component comprises an error condition. In some instances, an alert may be output based on at least one of detecting the threshold time period without reception of the state information for the component and determining that the received state information comprises an error condition. | 2015-02-19 |
20150052392 | Disconnected Operation for Systems Utilizing Cloud Storage - While connected to cloud storage, a computing device writes data and metadata to the cloud storage, indicates success of the write to an application of the computing device, and, after indicating success to the application, writes the data and metadata to local storage of the computing device. The data and metadata may be written to different areas of the local storage. The computing device may also determine that it has recovered from a crash or has connected to the cloud storage after operating disconnected and reconcile the local storage with the cloud storage. The reconciliation may be based at least on a comparison of the metadata stored in the area of the local storage with metadata received from the cloud storage. The cloud storage may store each item of data contiguously with its metadata as an expanded block. | 2015-02-19 |
20150052393 | FAST DATA BACK-UP AND RESTORE BETWEEN VOLATILE AND FLASH MEMORY - Back-up of data to flash memory. Data to back up is written into stripes, which are sets of pages across flash memory backup devices having the same block and page address. First metadata is embedded in each stripe indicating any blocks of the flash memory known to be bad. In response to encountering a new error in a block of flash memory during writing data to back up to a stripe, re-writing the stripe starting at the next available stripe excluding pages on the block of flash memory having the new error, writing subsequent stripes excluding pages on the block of flash memory having the new error, and embedding second metadata in the re-written and subsequent stripes indicating the location of the block having the new error. Responsive to finding no bad blocks indicated in the first metadata, initiating a write to two or more stripes simultaneously. | 2015-02-19 |
20150052394 | METHOD OF OPERATING NONVOLATILE MEMORY DEVICE COMPRISING RESISTANCE MATERIAL - A method of operating a nonvolatile memory device comprises applying a read current with a first level to a nonvolatile memory cell comprising a variable resistance material, determining read data based on the applied read current, checking a syndrome corresponding to the read data to determine whether the read data is pass or fail, changing the read current from the first level to a second level, which is different from the first level, according to the determination of whether the read data is pass or fail, and performing a read-retry operation comprising applying the read current of the second level to the nonvolatile memory cell. | 2015-02-19 |
20150052395 | ANNOTATED ATOMIC WRITE - Techniques are disclosed relating to writing data atomically to one or more recording media. In one embodiment, a request is received to perform an atomic write for a set of data. Responsive to the request, the set of data is written across a plurality of storage units including storing metadata at a dedicated location within at least one of the plurality of storage units. The metadata is usable to determine whether the writing completed successfully. In some embodiments, the request is received from an application that has been assigned an address range of the plurality of storage units. In such an embodiment, the address range is accessible to the application for storing data, and the dedicated location resides outside of the address range. In one embodiment, the metadata specifies an address range where the set of data was written and a sequence number. | 2015-02-19 |
20150052396 | STATE INFORMATION RECORDING APPARATUS, NON-TRANSITORY COMPUTER READABLE MEDIUM, AND STATE INFORMATION RECORDING METHOD - A state information recording apparatus includes a copying section that copies a recording program from a first memory to a second memory, a detector that detects occurrence of a fault in the state information recording apparatus, a determining section that determines whether or not the recording program copied to the second memory is destroyed, in response to detection of occurrence of the fault, a recording section that records the state information to the non-volatile memory, by executing the recording program in the second memory if it is determined that the recording program copied to the second memory is not destroyed, or by executing the recording program stored in the first memory if it is determined that the recoding program copied to the second memory is destroyed, and a reboot section that reboots the state information recording apparatus after the state information is recorded to the non-volatile memory. | 2015-02-19 |
20150052397 | MEMORY SYSTEM AND CONTROLLING METHOD OF MEMORY SYSTEM - According to one embodiment, when being notified of an interruption of an external electric power supply, a second processor performs a saving operation for storing management information and data stored in a first volatile memory to a first non-volatile memory, and records a progress log, indicating a progress of the saving operation, into a second volatile memory. The first processor periodically checks whether the progress log is recorded in the second volatile memory or not, and when the progress log is recorded in the second volatile memory, the first processor stores the progress log into the second non-volatile memory. | 2015-02-19 |
20150052398 | Out-of-Band Signaling Support Over Standard Optical SFP - An out-of-band to optical conversion component is provided that uses a transmit disable signal and a receive loss of signal (LOS) signal built into optical small form-factor pluggable transceiver and cable to pass the out-of-band protocol between serial attached. SCSI enclosures. The transmit disable signal, when asserted, turns off the optical output, while the receive LOS signal detects the loss of signal. The out-of-band to optical conversion component sits in line on the serial attached SCSI data traffic and strips off the out-of-band signals from the serial attached SCSI expander so that only data flows over the optical cable. The out-of-band to optical conversion component sends the out-of-band signals to the other enclosure using the transmit disable pin on the small form-factor pluggable transceiver and cable. The other enclosure receives the message on the receive LOS signal and transmit it back onto the serial attached SCSI receive data pair. | 2015-02-19 |