08th week of 2020 patent applcation highlights part 49 |
Patent application number | Title | Published |
20200058751 | Semiconductor Device and Method of Formation - A semiconductor device and method of formation are provided. The semiconductor device includes a channel surrounding a dielectric tube and a gate surrounding the channel. The dielectric tube comprises a high dielectric constant material that has or conducts few to no carriers, such as electrons or holes. The presence of the dielectric tube confines carriers to the channel, which is in close proximity to the gate. The proximity of the channel, and the carriers therein, to the gate affords greater control to the gate over the carriers, thus allowing a length of the channel to be decreased while experiencing little to no short channel effects, such as current leakage through the channel. | 2020-02-20 |
20200058752 | Trenched Bottom Electrode and Liftoff based Molecular Devices - A system and method for fabricating at least one of, a molecular device element and a TBELMD including depositing a first electrode material on an insulating substrate or layer, performing a photolithography process in the first electrode material, creating a trench component in the first electrode material with the photolithography process, determining a section of the electrode material to remove based on at least one of, a molecular device element and a TBELMD to be produced, removing the section of said first electrode material, oxidizing a portion of the first electrode material, creating a first insulator part from the oxidized portion of the first electrode material, in which the oxidized portion of the first electrode material includes at least a first electrode metal surface, depositing a second electrode material, and bridging the first and second electrode material. | 2020-02-20 |
20200058753 | VERTICAL TRANSPORT FETS HAVING A GRADIENT THRESHOLD VOLTAGE - Vertical transport field effect transistors (FETs) having improved device performance are provided. Notably, vertical transport FETs having a gradient threshold voltage are provided. The gradient threshold voltage is provided by introducing a threshold voltage modifying dopant into a physically exposed portion of a metal gate layer composed of an n-type workfunction TiN. The threshold voltage modifying dopant changes the threshold voltage of the original metal gate layer. | 2020-02-20 |
20200058754 | GATE SPACER AND METHODS OF FORMING - Methods and structures for forming devices, such as transistors, are discussed. A method embodiment includes forming a gate spacer along a sidewall of a gate stack on a substrate; passivating at least a portion of an exterior surface of the gate spacer; and epitaxially growing a material in the substrate proximate the gate spacer while the at least the portion of the exterior surface of the gate spacer remains passivated. The passivating can include using at least one of a thermal treatment, a plasma treatment, or a thermal treatment. | 2020-02-20 |
20200058755 | Semiconductor Structure and Manufacturing Method Thereof - A method for manufacturing a semiconductor structure includes forming a first dielectric layer on a gate structure and a source drain structure. A recess is formed at least partially in the first dielectric layer. A protection layer is formed at least on a sidewall of the recess. The recess is deepened to expose the source drain structure. A bottom conductor is formed in the recess and is electrically connected to the source drain structure. The protection layer is removed to form a gap between the bottom conductor and the sidewall of the recess. | 2020-02-20 |
20200058756 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME - A method for forming a semiconductor device structure is provided. The method includes forming a metal gate electrode structure and an insulating layer over the semiconductor substrate. The insulating layer surrounds the metal gate electrode structure. The method includes nitrifying a first top portion of the metal gate electrode structure to form a metal nitride layer over the metal gate electrode structure. | 2020-02-20 |
20200058757 | CONTACT STRUCTURES - The present disclosure generally relates to semiconductor structures and, more particularly, to contact structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions and sidewall spacers; contacts connecting to at least one gate structure of the plurality of gate structures; and at least one metallization feature connecting to the source and drain regions and extending over the sidewall spacers. | 2020-02-20 |
20200058758 | FORMING THERMALLY STABLE SALICIDE FOR SALICIDE FIRST CONTACTS - A method for forming a salicide includes forming, on at least one semiconductor fin, at least one source/drain (S/D) region including a (111) facet and having a cross-sectional quadrilateral shape, forming a conductive material on the (111) facet, annealing the conductive material to form a silicide on the (111) facet, and forming at least one contact to the silicide. | 2020-02-20 |
20200058759 | INVERSE T-SHAPED CONTACT STRUCTURES HAVING AIR GAP SPACERS - A method of fabricating air gap spacers is provided. The method includes forming gate structures to extend upwardly from a substrate with source or drain (S/D) regions disposed between the gate structures and with contact trenches defined above the S/D regions and between the gate structures. The method further includes disposing contacts in the contact trenches. The method also includes configuring the contacts to define open-ended air gap spacer trenches with the gate structures. In addition, the method includes forming a cap over the open-ended air gap spacer trenches to define the open-ended air gap spacer trenches as air gap spacers. The gate structures have an initial structure prior to and following the disposing and the configuring of the contacts and prior to and following the forming of the cap. | 2020-02-20 |
20200058760 | SiC Device with Buried Doped Region - A SiC device with a doped buried region is provided. The doped buried region may be formed by: forming a first trench which extends into a first side of a SiC epitaxial layer of a first conductivity type, the first trench terminating at a first depth in the SiC epitaxial layer; at least partly filling the first trench with an epitaxial material of a second conductivity type opposite the first conductivity type; forming a second trench which extends into the first side of the SiC epitaxial layer so that the second trench overlaps the first trench, the second trench terminates at a second depth in the SiC epitaxial layer which is less than the first depth, and the epitaxial material in the first trench laterally extends below a bottom of the second trench; and forming a gate electrode in the second trench and electrically insulated from the SiC epitaxial layer. | 2020-02-20 |
20200058761 | SEMICONDUCTOR DEVICE HAVING FIN-END STRESS-INDUCING FEATURES - Semiconductor devices having fin-end stress-inducing features, and methods of fabricating semiconductor devices having fin-end stress-inducing features, are described. In an example, a semiconductor structure includes a semiconductor fin protruding through a trench isolation region above a substrate. The semiconductor fin has a top surface, a first end, a second end, and a pair of sidewalls between the first end and the second end. A gate electrode is over a region of the top surface and laterally adjacent to a region of the pair of sidewalls of the semiconductor fin. The gate electrode is between the first end and the second end of the semiconductor fin. A first dielectric plug is at the first end of the semiconductor fin. A second dielectric plug is at the second end of the semiconductor fin. | 2020-02-20 |
20200058762 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device, a layout is prepared. The layout includes active region patterns, each of the active region patterns corresponding to one or two fin structures, first fin cut patterns and second fin cut patterns. At least one pattern selected from the group consisting of the first fin cut patterns and the second fin cut patterns has a non-rectangular shape. The layout is modified by adding one or more dummy active region patterns and by changing the at least one pattern to be a rectangular pattern. Base fin structures are formed according to a modified layout including the active region patterns and the dummy active region patterns. Part of the base fin structures is removed according to one of a modified layout of the first fin cut patterns and a modified layout of the second fin cut patterns. | 2020-02-20 |
20200058763 | SEMICONDUCTOR DEVICE WITH FIN END SPACER DUMMY GATE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride. | 2020-02-20 |
20200058764 | METAL GATE STRUCTURE TO REDUCE TRANSISTOR GATE RESISTANCE - A method for manufacturing a semiconductor device includes forming a channel layer on a semiconductor substrate and forming at least two spacers on the channel layer. A first portion of a gate metal layer is formed between the spacers, and a dielectric layer is conformally deposited on the spacers and the first portion of the gate metal layer. In the method, part of the dielectric layer is directionally removed from surfaces which are parallel to an upper surface of the substrate. A second portion of the gate metal layer is formed between remaining portions of the dielectric layer and on the first portion of the gate metal layer, and a cap layer is deposited on the second portion of the gate metal layer. A lateral width the second portion of the gate metal layer is less than a lateral width of the first portion of the gate metal layer. | 2020-02-20 |
20200058765 | Method of Forming MOSFET Structure - Devices are described herein that include an epitaxial layer, a cap layer above the epitaxial layer, a gate layer adjacent to the epitaxial layer on which an etching process is performed, a trench above the cap layer, and a source/drain portion includes the epitaxial layer. | 2020-02-20 |
20200058766 | GATE STACK RELIABILITY IN VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS - A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least one semiconductor fin. A first source/drain contacts the semiconductor fin. An interfacial layer contacts sidewalls of the semiconductor fin. An insulating layer contacts the interfacial layer. One or more conductive gate layers encapsulate the interfacial and insulating layers. A second source/drain is formed above the first source/drain. The method comprises forming at least one semiconductor fin. An interfacial layer is formed in contact with sidewalls of the semiconductor fin. An insulating layer is formed in contact with the interfacial layer. The interfacial layer and the insulating layer are encapsulated by one or more conductive gate layers. | 2020-02-20 |
20200058767 | VERTICAL FIN FIELD EFFECT TRANSISTOR DEVICES WITH SELF-ALIGNED SOURCE AND DRAIN JUNCTIONS - A method of forming a fin field effect transistor device is provided. The method includes forming a plurality of vertical fins on a substrate. The method further includes forming a bottom source/drain layer adjacent to the plurality of vertical fins, and growing a doped layer on the bottom source/drain layer and sidewalls of the plurality of vertical fins. The method further includes forming a dummy gate liner on the doped layer and the bottom source/drain layer, and forming a dummy gate fill on the dummy gate liner. The method further includes forming a protective cap layer on the dummy gate fill, and removing a portion of the protective cap layer to expose a top surface of the plurality of vertical fins. | 2020-02-20 |
20200058768 | TRANSISTOR WITH SUPERPOSED BARS AND DOUBLE-GATE STRUCTURE - A method of fabricating a double gate structure for transistors with superposed bars is provided, including: providing, on a support, a stack including an alternation of one or several first bars made of a first semiconducting material, and one or several second bars based on a second semiconducting material; removing lateral portions of the second bars; forming insulating plugs in contact with lateral regions of the second bars; removing the first bars; and forming a gate electrode facing an upper face and a lower face of the second bars, the insulating plugs being arranged in contact with the lateral regions of the second bars when the gate electrode is being formed. | 2020-02-20 |
20200058769 | METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE USING SELECTIVE FORMING PROCESS - Methods for forming semiconductor structures are provided. The method includes forming a gate structure over a substrate and forming a source/drain structure adjacent to the gate structure. The method further includes forming a mask structure over the gate structure and forming a contact over the source/drain structure. The method further includes selectively forming a metal-containing layer over a top surface of the contact and forming a dielectric layer over the substrate and covering the gate structure and the contact. The method further includes forming a trench through the dielectric layer and the metal-containing layer to expose the top surface of the contact and forming a conductive structure in the trench. | 2020-02-20 |
20200058770 | FinFET Device Including a Stem Region of a Fin Element - A finFET device having a substrate and a fin disposed on the substrate. The fin includes a passive region, a stem region overlying the passive region, and an active region overlying the stem region. The stem region has a first width and the active region has a second width. The first width is less than the second width. The stem region and the active region also have different compositions. A gate structure is disposed on the active region. | 2020-02-20 |
20200058771 | FIN FIELD-EFFECT TRANSISTORS WITH ENHANCED STRAIN AND REDUCED PARASITIC CAPACITANCE - A method of forming a semiconductor structure includes forming a substrate, the substrate having a first portion with a first height and second recessed portions with a second height less than the first height. The method also includes forming embedded source/drain regions disposed over top surfaces of the second recessed portions of the substrate, and forming one or more fins from a portion of the substrate disposed between the embedded source/drain regions, the one or more fins providing channels for fin field-effect transistors (FinFETs). The method further includes forming a gate stack disposed over the one or more fins, and forming inner oxide spacers disposed between the gate stack and the source/drain regions. | 2020-02-20 |
20200058772 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device, a fin structure is formed over a substrate. The fin structure is sculpted to have a plurality of non-etched portions and a plurality of etched portions having a narrower width than the plurality of non-etched portions. The sculpted fin structure is oxidized so that a plurality of nanowires are formed in the plurality of non-etched portions, respectively, and the plurality of etched portions are oxidized to form oxides. The plurality of nanowires are released by removing the oxides. | 2020-02-20 |
20200058773 | METHOD OF FABRICATING TRIMMED FIN AND FIN STRUCTURE - A method of fabricating a trimmed fin includes: forming a preliminary fin including silicon and germanium protruding from a substrate, in which the preliminary fin has a first germanium concentration at a top surface of the preliminary fin and a second germanium concentration at a position beneath the top surface of the preliminary fin, and the first germanium concentration is less than the second germanium concentration; oxidizing an exposed surface of the preliminary fin to form a trimmed fin covered by an oxide layer; and removing the oxide layer to obtain the trimmed fin. | 2020-02-20 |
20200058774 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device, a fin structure is formed over a substrate. The fin structure is sculpted to have a plurality of non-etched portions and a plurality of etched portions having a narrower width than the plurality of non-etched portions. The sculpted fin structure is oxidized so that a plurality of nanowires are formed in the plurality of non-etched portions, respectively, and the plurality of etched portions are oxidized to form oxides. The plurality of nanowires are released by removing the oxides. | 2020-02-20 |
20200058775 | TWIN GATE TUNNEL FIELD-EFFECT TRANSISTOR (FET) - A method of manufacturing a vertical transistor device comprises forming a bottom source region on a semiconductor substrate, forming a channel region extending vertically from the bottom source region, forming a top drain region on an upper portion of the channel region, forming a first gate region having a first gate length around the channel region, and forming a second gate region over the first gate region and around the channel region, wherein the second gate region has a second gate length different from the first gate length, and wherein at least one dielectric layer is positioned between the first and second gate regions. | 2020-02-20 |
20200058776 | III-V LATERAL BIPOLAR JUNCTION TRANSISTOR ON LOCAL FACETTED BURIED OXIDE LAYER - A bipolar junction transistor (LBJT) device that includes a base region of a first III-V semiconductor material having A first band gap; and emitter and collector regions present on opposing sides of the base region, wherein the emitter and collector regions are comprised of a second III-V semiconductor material having a wider band gap than the first III-V semiconductor material. A dielectric region is present underlying the base region, emitter region and the collect region. The dielectric region has an inverted apex geometry. The sidewalls of dielectric region that extend to the apex of the inverted apex geometry are present on facets of a supporting substrate III-V semiconductor material having a {110} crystalline orientation. | 2020-02-20 |
20200058777 | III-V LATERAL BIPOLAR JUNCTION TRANSISTOR ON LOCAL FACETTED BURIED OXIDE LAYER - A bipolar junction transistor (LBJT) device that includes a base region of a first III-V semiconductor material having A first band gap; and emitter and collector regions present on opposing sides of the base region, wherein the emitter and collector regions are comprised of a second III-V semiconductor material having a wider band gap than the first III-V semiconductor material. A dielectric region is present underlying the base region, emitter region and the collect region. The dielectric region has an inverted apex geometry. The sidewalls of dielectric region that extend to the apex of the inverted apex geometry are present on facets of a supporting substrate III-V semiconductor material having a {110} crystalline orientation. | 2020-02-20 |
20200058778 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor base; a trench insulating film | 2020-02-20 |
20200058779 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer, a second semiconductor layer selectively provided on the first semiconductor layer, a third semiconductor layer selectively provided on the second semiconductor layer, and a control electrode facing a portion of the second semiconductor layer via a first insulating film. The device further includes a fourth semiconductor layer provided on a lower surface side of the first semiconductor layer, a fifth semiconductor layer arranged with the fourth semiconductor layer along a lower surface of the first semiconductor layer, and a sixth semiconductor layer provided between the first and fifth semiconductor layers. The sixth semiconductor layer is connected to the fourth semiconductor layer. The device includes a connecting portion positioned between the first and fifth semiconductor layers. The connecting portion electrically connects the fifth semiconductor layer to the first semiconductor layer, and the sixth semiconductor layer is not provided at the connecting portion. | 2020-02-20 |
20200058780 | Field Plates on Two Opposed Surfaces of Double-Base Bidirectional Bipolar Transistor: Devices, Methods, and Systems - Dual-base two-sided bipolar power transistors which use an insulated field plate to separate the emitter/collector diffusions from the nearest base contact diffusion. This provides a surprising improvement in turn-off performance, and in breakdown voltage. | 2020-02-20 |
20200058781 | SILICON-CONTROLLED RECTIFIER STRUCTURE AND MANUFACTURING METHOD THEREFOR - The present disclosure provides a silicon-controlled rectifier structure and a manufacturing method therefor. The silicon-controlled rectifier structure comprises a substrate; and an N-Well and a P-Well in the substrate, wherein an N-type heavily-doped region | 2020-02-20 |
20200058782 | STACKED GROUP III-NITRIDE TRANSISTORS FOR AN RF SWITCH AND METHODS OF FABRICATION - A semiconductor device includes a silicon pillar disposed on a substrate, the silicon pillar has a sidewall. A group III-N semiconductor material is disposed on the sidewall of the silicon pillar. The group III-N semiconductor material has a sidewall. A doped source structure and a doped drain structure are disposed on the group III-N semiconductor material. A polarization charge inducing layer is disposed on the sidewall of the group III-N semiconductor material between the doped drain structure and the doped source structure. A plurality of portions of gate dielectric layer is disposed on the sidewalls of the group III-N semiconductor material and between the polarization charge inducing layer. A plurality of resistive gate electrodes separated by an interlayer dielectric layer are disposal adjacent to each of the plurality of portions of the gate dielectric layer. A source metal layer is disposed below and in contact with the doped source structure. | 2020-02-20 |
20200058783 | COMPOUND SEMICONDUCTOR DEVICE - A compound semiconductor device includes a compound semiconductor laminate structure including an electron transit layer and an electron supply layer, a gate electrode, a source electrode, and a drain electrode that are formed over the electron supply layer, a first insulating layer of diamond formed between the gate electrode and the drain electrode over the compound semiconductor laminate structure, and a second insulating layer formed between the gate electrode and the source electrode over the compound semiconductor laminate structure, wherein a positive compressive stress is applied from the first insulating layer to the electron supply layer, and a compressive stress from the second insulating layer to the electron supply layer is smaller than the compressive stress from the first insulating layer to the electron supply layer. | 2020-02-20 |
20200058784 | SEMICONDUCTOR DEVICE WITH FIN END SPACER DUMMY GATE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a plurality of fins on a substrate. A fin liner is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A plurality of polycrystalline silicon layers are formed on the insulating layer. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. One of the polycrystalline silicon layers is formed on a region spaced-apart from the fins. | 2020-02-20 |
20200058785 | VIA STRUCTURE WITH LOW RESISTIVITY AND METHOD FOR FORMING THE SAME - A semiconductor device structure is provided. The semiconductor device structure includes a gate stack over a substrate and an insulating capping layer over the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack and having an upper surface that is substantially level with the upper surface of the insulating capping layer. The semiconductor device structure also includes a first via structure passing through the insulating capping layer and electrically connected to the gate stack, and a second via structure above and electrically connected to the source/drain contact structure. The first via structure and the second via structure have different vertical heights. | 2020-02-20 |
20200058786 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor body, first and second electrodes, and a control electrode. The semiconductor body includes first to fourth semiconductor layers. The first electrode is provided on a front surface of the semiconductor body. The second electrode is provided on a back surface of the semiconductor body. The control electrode is provided between the semiconductor body and the first electrode. The second semiconductor layer is positioned between a portion and other portion of the first semiconductor layer in a first direction directed along the front surface. The third semiconductor layer contacts the portion of first semiconductor layer and the second semiconductor layer. The third semiconductor layer includes a first end portion positioned in the portion of the first semiconductor layer and a second end portion positioned in the second semiconductor layer. The fourth semiconductor layer is selectively provided in the second end portion. | 2020-02-20 |
20200058787 | Semiconductor Device with Latchup Immunity - A semiconductor device includes a body region of a second conductivity type, a body contact region of the second conductivity type formed in the body region and having a higher average doping concentration than the body region, a source region of a first conductivity type opposite the second conductivity type formed in the body region adjacent the body contact region, a drift zone of the first conductivity type spaced apart from the source region by a section of the body region which forms a channel region of the semiconductor device, and a gate electrode configured to control the channel region. The body contact region extends under a majority of the source region in a direction towards the channel region and has a doping concentration of at least 1e18 cm | 2020-02-20 |
20200058788 | SOURCE CONTACT FORMATION OF MOSFET WITH GATE SHIELD BUFFER FOR PITCH REDUCTION - A semiconductor structure that includes at least one lateral diffusion field effect transistor is described. The structure includes a source contact and a gate shield that enables the line width of an ohmic region that electrically connects the source/body region to the gate shield to be smaller than the minimum contact feature size. The gate shield defines a bottom recess for forming a narrower bottom portion of the source contact, and a section that flares outward with distance from the ohmic region to extend above and laterally beyond the ohmic region. By providing a wider area for the source contact, the flared portion of the gate shield allows the portion of the gate shield that contacts the ohmic region to be narrower than the minimum contact feature size. As a result, the cell pitch of the lateral diffusion field effect transistor can be reduced. | 2020-02-20 |
20200058789 | SEMICONDUCTOR STRUCTURE AND ASSOCIATED FABRICATING METHOD - A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an isolation region adjacent to the drain region; a gate electrode over the substrate and further downwardly extends into the substrate, wherein a portion of the gate electrode below a top surface of the substrate abuts the isolation region; and a source region and a drain region formed in the substrate on either side of the gate structure. An associated method for fabricating the semiconductor structure is also disclosed. | 2020-02-20 |
20200058790 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING GATE STRUCTURE WITH BENT SIDEWALLS - A method of fabricating a semiconductor device includes forming a dummy gate structure on a substrate, forming gate spacers on sidewalls of the dummy gate structure, and depositing an interlayer dielectric layer around the gate spacers. The method also includes removing the dummy gate structure to form a space between the gate spacers, and forming a gate structure in the space, wherein the gate structure includes a gate dielectric layer and a gate electrode layer over the gate dielectric layer. The method further includes removing a portion of the gate electrode layer to form a recess that is surrounded by the gate dielectric layer. In addition, the method includes implanting on the interlayer dielectric layer to form a strained layer for bending the gate dielectric layer and the gate spacers towards the recess. | 2020-02-20 |
20200058791 | SEMICONDUCTOR DEVICE HAVING TIPLESS EPITAXIAL SOURCE/DRAIN REGIONS - A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device comprises a gate stack on a substrate. The gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in the substrate. The semiconductor device also comprises a pair of source/drain regions in the substrate on either side of the channel region. The pair of source/drain regions is in direct contact with the gate dielectric layer and the lattice constant of the pair of source/drain regions is different than the lattice constant of the channel region. In one embodiment, the semiconductor device is formed by using a dielectric gate stack placeholder. | 2020-02-20 |
20200058792 | CIRCUITS HAVING A DIFFUSION BREAK WITH AVOIDED OR REDUCED ADJACENT SEMICONDUCTOR CHANNEL STRAIN RELAXATION, AND RELATED METHODS - Cell circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation and related methods are disclosed. In one aspect, a cell circuit includes a substrate of semiconductor material and a semiconductor channel structure(s) of a second semiconductor material disposed on the substrate. The semiconductor material applies a stress to the formed semiconductor channel structure(s) to induce a strain in the semiconductor channel structure(s) for increasing carrier mobility. A diffusion break comprising a dielectric material extends through a surrounding structure of an interlayer dielectric, and the semiconductor channel structure(s) and at least a portion of the substrate. The relaxation of strain in areas of the semiconductor channel structure(s) adjacent to the diffusion break is reduced or avoided, because the semiconductor channel structure(s) is constrained by the surrounding structure. | 2020-02-20 |
20200058793 | STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE WITH ETCH STOP LAYER - A method for forming a semiconductor device structure is provided. The method includes providing a substrate. The method includes forming a gate structure over the substrate. The gate structure has a first sidewall. The method includes forming a spacer element over the first sidewall of the gate structure. The method includes forming a source/drain portion adjacent to the spacer element and the gate structure. The source/drain portion has a first top surface. The method includes depositing an etch stop layer over the first top surface of the source/drain portion. The etch stop layer is made of nitride. The method includes forming a dielectric layer over the etch stop layer. The dielectric layer has a second sidewall and a bottom surface, the etch stop layer is in direct contact with the bottom surface, and the spacer element is in direct contact with the second sidewall. | 2020-02-20 |
20200058794 | METHOD FOR FORMING FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE WITH CONDUCTIVE LAYER BETWEEN GATE AND GATE CONTACT - A method for forming a FinFET device structure is provided. The method includes forming a fin structure over a substrate and forming a gate dielectric layer over the fin structure. The method also includes forming a gate electrode layer over the gate dielectric layer and forming a source/drain (S/D) structure adjacent to the gate electrode layer. In addition, the method includes forming an S/D contact structure over the S/D structure. The method also includes forming a first conductive layer in direct with the gate electrode layer. A bottom surface of the first conductive layer is lower than a top surface of the gate dielectric layer. The method further includes forming a second conductive layer over the first conductive layer. The gate electrode layer is electrically connected to the second conductive layer by the first conductive layer. | 2020-02-20 |
20200058795 | ANTIFERROMAGNET FIELD-EFFECT BASED LOGIC CIRCUITS INCLUDING SPIN ORBITAL COUPLING CHANNELS WITH OPPOSING PREFERRED CURRENT PATHS AND RELATED STRUCTURES - An anti-ferromagnetic (AFM) voltage-controlled field effect logic device structure can include an AFM material that extends in a first direction and an input voltage terminal that extends opposite the AFM material. An oxide material can be located between the AFM material and the input voltage terminal. A first spin orbital coupling (SOC) material can extend in a second direction across the AFM material to provide a first SOC channel with a drain voltage terminal at a first end of the first SOC channel and an output voltage terminal at a second end of the first SOC channel that is opposite the first end. A contact can be electrically coupled to the output voltage terminal and configured to electrically couple to a second SOC material extending in the second direction spaced apart from the first SOC material to provide a second SOC channel. | 2020-02-20 |
20200058796 | DISPLAY PANEL AND DISPLAY DEVICE - This application discloses a display panel and a display device. The display panel includes a substrate, an active switch array and a color filter layer, where the color filter layer is formed on the active switch array, the active switch array includes a metal layer, the metal layer is arranged on the substrate, the substrate is provided thereon with at least two protective layers, the protective layers are covered on the metal layer, the metal layer is separated from the color filter layer by the protective layers. | 2020-02-20 |
20200058797 | Display Device and Method for Manufacturing the Same - Provided are a display device and a method for manufacturing the same. The display device includes: a connection source electrode and a connection drain electrode connected to a first source electrode a the first drain electrode, respectively by penetrating an isolation insulating layer and a second interlayer dielectric layer to enhance a characteristic of an element and reliability of the display device. | 2020-02-20 |
20200058798 | VERTICAL TRANSISTOR DEVICES AND TECHNIQUES - Disclosed herein are vertical transistor devices and techniques. In some embodiments, a device may include: a semiconductor substrate; a first transistor in a first layer on the semiconductor substrate; and a second transistor in a second layer, wherein the second transistor includes a first source/drain (S/D) contact and a second S/D contact, the first layer is between the second layer and the semiconductor substrate, and the first S/D contact is between the second S/D contact and the first layer. In some embodiments, a device may include: a semiconductor substrate; and a transistor above the semiconductor substrate, wherein the transistor includes a channel and a source/drain (S/D) contact between the channel and the semiconductor substrate. | 2020-02-20 |
20200058799 | VERTICAL THIN FILM TRANSISTOR - A semiconductor device includes a stack of layers stacked vertically and including a source layer, a drain layer and a channel layer between the source layer and the drain layer. A gate electrode is formed in a common plane with the channel layer and a gate dielectric is formed vertically between the gate electrode and the channel layer. A first contact contacts the stack of layers on a first side of the stack of layers, and a second contact formed on an opposite side vertically from the first contact. | 2020-02-20 |
20200058800 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME - A semiconductor structure and a method for forming same are provided. One form of the method includes: providing a substrate including a device unit area, where at least two fins are formed on the substrate of the device unit area, a channel structure layer is formed on the fins, the channel structure layer includes a first channel structure layer located on at least one fin and a second channel structure layer located on at least one fin, the first channel structure layer includes multiple channel laminates, each channel laminate includes a first sacrificial layer and a first channel layer located on the first sacrificial layer, and the second channel structure layer is a second channel layer of a single-layer structure; forming a dummy gate structure across the channel structure layer of the device unit area; forming a source-drain doping layer in the channel structure layer on two sides of the dummy gate structure; forming an interlayer dielectric layer on the substrate exposed by the dummy gate structure; and after forming the interlayer dielectric layer, forming a gate structure at positions of the dummy gate structure and the first sacrificial layer. The present disclosure can improve overall performance of a device. | 2020-02-20 |
20200058801 | MULTIPLE WIDTH NANOSHEET DEVICES - A technique relates to a semiconductor device. A first stack includes a first plurality of nanowires respectively coupled to first source and drain regions, and a second stack includes a second plurality of nanowires respectively coupled to second source and drain regions. First source and drain contacts couple to a first predefined number of the first plurality of nanowires. Second source and drain contacts to couple to a second predefined number of the second plurality of nanowires, wherein the first predefined number is different from the second predefined number. | 2020-02-20 |
20200058802 | MAGNETORESISTANCE EFFECT DEVICE - A magnetoresistance effect device includes a magnetoresistance effect element, and an external magnetic field application unit for applying an external magnetic field to the magnetoresistance effect element. The magnetoresistance effect element includes a first ferromagnetic layer, a second ferromagnetic layer, and a spacer layer. The external magnetic field application unit includes a magnetization retention section and a magnetization setting section. The magnetization setting section has a function of setting a magnetization to be used to generate the external magnetic field into the magnetization retention section by applying a magnetization-setting magnetic field to the magnetization retention section and then stopping the application of the magnetization-setting magnetic field. The magnetization retention section has a function of retaining the set magnetization after the application of the magnetization-setting magnetic field is stopped. | 2020-02-20 |
20200058803 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate including a drift region of a first conductivity type, a transistor portion provided in the substrate, and an adjacent element portion provided in the substrate, the adjacent element and transistor portions being arranged along an arrangement direction. The transistor and adjacent element portions both include a base region of a second conductivity type provided above the drift region, trench portions formed through the base region, extending in an extending direction orthogonal to the arrangement direction on the upper surface, and having a conducting portion therein, and a first lower surface side lifetime control region provided, on a lower surface side, continuously from the transistor portion to the adjacent element portion and includes a lifetime killer. The lifetime control region is provided over entirety of the transistor portion and in a part of the adjacent element portion in a top view of the substrate. | 2020-02-20 |
20200058804 | SCHOTTKY BARRIER DIODE AND ELECTRONIC CIRCUIT PROVIDED WITH SAME - An object of the present invention is to provide a Schottky barrier diode using gallium oxide capable of suppressing heat generation and enhancing heat radiation performance while ensuring mechanical strength and handling performance. A Schottky barrier diode includes a semiconductor substrate | 2020-02-20 |
20200058805 | TRENCH CAPACITOR AND METHOD FOR MANUFACTURING THE SAME - An embodiment of the present application relates to a trench capacitor and a method for manufacturing the same. The method for manufacturing the capacitor includes: fabricating a trench reaching a depth of a middle insulating layer on a semiconductor layer of an SOI substrate; and further growing an epitaxial layer of the semiconductor layer on a sidewall of the trench by selective epitaxial growth technology so as to further reduce a width of the trench; filling the trench with an electrically insulating material; and finally, fabricating two electrodes of the capacitor separately through a surface electrode. According to a trench capacitor and a method for manufacturing the same provided in an embodiment of the present application, a process flow is simple, and the capacitor manufactured has two advantages of high capacitance density and high breakdown voltage. | 2020-02-20 |
20200058806 | Crystalline Solar Cell Comprising a Transparent, Conductive Layer Between the Front-Side Contacts and Method for Producing Such a Solar Cell - A monofacial or bifacial crystalline solar cell, on the front face of which over the entire area a first surface passivation layer is arranged directly on the semiconductor interface and above this a first optically opaque, electrically conductive material is arranged in first lateral regions as a front face contact, and a first optically transparent, electrically conductive material is arranged exclusively in second lateral regions. The first optically transparent, electrically conductive material is electrically conductively connected to the front face contact and to a first region of the semiconductor material of the solar cell. The method provides for application of the first optically transparent, electrically conductive material only after the first optically opaque, electrically conductive material has been applied, in such a way that firing of the front face contact is avoided. | 2020-02-20 |
20200058807 | INTEGRATED PHOTODETECTOR WAVEGUIDE STRUCTURE WITH ALIGNMENT TOLERANCE - An encapsulated integrated photodetector waveguide structures with alignment tolerance and methods of manufacture are disclosed. The method includes forming a waveguide structure bounded by one or more shallow trench isolation (STI) structure(s). The method further includes forming a photodetector fully landed on the waveguide structure. | 2020-02-20 |
20200058808 | PHOTODETECTION DEVICE AND PHOTODETECTION SYSTEM - A semiconductor substrate has a first surface and a second surface which is opposite to the first surface. A photoelectric conversion portion has a PN junction configured with first and second semiconductor regions of different conductivity types. A buried portion is buried in the semiconductor substrate and includes an electrode and a dielectric member located between the electrode and the semiconductor substrate and in contact with the second semiconductor region. The second semiconductor region is located in a position deeper than the first semiconductor region. The buried portion is located to extend from a first surface to a position deeper than the first semiconductor region. Electric potentials are supplied to the first semiconductor region, the second semiconductor region, and the electrode in such a manner that an inversion layer occurring between the electrode and the second semiconductor region and the first semiconductor region are in contact with each other. | 2020-02-20 |
20200058809 | SOLID STATE IMAGING APPARATUS, PRODUCTION METHOD THEREOF AND ELECTRONIC DEVICE - A solid state imaging apparatus includes an insulation structure formed of an insulation substance penetrating through at least a silicon layer at a light receiving surface side, the insulation structure having a forward tapered shape where a top diameter at an upper portion of the light receiving surface side of the silicon layer is greater than a bottom diameter at a bottom portion of the silicon layer. Also, there are provided a method of producing the solid state imaging apparatus and an electronic device including the solid state imaging apparatus. | 2020-02-20 |
20200058810 | HIGH EFFICIENCY SOLAR CELL AND METHOD FOR MANUFACTURING HIGH EFFICIENCY SOLAR CELL - A solar cell including a semiconductor substrate having a first conductivity type an emitter region, having a second conductivity type opposite to the first conductivity type, on a first main surface of the semiconductor substrate an emitter electrode which is in contact with the emitter region a base region having the first conductivity type a base electrode which is in contact with the base region and an insulator film for preventing an electrical short-circuit between the emitter region and the base region, wherein the insulator film is made of a polyimide, and the insulator film has a C | 2020-02-20 |
20200058811 | ELECTRODE FORMATION FOR HETEROJUNCTION SOLAR CELLS - A method for forming a photovoltaic device includes forming a doped layer on a crystalline substrate, the doped layer having an opposite dopant conductivity as the substrate. A non-crystalline transparent conductive electrode (TCE) layer is formed on the doped layer at a temperature less than 150 degrees Celsius. The TCE layer is flash annealed to crystallize material of the TCE layer at a temperature above about 150 degrees Celsius for less than 10 seconds. | 2020-02-20 |
20200058812 | SHINGLED ARRAY MODULE FOR VEHICLE SOLAR ROOF - A solar module for incorporation in a motor vehicle including a front sheet having a curvature in at least two directions, at least one set of strings, wherein each string is formed of a plurality strips of a solar cell, and each of the strips is arranged in an overlapping manner with an adjacent strip, and electrically connected to an adjacent strip with an electrically conductive adhesive. The module further includes a first encapsulation layer disposed between the front sheet and a first side of the at least one set of strings, a second encapsulation layer formed on a second side of the ate least one set of strings, and a back sheet formed on the second encapsulation layer. | 2020-02-20 |
20200058813 | CONDUCTIVE FILM, PHOTOVOLTAIC CELL UNIT, AND PHOTOVOLTAIC CELL MODULE - A conductive film, a photovoltaic cell unit, and a photovoltaic cell module are disclosed. The conductive film adapted to electrically connect two adjacent photovoltaic cells in series includes at least one wire, a light transmissive layer, and a light transmissive resin layer, the light transmissive layer covers the wire, and the light transmissive resin layer is at least disposed between the wire and the light transmissive layer. | 2020-02-20 |
20200058814 | DEVICE AND REALIZATION METHOD OF LUMINESCENT SOLAR CONCENTRATORS BASED ON SILICON NANOSTRUCTURES - An energy conversion device, particularly electromagnetic energy, such as sunlight and the like, comprising a transparent polymer sheet having an edge and a surface, on which said electromagnetic radiation can impact, and a photovoltaic cell mechanically coupled with said edge of said polymer sheet, capable of transforming in an electrical current the radiation incident on it, characterized in that said polymer sheet comprises a polymeric matrix having silicon nanostructures, functionalized with organic binders, said polymeric sheet being then luminescent with respect to a portion of said electromagnetic radiation, so as to convey the same, through a wave-guide, towards said photovoltaic cell. Also disclosed is a method for realizing a polymeric matrix, for the manufacture of a transparent polymer sheet. | 2020-02-20 |
20200058815 | METHOD FOR FABRICATING A SOLAR MODULE OF REAR CONTACT SOLAR CELLS USING LINEAR RIBBON-TYPE CONNECTOR STRIPS AND RESPECTIVE SOLAR MODULE - A solar module and a method for fabricating a solar module comprising a plurality of rear contact solar cells are described. Rear contact solar cells ( | 2020-02-20 |
20200058816 | OPTICAL SHIELD FOR PHOTOVOLTAIC CELL - An optical shield for a photovoltaic cell is provided, comprising an at least one carrier element, the carrier element comprises a number of embedded optically functional cavities arranged into an at least one predetermined optical relief pattern, wherein each embedded optically functional cavity in the at least one carrier element is positioned and aligned over an individual surface structure, such as an electrode, a contact, a finger, or a busbar, provided on the surface of the photovoltaic cell. | 2020-02-20 |
20200058817 | BIFACIAL TUBE-TYPE PERC SOLAR CELL, PREPARATION METHOD THEREOF, AND PRODUCTION DEVICE THEREFOR - The present invention discloses a bifacial tube-type PERC solar cell, which comprises a rear silver major grid line, a rear aluminum grid line, a rear surface composite film, P-type silicon, an N-type emitter, a front surface silicon nitride film, and a front silver electrode. The present invention also discloses a method and a device for preparing a bifacial tube-type PERC solar cell. The present invention absorbs sunlight on both surfaces, has high photoelectric conversion efficiency, high appearance quality, and high EL yield, and could solve the problems of both scratching and undesirable deposition. | 2020-02-20 |
20200058818 | PHOTOVOLTAIC DEVICES AND METHOD OF MANUFACTURING - A photovoltaic device includes a substrate structure and at least one Se-containing layer, such as a CdSeTe layer. A process for manufacturing the photovoltaic device includes forming the CdSeTe layer over a substrate by at least one of sputtering, evaporation deposition, CVD, chemical bath deposition process, and vapor transport deposition process. The process can also include controlling a thickness range of the Se-containing layer. | 2020-02-20 |
20200058819 | MULTIJUNCTION PHOTOVOLTAIC DEVICE - There is provided a multi junction photovoltaic device comprising a first sub-cell comprising a photoactive region comprising a layer of perovskite material, a second sub-cell comprising a photoactive silicon absorber. and an intermediate region disposed between and connecting the first sub-cell and the second sub-cell. The intermediate region comprises an interconnect layer, the interconnect layer comprising a two-phase material comprising elongate (i.e. filament like) silicon nanocrystals embedded in a silicon oxide matrix. | 2020-02-20 |
20200058820 | ELECTRICAL CONDUCTIVITY BY MICROWAVE SINTERING - The invention relates to a method for making a HIT solar cell comprising the steps of providing a substrate wherein the substrate comprises amorphous layers on the surfaces of the substrate respectively, providing an electroconductive paste comprising as constituents metallic particles and a polymer system then applying the electroconductive paste to the substrate surface to obtain a precursor and finally heating the precursor through microwave radiation to obtain a solar cell. | 2020-02-20 |
20200058821 | LIGHT DETECTION DEVICE - A photodetecting device includes a semiconductor substrate including a one-dimensionally distributed plurality of pixels. The photodetecting device includes, for each pixel, a plurality of avalanche photodiodes arranged to operate in Geiger mode, a plurality of quenching resistors electrically connected in series with the respective avalanche photodiodes, and a signal processing unit arranged to process output signals from the plurality of avalanche photodiodes. Light receiving regions of the plurality of avalanche photodiodes are two-dimensionally distributed for each pixel. Each signal processing unit includes a gate grounded circuit and a current mirror circuit electrically connected to the gate grounded circuit. The gate grounded circuit is electrically connected to the plurality of avalanche photodiodes of the corresponding pixel via the plurality of quenching resistors. The current minor circuit is arranged to output a signal corresponding to output signals from the plurality of avalanche photodiodes. | 2020-02-20 |
20200058822 | OPTOELECTRONIC SEMICONDUCTOR STRUCTURE HAVING A BIPOLAR PHOTOTRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - An optoelectronic semiconductor structure includes a first n-type semiconductor layer, a first quantum well layer, a first p-type semiconductor layer, and a second n-type semiconductor layer. The first quantum well layer is disposed on the first n-type semiconductor layer. The first p-type semiconductor layer is disposed on the first quantum well layer. The second n-type semiconductor layer is disposed on the first p-type semiconductor layer. The second n-type semiconductor layer includes both an n-type dopant and a p-type dopant. The concentration of the n-type dopant in the second n-type semiconductor layer is greater than the concentration of the p-type dopant in the second n-type semiconductor layer. The first n-type semiconductor layer, the first quantum well layer, the first p-type semiconductor layer, and the second n-type semiconductor layer form a bipolar phototransistor structure. A manufacturing method of the optoelectronic semiconductor structure is also provided. | 2020-02-20 |
20200058823 | LIGHT-SENSING APPARATUS AND ELECTRONIC DEVICE - An apparatus disposed below a housing, the apparatus including: a light-sensing element having a light-sensing region, and being configured to sense light reaching the light-sensing region through a first light-transmitting region of the housing; and where when the energy of the light that reaches the light-sensing region is reduced relative to the energy of the light that is expected to reach the light-sensing region, the area of the light-sensing region located under the first light-transmitting region increases. | 2020-02-20 |
20200058824 | LIGHT EMITTING DEVICE - A light emitting device including a first light emitting part including a first n-type semiconductor layer, and a first mesa structure including a first active layer, a first p-type semiconductor layer, and a first transparent electrode vertically stacked one over another and exposing a portion of a first surface the first n-type semiconductor layer, a second light emitting part disposed on the exposed portion of the first n-type semiconductor layer and spaced apart from the first mesa structure, and including a second n-type semiconductor layer, a second active layer, a second p-type semiconductor layer, and a second transparent electrode, and a first bonding part bonding and electrically coupling the first n-type semiconductor layer and the second n-type semiconductor layer to each other. | 2020-02-20 |
20200058825 | LIGHT EMITTING DEVICE - A light emitting device including first, second, and third light emitting parts disposed one over another and each including an n-type semiconductor layer, an active layer, a p-type semiconductor layer, a first adhesion layer disposed between the first and second light emitting parts and including first coupling patterns that are adhesive and conductive, and a second adhesion layer disposed between the second and third light emitting parts and including second coupling patterns that are adhesive and conductive, in which the third light emitting part has a mesa structure exposing a portion of the second coupling patterns of the second adhesion layer. | 2020-02-20 |
20200058826 | Method for Producing an Output Coupling Element for an Optoelectronic Component and Optoelectronic Component - A method for producing an output coupling element and an optoelectronic component are disclosed. In an embodiment, a method includes providing an inorganic dielectric element with a surface in a chamber, wherein the inorganic dielectric element rotates in the chamber during operation and providing a structuring agent comprising water and ozone and introducing the structuring agent into the chamber so that the structuring agent contacts the surface of the inorganic dielectric element and a roughening is produced in the surface, wherein the inorganic dielectric element comprises aluminum oxide. | 2020-02-20 |
20200058827 | Near-Ultraviolet Light-Emitting Semiconductor Light-Emitting Element And Group III Nitride Semiconductor Template Used Therefor - Disclosed is a Group III nitride semiconductor template for a 300-400 nm near-ultraviolet light emitting semiconductor device, the template including: a growth substrate; a nucleation layer based on Al | 2020-02-20 |
20200058828 | AlInN FILM, TWO-DIMENSIONAL PHOTONIC CRYSTAL RESONATOR, METHOD FOR MANUFACTURING THESE, AND SEMICONDUCTOR LIGHT-EMITTING ELEMENT - Provided is a technique for manufacturing a semiconductor light-emitting element for which it is possible to dramatically increase light emission efficiency to a greater degree than in the past. An AlInN film provided on a GaN epitaxial film that is formed on a substrate, wherein: the AlInN film is formed by lamination of AlInN layers; between the laminated AlInN layers, there is provided a cap layer that comprises GaN, AlN, or AlGaN, and has a thickness of 0.1-10 nm; a super lattice structure is formed; the total thickness exceeds 200 nm; and the root-mean-square height RMS is 3 nm or less. A method for forming an AlInN film, the method being such that: a step for forming an AlInN layer is repeated a plurality of times, said step involving using any of an organometallic vapor phase growth method, a molecular beam epitaxy method, and a sputtering method to form the AlInN layer to a thickness of 200 nm or less by epitaxial growth in an atmosphere of 700-850° C. on a GaN epitaxial film formed on a substrate; and the AlInN layer is grown until a prescribed thickness is reached. | 2020-02-20 |
20200058829 | LIGHT EMITTING DEVICE PACKAGE AND LIGHT SOURCE UNIT - A light emitting device package disclosed to an embodiment of the invention includes a body including an upper surface and a lower surface, the body including a first recess and a second recess concaved from the lower surface toward the upper surface; a light emitting device disposed on the body and including a first bonding portion and a second bonding portion; and first and second conductive portions respectively disposed in the first recess and the second recess, wherein the body includes a first through hole and a second through hole penetrating an upper surface of each of the first recess and the second recess and the upper surface of the body, and wherein each of the first and second conductive portions extends into the first and second through holes and is electrically connected to the first bonding portion and the second bonding portion, respectively. | 2020-02-20 |
20200058830 | WAVELENGTH CONVERSION MEMBER AND LIGHT EMITTING DEVICE - Provided is a wavelength conversion member capable of suppressing excessive heating of a phosphor layer and a light emitting device using the same. The wavelength conversion member | 2020-02-20 |
20200058831 | Method for Producing an Output Coupling Element for an Optoelectronic Component and Output Coupling Element - A method for producing an output coupling element and an output coupling element are disclosed. In an embodiment a method includes producing a suspension having quantum dots in a suspension medium, wherein each quantum dot comprises a core having a semiconductor material, directly applying the suspension onto a surface of an optoelectronic component and/or onto a surface of a carrier and removing the suspension medium for producing the output coupling element, wherein the output coupling element is matrix-free and transparent to radiation of a red range and/or a IR range. | 2020-02-20 |
20200058832 | LED LIGHT BULB HAVING FILAMENT WITH BEING PARTIALLY COATED BY LIGHT CONVERSION LAYER - An LED light bulb, consisting of: a lamp housing doped with a golden yellow material or its surface coated with a yellow film; a bulb base connected to the lamp housing; a stem connected to the bulb base and located in the lamp housing, the stem comprises a stand extending to the center of the lamp housing; and a single LED filament, disposed in the lamp housing, the LED filament comprising: a light conversion layer, coated on at least two sides of the LED chip and the conductive electrodes, and a portion of each of the conductive electrodes is not coated with the light conversion layer, the light conversion layer has at least one top layer and one base layer, the top layer and the base layer are disposed on the opposing surface of the LED chip, wherein the top layer of the light conversion layer in the conductive section comprises a wavy concave structure with groove, the two adjacent grooves of the wavy concave structure have different width at the positions aligned in the axial direction of the LED filament. | 2020-02-20 |
20200058833 | LED LIGHT BULB HAVING FILAMENT WITH CONDUCTIVE SECTION PROVIDING WITH RIVET STRUCTURE - An LED light bulb, comprising of: a lamp housing; a bulb base connected to the lamp housing; a stem connected to the bulb base and located in the lamp housing, the stem comprises a stand extending to the center of the lamp housing; a single LED filament, disposed in the lamp housing, the LED filament comprising: a plurality of LED sections, each of the LED sections includes at least two LED chips that are electrically connected to each other; a plurality of conductive sections, each of the conductive sections is located between the two adjacent LED sections and configured to electrically connect the two adjacent LED sections, each of the conductive sections includes at least one conductor that connects the two adjacent LED sections, each of the conductor has at least one through hole; a light conversion layer comprising a base layer and a top layer, wherein the base layer of the light conversion layer is filled into the through hole of the conductor and then contacting the surface of the top layer. | 2020-02-20 |
20200058834 | DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF - A display apparatus includes a plurality of unit modules; and a cover configured to support the plurality of unit modules. Each of the plurality of unit modules includes: a substrate; a plurality of inorganic light emitting diodes provided on a mounting surface of the substrate; and an encapsulation layer formed on the mounting surface of the substrate to cover the plurality of inorganic light emitting diodes and the mounting surface of the substrate. The encapsulation layer includes a viscoelastic material having varying viscoelasticity based on temperature being applied to the viscoelastic material. | 2020-02-20 |
20200058835 | LED FILAMENT WITH COLORED OFF STATE MASKING - An LED filament includes an underlying layer exhibiting a first appearance at a first temperature, and an over-coated layer comprising a thermochromic material that exhibits at the first temperature, a preselected appearance other than the first appearance, and at a second temperature, a transparent or translucent appearance. | 2020-02-20 |
20200058836 | METHOD OF PRODUCING SIDE-EMITTING COMPONENTS AND SIDE-EMITTING COMPONENT - A method of producing side-emitting components includes providing a plurality of semiconductor chips on an auxiliary carrier, wherein the semiconductor chips on the auxiliary carrier are spaced apart from each other and each have a side surface provided with a transparent protective layer; covering the semiconductor chips with a radiation-reflecting molding compound so that in a plan view of the auxiliary carrier, the semiconductor chips are completely covered by the molding compound; and singulating the molding compound and the semiconductor chips into a plurality of components so that the components each include a semiconductor chip, wherein the components are singulated at the associated transparent protective layer, as a result of which the components each have a radiation exit surface exposed by the molding compound and formed by a surface of the remaining or exposed transparent protective layer. | 2020-02-20 |
20200058837 | METHOD FOR PRODUCING A MICROELECTRONIC CHIP TO BE HYBRIDISED TO A SECOND CHIP - The invention relates to a method for producing a first microelectronic chip including a layer of interest having a connection face, intended to be hybridized with a second microelectronic chip. The method including depositing a layer of adhesive on a face of the layer of interest opposite to the first connection face and fastening a handle layer to the layer of adhesive. The method also includes, prior to the steps of depositing the adhesive and fastening the handle layer, defining, on the one hand, a maximum thickness e | 2020-02-20 |
20200058838 | DISPLAY APPARATUS USING SEMICONDUCTOR LIGHT EMITTING DEVICE, AND MANUFACTURING METHOD THEREFOR - The present invention relates to a display apparatus using a semiconductor light emitting device and a manufacturing method therefor and, more specifically, to a display apparatus using a semiconductor light emitting device. The display apparatus according to the present invention comprises: a wiring board which comprises a wiring electrode; a conductive adhesive layer which covers the wiring electrode; and a plurality of semiconductor light emitting devices which are coupled to the conductive adhesive layer and are electrically connected to the wiring electrode, wherein the conductive adhesive layer is applied in a patterned form on each electrode of the semiconductor light emitting devices such that a plurality of adhesive regions are provided spaced apart from each other on the wiring board. | 2020-02-20 |
20200058839 | LIGHT-EMITTING DEVICE PACKAGE - A light-emitting device package includes a lead frame, a light-emitting device chip, a molding structure, and a plurality of slots. The lead frame includes a first lead and a second lead including metal and spaced apart from each other. The light-emitting device chip is mounted on a first area of the lead frame, which includes a part of the first lead and a part of the second lead. The molding structure includes an outer barrier surrounding an outside of the lead frame and an inner barrier. The plurality of slots are formed in each of the first lead and the second lead. The inner barrier divides the lead from into the first area and a second area. The inner barrier fills between the first lead in the second lead. The second area is located outside of the first area. The plurality of slots are filled by the molding structure. | 2020-02-20 |
20200058840 | OPTOELECTRONIC SEMICONDUCTOR CHIP AND METHOD OF PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR CHIP - An optoelectronic semiconductor chip includes a semiconductor layer sequence having an active layer that generates electromagnetic radiation, two contact elements on a back side of the semiconductor layer sequence, a radiolucent cooling element on a front side of the semiconductor layer sequence opposite the back side, and a siloxane-containing converter layer between the cooling element and the semiconductor layer sequence, wherein the contact elements are configured for electrical contacting of the semiconductor chip and are exposed in the unmounted state of the semiconductor chip, the cooling element is different from a growth substrate of the semiconductor layer sequence, and the cooling element has a thermal conductivity of at least 0.7 W/(m·K). | 2020-02-20 |
20200058841 | THERMOELECTRIC MATERIALS AND RELATED COMPOSITIONS AND METHODS - A thermoelectric material includes a polymer matrix and a plurality of partially coated particles dispersed within the polymer matrix. Each particle of the plurality has a discontinuous coating of metal on a carbon-based material. A method includes dispersing functionalized particles comprising a carbon-based material in a solvent; providing a metal salt in the solvent; and forming a plurality of distinct metal volumes on a surface of the functionalized particles to form partially coated particles. The distinct metal volumes are thermally insulated from other volumes of the plurality. A composition of matter includes a discontinuous coating of metal on a surface of a carbon-based material. The carbon-based material is selected from the group consisting of graphene oxide and functionalized carbon nanotubes. | 2020-02-20 |
20200058842 | COMPOSITE SUBSTRATE, SURFACE ACOUSTIC WAVE DEVICE, AND METHOD FOR MANUFACTURING COMPOSITE SUBSTRATE - There are provided a method for manufacturing a substrate excellent in heat dissipation with a small loss in radio frequencies with no need of a high temperature process in which a metal impurity is diffused, and a substrate of high thermal conductivity. A composite substrate according to the present invention is a composite substrate having a piezoelectric single crystal substrate, a support substrate, and an intermediate layer provided between the piezoelectric single crystal substrate and the support substrate. The intermediate layer is a film formed of an inorganic material, and at least a part of the film is thermally synthesized silica. The intermediate layer may be separated into at least two layers along the bonding surface of the composite substrate. The first intermediate layer in contact with the support substrate may be a layer including thermally synthesized silica. | 2020-02-20 |
20200058843 | VIBRATOR DEVICE, METHOD OF MANUFACTURING VIBRATOR DEVICE, ELECTRONIC APPARATUS, AND VEHICLE - A vibrator device including a vibrator element, an IC substrate including a semiconductor substrate configured of a semiconductor having a first conductive type and a circuit electrically coupled to the vibrator element, the first conductive type being any one of an N-type and a P-type, and a lid directly bonded to the semiconductor substrate and configured of a semiconductor having the first conductive type. | 2020-02-20 |
20200058844 | PIEZOELECTRIC SUBSTRATE, SENSOR, ACTUATOR, BIOLOGICAL INFORMATION ACQUISITION DEVICE, AND PIEZOELECTRIC FIBER STRUCTURE - Provided is a piezoelectric substrate, containing an elongate piezoelectric body that is helically wound, in which the piezoelectric body includes an optically active polypeptide, a length direction of the piezoelectric body and a main orientation direction of the optically active polypeptide included in the piezoelectric body are substantially parallel to each other, and the piezoelectric body has a degree of orientation F of from 0.50 to less than 1.00, as determined from X-ray diffraction measurement by the following Formula (a): | 2020-02-20 |
20200058845 | Multilayered magnetic free layer structure for spin-transfer torque (STT) MRAM - A multilayered magnetic free layer structure is provided that includes a first magnetic free layer and a second magnetic free layer separated by a non-magnetic layer in which the second magnetic free layer has higher magnetic damping (greater than 0.01) as compared with the first magnetic free layer. Such a multilayered magnetic free layer structure substantially reduces the switching current needed to reorient the magnetization of the magnetic free layers. The higher magnetic damping value of the second magnetic free layer as compared to the first magnetic free layer improves the switching speed of the magnetic free layers and thus reduces, and even eliminates, write errors. | 2020-02-20 |
20200058846 | MAGNETIC TUNNEL JUNCTION DEVICE AND MAGNETIC RESISTANCE MEMORY DEVICE - Disclosed is a magnetic tunnel junction device whose fixed layer has a simplified structure and in which the number of stacked layers is reduced. The magnetic tunnel junction device comprises a free layer whose magnetization direction is variable, a fixed layer whose magnetization direction is fixed and that is formed as a single layer, and a dielectric layer stacked between the free layer and the fixed layer. One or more of the free layer and the fixed layer are an L1 | 2020-02-20 |
20200058847 | PERPENDICULARLY MAGNETIZED SPIN-ORBIT MAGNETIC DEVICE - A perpendicularly magnetized spin-orbit magnetic device including a heavy metal layer, a magnetic tunnel junction, a first antiferromagnetic layer, a first block layer and a first stray field applying layer is provided. The magnetic tunnel junction is disposed on the heavy metal layer. The first block layer is disposed between the magnetic tunnel junction and the first antiferromagnetic layer. The first stray field applying layer is disposed between the first antiferromagnetic layer and the first block layer. The magnetic tunnel junction comprises a free layer, a tunneling barrier layer, and pinned layer. The tunneling barrier layer is disposed on the free layer. The pinned layer is disposed on the tunneling barrier layer. A film plane area of the free layer is greater than a film plane area of the tunneling barrier layer and a film plane area of the pinned layer. | 2020-02-20 |
20200058848 | Phase-Change Material (PCM) Radio Frequency (RF) Switch with Reduced Parasitic Capacitance - A reduced parasitic capacitance radio frequency (RF) switch includes a phase-change material (PCM) and a heating element underlying an active segment of the PCM and extending outward and transverse to the PCM. A PCM contact connects a PCM routing interconnect with a passive segment of the PCM, wherein the passive segment extends outward and is transverse to the heating element. A heating element contact connects a heating element routing interconnect with a terminal segment of the heating element. The heating element contact is situated cross-wise to the PCM contact. The heating element routing interconnect is situated at a different interlayer metal level relative to the PCM routing interconnect so as to achieve the reduced parasitic capacitance. The heating element routing interconnect can be situated above the heating element. Alternatively, the heating element routing interconnect can be situated below the heating element. | 2020-02-20 |
20200058849 | Phase-Change Material (PCM) Radio Frequency (RF) Switch Using a Chemically Protective and Thermally Conductive Layer - A radio frequency (RF) switch includes a heating element, an aluminum nitride layer situated over the heating element, and a phase-change material (PCM) situated over the aluminum nitride layer. An inside segment of the heating element underlies an active segment of the PCM, and an intermediate segment of the heating element is situated between a terminal segment of the heating element and the inside segment of the heating element. The aluminum nitride layer situated over the inside segment of the heating element provides thermal conductivity and electrical insulation between the heating element and he active segment of the PCM. The aluminum nitride layer extends into the intermediate segment of the heating element and provides chemical protection to the intermediate segment of the heating element, such that the intermediate segment of the heating element remains substantially unetched and with substantially same thickness as the inside segment. | 2020-02-20 |
20200058850 | Circuits for Reducing RF Signal Interference and for Reducing DC Power Loss in Phase-Change Material (PCM) RF Switches - A circuit according to the present application includes a diode or other non-linear device coupled to a heating element of a phase-change material (PCM) radio frequency (RF) switch. The diode or other non-linear device allows an amorphizing pulse or a crystallizing pulse to pass to a first terminal of the heating element. The diode or other non-linear device substantially prevents a pulse generator providing the amorphizing pulse or crystallizing pulse from interfering with RF signals at RF terminals of the PCM RF switch. In an array of PCM cells each including a diode or other non-linear device, the diode or other non-linear device substantially prevents sneak paths that would otherwise enable an amorphizing or crystallizing pulse intended for a heating element of a selected cell of the array to be provided to heating elements of unselected cells of the array. | 2020-02-20 |