08th week of 2013 patent applcation highlights part 16 |
Patent application number | Title | Published |
20130043878 | COMMUNICATION LINE DRIVER PROTECTION CIRCUITRY, SYSTEMS AND METHODS - Embodiments relate to fault detection comparator circuitry and methods that can operate in conjunction with a power-on-reset (POR) scheme to put a chip into a reliable power-down mode upon fault detection to avoid disrupting the communication bus link such that other connected chips and the host can continue to operate. Power-on of the affected chip can then be carried out when the connection with that chip is restored. | 2013-02-21 |
20130043879 | METHOD AND APPARATUS FOR DETECTING EARTH FAULT - A method and an apparatus for detecting an earth fault on a three-phase electric line are provided. The apparatus includes means for determining a neutral admittance on the basis of a residual current and a residual voltage, means for comparing the determined neutral admittance to a predetermined operation characteristic to detect an earth fault on the three-phase electric line, and means for determining one or more harmonic components of the residual current and one or more harmonic components of the residual voltage. The harmonic components have frequencies n*fn such that n≧2 and fn is a fundamental frequency. The means for determining a neutral admittance are configured to use at least one of the determined one or more harmonic components of the residual current and at least one of the determined one or more harmonic components of the residual voltage for determining the neutral admittance. | 2013-02-21 |
20130043880 | Determination of the Fault Current Component of a Differential Current - For the purpose of determining a fault current component of a differential current which is measured as a current sum over a plurality of lines carrying a current of an AC current generator, an electric signal which depends on generator voltages present at the AC current generator with respect to earth potential and which is in phase with a leakage current component of the differential current is generated. The electric signal is scaled by multiplying it by a scaling factor; and the scaled electric signal is subtracted from the differential current to obtain a remainder. The scaling factor is repeatedly updated such that the effective value of the remainder reaches a minimum at the present value of the scaling factor. | 2013-02-21 |
20130043881 | APPARATUS AND METHOD FOR IDENTIFYING HIGH RISK NON-CERAMIC INSULATORS (NCI) WITH CONDUCTIVE OR HIGH PERMITTIVITY DEFECTS - An apparatus and method for identifying the presence of high conductivity or permittivity conditions in a wide range of electrically insulating materials is disclosed. The apparatus includes a grounded enclosure containing electronics for controlling measurement and communication processes and first and second spaced-apart electrode assemblies for engaging an insulator to be tested. The first and second electrode assemblies are mounted in the enclosure for linear movement such that pressing of the first and second electrodes against an insulator causes the electronics to initiate a measurement. | 2013-02-21 |
20130043882 | APPARATUS AND METHOD FOR TESTING ELECTRONIC EQUIPMENT - A thermal wrap for testing electronic components has a web having an inside and an outside surface and a first end and a second end and a thermal element incorporated in said web. An edge element incorporated substantially along at least one edge of said web promotes a thermal seal between said web and the electronic component being tested when the electronic component in installed in the wrap. A closure disposed on the ends may be reversibly closed sufficiently tightly to promote the thermal seal. | 2013-02-21 |
20130043883 | SIGNAL TEST APPARATUS FOR SAS DEVICES - A signal test apparatus for a serial attached Small Computer System Interface (SAS) device includes an SAS female connector to be connected to the SAS device, an SAS male connector to be connected to a server, first and second pairs of subminiature version A (SMA) connectors, and first and second groups of switches. When the first pair of SMA connectors is connected to an oscillograph to test a pair of output signals from the SAS device, the second group of switches are turned on and the first group of switches are turned off to communicate the SAS device with the server. When the second pair of SMA connector is connected to the oscillograph to test another pair of output signals from the SAS device, the first group of switches are turned on and the second group of switches are turned off to communicate the SAS device with the server. | 2013-02-21 |
20130043884 | METHOD AND APPARATUS FOR CALIBRATING DEEP-READING MULTI-COMPONENT INDUCTION TOOLS WITH MINIMAL GROUND EFFECTS - An apparatus and method for calibrating a multi-component induction logging tool. The method may include orienting a Z-transmitter coil to be substantially orthogonal to at least one Z-receiver coil, positioning an X-transmitter coil disposed on the logging tool so that the X-transmitter coil is substantially parallel to a conducting surface; encompassing the Z-transmitter coil, the X-transmitter coil, and at least one Z-receiver coil of the logging tool with at least one conducting loop of a calibrator; and calibrating the logging tool using the calibrator. The apparatus may include a calibrator configured to receive the logging tool. The Z-transmitter coil and the Z-receiver coil may be located on separate subs that are detachable from one another. | 2013-02-21 |
20130043885 | ANTENNA SYSTEM FOR ELECTROMAGNETIC COMPATIBILITY TESTING - An antenna system for electromagnetic compliance testing within a frequency range includes a driven element mounted on a boom and including opposed first and second length-adjustable conductors. A length-adjustable passive element is mounted on the boom and spaced apart from the driven element and including opposed third and fourth length-adjustable conductors. An RF input connector is coupled between a feed path to a feed end of each length-adjustable conductors in the driven element. The feed path is configured to minimize stray reactances and stub effects within the frequency range. | 2013-02-21 |
20130043886 | System for Measuring a Peak Frequency of a Signal for Analyzing Condition of a Subject - A system for measuring a peak frequency of a signal applies a Maximum Entropy Method (MEM) to the signal obtained through transmission and reception of an electromagnetic wave to a subject to obtain a frequency of a peak component to be measured, thus permitting to make an appropriate assessment on a state of the subject. A signal analysis unit performs a spectrum estimation utilizing the MEM applied to a signal part of the phase difference signal with a predetermined short analysis duration, from a phase difference signal obtained by an electromagnetic wave transmitting and receiving unit, to obtain a frequency indicative of occurrence frequency of the peak component, and conducts repeatedly the same process, while shifting a position to be analyzed, corresponding to the analysis duration, thus introducing continuously the frequency. It is therefore possible to know a transition with time of the frequency of the peak component. | 2013-02-21 |
20130043887 | COMMUNICATION METHOD FOR MONITORING PIPELINES - A method for underground pipeline monitoring in which a continuous alternating electrical current having a current frequency in a range of about 1 kHZ to about 8 kHz is imparted onto a pipeline, producing an alternating magnetic field at the current frequency along the pipeline. Distributed along the pipeline is a network of RFID tag sensors which absorb an amount of energy from the alternating magnetic field. The impedance of the sensors is modulated, producing a modulated sensor impedance which is detected at a location proximate the location at which the continuous alternating electrical current is imparted onto the pipeline. | 2013-02-21 |
20130043888 | WIRELESS METHOD AND APPARATUS FOR DETECTING DAMAGE IN CERAMIC BODY ARMOR - A wireless damage detector for ceramic armor plates includes an interrogator and a body armor ceramic plate. The interrogator includes an inductive primary coil having a resonant frequency. The plate includes a corresponding inductive secondary coil adapted to cooperate with the primary coil when the interrogator is positioned in an interrogation position wirelessly adjacent the plate. When in the interrogation position, the primary and secondary coils are inductively coupled, that is, form an inductive coupling, when the primary coil is energized at the resonant frequency. The plate includes at least one self-contained frangible continuity circuit electrically connected to the secondary coil. The inductive coupling induces an electrical current flow in the continuity circuit when the circuit is undamaged. A detector cooperates with the primary and secondary coils when the interrogator is in the interrogation position. The detector detects the inductive coupling. An indicator cooperates with the detector. | 2013-02-21 |
20130043889 | CAPACITANCE EVALUATION APPARATUSES AND METHODS - Apparatus and methods for evaluating leakage currents of capacitances are described. Capacitances having excessive leakage currents may be disabled from use. An example apparatus includes a leakage detection circuit configured to be coupled to a capacitance block. The leakage detection circuit is configured to determine whether a leakage current of a capacitance of the capacitance block exceeds a current limit and is further configured to provide an output indicative of a status of the capacitance. A detection controller is coupled to the leakage detection circuit and a register, and the detection controller is configured to store data in the register indicative of the status of the capacitance based at least in part on the signal from the leakage detection circuit. | 2013-02-21 |
20130043890 | Sensing Method and Circuit for Use with Capacitive Sensing Devices - A sensing method is used for a capacitive sensing device, wherein the capacitive sensing device has a plurality of capacitive sensing components, each of which is charged or discharged by a charging component respectively. The sensing method comprises the steps of: a first sampling step of sampling at least one of charging or discharging time of a capacitive sensing component of the plurality of capacitive sensing components to determine a first sample time for the component sampled, wherein the component sampled and at least one another component of the plurality of capacitive sensing components are charged or discharged simultaneously during the first sampling step; a first comparing step of comparing the first sample time for the component sampled with a reference time; and an outputting step of outputting a trigger signal in the event that the first sample time exceeds the reference time. | 2013-02-21 |
20130043891 | High Voltage Sensing Capacitor and Indicator Device - A high-voltage sensing capacitor as an interface apparatus that may be used to attach an indicator unit to a high-voltage AC electrical bus and to provide safety to maintenance personnel. The high-impedance nature of the sensing capacitor effectively isolates the indicator unit from the high-voltage source to which it is connected. The sensing capacitor can be directly mounted between a high-voltage busbar and an indicator unit to provide visual and/or audible alerts to maintenance personnel when high voltage conditions are detected on the busbar. The sensing capacitor is comprised of a portable, unitary capacitive structure that includes a molded insulator body encapsulating two electrodes. The electrodes only partially or incompletely overlap within the insulator body. The electrode spacing and configuration is structured to provide a deliberate amount of coupling between the two electrodes in the presence of an AC electric field. | 2013-02-21 |
20130043892 | RESISTANCE MEASUREMENT CIRCUIT - A resistance measuring circuit for measuring a resistor includes an amplifier, a transistor, a variable resistor, a first resistor, and a second resistor. The transistor includes a base connected to the output of the amplifier, a collector connected to a direct current (DC) power supply, and an emitter. The first resistor includes a first terminal connected to the DC power source, and a second terminal grounded through the variable resistor and connected to the non-inverting terminal of the amplifier. The second resistor includes a first terminal connected to the inverting terminal of the amplifier and connected to the emitter of the transistor through the resistor to be measured, and a second terminal grounded. | 2013-02-21 |
20130043893 | USE OF SPECIFIC RESISTIVITY MEASUREMENT FOR INDIRECT DETERMINATION OF THE PURITY OF SILANES AND GERMANES AND A CORRESPONDING PROCESS - The invention relates to a method for indirectly determining the purity of silanes and germanes using a device for measuring specific resistance. The invention further relates to a system for industrially producing and/or filling containers with silanes or germanes, including a quality control in which a device is used for measuring specific resistance. | 2013-02-21 |
20130043894 | METHOD AND ARRANGEMENT FOR DETERMINING IMPEDANCE VALUES - A method and an arrangement are provided for determining values of impedance parameters related to a transformer configuration including three single pole voltage transformers each respectively having at least a primary winding, a secondary winding and a tertiary winding. The primary windings are connected to phases of a three phase electric system. The arrangement is configured to conduct an earth fault in the three phase electric system, measure a primary voltage from the faulted phase, measure secondary voltages from the secondary windings, and determine values of one or more impedance parameters related to the transformer configuration on the basis of the measured primary voltage, the measured secondary voltages and an equation relating the primary voltage to the secondary voltages and the one or more impedance parameters. | 2013-02-21 |
20130043895 | FAN SPEED CONTROL DEVICE - A fan speed control device is applied to a fan including a speed control signal port and a speed signal port. The fan speed control device includes a speed regulating circuit. The speed regulating circuit includes a signal control unit electrically connected to the speed signal port of the fan, and an adjustable resistor is electrically connected between the signal control unit and the speed control signal port of the fan. The resistance of the adjustable resistor may be varied to change the voltage and current supplied to the fan, and the rotational speed of the fan changes according to the operating voltage and current supplied. The signal control unit obtains speed signals from the speed signal port and processes and displays the current testing parameters of the fan. | 2013-02-21 |
20130043896 | TEST DEVICE FOR PRINTED CIRCUIT BOARD - A test device for testing a printed circuit board (PCB) includes a base and a measuring device. The measuring device includes a testing pin and is capable of measuring any desired point of the PCB on condition that the pin makes contact with the point at an included angle between the pin and a back surface of the PCB which is larger than a predetermined angle. The distance between the base and the PCB satisfies: H>L tan θ, where H is the vertical distance between the PCB and the base, L is the maximum length of an orthogonal projection of the pin on the PCB when the pin is contacting the point, and θ is the predetermined angle. | 2013-02-21 |
20130043897 | TESTING STACKED DIE - An integrated circuit configured for at-speed testing is described. The integrated circuit includes a first die. The first die includes a transition launch point. The integrated circuit also includes a second die. The second die includes a first observe point. The integrated circuit further includes a first through silicon via. The first through silicon via couples the first die to the second die. | 2013-02-21 |
20130043898 | SYSTEM WITH A DEFECT TOLERANT CONFIGURABLE IC - Some embodiments of the invention provide a system that includes a first defect tolerant configurable integrated circuit and a second IC communicatively coupled to the defect tolerant configurable first IC. | 2013-02-21 |
20130043899 | PARALLEL SCAN DISTRIBUTORS AND COLLECTORS AND PROCESS OF TESTING INTEGRATED CIRCUITS - An integrated circuit ( | 2013-02-21 |
20130043900 | ADJUSTABLE DATA DRIVERS AND METHODS FOR DRIVING DATA SIGNALS - Apparatuses and methods for driving input data signals onto signal lines as output data signals are disclosed. An example apparatus includes a detection circuit, a driver adjust circuit, and a data driver. The detection circuit is configured to detect a characteristic(s) of a group of input data signals to be driven onto adjacent signal lines. A characteristic could be, for example, a particular combination of logic levels and/or transitions for, the group of input data signals. The driver adjust circuit is configured to provide a driver adjustment signal based at least in part on a detection signal, that is provided by the detection circuit. A data driver is configured to drive a respective one of the group of input data signals as a respective one of the output data signals, wherein the data driver is adjusted based at least in part on the driver adjustment signal. | 2013-02-21 |
20130043901 | ON-DIE TERMINATION CIRCUIT - An on-die termination circuit includes a reference period signal generation circuit that generates a reference period signal according to a level of a reference voltage, a first period signal generation circuit that generates a first period signal according to a voltage level of a pad, a period comparison circuit that compares a period of the first period signal with a period of the reference period signal and count a plurality of driving signals, and a driver circuit that drives the pad in response to the plurality of driving signals. | 2013-02-21 |
20130043902 | APPARATUS FOR IMPROVING PERFORMANCE OF FIELD PROGRAMMABLE GATE ARRAYS AND ASSOCIATED METHODS - A field programmable gate array (FPGA) includes a set of monitor circuits adapted to provide indications of process, voltage, and temperature for at least one circuit in the FPGA, and a controller adapted to derive a range of body-bias values for the at least one circuit from the indications of process, voltage, and temperature for the at least one circuit. The FPGA further includes a body-bias generator adapted to provide a body-bias signal to at least one transistor in the at least one circuit. The body-bias signal has a value within the range of body-bias values. | 2013-02-21 |
20130043903 | RADIATION-TOLERANT LEVEL SHIFTING - A system and method for radiation-tolerant level shifting are disclosed. In some embodiments, an integrated circuit may include a plurality of level shifters, where each of the plurality of level shifters configured receive a same logic level in a first voltage domain and to output candidate logic levels in a second voltage domain, and where at least one of the candidate logic levels subject to being different from another one of the candidate logic levels. The integrated circuit may also include a voting circuit coupled to the plurality of level shifters, where the voting circuit is configured to evaluate the candidate logic levels and output a selected logic level based, at least in part, upon the evaluation. | 2013-02-21 |
20130043904 | INTEGRATED CIRCUIT DEVICE, SYNCHRONISATION MODULE, ELECTRONIC DEVICE AND METHOD THEREFOR - An integrated circuit device includes at least a functional module arranged to receive a reference clock signal; a gating component configurable to perform gating of the reference clock signal; and a synchronisation module. The synchronisation module includes a trigger component arranged to receive a request for the functional module, the request being asynchronous with the reference clock signal, and to set an enable signal for the functional module in response to receiving the request therefor; and a synchronisation component arranged to receive the enable signal, and in response to the enable signal being set to: configure the gating component to un-gate the reference clock signal; and synchronize an initial clock cycle of the reference clock signal received by the functional module following the reference clock signal being un-gated. | 2013-02-21 |
20130043905 | GLITCH FREE CLOCK SWITCHING CIRCUIT - A glitch free clock switching circuit includes a first enable synchronization logic that generates a first clock enable in response to a first enable from a first enable generation logic. The clock switching circuit includes a second enable synchronization logic that generates a second clock enable in response to a second enable from a second enable generation logic. A logic gate is coupled to an output of the second enable synchronization logic that selects the second clock signal as a logic gate output if the second enable is logic high. A priority multiplexer receives a first clock signal, the first enable and the logic gate output. The multiplexer configured to select the first clock signal as the clock output if the first enable is logic high, irrespective of the logic gate output. | 2013-02-21 |
20130043906 | CMOS LOGIC CIRCUIT - A CMOS logic circuit includes a resistive element that is connected to a first voltage line at a first end thereof. The CMOS logic circuit includes a first inverter circuit having a first MOS transistor and a second MOS transistor. The CMOS logic circuit includes a second inverter circuit having a third MOS transistor and a fourth MOS transistor. The CMOS logic circuit includes a fifth MOS transistor that is connected in parallel with the resistive element between the first voltage line and the first end of the first MOS transistor and the gate of which is connected to the second end of the third MOS transistor. The CMOS logic circuit includes a sixth MOS transistor that is connected between the first voltage line and the first output terminal. | 2013-02-21 |
20130043907 | Method and system for measuring amplitude and phase difference between two sinusoidal signals - A method and a system for measuring amplitude and phase difference between two sinusoidal signals, using an adaptive filter. The method generally comprises measuring a sample of an output signal of a system excited by a sample of a reference signal; using an adaptive filter and the sample of the reference signal to determine a and b coefficients that minimize a prediction error on the sample of the output signal, iteratively, and determining the amplitude and/or phase of the output of the system using the a and b coefficients. | 2013-02-21 |
20130043908 | SENSOR INTERFACE MAKING USE OF VIRTUAL RESISTOR TECHNIQUES - Some embodiments of the present disclosure relate to a sensor interface module. The sensor interface module includes a comparator having a first comparator input, a second comparator input, and a comparator output. A current- or voltage-control element has a control terminal coupled to the comparator output and also has an output configured to deliver a modulated current or modulated voltage signal to an output of the sensor interface module. A first feedback path couples the output of the current- or voltage-control element to the first comparator input. A summation element has a first summation input, a second summation input, and a summation output, wherein the summation output is coupled to the second comparator input. A supply voltage module provides a supply voltage signal to the first summation input. A second feedback path couples the comparator output to the second summation input. | 2013-02-21 |
20130043909 | PHASE ADJUSTMENT APPARATUS AND CLOCK GENERATOR THEREOF AND METHOD FOR PHASE ADJUSTMENT - A phase adjustment apparatus for providing a clock signal to a core circuit is provided. The core circuit is powered by a core voltage. The phase adjustment apparatus includes two clock receiving ends, a plurality of digital receiving ends and a combination circuit. The two clock receiving ends receive two original clocks having a same frequency while the two original clock signals possess different phases. The digital receiving ends receive a plurality of phase selection signals. The synthesizing circuit is powered by a first voltage lower than the core voltage, and generates the clock signal according to the phase control signals and the two original clock signals. | 2013-02-21 |
20130043910 | DRIVER CIRCUIT FOR DRIVING A LOAD CIRCUIT - Driver circuits ( | 2013-02-21 |
20130043911 | Semiconductor Device and Electronic Device Including Semiconductor Device - It is an object to suppress deterioration in characteristics of a transistor in a driver circuit. A driver circuit includes a first transistor, a second transistor including a gate and one of a source and a drain to which a second signal is inputted, a third transistor whose gate is electrically connected to one of a source and a drain of the first transistor and which controls whether a voltage state of an output signal is set or not by being turned on/off, and a fourth transistor whose gate is electrically connected to the other of the source and the drain of the second transistor and which controls whether a voltage state of an output signal is set or not by being turned on/off. | 2013-02-21 |
20130043912 | START-UP CIRCUIT - Aspects of the disclosure provide a circuit. The circuit includes a depletion mode transistor coupled to a power supply and a current path coupled with the depletion mode transistor in series to provide a current to charge a capacitor. The current path has a first resistance during a first stage, such as when the circuit initially receives power, and has a second resistance during a second stage when the capacitor is charged to have a predetermined voltage level. | 2013-02-21 |
20130043913 | FREQUENCY DIVIDER FOR GENERATING OUTPUT CLOCK SIGNAL WITH DUTY CYCLE DIFFERENT FROM DUTY CYCLE OF INPUT CLOCK SIGNAL - A frequency divider includes a plurality of logic circuit blocks. Each of the logic circuit blocks has a plurality of control terminals. At least one of the control terminals of one of the logic circuit blocks is arranged to receive an input clock signal having a first duty cycle. At least one of the remaining control terminals of the one of the logic circuit blocks is arranged to couple another one of the logic circuit blocks by a positive feedback. A clock signal at the at least one of the remaining control terminals has a second duty cycle different from the first duty cycle. Each of the logic circuit blocks includes a plurality of first transistors coupled in parallel between a first reference voltage and an output terminal, and a plurality of second transistors coupled in series between a second reference voltage and the output terminal. | 2013-02-21 |
20130043914 | TIME-BASED APPARATUS AND METHOD TO MITIGATE SEMICONDUCTOR AGING EFFECTS - Systems, methods, and computer readable media that can mitigate the effects of semiconductor aging in a semiconductor device are described. Traditional methods of mitigating semiconductor aging can be wasteful since they overcorrect for aging using a high operational voltage. The approach discussed herein steps up the operational voltage for the electronic device with time based on predetermined aging models. This allows power consumption by the electronic device, particularly early in the designed operational life, to be much less than it would otherwise be. | 2013-02-21 |
20130043915 | CIRCUITS AND METHODS FOR SIGNAL TRANSFER BETWEEN DIFFERENT CLOCK DOMAINS - In certain embodiments, a circuit for transferring signals from a source clock domain to a destination clock domain comprises a first pulse generation circuit, a hold flip-flop circuit, a clocked synchronizer circuit and a second pulse generation circuit. The first pulse generation circuit, operable in the source clock domain, generates a source data pulse from a source data signal. The hold flip-flop circuit, operable in the source clock domain, is configured to hold the source data pulse. The clocked synchronizer circuit, operable in the destination clock domain, samples the source data pulse received from the hold flip-flop circuit, where source data pulse held at the output of the hold flip-flop circuit is cleared when the source data pulse is sampled by the clocked synchronizer circuit. The second pulse generation circuit, operable in the destination clock domain, is configured to generate a destination data pulse from the sampled source data pulse. | 2013-02-21 |
20130043916 | Wave Clocking - Embodiments provide systems and methods for dynamically regulating the clock frequency of an integrated circuit (IC) based on the IC supply voltage. By doing so, the clock frequency is no longer constrained by a worst-case voltage level, and a higher effective clock frequency can be supported, increasing the IC performance. Embodiments include a wave clocking system which uses a plurality of delay chains configured to match substantially the delays of respective logic paths of the IC. As the delays of the logic paths vary with supply voltage and temperature changes, the delay chains matched to the logic paths experience substantially similar changes and are used to regulate the clock frequency of the IC. | 2013-02-21 |
20130043917 | HARDWARE CONTROLLED PLL SWITCHING - A system and method for efficiently managing multiple PLLs on a system on a chip (SOC). A SOC includes a hardware phase lock loop (PLL) switching control block coupled to a software interface. The hardware PLL switching (HPS) control block receives PLL switch requests from software. The request identifies a given core clock received by a given processing core of multiple processor cores on the SOC and indicates the identified core clock is not to be provided anymore by a current PLL. The request indicates a given search method including search conditions. The HPS control block searches for a target PLL that satisfies these search conditions. In response to finding the target PLL, the HPS control block changes clock network connections and parameters across the die of the SOC. These changes across the die disconnect the identified core clock from the current PLL and connects the identified core clock to the target PLL. | 2013-02-21 |
20130043918 | MULTI PHASE CLOCK SIGNAL GENERATOR, SIGNAL PHASE ADJUSTING LOOP UTILIZING THE MULTI PHASE CLOCK SIGNAL GENERATOR, AND MULTI PHASE CLOCK SIGNAL GENERATING METHOD - A multi-phase clock signal generator, comprising: a ring phase shifting loop, including a plurality of controllable delay cells, for generating output clock signals having different phases via the controllable delay cells according to a input clock signal, wherein delay amount of the controllable delay cells are determined by a biasing voltage; a phase skew detecting circuit, for computing phase differences of the output clock signals to generate a phase skew detecting signal; and a biasing circuit, for providing the biasing voltage according to the phase skew detecting signal. The above-mentioned ring phase shifting loop can operate independently from the multi-phase clock signal generator, without receiving the biasing voltage, for phase-shifting a input clock signal to generate output clock signals with different phases, wherein the output clock signals are respectively output at different output terminals respectively located between the phase shifting units. | 2013-02-21 |
20130043919 | SEMICONDUCTOR DEVICE HAVING DELAY LINE - Disclosed herein is a device that includes a plurality of one-shot pulse generation circuits connected in series between an input node and an output node. Each of the one-shot pulse generation circuits receives an input clock signal supplied from previously connected one-shot pulse generation circuit to output an output clock signal to subsequently connected one-shot pulse generation circuit. Both of a rising edge and a falling edge of the output clock signal are controlled based on one of a rising edge and a falling edge of the input clock signal. A time period from one of the rising edge and the falling edge of the output clock signal to the other of the rising edge and the falling edge of the output clock signal being variable. | 2013-02-21 |
20130043920 | DIGITAL PHASE-LOCKED LOOP APPARATUS USING FREQUENCY SHIFT KEYING AND METHOD OF CONTROLLING THE SAME - A digital phase-locked loop apparatus using FSK includes a PFD detecting phase differences between a reference clock and a frequency-divided signal, and a first adder for generating first digital control codes by adding first digital codes, second digital codes, and channel frequency codes including channel information to each other, the first digital codes being converted from time differences between first and second pulses. The apparatus further includes a digital filter correcting errors of the first digital control codes to generate second digital control codes, a DCO for varying an oscillating frequency in accordance with a digital tuning word based on the second digital control codes, and a dual modulus division unit dividing the oscillating frequency into a frequency-divided signal. | 2013-02-21 |
20130043921 | GLITCH HARDENED FLOP REPEATER - A repeater circuit is disclosed. The circuit includes an input stage configured to receive an input signal and a clock signal. An output stage is configured to drive an output signal on an output node to a first state responsive to a first transition of the input signal on the input node concurrent with a first phase of the clock signal. The input stage is configured to activate a first driver circuit of the output stage responsive to a first transition of the input signal. A reverse stage is configured to assert a first inhibit signal at a delay time subsequent to activation of the first driver circuit, which is configured to be deactivated responsive to assertion of the first inhibit signal. Assertion of the first inhibit signal is prevented responsive to a second transition of the input data signal occurring before the delay time has elapsed. | 2013-02-21 |
20130043922 | SUPPLY COLLAPSE DETECTION CIRCUIT - A supply collapse detection circuit is described. The supply collapse detection circuit includes threshold detection circuitry coupled to a first power supply and to a second power supply that provides a second voltage. The supply collapse detection circuit also includes supply collapse output circuitry coupled to the threshold detection circuitry to receive a detection signal when the second voltage drops. The supply collapse output circuitry includes an output node to provide an output signal indicating the drop. The supply collapse detection circuit additionally includes feedback circuitry coupled to the first power supply, to the threshold detection circuitry and to the supply collapse output circuitry. The feedback circuitry reduces leakage when the second voltage drops. | 2013-02-21 |
20130043923 | UNIFORM-FOOTPRINT PROGRAMMABLE MULTI-STAGE DELAY CELL - Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay values. The delay stage includes M parallel-coupled inverter stages. Each parallel-coupled inverter stage includes N pairs of stacked PMOS transistors and stacked NMOS transistors. The N transistor pairs have configurable source-drain node connections between a drain node and a source node of each transistor in the pair, wherein the selectable delay value corresponds to a configuration of the configurable source-drain node connections to adjust a delay value of each of the M inverter stages. | 2013-02-21 |
20130043924 | Systems, Methods, and Apparatus for High-Speed Signal Buffer Circuitry - Certain embodiments of the invention may include systems, methods, and apparatus for providing an integrated high-speed signal buffer circuit. According to an example embodiment of the invention, a method is provided for driving a clock signal. The method includes configuring a clock driver circuit with a differential clock buffer output connected to one or more clock lines; matching an operational output resistance of the differential clock buffer output approximately with an input impedance associated with the one or more clock lines; receiving a clock reference signal; applying the clock reference signal to inputs associated with the differential clock driver circuit; and driving the one or more clock lines with the differential clock buffer output. | 2013-02-21 |
20130043925 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING VOLTAGE STABILIZING CIRCUIT - A semiconductor integrated circuit includes a first voltage supply unit, a second voltage supply unit configured to supply a voltage with a level different from that of the first voltage supply unit, and a voltage stabilizing unit connected between the first and second voltage supply units, and including at least one discharge path that includes a clamping section configured to temporarily drop a level of a voltage introduced from the first or second voltage supply unit, and a discharge section configured to discharge the voltage having passed through the clamping section to the second or first voltage supply unit. | 2013-02-21 |
20130043926 | LEVEL SHIFT CIRCUIT - In a level shift circuit allows satisfactory operation with short delay time in the case of low-voltage setting of a low-voltage source, for example, when a state of an input signal IN transitions from a H (VDD) level to a L level, a node W | 2013-02-21 |
20130043927 | Integrated Circuit With Pre-Heating For Reduced Subthreshold Leakage - Certain semiconductor processes provide for the use of multiple different types of transistors with different threshold voltages in a single IC. It can be shown that in certain ones of these semiconductor processes, the speed at which high threshold transistors can operate at decreases with decreasing temperature. Thus, the overall processing speed of an IC that implements high threshold transistors is often limited by the lowest temperature at which the IC is designed (or guaranteed) to properly function. Embodiments of a system and method that overcome this deficiency by “pre-heating” the IC (or at least portions of the IC that implement the high threshold transistors) such that the IC can operate at a frequency (once pre-heated) higher than what would otherwise be possible for a given, minimum temperature at which the IC is designed (or guaranteed) to properly function at are provided. | 2013-02-21 |
20130043928 | MOTION SENSING SWITCH - Disclosed is a motion detection switch, and more particularly a motion detection switch which can recognize motion of a reflector moved at an upper side of a display part of a mobile phone, and can control the mobile phone without any touching operation. The motion detection switch recognizes motion of a reflection body moved at an upper side of a display part of a portable terminal and controls the portable terminal, including a base which is disposed at an upper side of a main body of the portable terminal having the display part, which is outside the display part; a light receiving device which is disposed at the base; a plurality of light emitting devices which are disposed at the base so as to be symmetric with respect to the light receiving device; and a control device which operates the light emitting devices. | 2013-02-21 |
20130043929 | POWER SUPPLY DEVICES AND CONTROL METHOD THEREOF - A power supply device is provided. The power supply device provides a maintenance voltage at an output terminal to a system chip of a system and includes a first battery, a capacitor, a charging circuit, and a monitoring circuit. The first battery provides a battery voltage. The capacitor stores a capacitor voltage. The charging circuit is coupled to the capacitor. The monitoring circuit detects whether the battery voltage is less than a first threshold and whether the capacitor voltage is larger than a second threshold and generates a control signal according to the determination result. When the monitoring circuit detects that the battery voltage is less than the first threshold and the capacitor power supply device voltage is not larger than the second threshold, the monitoring circuit asserts the control signal to control the charging circuit to charge the capacitor. | 2013-02-21 |
20130043930 | CHARGE PUMP - A charge pump exhibiting a voltage compensation function is provided. The charge pump includes: a first current generator, a first semiconductor device, a second current generator, a second semiconductor device, and a voltage regulator. The voltage regulator dynamically adjusts a voltage level at the gate of the first or second semiconductor device so as to adjust a first current or a second current outputted to a current output node. In addition, the voltage regulator provides a bias voltage at the current output node when both the first and second semiconductor devices are turned off. | 2013-02-21 |
20130043931 | SINGLE CHARGE-PUMP BUCK-BOOST FOR PROVIDING INDEPENDENT VOLTAGES - Disclosed is a charge pump having first and second outputs and at least one capacitor. A plurality of switches are coupled to the at least one capacitor for selectively coupling the at least one capacitor between a high voltage node and a low voltage node, and for selectively coupling the at least one capacitor to the first output and the second output. A switch controller is adapted to generate control signals for the plurality of switches to selectively couple the at least one capacitor between the high voltage node and the low voltage node during charging, and to selectively couple the at least one capacitor to the first output and the second output during discharging that output a first voltage pulse from the first output and a second voltage pulse from the second output such that the first voltage pulse and the second voltage pulse are asymmetrical and coincidental. | 2013-02-21 |
20130043932 | CHARGE-PUMP SYSTEM FOR PROVIDING INDEPENDENT VOLTAGES - Disclosed is a charge pump system having a charge pump with a switch control input, a voltage output terminal, a high voltage terminal coupled to a high voltage node and a low voltage terminal coupled to a low voltage node. Also included is a first buck/boost switch having a first terminal coupled to the voltage output terminal, a second terminal coupled to a first output node, and a first control terminal for receiving a first control signal. A second buck/boost switch includes a first terminal coupled to the voltage output terminal, a second terminal coupled to a second output node, and a control terminal for receiving a second control signal. Further included is a switch controller that is adapted to generate the first control signal and the second control signal such that voltage pulses output from the first output node and the second output node, respectively, are asymmetrical and coincidental. | 2013-02-21 |
20130043933 | INTERNAL VOLTAGE GENERATOR AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A semiconductor device including an internal voltage generator circuit that provides an internal voltage having a different level depending on the operation speed is provided. The semiconductor device includes an internal voltage generator circuit configured to receive operation speed information to generate an internal voltage having a different level depending on the operation speed; and an internal circuit operated using the internal voltage. | 2013-02-21 |
20130043934 | Analog floating gate charge loss compensation circuitry and method - An analog floating gate circuit ( | 2013-02-21 |
20130043935 | POWER BOOSTING CIRCUIT FOR SEMICONDUCTOR PACKAGING - A microelectronic package includes a microelectronic element operable to output a discrete-value logic signal indicating an imminent increase in demand for current by at least some portion of the microelectronic element. An active power delivery element within the package is operable by the logic signal to increase current delivery to the microelectronic element. | 2013-02-21 |
20130043936 | Method And Apparatus For Controlling Power Supply - A method for controlling the power supply of an integrated circuit, the power supply comprising a power supply unit powered by a main voltage and possessing several transistor groups, comprising turning on in succession at least two transistor groups in order to deliver, as an output from each group, to at least one part of the integrated circuit, an elementary supply voltage derived from the main voltage, characterized in that the method comprises at least one elementary power phase for supplying power to said at least one part of the integrated circuit, wherein the phase comprises defining voltage thresholds respectively associated with the transistor groups, turning on a first transistor group, the first group delivering a first elementary supply voltage and turning on at least one second group when the first elementary supply voltage is higher than or equal to the voltage threshold associated with the second group. | 2013-02-21 |
20130043937 | APPARATUS AND METHOD FOR ELECTRICAL BIASING - As provided herein, in some embodiments, power consumption and/or chip area is reduced by bias circuits configured to provide bias conditions for more than one active circuit, thereby reducing the number of bias circuits in a design. Shared bias circuits may reduce the aggregate amount of on-chip area utilized by bias circuitry and may also reduce the total power consumption of a chip. Additionally and/or alternatively, bias circuits disclosed herein are configured to provide outputs that are less susceptible to changes in the voltage supply level. In particular, in some embodiments, bias circuits are configured to provide relatively constant bias conditions despite changes in the voltage supply level. In some embodiments, bias circuits are configured to provide bias conditions that compensate for perturbations caused by changes other inputs, in order to stabilize a particular operating point. | 2013-02-21 |
20130043938 | LOW VOLTAGE ANALOG SWITCH - A switch for an analog signal may include a main MOS transistor whose source forms an input terminal of the switch and whose drain forms an output terminal of the switch, a capacitor having a first terminal permanently connected to the source of the main transistor, a circuit for charging the capacitor, and a first auxiliary transistor configured to connect the second terminal of the capacitor to the gate of the main transistor in response to a control signal. The charge circuit may include a resistor permanently connecting the second terminal of the capacitor to a power supply line. The capacitor and the resistor may form a high-pass filter having a cutoff frequency lower than the frequency of the analog signal. | 2013-02-21 |
20130043939 | Integrated Circuit With an Adaptable Contact Pad Reconfiguring Architecture - An apparatus and method are disclosed for providing test mode contact pad reconfigurations that expose individual internal functional modules or block groups in an integrated circuit for testing and for monitoring. A plurality of switches between each functional module switches between passing internal signals among the blocks and passing in/out signals external to the block when one or more contact pads are strapped to input a pre-determined value. Another set of switches between the functional modules and input/output contact pads switch between functional inputs to and from the functional modules and monitored signals or input/output test signals according to the selected mode of operation. | 2013-02-21 |
20130043940 | BACK-TO-BACK STACKED DIES - Embodiments disclosed herein provide for a circuit including first die having an active side and a backside, wherein the first die is flip-chip mounted to a carrier. The circuit also includes a second die stacked on the backside of the first die, wherein the second die is stacked on the first die such that a backside of the second die is facing the backside of the first die and an active side of the second die faces away from the first die. | 2013-02-21 |
20130043941 | CURRENT-SENSING CIRCUIT - In one embodiment, a circuit is provided. The circuit includes a low-ohmic circuit and a a power supply node configured and arranged for providing a supply voltage across the low-ohmic circuit to a load from which current can be drawn. The circuit also includes a current reference circuit, configured and arranged for setting a current reference level that is based on a portion of the current from the power supply node, and a current-sensing circuit. The current-sensing circuit senses and is responsive to current passing through the low-ohmic circuit. The current-sensing circuit operates in a normal mode, in which the current-sensing circuit senses an amount of current passing through the low ohmic circuit that is less than the current threshold level, and in an over-current mode, in which the current-sensing circuit senses an amount of current passing through the low ohmic circuit that is greater than the current threshold level. | 2013-02-21 |
20130043942 | SENSING DEVICES AND DISPLAY DEVICES - A sensing device is provided. The sensing device successively operates in a plurality of operation periods and includes a plurality of first electrodes, a plurality of differential amplifiers, and a plurality of sensing circuits. The first electrodes are disposed successively. The differential amplifiers at least comprise a first differential amplifier and a second differential amplifier. Each of the differential amplifiers comprises a first input terminal and a second input terminal. Each of the sensing circuits has an input terminal and an output terminal. The sensing circuits at least comprise first, second, and third sensing circuits. The input terminals of the sensing circuits are coupled to the first electrodes. The output terminals of sensing circuits are coupled to the differential amplifiers. The output terminal of at least one of the sensing circuits is coupled to both of the first differential amplifier and the second differential amplifier. | 2013-02-21 |
20130043943 | GAIN STAGE WITH DC OFFSET COMPENSATION AND METHOD THEREOF - A gain stage with DC offset compensation includes a gain amplifier and a compensation device. The gain amplifier is arranged to amplify an input signal according to a gain control signal. The compensation device is arranged to perform a DC offset compensation applied to the gain amplifier with an operating configuration based on the gain control signal. | 2013-02-21 |
20130043944 | CASCADED CONVERGED POWER AMPLIFIER - A first radio frequency (RF) power amplifier (PA) stage, a second RF PA stage, and an alpha RF switch are disclosed. The first RF PA stage provides a first RF output signal. During a first alpha mode, the alpha RF switch forwards the first RF output signal to the second RF PA stage, such that the first RF PA stage functions as a driver stage and the second RF PA stage functions as a final stage. However, during one of a group of alpha modes, the alpha RF switch forwards the first RF output signal to provide a corresponding one of a group of alpha transmit signals, such that the first RF PA stage functions as a final stage. Further, the first alpha mode is not one of the group of alpha modes. | 2013-02-21 |
20130043945 | System and Method for High-Frequency Amplifier - A system and method for operating an amplifier system is provided. The amplifier system includes an input providing a direct coupling configured to receive a high-frequency input signal having a frequency in at least one of a radiofrequency (RF) and microwave range. The amplifier system also includes an amplifier including a dielectric material separating at least two superconducting layers forming an amplifier loop configured to receive the high-frequency input signal and deliver an amplified signal. The amplifier system includes an output providing a direct coupling configured to deliver the amplified signal. | 2013-02-21 |
20130043946 | LOW NOISE AMPLIFIERS WITH COMBINED OUTPUTS - Multiple low noise amplifiers (LNAs) with combined outputs are disclosed. In an exemplary design, an apparatus includes a front-end module and an integrated circuit (IC). The front-end module includes a plurality of LNAs having outputs that are combined. The IC includes receive circuits coupled to the plurality of LNAs via a single interconnection. In an exemplary design, each of the plurality of LNAs may be enabled or disabled via a respective control signal for that LNA. The front-end module may also include receive filters coupled to the plurality of LNAs and a switchplexer coupled to the receive filters. The front-end module may further include at least one power amplifier, and the IC may further include transmit circuits coupled to the at least one power amplifier. | 2013-02-21 |
20130043947 | OUTPUT CIRCUIT - An output circuit includes first to fourth transistors, first and second constant current units, and a differential pain The gates of the first and second transistors are supplied with two input signals, respectively. The drain of the first transistor is coupled to the drain of the third transistor and the gate of the fourth transistor. The drain of the second transistor is coupled to the gate of the third transistor and the drain of the fourth transistor. The first constant current unit is coupled to the sources of the third and fourth transistors. The differential pair includes two transistors, and the gates of the two transistors are coupled to the drains of the first and second transistors, respectively. The second constant current unit is coupled to the sources of the two transistors. Two output signals are output from two nodes respectively corresponding to the drains of the two transistors. | 2013-02-21 |
20130043948 | SEMICONDUCTOR DEVICE FOR SIGNAL AMPLIFICATION - A semiconductor device for transmitting-signal amplification which has a fine resolution, a high dynamic range, a small occupied area, and low power consumption, is realized. An input signal amplitude is reduced every one half by a ladder network, and a transconductance amplifier stage is arranged corresponding to each node of the ladder network. An output of the transconductance amplifier stage is coupled to an output signal line in common. According to a control word WC<21:0>, the transconductance amplifier stage is enabled selectively, and the output current which appears in the output signal line is added. | 2013-02-21 |
20130043949 | METHOD OF FORMING A CIRCUIT HAVING A VOLTAGE REFERENCE AND STRUCTURE THEREFOR - In one embodiment, two transistors are coupled in a current mirror configuration to form a delta voltage, and an amplifier is configured to control a first current carrying electrode of each of the first and second transistors at a substantially constant voltage. | 2013-02-21 |
20130043950 | COMMON MODE INPUT CONTROL FOR SWITCH CAPACITOR AMPLIFIER IN PIPELINE ANALOG-TO-DIGITAL CONVERTER - A common mode bias circuit may include a weak common mode bias generator and a common mode bias capacitance. During a first state of the common mode bias circuit, the weak common mode bias generator may be coupled to the common mode bias capacitance and may impart to them a predefined common mode signal level. During a second state of the common mode bias circuit, the common mode bias capacitance may be coupled to differential inputs of an amplifier in a manner that establishes an input common mode level for the amplifier. | 2013-02-21 |
20130043951 | CLASS E AMPLIFIER OVERLOAD DETECTION AND PREVENTION - Systems, methods and apparatus are disclosed for amplifiers for wireless power transfer. In one aspect a method is provided for controlling operation of an amplifier, such as a class E amplifier. The method may include monitoring an output of the amplifier. The method may further include adjusting a timing of an enabling switch of the amplifier based on the output of the amplifier. | 2013-02-21 |
20130043952 | Circuit and Method for Adjusting an Offset Output Current for an Input Current Amplifier - A circuit and a method for correcting an offset is provided that includes a current amplifier and an adjusting circuit for correcting an offset of an output current of the current amplifier. Wherein the adjusting circuit has a controlled current source, an output of the controlled current source is connected to the current amplifier for impressing an output current of the controlled current source in the current amplifier, an input of the controlled current source to form a regulation element of a control loop is connected by a first switching device of the adjusting circuit to an output of the current amplifier and to form a holding element is disconnected from the output of the current amplifier by the first switching device. The controlled current source, acting as a regulation element in the control loop, is set up to regulate the offset to a minimum by setting of a current value of the output current, and the controlled current source, acting as a holding element, is set up to hold the current value, associated with the minimum, of the output current. | 2013-02-21 |
20130043953 | METHODS, CIRCUITS AND SYSTEMS FOR REGULATING THE OUTPUT POWER OF A TRANSMISSION SYSTEM - Disclosed are methods, circuits and systems for regulating the output power of a transmission system. There may be provided a power amplifier (“PA”) adapted to operate across a range of supply voltages. The PA may operate under different bias profiles. There may be provided power amplifier regulation circuitry which may include a PA bias profile generator adapted to generate one or more bias profiles, wherein a given bias profile is associated with a given bias signal for the PA. A bias profile associated with a given bias signal for a given PA may include one or more PA parameters or settings to be applied to the given PA when it is operating with the given bias signal. | 2013-02-21 |
20130043954 | MONOLITHIC MICROWAVE INTEGRATED CIRCUIT (MMIC) INCLUDING AIR BRIDGE COUPLER - A monolithic microwave integrated circuit (MMIC) includes a transistor, coupled line and multiple air bridges. The coupled line is configured to output a coupled signal from the transistor, the coupled line running parallel to a drain of the transistor. The air bridges connect the drain of the transistor with a bond pad for outputting a transistor output signal, the bridges being arranged parallel to one another and extending over the coupled line. The air bridges and the coupled line effectively provide coupling of the transistor output signal to a load. | 2013-02-21 |
20130043955 | SIGNAL AMPLIFICATION CIRCUITS FOR RECEIVING/TRANSMITTING SIGNALS ACCORDING TO INPUT SIGNAL - An exemplary signal amplification circuit includes an input stage, a plurality of output stages and a selecting stage. The input stage has an input node for receiving an input signal and an output node for outputting an intermediate signal. The output stages are coupled to a plurality of output ports of the signal amplification circuit, respectively. Each output stage generates a corresponding processed signal to a corresponding output port according to a gain and the intermediate signal when enabled. The selecting stage selectively couples the output node of the input stage to at least one of the output stages. The signal amplification circuit outputs a first number of processed signal(s) when operated under a first operational mode, and outputs a second number of processed signal(s) when operated under a second operational mode. | 2013-02-21 |
20130043956 | SYSTEMS AND METHODS FOR A NANOFABRICATED OPTICAL CIRCULAR POLARIZER - System and methods for a nanofabricated optical circular polarizer are provided. In one embodiment, a nanofabricated circular polarizer comprises a quarter wave plate; and a linear polarizer formed on a surface of the quarter wave plate. | 2013-02-21 |
20130043957 | LOW DISTORTION IMPEDANCE SELECTION AND TUNABLE IMPEDANCE CIRCUITS - A tunable impedance circuit can include a fixed impedance and one or more impedance selection circuits. Each impedance selection circuit can include a first impedance connected to a first interface terminal, a second impedance connected to a second interface terminal, and a plurality of series-connected transistors connected between the first and second impedances. Each impedance selection circuit can also include a plurality of drive impedance networks connected to gates, sources, drains, bodies, and isolation regions of the series-connected transistors, and a control circuit to provide a plurality of control signals to the drive impedance networks to turn on and turn off the series-connected transistors. For each impedance selection circuit, turning on and turning off the respective plurality of series-connected transistors can bring the series combination of the respective first and second impedances into and out of electrical communication with, e.g., into and out of parallel with, the fixed impedance. | 2013-02-21 |
20130043958 | DIGITALLY CONTROLLED OSCILLATOR - A digitally controlled oscillator is provided. The digitally controlled oscillator includes a pair of transistors cross-coupled to each other, a switched capacitor array coupled to the pair of transistors and a plurality of frequency tracking units coupled to the pair of transistors. The pair of transistors provides an output signal. The switched capacitor array tunes a frequency of the output signal. The frequency tracking units tune the frequency of the output signal to a target frequency. At least one of the frequency tracking units is capable of selectively providing a first capacitance and a second capacitance. A tuning resolution of the frequency tracking unit is determined by a difference between the first and second capacitances. | 2013-02-21 |
20130043959 | RESONATING ELEMENT, RESONATOR, ELECTRONIC DEVICE, ELECTRONIC APPARATUS, AND MOBILE OBJECT - A piezoelectric resonating element includes a piezoelectric substrate that includes a rectangular vibrating section and a thick section integrally formed with the vibrating section, excitation electrodes, and lead electrodes. The thick section includes a first thick section and a second thick section of which one end is formed continuous to the first thick section. The first thick section includes a first inclined section of which the thickness changes and a first thick section main body of a quadrangle column shape, and at least one slit is provided in the first thick section. | 2013-02-21 |
20130043960 | RESONATING ELEMENT, RESONATOR, ELECTRONIC DEVICE, ELECTRONIC APPARATUS, MOVING VEHICLE, AND METHOD OF MANUFACTURING RESONATING ELEMENT - A piezoelectric resonating element includes a piezoelectric substrate having a rectangular vibrating portion and a thick-walled portion, excitation electrodes and, and lead electrodes. The thick-walled portion includes a fourth thick-walled portion, a third thick-walled portion, a first thick-walled portion, and a second thick-walled portion. The third thick-walled portion includes a third slope portion and a third thick-walled body, and at least one slit is formed in the third thick-walled portion. | 2013-02-21 |
20130043961 | DUPLEXER WITH SHIELDING BONDWIRES BETWEEN FILTERS - A duplexer includes first and second filters, and a first shielding bondwire. The first filter includes a first bondwire connecting the first filter to a printed circuit board, the first bondwire forming a portion of a first virtual loop having a first virtual area, where first current passing through the first bondwire generates a first magnetic field. The second filter includes a second bondwire connecting the second filter to the printed circuit, the second bondwire forming a portion of a second virtual loop having a second virtual area. The first shielding bondwire includes first and second ends connected to a conductor of the printed circuit board to form a closed electrical first shielding loop having a corresponding first shielding area. The magnetic field induces shielding current in the first shielding loop, which generates a first compensating magnetic field that attenuates the first magnetic field. | 2013-02-21 |
20130043962 | DIGITAL STEP ATTENUATOR UTILIZING THERMOMETER ENCODED MULTI-BIT ATTENUATOR STAGES - A digital step attenuator with thermometer encoded attenuator stages is disclosed. In one embodiment, Embodiments disclosed in the detailed description may include a digital step attenuator, programmable thermometer encoded attenuator stages, the digital step attenuator may include a cascade of programmable thermometer encoded attenuator stages. Each stage may be provided by a programmable impedance array including a plurality of impedances arranged in parallel. The impedance of each of the plurality of each stage may change monotonically by switchably inserting or removing one of the plurality of impedances in the arrays. The control circuit may govern the attenuation level of each of the thermometer encoded accumulator stages as a function of a thermometric codeword, which controls the switches in the arrays. | 2013-02-21 |
20130043963 | OVERCURRENT SWITCHING DEVICE - An overcurrent switching device for an electric circuit to be monitored, which has interrupter contact means ( | 2013-02-21 |
20130043964 | High-Frequency Transformer - A high-frequency transformer includes a plurality of cores having a central leg, the cores being arranged to form core windows that are separated by the central legs. A primary winding has a predetermined length of electrically conductive wire that is wound about the central legs and extends through each of the core windows. One or more secondary windings extend through each core window, generally adjacent to the primary winding. The core windows are sized and shaped to provide a predetermined amount of leakage inductance between the primary and secondary windings, and are further adapted to provide a path for cooling air through an interior portion of the transformer. | 2013-02-21 |
20130043965 | REDUCED NOISE HIGH- OR MEDIUM-VOLTAGE EQUIPMENT INCLUDING AN IMMERSED INDUCTION-ACTIVATED PORTION - High- or medium-voltage equipment comprising an induction-activated portion, a tank surrounding the active portion and filled with a dielectric fluid, such as oil, and passive acoustic reduction means for reducing acoustic waves coming from the active portion and propagating in the dielectric fluid. According to the invention, the passive means create an interference field that divides the propagated waves into two groups of waves of opposite phase that interfere with each other in a zone that is at a distance from the walls of the tank so as to at least limit the amplitude of the waves before they make contact with said walls. The equipment provides an effective solution for significantly reducing the noise that is propagated by the dielectric fluid medium. | 2013-02-21 |
20130043966 | TRANSFORMER TAP PROJECTION AND COVER - Tap covers and projections for an electrical device are provided. The tap projections have bosses or taps raised from a surface of the tap projection and encapsulated with a resin except for an outer surface of the bosses or taps. The tap projections may have a channel or recess between individual bosses or taps to prevent degradation of the insulation between the respective adjacent bosses or taps. When a tap cover is provided, it is pushed on or bolted to the tap projection. The tap cover may be provided for an individual tap or an entire tap projection and may be formed of a resin or an elastomeric material. The tap cover has a first generally planar surface and a second generally annular surface having a circumferentially-extending groove on an inside surface. The circumferentially-extending groove is located slightly beneath the second generally annular surface. The groove of the tap cover is designed to fully engage with a raised lip of a tap projection or individual tap of a transformer. Another embodiment of the tap cover has openings to receive epoxy-headed bolts that are used to connect the tap cover to the tap projection through the tap connectors. | 2013-02-21 |
20130043967 | ROGOWSKI COIL ASSEMBLIES AND METHODS FOR PROVIDING THE SAME - Rogowski coil assemblies and methods for providing or forming Rogowski coil assemblies are provided. A Rogowski coil assembly may include a printed circuit board and a plurality of Rogowski coil sections mounted to an external surface of the printed circuit board by one or more respective circuit traces. The circuit traces may retain and connect the plurality of Rogowski coil sections. | 2013-02-21 |
20130043968 | VERTICALLY ORIENTED SEMICONDUCTOR DEVICE AND SHIELDING STRUCTURE THEREOF - The present disclosure provides a semiconductor device. The semiconductor device includes a substrate that spans in an X-direction and a Y-direction that is orthogonal to the X-direction. The semiconductor device includes an interconnect structure formed over the substrate in a Z-direction that is orthogonal to both the X-direction and the Y-direction. The interconnect structure includes a plurality of metal lines interconnected together in the Z-direction by a plurality of vias. The interconnect structure contains a transformer device that includes a primary coil and a secondary coil. The primary coil and the secondary coil are each wound at least partially in the Z-direction. | 2013-02-21 |
20130043969 | CHOKE COIL - The present invention provides a choke coil capable of applying an optimum magnetic bias without causing degradation of magnetic characteristics and any adverse effect on a neighboring device which would be caused by a temperature rise, therefore capable of adequately accommodating higher current. A choke coil according to the present invention includes a toroid coil | 2013-02-21 |
20130043970 | METHOD AND APPARATUS FOR ACHIEVING GALVANIC ISOLATION IN PACKAGE HAVING INTEGRAL ISOLATION MEDIUM - An inductor device having an improved galvanic isolation layer arranged between a pair of coil and methods of its construction are described. | 2013-02-21 |
20130043971 | SERVICE DISCONNECT COVER WITH FUSE/TERMINAL RETENTION - An assembly in which a housing and cover enclose an electric component and lock the electric component into place is provided. The electric component has two L-shaped terminals with notches formed in them that provide lock surfaces for the housing body. The housing body has locking arms that flex during installation and lock the electric component into place by mating with the lock surfaces. The cover body has bosses which push down upon the electric component during installation and lock pins which lock the flexible locking arms into place. The lock pins occupy the space between the locking arms and the backstops of the housing body thereby preventing the locking arms from moving out of position and disengaging the lock surfaces of the locking arms and terminals. | 2013-02-21 |
20130043972 | ELECTRICAL FUSE STRUCTURE - An electrical fuse structure includes a top conductive pattern having a top fuse and a top fuse extension portion, a bottom conductive pattern having a bottom fuse and a bottom fuse extension portion corresponding to the top fuse extension portion, and a via conductive layer positioned between the top fuse extension portion and the bottom fuse extension portion for electrically connecting the top fuse extension portion and the bottom fuse extension portion. | 2013-02-21 |
20130043973 | Electronic lock and method - An electronic lock, system and method for dynamic controlled access, without the lock communicating with or connected to a code server, are provided. The lock includes a locking mechanism, a clock, a microprocessor, and a memory storing a hash function and programmed instructions for the microprocessor to perform certain operations. The microprocessor and memory may be comprised in a microcontroller. When an access code is entered into the lock, the lock microcontroller hashes currently valid access start date/duration combinations with lock identifying data to return valid access codes. If the entered access code equals any of the valid access codes, the locking mechanism is opened. The lock identifying data may include data stored by a lock manufacturer and/or data created by a lock owner. Static access codes may also be programmed into the lock if desired. Caching of valid access codes may be used to reduce processing time. | 2013-02-21 |
20130043974 | Systematic distillation of status data relating to regimen compliance - Configuration technologies for cost-effectively monitoring indicia of regimen compliance or noncompliance in response to one or more indications of symptoms or actions or other data on data-bearing media or in wireless transmissions, such as implementing techniques for providing or preventing access or otherwise acting on or communicating incremental or definitive indicia of compliance or noncompliance. | 2013-02-21 |
20130043975 | Systematic distillation of status data relating to regimen compliance - Configuration technologies for cost-effectively monitoring indicia of regimen compliance or noncompliance in response to one or more indications of symptoms or actions or other data on data-bearing media or in wireless transmissions, such as implementing techniques for providing or preventing access or otherwise acting on or communicating incremental or definitive indicia of compliance or noncompliance. | 2013-02-21 |
20130043976 | SYSTEM AND METHOD FOR DETECTING PRESENCE OF ONE OR MORE USER IDENTIFICATION DEVICE - A method for detecting presence of one or more security token comprises a host device transmitting a wake-up message for receipt by the security token. Based on the wake-up message and a condition of the one or more security token, the security token either awakens or returns to an inactive state. The wake-up message comprises a security code that is unique to a host device and an instruction code that is configured to selectively instruct at least one of the one or more security tokens associated with the vehicle to awaken. A system for detecting presence of a user includes a host device configured for transmitting a wake-up message to be received by a security token. The wake-up message comprises a unique security code and an instruction code that is configured to instruct security tokens associated with the vehicle to awaken. | 2013-02-21 |
20130043977 | METHODS AND SYSTEMS FOR SPEAKER IDENTITY VERIFICATION - A system for confirming that a subject is the source of spoken audio and the identity of the subject providing the spoken audio is described. The system includes at least one motion sensor operable to capture physical motion of at least one articulator that contributes to the production of speech, at least one acoustic signal sensor to receive acoustic signals, and a processing device comprising a memory and communicatively coupled to the at least one motion sensor and the at least one acoustic signal sensor. The processing device is programmed to correlate physical motion data with acoustical signal data to uniquely characterize the subject for purposes of verifying the subject is the source of the acoustical signal data and the identity of the subject. | 2013-02-21 |