08th week of 2016 patent applcation highlights part 43 |
Patent application number | Title | Published |
20160055049 | ULTRA LOW POWER PROGRAMMABLE SUPERVISORY CIRCUIT - An ultra-low-power supervisory circuits can employ floating gate transistors. In an example, a supervisory circuit can include a reset output circuit, a voltage comparator circuit configured to reset the reset output circuit when a first input voltage falls below a reference voltage, and a watchdog circuit configured to receive a watchdog signal and to reset the reset output circuit if the watchdog signal does not transition within a predetermined watchdog interval. The voltage comparator circuit can include a first floating gate transistor circuit configured to establish a reference current for generating the reference voltage, and the watchdog circuit can include a second floating gate transistor circuit for selecting the predetermined watchdog interval. | 2016-02-25 |
20160055050 | HARDWARE DEVICE CONTROLLER, IMAGE FORMING APPARATUS, AND CONTROL METHOD - A hardware device controller includes a controlling unit, a relay unit, and a watchdog timer. The controlling unit outputs a control signal to control a hardware device. The relay unit outputs, on the basis of the control signal, a control signal to the hardware device. When not receiving a first signal output from the controlling unit via the relay unit for a predetermined length of time or longer, the watchdog timer outputs a second signal. When the second signal is output, the controlling unit and the relay unit perform initialization process, and the hardware device stops driving. | 2016-02-25 |
20160055051 | MANAGING STORAGE PROTECTION FAULTS - Management of storage used by pageable guests of a computing environment is facilitated. A query instruction is provided that details information regarding the storage location indicated in the query. It specifies whether the storage location, if protected, is protected by host-level protection or guest-level protection. | 2016-02-25 |
20160055052 | MEMORY DEVICES AND MODULES - An embodiment includes a memory module, comprising: a module error interface; and a plurality of memory devices, each memory device coupled to the module error interface, including a data interface and an device error interface, and configured to communicate error information through the device error interface and the module error interface. | 2016-02-25 |
20160055053 | METHODS AND APPARATUSES UTILIZING CHECK BIT DATA GENERATION - Certain exemplary aspects of the present disclosure are directed towards methods and apparatuses in which logic circuitry generates an error detection code based on user data received from a host, and further generates a first set of check bits, to be written to the non-volatile memory circuit in conjunction with the user data, by combining the error detection code with a hashed data address of the user data. In some embodiments, the check bits associated with the user data providing verification that the user data was written in the appropriate physical block address of the non-volatile memory circuit. | 2016-02-25 |
20160055054 | Data Reconstruction in Distributed Data Storage System with Key-Based Addressing - In a Distributed Virtual Array data storage system, data chunks making up data containers are stored in a key order in storage devices according to layouts specified in a layout data structure. When any of the storage devices becomes inaccessible, the storage devices iteratively return, in storage order, their stored chunks. Chunks belonging to the same container are identified and, if that container had a chunk in the inaccessible storage device, are used to reconstruct the inaccessible chunk. The chunks of the container are then stored according to an updated layout. The keys are independent of physical storage locations. | 2016-02-25 |
20160055055 | MEMORY SYSTEM AND ERROR CORRECTION DECODING METHOD - According to one embodiment, there is provided a memory system including a first generating unit, a buffer unit, a decoding unit, and an update unit. The first generating unit generates logarithm likelihood ratios for plural pieces of data read from a plurality of memory cells. The buffer unit stores the logarithm likelihood ratios. The decoding unit performs first error correction decoding process on the logarithm likelihood ratios, and estimates a logarithm likelihood ratio of data corresponding to an error memory cell among the plural pieces of read data. The update unit updates the logarithm likelihood ratios stored in the buffer unit using the estimated logarithm likelihood ratio. | 2016-02-25 |
20160055056 | MEMORY DEVICE HAVING ERROR NOTIFICATION FUNCTION - A memory device having an error notification function includes an error correction code (ECC) engine detecting and correcting an error bit by performing an ECC operation on data of the plurality of memory cells, and an error notifying circuit configured to output an error signal according to the ECC operation. The ECC engine outputs error information corresponding to the error bit corresponding to a particular address corrected by the ECC operation. The error notifying circuit may output the error signal when the particular address is not the same as any one of existing one or more failed addresses. | 2016-02-25 |
20160055057 | STORAGE DEVICE INCLUDING ERROR CORRECTION DECODER AND OPERATING METHOD OF ERROR CORRECTION DECODER - An operating method of an error correction decoder includes receiving data, setting initial log-likelihood values of variable nodes, and decoding the received data by updating a log-likelihood value of a selected variable node by use of a minimum value and a minimum candidate value associated with the selected variable node. The minimum value indicates a minimum value of absolute values of log-likelihood values of first variable nodes sharing a check node with the selected variable node and including the selected variable node. The minimum candidate value indicates one, greater than the minimum value and smallest, from among absolute values of log-likelihood values of second variable nodes that are selected later than one, corresponding to the minimum value, from among the first variable nodes. | 2016-02-25 |
20160055058 | MEMORY SYSTEM ARCHITECTURE - An embodiment includes a system, comprising: a memory configured to store data, correct an error in data read from the stored data, and generate error information in response to the correcting of the error in the data read from the stored data; and a processor coupled to the memory through a first communication path and a second communication path and configured to: receive data from the memory through the first communication path; and receive the error information from the memory through the second communication path. | 2016-02-25 |
20160055059 | MEMORY DEVICES AND MODULES - An embodiment includes a memory device, comprising: a memory configured to store data; a data interface; an error interface; and a controller coupled to the data interface, the error interface, and the memory. The controller is configured to transmit data stored in the memory through the data interface; and the controller is configured to transmit error information generated in response to correcting an error in data read from memory through the error interface. | 2016-02-25 |
20160055060 | UTILIZING A LOCAL AREA NETWORK MEMORY AND A DISPERSED STORAGE NETWORK MEMORY TO ACCESS DATA - A method includes storing, by non-local DSN memory, redundancy encoded data slices of a set of encoded data slices. The method includes storing, by each DS processing module, a copy of the decode threshold number of encoded data slices in local memory. The method includes receiving, by the plurality of DS processing modules, read requests for the set of encoded data slices from user devices. The method includes, in response to a read request, determining, by a DS processing module, that at least one encoded data slice is unavailable; retrieving, by the DS processing module, at least one of the redundancy encoded data slices from the non-local DSN memory; and processing, by the DS processing module, the read request based on the retrieved at least one of the redundancy encoded data slice and available encoded data slices of the local copy of the decode threshold number of encoded data slices. | 2016-02-25 |
20160055061 | VIRTUAL MEMORY MAPPING IN A DISPERSED STORAGE NETWORK - A method for generating virtual dispersed storage network (DSN) addresses includes dispersed storage error encoding a data segment of a data object to produce a set of encoded data slices of a plurality of sets of encoded data slices of the pluralities of sets of encoded data slices. The method further includes generating, for each encoded data slice of the set of encoded data slices, a virtual DSN address having a slice name that includes a vault identifier, a slice index, a data object identifier, and a data segment identifier. The method further includes obtaining a mapping of a vault to a set of storage units of the DSN, wherein the mapping indicates how the set of encoded data slices are to be stored. The method further includes outputting the set of encoded data slices to the set of storage units in accordance with the mapping. | 2016-02-25 |
20160055062 | Systems and Methods for Maintaining a Virtual Failover Volume of a Target Computing System - Some of the methods provided herein may include periodically revising a mirror of the target computing system, according to a predetermined backup schedule, the mirror being stored on the virtual failover volume resident on an appliance that is operatively associated with the target computing system, by periodically comparing the mirror to a configuration of the target computing system to determine changed data blocks relative to the mirror, storing the changed data blocks as one or more differential files in the virtual failover volume, and incorporating the changed data blocks into the mirror. In some embodiments, the systems and methods may be utilized to resparsify the virtual failover volume. | 2016-02-25 |
20160055063 | PROGRESS RECORDING METHOD AND RECOVERING METHOD FOR ENCODING OPERATION ON STORAGE DEVICE - A recovering method is adapted to an encoding operation performed on a storage area of a storage device. The recovering method includes: reading a variable set, wherein the encoding operation comprises a plurality of sub-operations, and each of the sub-operations is corresponding to at least one flag variable in the variable set; determining whether any one of the sub-operations is interrupted according to the variable set; when one of the sub-operations is interrupted, recovering the sub-operation according to the at least one flag variable corresponding to the sub-operation; and carrying on the encoding operation according to a process recorded by the flag variables in the variable set. | 2016-02-25 |
20160055064 | USER AUTHORIZATION FOR FILE LEVEL RESTORATION FROM IMAGE LEVEL BACKUPS - Embodiments provide systems, methods, and computer program products for enabling user authorization to perform a file level recovery from an image level backup of a virtual machine without the need for access control by an administrator. Specifically, embodiments enable an access control mechanism for controlling access to stored image level backups of a virtual machine. In an embodiment, the virtual machine includes a backup application user interface that can be used to send a restoration request to a backup server. The restoration request can include a machine identifier and a user identifier of the user logged onto the virtual machine. The backup server includes a backup application that determines whether or not the machine identifier contained in the restoration request can be matched to a machine identifier of a virtual machine present in one of the virtual machine backups stored on the backup server. | 2016-02-25 |
20160055065 | DATA PROCESSING APPARATUS AND METHOD - Operating a data processing and storage apparatus to perform continuous backup monitoring for a collection of stored file system objects. In response to changes respective to a number of the file system objects, a set of Data Management Application Program Interface (DMAPI) events is created. For each of the events, accessory file system object information relative to a file system object subject to the change is determined. The events are grouped into an event group and a unique group identifier and an overall group size count are assigned to each of the events included in the event group. The events are sent together with the respective accessory file system object information, the respective group identifier and the respective group size to a number of backup clients registered as applications. The backup clients are to process the events together with the respective accessory file system object information, the respective group identifier and the respective group size into a number of backup requests. | 2016-02-25 |
20160055066 | FAULT TOLERANCE FOR COMPLEX DISTRIBUTED COMPUTING OPERATIONS - A method for enabling a distributed computing system to tolerate system faults during the execution of a client process. The method includes instantiating an execution environment relating to the client process; executing instructions within the execution environment, the instructions causing the execution environment to issue further instructions to the distributing computing system, the further instructions relating to actions to be performed with respect to data stored on the distributed computing system. An object interface proxy receives the further instructions and monitors the received to determine if the execution environment is in a desired save-state condition; and, if so, save a current state of the execution environment in a data store. | 2016-02-25 |
20160055067 | DATA TRANSFER AND RECOVERY PROCESS - A backup image generator can create a primary image and periodic delta images of all or part of a primary server. The images can be sent to a network attached storage device and a remote storage server. In the event of a failure of the primary server, the failure can be diagnosed to develop a recovery strategy. Based on the diagnosis, at least one delta image may be applied to a copy of the primary image to generate an updated primary image at either the network attached storage or the remote storage server. The updated primary image may be converted to a virtual server in a physical to virtual conversion at either the network attached storage device or remote storage server and users may be redirected to the virtual server. The updated primary image may also be restored to the primary server in a virtual to physical conversion. As a result, the primary data storage may be timely backed-up, recovered and restored with the possibility of providing server and business continuity in the event of a failure. | 2016-02-25 |
20160055068 | Recovering from Compromised System Boot Code - In a state of a system in which a processor of the system is not accessing a first memory, a controller in the system determines whether system boot code from the first memory in the system is compromised, wherein the first memory is accessible by the processor and the controller over a bus. In response to determining that the system boot code is compromised, the controller retrieves system boot code from a second memory in the computing device to replace the system boot code in the first memory, where the second memory is electrically isolated from the bus and is inaccessible by the processor. | 2016-02-25 |
20160055069 | Repairing Compromised System Data in a Non-Volatile Memory - A first non-volatile memory stores a redundant copy of system data that relates to a configuration of at least one physical component of a system, where the first non-volatile memory is accessible by a controller in the system and inaccessible to a processor in the system. It is determined whether system data in a second non-volatile memory accessible by the processor is compromised. In response to determining that the system data in the second non-volatile memory is compromised, the compromised system data in the second non-volatile memory is repaired. | 2016-02-25 |
20160055070 | SEMICONDUCTOR DEVICE AND FAULT DETECTION METHOD THEREFOR - According to one embodiment, a semiconductor device includes a memory-transfer control unit that controls data transfer between a memory and a sound unit. A plurality of sound data transfer routes are configured by one memory-transfer control unit and one sound unit. The semiconductor device outputs reproduction sound data via at least one sound data transfer route and acquires at least two pieces of recording sound data on account of one piece of reproduction sound data via at least two sound data transfer routes. | 2016-02-25 |
20160055071 | MEASURING USER SATISFACTION FOR APPLICATION PROGRAMS RUNNING ON MOBILE DEVICES - A quality score for a computer application release is determined using a first number of unique users who have launched the computer application release on user devices and a second number of unique users who have encountered at least once an abnormal termination with the computer application release on user devices. Additionally or optionally, an application quality score can be computed for a computer application based on quality scores of computer application releases that represent different versions of the computer application. Additionally or optionally, a weighted application quality score can be computed for a computer application by further taking into consideration the average application quality score and popularity of a plurality of computer applications. | 2016-02-25 |
20160055072 | METHOD, DEVICE, AND PROGRAM STORAGE DEVICE FOR AUTONOMOUS SOFTWARE LIFE CYCLE MANAGEMENT - A method of searching for and installing a software product on a device is provided. One or more capabilities needed by the device to be served by a software product are determined. The one or more capabilities needed by the device are communicated from a software life cycle management agent on the device to a yellow pages agent outside the device, the communicating comprising formulating a request comprising a list of the capabilities encoded in a description language that defines the capabilities semantically. Then locations of one or more software products matching the one or more capabilities needed by the device may be received from the yellow pages agent. One of the one or more software products to install may be selected based on automatically evaluated criteria. Then the selected software product may be downloaded using its received location, and the selected software product may be installed on the device. | 2016-02-25 |
20160055073 | COMPUTER SOFTWARE APPLICATION SELF-TESTING - Testing a computer software application by detecting an arrival of input data provided as input to a computer software application from a source external to the computer software application, modifying the detected input data to include test data configured to test the computer software application in accordance with a predefined test, thereby creating a modified version of the detected input data, and processing the modified version of the detected input data, thereby performing the predefined test on the computer software application using the test data. | 2016-02-25 |
20160055074 | PROGRAM ANALYSIS DEVICE, PROGRAM ANALYSIS METHOD, AND PROGRAM ANALYSIS PROGRAM - An application list reading part | 2016-02-25 |
20160055075 | MONITORING ACTIVITIES OF A SOFTWARE APPLICATION - Disclosed are a method and a system for monitoring one or more activities offered by a software application in a computer network. The method comprises monitoring a response time for one or more activities. The one or more activities are performed by a software application. The method further comprises comparing the response time of the one or more activities with a corresponding pre-defined threshold time. The method also comprises detecting a faulty activity of the one or more activities based on the comparison. The method further comprises highlighting a code snippet corresponding to the faulty activity in a source code of the software application. | 2016-02-25 |
20160055076 | SOFTWARE TESTING CAPABILITY ASSESSMENT FRAMEWORK - An improved testing assessment tool and methodology maps the Testing Maturity Model (TMM) structure to individual test areas, thereby enabling comprehensive and targeted improvement. In this way, the present invention uses the five TMM maturity levels to assess individual areas, rather than merely assigning a single maturity level to the entire organization. Embodiments of the present invention include a quick assessment that includes a relatively small number of questions to be subjectively answered using the TMM hierarchy. Embodiments of the present invention further include a full assessment that includes a relatively large number of questions to be discretely answered, with these results being use to evaluate various testing areas using the TMM hierarchy. | 2016-02-25 |
20160055077 | METHOD, DEVICE, AND PROGRAM STORAGE DEVICE FOR AUTONOMOUS SOFTWARE PRODUCT TESTING - A method of testing a software product is performed. The software product is downloaded to a sandbox located on a device, the sandbox constructed so that actions taken by software inside the sandbox do not affect operations of modules on the device located outside of the sandbox. Information about the software product is obtained. Then one or more test libraries are automatically generated, based on the information, each of the test libraries containing one or more executable functions to test the software product. Then the software product is tested in the sandbox using the one or more test libraries and test data, producing test results, wherein the testing includes obtaining information from one or more components of the device outside of the sandbox. Based at least on the test results, it is determined that the software product should be installed fully on the device. | 2016-02-25 |
20160055078 | DECREASING USER MANAGEMENT OF AN APPLIANCE - In a method for decreasing user management of a pre-configured hyper-converged computing device, software updates of installed software on an underlying hardware platform of said pre-configured hyper-converged computing device are tested by a first party, wherein the installed software is provided by the first party. The software updates are provided by the first party for updating the installed software on the pre-configured hyper-converged computing device. Installation of the software updates is enabled on the pre-configured hyper-converged computing device such that user management of the pre-configured hyper-converged computing device is decreased based on the software updates previously tested on the underlying hardware platform. | 2016-02-25 |
20160055079 | SOFTWARE APPLICATION LIFECYCLE MANAGEMENT - In association with a predefined requirement of a software application, a plurality of inputs associated with a scenario that provides a context for the predefined requirement are received, including a scenario name, description, expected behavior, and indicators of a likelihood of the scenario occurring, of an impact of a failure of the scenario, and of a probability of the failure of the scenario occurring. A testing priority is calculated for the scenario based on the indicator of the likelihood of the scenario occurring, the indicator of the impact of the failure of the scenario, and the indicator of the probability of the failure of the scenario occurring. A report that includes the testing priority for the scenario and one or more other testing priorities for one or more other scenarios of the predefined requirement is provided. | 2016-02-25 |
20160055080 | MEMORY SYSTEM - A memory system according to an embodiment of the present invention comprises: speed of processing for searching through management tables is increased by providing a forward lookup table for searching for, respectively in track and cluster units, from a logical address, a storage device position where data corresponding to the logical address and a reverse lookup table for searching for, from a position of the storage device, a logical address stored in the position and linking these tables. | 2016-02-25 |
20160055081 | NON-PRECISE GARBAGE COLLECTION IN NON-COOPERATIVE SYSTEMS - Embodiments are directed towards garbage collection for an application running on a non-cooperative target platform. Where the garbage collection optimistically manages thread state for transitions to and from native and managed code and that some threads are suspended while others are left executing during garbage collection. When a characteristic of the native code call indicates that a duration of the native code call may exceed a defined duration, state information for the thread may be updated to transition the thread to the unmanaged code environment. When a garbage collection event occurs, thread state information is updated to communicate suspend requests to the threads. Then the runtime may wait for each thread in the managed code environment to be reach a safe state before garbage collection may commence. | 2016-02-25 |
20160055082 | MEMORY ALLOCATING METHOD AND ELECTRONIC DEVICE SUPPORTING THE SAME - An electronic device, including an application configured to request a page allocation of a process, a cache management module configured to allocate a page in a page group including uninterrupted (or consecutive, or contiguous) pages to the process, and a page buffer configured to manage the at least one page group, is disclosed. | 2016-02-25 |
20160055083 | PROCESSORS AND METHODS FOR CACHE SPARING STORES - In one aspect, a processor has a register file, a private Level 1 (L1) cache, and an interface to a shared memory hierarchy (e.g., an Level 2 (L2) cache and so on). The processor has a Load Store Unit (LSU) that handles decoded load and store instructions. The processor may support out of order and multi-threaded execution. As store instructions arrive at the LSU for processing, the LSU determines whether a counter, from a set of counters, is allocated to a cache line affected by each store. If not, the LSU allocates a counter. If so, then the LSU updates the counter. Also, in response to a store instruction, affecting a cache line neighboring a cache line that has a counter that meets a criteria, the LSU characterizes that store instruction as one to be effected without obtaining ownership of the effected cache line, and provides that store to be serviced by an element of the shared memory hierarchy. | 2016-02-25 |
20160055084 | NON-BLOCKING WRITES TO FILE DATA - Techniques and systems are disclosed for implementing non-blocking writes to eliminate the fetch-before-write requirement by creating an in-memory patch for the updated page and unblocking the calling process. Non-blocking writes eliminate such blocking by buffering the written data elsewhere in memory and unblocking the writing process immediately. Subsequent reads to the updated page locations are also made non-blocking and, in some cases, can be eliminated when the read request can be serviced from in-memory patches. | 2016-02-25 |
20160055085 | ENFORCING ORDERING OF SNOOP TRANSACTIONS IN AN INTERCONNECT FOR AN INTEGRATED CIRCUIT - An interconnect has transaction tracking circuitry for enforcing ordering of a set of data access transactions so that they are issued to slave devices in an order in which they are received from master devices. The transaction tracking circuitry is reused for also enforcing ordering of snoop transactions which are triggered by the set of data access transactions, for snooping master devices identified by a snoop filter as holding cache data for the target address of the transactions. | 2016-02-25 |
20160055086 | DYNAMIC CACHE PARTITIONING APPARATUS AND METHOD - A dynamic cache partitioning apparatus and method is described, which may be used in a multi-core system having a plurality of cores. The apparatus includes at least one multi-core processor and at least one shared cache shared by a plurality of processing cores, the shared cache including a plurality of cache lines and being partitioned into a plurality of sub-caches including at least one private sub-cache for each single processing core and at least one public sub-cache being shared by all of the processing cores; means for detecting shared cache hit information for each respective processing core of the plurality of processing cores; and means for determining whether a cache line should be allocated to public sub-cache or to a private sub-cache associated with one of the plurality of processing cores. | 2016-02-25 |
20160055087 | SYSTEM AND METHOD FOR MANAGING CACHE REPLACEMENTS - A system and method for managing cache replacements and a memory subsystem incorporating the system or the method. In one embodiment, the system includes: ( | 2016-02-25 |
20160055088 | CROSS-PAGE PREFETCHING METHOD, APPARATUS, AND SYSTEM - A cross-page prefetching method, apparatus, and system are disclosed, which can improve a prefetching hit ratio of a prefetching device, and further improve efficiency of memory access. The method includes: receiving an indication message, sent by a cache, that a physical address is missing, where the indication message carries a mapped-to first physical address and contiguity information of a first physical page to which the first physical address belongs; acquiring a prefetching address according to the first physical address and a step size that is stored in a prefetching device; and if a page number of a physical page to which the prefetching address belongs is different from a page number of the first physical page, and it is determined, according to the contiguity information of the first physical page, that the first physical page is contiguous, prefetching data at the prefetching address. | 2016-02-25 |
20160055089 | CACHE CONTROL DEVICE FOR PREFETCHING AND PREFETCHING METHOD USING CACHE CONTROL DEVICE - The present examples relate to prefetching, and to a cache control device for prefetching and a prefetching method using the cache control device, wherein the cache control device analyzes a memory access pattern of program code, inserts, into the program code, a prefetching command generated by encoding the analyzed access pattern, and executes the prefetching command inserted into the program code in order to prefetch data into a cache, thereby maximizing prefetching efficiency. | 2016-02-25 |
20160055090 | ADAPTIVE RECORD CACHING FOR SOLID STATE DISKS - A storage controller receives a request that corresponds to an access of a track. A determination is made as to whether the track corresponds to data stored in a solid state disk. Record staging to a cache from the solid state disk is performed, in response to determining that the track corresponds to data stored in the solid state disk, wherein each track is comprised of a plurality of records. | 2016-02-25 |
20160055091 | FUZZY COUNTERS FOR NVS TO REDUCE LOCK CONTENTION - A method for data management in a computing storage environment includes a processor device, operable in the computing storage environment, that divides a plurality of counters tracking write and discard storage operations through Non Volatile Storage (NVS) space into first, accurate, and second, fuzzy, groups where the first, accurate, group is one of updated on a per operation basis, while the second, fuzzy, group is one of updated on a more infrequent basis as compared to the first, accurate group. | 2016-02-25 |
20160055092 | ADAPTIVE RECORD CACHING FOR SOLID STATE DISKS - A storage controller receives a request that corresponds to an access of a track. A determination is made as to whether the track corresponds to data stored in a solid state disk. Record staging to a cache from the solid state disk is performed, in response to determining that the track corresponds to data stored in the solid state disk, wherein each track is comprised of a plurality of records. | 2016-02-25 |
20160055093 | Supplemental Write Cache Command For Bandwidth Compression - Aspects include computing devices, systems, and methods for implementing a cache memory access requests for data smaller than a cache line and eliminating overfetching from a main memory by writing supplemental data to the unfilled portions of the cache line. A cache memory controller may receive a cache memory access request with a supplemental write command for data smaller than a cache line. The cache memory controller may write supplemental to the portions of the cache line not filled by the data in response to a write cache memory access request or a cache miss during a read cache memory access request. In the event of a cache miss, the cache memory controller may retrieve the data from the main memory, excluding any overfetch data, and write the data and the supplemental data to the cache line. Eliminating overfetching reduces bandwidth and power required to retrieved data from main memory. | 2016-02-25 |
20160055094 | Power Aware Padding - Aspects include computing devices, systems, and methods for implementing a cache memory access requests for data smaller than a cache line and eliminating overfetching from a main memory by combining the data with padding data of a size of a difference between a size of a cache line and the data. A processor may determine whether the data, uncompressed or compressed, is smaller than a cache line using a size of the data or a compression ratio of the data. The processor may generate the padding data using constant data values or a pattern of data values. The processor may send a write cache memory access request for the combined data to a cache memory controller, which may write the combined data to a cache memory. The cache memory controller may send a write memory access request to a memory controller, which may write the combined data to a memory. | 2016-02-25 |
20160055095 | STORING DATA FROM CACHE LINES TO MAIN MEMORY BASED ON MEMORY ADDRESSES - A method for performing memory operations is provided. One or more processors can determine that at least a portion of data stored in a cache memory of the one or more processors is to be stored in the main memory. One or more ranges of addresses of the main memory is determined that correspond to a plurality of cache lines in the cache memory. A set of cache lines corresponding to addresses in the one or more ranges of addresses is identified, so that data stored in the identified set can be stored in the main memory. For each cache line of the identified set having data that has been modified since that cache line was first loaded to the cache memory or since a previous store operation, data stored in that cache line is caused to be stored in the main memory. | 2016-02-25 |
20160055096 | Multi-Processor, Multi-Domain, Multi-Protocol Cache Coherent Speculation Aware Shared Memory Controller and Interconnect - This invention combines a multicore shared memory controller and an asynchronous protocol converting bridge to create a very efficient heterogeneous multi-processor system. After traversing the protocol converting bridge the commands travel through the regular processor port. This allows the interconnect to remain unchanged while having any combination of different processors connected. This invention tightly integrates all of the processors into the same memory controller/interconnect. | 2016-02-25 |
20160055097 | HETEROGENEOUS UNIFIED MEMORY - Inventive aspects include a heterogeneous unified memory section, which includes an extended unified memory space across a plurality of physical heterogeneous memory modules. A cold page reclamation logic section can receive and prioritize cold pages from a system memory. The cold pages can include a first subset of memory pages having a first type of memory data and a second subset of memory pages having a second type of memory data. For example, the cold pages can include anon-type memory pages and file-type memory pages. A dynamic tuning logic section can manage space allocation within the extended unified memory space. An intelligent page sort logic section can distribute the cold pages among different pools of physical heterogeneous memory modules based on varying characteristics of the pools, and based on the assigned priorities. | 2016-02-25 |
20160055098 | COMPUTER SYSTEM WITH MEMORY AGING FOR HIGH PERFORMANCE - A memory manager in a computer system that ages memory for high performance. The efficiency of operation of the computer system can be improved by dynamically setting an aging schedule based on a predicted time for trimming pages from a working set. An aging schedule that generates aging information that better discriminates among pages in a working set based on activity level enables selection of pages to trim that are less likely to be accessed following trimming. As a result of being able to identify and trim less active pages, inefficiencies arising from restoring trimmed pages to the working set are avoided. | 2016-02-25 |
20160055099 | Least Recently Used Mechanism for Cache Line Eviction from a Cache Memory - A mechanism for evicting a cache line from a cache memory includes first selecting for eviction a least recently used cache line of a group of invalid cache lines. If all cache lines are valid, selecting for eviction a least recently used cache line of a group of cache lines in which no cache line of the group of cache lines is also stored within a higher level cache memory such as the L1 cache, for example. Lastly, if all cache lines are valid and there are no non-inclusive cache lines, selecting for eviction the least recently used cache line stored in the cache memory. | 2016-02-25 |
20160055100 | SYSTEM AND METHOD FOR REVERSE INCLUSION IN MULTILEVEL CACHE HIERARCHY - A processing system having multilevel cache employs techniques for identifying and selecting valid candidate cache lines for eviction from a lower level cache of an inclusive cache hierarchy, so as to reduce invalidations resulting from an eviction of a cache line in a lower level cache that also resides in a higher level cache. In response to an eviction trigger for a lower level cache, a cache controller identifies candidate cache lines for eviction from the cache lines residing in the lower level cache based on the replacement policy. The cache controller uses residency metadata to identify the candidate cache line as a valid candidate if it does not also reside in the higher cache and as an invalid candidate if it does reside in the higher cache. The cache controller prevents eviction of invalid candidates, so as to avoid unnecessary invalidations in the higher cache while maintaining inclusiveness. | 2016-02-25 |
20160055101 | METHOD AND APPARATUS TO GENERATE ZERO CONTENT OVER GARBAGE DATA WHEN ENCRYPTION PARAMETERS ARE CHANGED - A memory device including at least one memory location for storing information representing data written using a first encryption/decryption method, and a read channel using a second encryption/decryption method for reading and decrypting information as written. The memory device also includes an apparatus that prevents the reading of the at least one memory location using the second encryption/decryption method, in response to an indication that the at least one memory location was written using the first encryption/decryption method. In another embodiment, a reading of all zeroes is returned in response to an indication of another encryption/decryption method. | 2016-02-25 |
20160055102 | Managing Security in a System on a Chip (SOC) that Powers Down a Secure Processor - An SOC includes a secure processor and an always-on component. The always-on component may remain powered even during times that other parts of the SOC are powered off. Particularly, the secure processor and related circuitry may be powered off, while various state for the secure processor may be stored in memory in an encrypted form. Certain state may be stored in the always-on component. When the secure processor is powered on again, the secure processor may check for the state in the always-on component. If the state is found, the secure processor may retrieve the state and use the state to access the encrypted memory state. | 2016-02-25 |
20160055103 | APPARATUS, ELECTRONIC DEVICES AND METHODS ASSOCIATED WITH AN OPERATIVE TRANSITION FROM A FIRST INTERFACE TO A SECOND INTERFACE - Subject matter disclosed herein relates to an apparatus comprising memory and a controller, such as a controller which determines block locking states in association with operative transitions between two or more interfaces that share at least one block of memory. The apparatus may support single channel or multi-channel memory access, write protection state logic, or various interface priority schemes. | 2016-02-25 |
20160055104 | APPARATUS AND METHOD FOR COPYING RULES BETWEEN DEVICES - Devices, systems, and methods are described for allowing rules that are applied to one device to be applied to another device based on a user's interaction with only the devices. A rule-copy action, such as simultaneous shaking of the two devices, proximity of the two devices to each other, and/or the relative positions of the two devices, may be detected at one of the devices (e.g., a first device to which the user desires the rules or a copy of the rules to apply). In response to the rule-copy action, another device (e.g., a second device configured to operate according to the at least one rule) may be identified. The at least one rule may then be caused to be applied to the first device in response to detection of the rule-copy action, so as to configure the first device to operate according to the at least one rule. | 2016-02-25 |
20160055105 | ELECTRONIC DEVICE AND METHOD FOR AVOIDING MUTUAL INTERFERENCE BETWEEN MULTIPLE INPUT DEVICES - A method for avoiding mutual interference between multiple input devices is provided. The method is applied to an electronic device. The method includes: setting corresponding priority for multiple input devices of the electronic device according to a priority setting result; determining whether any other input device is functioning when a first input event of a first input device is received; and when a second electronic device is functioning, determining whether to process or ignore the first input event according to the priority of the first input device and the priority of the second input device. When the priority of the first input device is higher than that of the second input device, the first input event is processed. When the priority of the second input device is higher than that of the first input device, the first input event is ignored. | 2016-02-25 |
20160055106 | MECHANISM FOR INTER-PROCESSOR INTERRUPTS IN A HETEROGENEOUS MULTIPROCESSOR SYSTEM - Apparatus and methods for handling inter-processor interrupts (IPIs) in a heterogeneous multiprocessor system are provided. The scalable IPI mechanism provided herein entails minimal logic and can be used for heterogeneous inter-processor communication, such as between application processors, real-time processors, and FPGA accelerators. This mechanism is also low cost, in terms of both logic area and programmable complexity. One example system generally includes a first processor, a second processor being of a different processor type than the first processor, and an IPI circuit. The IPI circuit typically includes a first register associated with the first processor, wherein a first bit in the first register indicates whether the first processor has requested to interrupt the second processor; and a second register associated with the second processor, wherein a second bit in the second register indicates whether the second processor has requested to interrupt the first processor. | 2016-02-25 |
20160055107 | DATA PROCESSING APPARATUS AND METHOD - A data processing apparatus is provided, which includes: a plurality of processor cores; a shared processor cache, the shared processor cache being connected to each of the processor cores and to a main memory; a bus controller, the bus controller being connected to the shared processor cache and performing, in response to receiving a descriptor sent by one of the processor cores, a transfer of requested data indicated by the descriptor from the shared processor cache to an input/output (I/O) device; a bus unit, the bus unit being connected to the bus controller and transferring data to/from the I/O device; wherein the shared processor cache includes means for prefetching the requested data from the shared processor cache or main memory by performing a direct memory access in response to receiving a descriptor from the one of the processor cores. | 2016-02-25 |
20160055108 | MANAGING MESSAGE SIGNALED INTERRUPTS IN VIRTUALIZED COMPUTER SYSTEMS - Systems and methods for managing message signaled interrupts in virtualized computer systems. An example method may comprise: intercepting, by a hypervisor running on a host computer system, a memory read operation initiated by a virtual machine with respect to a first interrupt mapping table, the first interrupt mapping table stored by a physical device associated with the virtual machine, the memory read operation specifying an offset relative to a base address of the first interrupt mapping table; reading at least part of the first interrupt mapping table; and returning, to the virtual machine, a value referenced by the offset within a second interrupt mapping table, the second interrupt mapping table residing in a memory of the host computer system. | 2016-02-25 |
20160055109 | BUS RELAYING DEVICE - A relaying device, when having received an interrupt notification | 2016-02-25 |
20160055110 | Transaction Filter for On-Chip Communications Network - A transaction filter for an on-chip communications network is disclosed. In one embodiment, an integrated circuit (IC) include a number of functional circuit blocks, some of which may be placed in a sleep mode (e.g., power-gated). The IC also includes a number of transaction filters that are each associated with a unique one of the functional circuit blocks. Responsive to its associated functional circuit block generating a transaction, a given transaction filter may determine whether the functional circuit block to which the transaction is destined is in a sleep mode. If it is determined that the transaction is destined for a functional circuit block that is currently in the sleep mode, the transaction filter may block the transaction from being conveyed. | 2016-02-25 |
20160055111 | USING A CREDITS AVAILABLE VALUE IN DETERMINING WHETHER TO ISSUE A PPI ALLOCATION REQUEST TO A PACKET ENGINE - In response to receiving a novel “Return Available PPI Credits” command from a credit-aware device, a packet engine sends a “Credit To Be Returned” (CTBR) value it maintains for that device back to the credit-aware device, and zeroes out its stored CTBR value. The credit-aware device adds the credits returned to a “Credits Available” value it maintains. The credit-aware device uses the “Credits Available” value to determine whether it can issue a PPI allocation request. The “Return Available PPI Credits” command does not result in any PPI allocation or de-allocation. In another novel aspect, the credit-aware device is permitted to issue one PPI allocation request to the packet engine when its recorded “Credits Available” value is zero or negative. If the PPI allocation request cannot be granted, then it is buffered in the packet engine, and is resubmitted within the packet engine, until the packet engine makes the PPI allocation. | 2016-02-25 |
20160055112 | RETURN AVAILABLE PPI CREDITS COMMAND - In response to receiving a novel “Return Available PPI Credits” command from a credit-aware device, a packet engine sends a “Credit To Be Returned” (CTBR) value it maintains for that device back to the credit-aware device, and zeroes out its stored CTBR value. The credit-aware device adds the credits returned to a “Credits Available” value it maintains. The credit-aware device uses the “Credits Available” value to determine whether it can issue a PPI allocation request. The “Return Available PPI Credits” command does not result in any PPI allocation or de-allocation. In another novel aspect, the credit-aware device is permitted to issue one PPI allocation request to the packet engine when its recorded “Credits Available” value is zero or negative. If the PPI allocation request cannot be granted, then it is buffered in the packet engine, and is resubmitted within the packet engine, until the packet engine makes the PPI allocation. | 2016-02-25 |
20160055113 | Redundant System Boot Code in a Secondary Non-Volatile Memory - A controller determines whether system boot code stored in a first non-volatile memory is compromised and non-recoverable. In response to determining that the system boot code is compromised and non-recoverable, switch logic is activated to connect a second non-volatile memory to the shared bus and to disconnect the first non-volatile memory from the shared bus. | 2016-02-25 |
20160055114 | HIGH-SPEED SERIAL RING - Methods and systems for transferring a high-speed data signal between more than two electronic devices within a system comprising a master device and a plurality of slave devices are presented. The master device and the plurality of slave devices are connected through high-speed links between high-speed interfaces, thereby forming a closed ring. The high-speed interfaces are comprised by the master device and each of the plurality of slave devices, respectively. A common low frequency clock signal is provided by the master device to each of the slave devices, and a high-speed interface communication method for communication between the master device and the plurality of slave devices through the high-speed links is used. | 2016-02-25 |
20160055115 | DATA STORAGE DEVICE CARRIER SYSTEM - A data storage device carrier system includes a carrier configured to support one or more data storage devices, a backplane, including one or more coupling connector devices configured to electrically couple with a motherboard, and an interposer board operable to couple a plurality of the data storage devices supported by the carrier with the backplane. In an embodiment, the one or more coupling connector devices are operable to transfer communication signals and electrical power. The interposer board is operable to provide the electrical power from a single port on the backplane to each of the plurality of the data storage devices. The interposer board is also operable to pass communication signals between a primary port on the backplane to a first one of the plurality of the data storage devices, and to pass communication signals between a secondary port on the backplane to a second one of the plurality of the data storage devices. | 2016-02-25 |
20160055116 | DYNAMIC VEHICLE BUS SUBSCRIPTION - A method of controlling access at a vehicle to information communicated over a vehicle bus includes: storing one or more electronic control unit (ECU) identities in a central gateway module (CGM) that is communicatively linked with a vehicle bus; associating one or more message permissions for receiving messages via the vehicle bus with one of the ECU identities in the CGM that represents an ECU communicatively linked with the vehicle bus; wirelessly receiving a computer-readable instruction at the vehicle directing the CGM to change one or more message permissions associated with the ECU identity; and storing the changed message permissions in the CGM. | 2016-02-25 |
20160055117 | Dual Mode USB and Serial Console Port - An information handling system includes a service connector operable to receive an RS-232 signal and a USB signal. The service connector is a USB type connector. The information handling system also includes a voltage converter operable to convert the RS-232 signal from a first voltage level to a first serial signal at a second voltage level when a signal received by the service connector is the RS-232 signal, a protocol converter operable to convert the USB signal to a second serial signal at the second voltage level when the signal received by the service connector is the USB signal, and a UART operable to receive the first serial signal and the second serial signal. | 2016-02-25 |
20160055118 | PACKET BUFFER WITH DYNAMIC BYPASS - A write queue, for queuing a packet in a traffic manager coupled to a memory device, is selected from among a preemptable write queue configured to queue packets that are candidates for being retrieved from the traffic manager before the packets are written to the memory device and a non-preemptable write queue configured to queue packets that are not candidates for being retrieved from the traffic manager before the packets are written to the memory device. The packet is written to the selected write queue. A read request is generated for retrieving the packet from the memory device, and it is determined whether the packet is queued in the preemptable write queue. If the packet is queued in the preemptable write queue, the packet is extracted from the preemptable write queue for retrieving the packet from the traffic manager before the packet is written to the memory device. | 2016-02-25 |
20160055119 | Disaggregated Server Architecture for Data Centers - A system comprising a unified interconnect network, a plurality of process memory modules, and a plurality of processor modules configured to share access to the memory modules via the unified interconnect network. Also disclosed is a method comprising communicating data between a plurality of processor modules and a plurality of shared resource pools via a unified interconnect network, wherein the communications comprise a protocol that is common to all resource pools, and wherein each resource pool comprises a plurality of resource modules each configured to perform a common function. Also disclosed is an apparatus comprising a network interface controller (NIC) module configured to receive data from a plurality of processor modules via a unified interconnect network, and provide core network connectivity to the processor modules. | 2016-02-25 |
20160055120 | Integrated data processing core and array data processor and method for processing algorithms - An integrated data processing core and a data processor are provided on a single integrated circuit and command sequences are forwarded from the data processing core to be executed on the array data processor wherein the command sequences comprise a group of instructions defining an algorithm. | 2016-02-25 |
20160055121 | NODE-BASED SEQUENTIAL IMPLICIT ENUMERATION METHOD AND SYSTEM THEREOF - A node-based sequential implicit enumeration method is provided, including: setting a multistate flow network, building an integer programming model of the multistate flow network, and finding a solution set of level number 1 and a number of elements in the solution set from the integer programming model according to the flow conservation law, then using one of the elements to sequentially find a solution set of a next level number and a number of elements in the solution set until the level number being N−1 to complete a new complete solution set, afterward, sequentially returning to the preceding level numbers to determine whether there are other elements in the solution set, and if so, repeating above steps to produce another new complete solution set until the solution sets of all level numbers have been checked, and determining the final complete solution set as a set of the minimal path satisfying the required flow, so as to find all d-MP in the integer programming model of the multistate flow network efficiently. | 2016-02-25 |
20160055122 | DESIGN AND ANALYSIS OF SILICON PHOTONICS ARRAY WAVE GUIDES - Methods and apparatus are disclosed for symbolic methods using algebraic geometry (e.g., based on a Gröbner basis of tangent space polynomials of parametric curves). For example, the design, optimization and verification of silicon photonic wave guides using parametric polynomials and/or Gröbner basis functions can be used to perform envelope generation, rectification, manufacturability, singularity detection, reticle and etch processing model generation, tapering loss minimization, and bend loss minimization. In one example, a method of analyzing a layout to be manufactured using a photolithographic process includes producing an envelope of a curve representing a layout object based at least in part on a Gröbner basis and performing one or more analysis operations for the envelope to perform verification and manufacturability checks. | 2016-02-25 |
20160055123 | Method for Representing and Solving Algebraic Equations with a Physical or Virtual Gear System - A method for representing and solving algebraic equations that allows a user to view and solve algebraic equation with a virtual gear system. The virtual gear system includes a virtual primary cog and virtual secondary cogs. The virtual primary cog represents a range of outcomes for the virtual gear system and contains a number of teeth that is quantitatively greater than a numerical constant of the algebraic equation; amongst the teeth is a target tooth that represents the numerical constant. Each virtual secondary cogs represent a term of the algebraic equation and includes a coefficient and a variable. Each of the virtual secondary cogs contains a number of teeth equal to the coefficient. The equation is solved by rotating the virtual secondary cogs until the target tooth is aligned with a fixed pointer where rotation of the virtual secondary cog represents a value input for the variable of a term. | 2016-02-25 |
20160055124 | SYSTEMS AND METHODS FOR LOW-RANK MATRIX APPROXIMATION - Systems and methods for generating a low-rank approximation of a matrix are provided. The various systems and methods may identify at least a first set of right singular vectors and a first set of singular values of a subset of the matrix, reduce the subset by an amount of energy of a selected data entry of the subset based on the first set of right singular vectors and the first set of singular values, incorporate a new data entry from the matrix into the subset, update the first set of right singular vectors and the first set of singular values of the subset based on the new data entry by a singular value decomposition (SVD) update, and generate the low-rank approximation of the matrix based on the updated first set of right singular vectors and the updated first set of singular values. | 2016-02-25 |
20160055125 | METHODS AND SYSTEMS FOR DETERMINING GLOBAL SENSITIVITY OF A PROCESS - Systems and methods for determining the sensitivity of a model to a factor are disclosed. A directional variogram corresponding to a response surface of the model is determined. The variogram is then output as an indication of the sensitivity of the model. | 2016-02-25 |
20160055126 | USER INTERFACES GENERATED BY A WORKFLOW ENGINE - According to one embodiment of the present disclosure, a first processor with a store of application rules and a second processor communicably coupled to the first processor. The second processor generates a request for a next user application screen. The request comprises a current application screen identifier and user data. The second processor transmits the request for the user application screen to the first processor. The first processor receives the request for the next user application screen and determines dynamically, based on the current application screen identifier, the user data, and the plurality of application rules, user interface contents of the next user application screen. The first processor formats a response describing the user interface contents of the next user application screen and transmits the response to the second processor. The second processor receives the response and renders the next user application screen. | 2016-02-25 |
20160055127 | DISPLAY CONTROL DEVICE, TERMINAL APPARATUS, NON-TRANSITORY COMPUTER READABLE MEDIUM, AND DISPLAY CONTROL METHOD - A display control device includes a memory controller, a display controller, and a notification unit. The memory controller causes a document file managed by a document management apparatus to be stored in a memory. The display controller causes a document represented by the document file stored in the memory to be displayed over an entire range of a display area of a display during a presentation. The notification unit notifies a user of presence of a difference between the document file stored in the memory and the document file managed by the document management apparatus, while the document is being displayed over the entire range of the display area, by displaying the difference in an area where the document is being displayed. | 2016-02-25 |
20160055128 | INTERACTING WITH DATA FROM A DOCUMENT VIA DOCUMENT AN APPLICATION PAGES - A document application is used to interact with a document as if the document was an application. Data from the document is automatically/manually selected to be associated with the document application. The document application displays document application pages (DAPs) that are used to interact with the document. One or more DAPs are automatically created using the selected data along with any rules associated with the data. For example, column names from selected data in the document may be used to create data entry/display fields within one or more DAPs and the rules may be used to specify how to interact with the data in the document application. The automatically created default DAPs may be customized by a user. For example, one DAP may be configured to be the starting page for the document application and another DAP may be configured to display a chart. | 2016-02-25 |
20160055129 | MULTI-LEVEL ARCHITECTURE FOR IMAGE DISPLAY - A system and method for providing the dynamic display of content and related advertisements are provided. The advertisements are displayed based on predetermined customer types. A network resource, such as Web page, can include a plurality of dynamic content modules. Depending on the available display area and additional display criteria, each dynamic content module displays a subset content and related advertisements. Each dynamic content module corresponds to an integration of multiple layers of content, such as text, graphics, and image rendering information. | 2016-02-25 |
20160055130 | REMOTE MANAGEMENT OF A GRAPHICAL USER INTERFACE - On a computing device, a user interface (UI) layout file is received. The UI layout file defines a visual layout of the GUI. The UI layout file includes a plurality of UI elements each including a UI element identifier and a UI element descriptor. The GUI is displayed via a display according to the UI layout file. An update object specifying UI elements in the UI layout file to be changed is received. The update object includes for each UI element to be changed, the UI element identifier and an update payload including updated information to be displayed via the UI element. The GUI is changed via the display according to the update object. | 2016-02-25 |
20160055131 | SYSTEMS AND METHODS FOR PROCESSING INPUT STREAMS OF CALENDAR APPLICATIONS - Systems and methods for processing input streams of calendar applications. An example method, performed by a computer system, may comprise receiving an input stream; processing the input stream to produce a sequence of characters; responsive to determining that the sequence of characters comprises a time reference, storing, in a memory, a calendar entry in a first data structure of a first type, the calendar entry comprising an identifier of a time referenced by the time reference; responsive to determining that the sequence of characters does not comprise a time reference, storing, in the memory, a memorandum in a second data structure of a second type, the memorandum comprising at least part of the sequence of characters. | 2016-02-25 |
20160055132 | AUTOMATED CUSTOMIZED WEB PORTAL TEMPLATE GENERATION SYSTEMS AND METHODS - An automated Web portal template generation method includes parsing, via a parser subsystem, a number of Webpages of a first Website from which a Web portal template to be customized is to be accessed. The method further includes producing an entity feature set for the first Website based on a result of the parsing and processing the entity feature set for the first Website via a classifier subsystem to produce a set of data that represents, for each of a plurality of entities, a respective probability of the entity belonging to a respective one of a plurality of classes. The method additionally includes performing, by a color matching subsystem, color matching on the set of data produced by the classifier subsystem to generate a number of proposed color combinations for a proposed customization of the Web portal template. | 2016-02-25 |
20160055133 | SYSTEMS AND METHODS FOR DIRECTING ACCESS TO PRODUCTS AND SERVICES - In a system for enabling a user to access a product or service, resources for accessing the product or service, such as apps on a user device, are explored in a specified order. A relatively lower priority resource is not explored until it is determined that all higher priority resources are unavailable. Within the content corresponding to an available resource, the user can be readily directed to the portion of the content that is associated with the particular product or service. | 2016-02-25 |
20160055134 | METHOD AND APPARATUS FOR PROVIDING SUMMARIZED CONTENT TO USERS - A method of displaying summarized content by an electronic device includes: performing a text analysis on first content accessed by a user to acquire a plurality of subject words; displaying the acquired plurality of subject words; and displaying second content corresponding to at least one of the acquired plurality of subject words based on an external input, wherein the second content is summarized content of the first content. | 2016-02-25 |
20160055135 | METHOD AND APPARATUS FOR REDUCING PAGE LOAD TIME IN COMMUNICATION SYSTEM - The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). Provided are a method and apparatus for reducing the page load time in a wireless communication system. The method for page loading in a mobile terminal may include: selecting, when a page is visited, a candidate page to be pre-inspected with respect to the page; performing pre-inspection of the candidate page and determining types of objects associated with the candidate page; generating tree information for the candidate page based on a result of the determination; and computing the loading time of the candidate page based on the tree information and determining download priorities of objects that are to be downloaded when the candidate page is visited. | 2016-02-25 |
20160055136 | CREATING HIGH FIDELITY PAGE LAYOUT DOCUMENTS - A computer-based method for creating a high fidelity page layout document is provided. The method includes assigning an identifier to each element of a plurality of elements in a reflowable document, creating a fixed page layout document, including the identifiers, from the reflowable document, parsing the fixed page layout document into a plurality of elements based on the identifiers, each element being associated with an identifier, linking the elements of the reflowable document to the elements of the fixed page layout document based on the identifiers, and creating a final document based on the reflowable document, the fixed page layout document and the identifiers, each element of the final document having a fixed position on a page. | 2016-02-25 |
20160055137 | INFORMATION PROCESSING APPARATUS PROVIDED WITH ELECTRONIC BOOK EDITING TECHNIQUE, CONTROL METHOD THEREFOR AND STORAGE MEDIUM - An information processing apparatus making it possible for a user to easily realize changes in the whole electronic book accompanying an editing operation performed by the user. Changes in the edited electronic book are extracted and displayed on the display unit. The extracted changes are classified into first changes related to pages before a displayed page and second changes related to pages after the displayed page. The changes are caused to be displayed on the page displayed on the display unit such that the changes can be discriminated as any of the first changes or the second changes. | 2016-02-25 |
20160055138 | DOCUMENT ORDER REDEFINITION FOR ASSISTIVE TECHNOLOGIES - Embodiments of the present invention provide a method, system and computer program product for document content re-ordering for assistive technology processing. In an embodiment of the invention, a method for document content re-ordering for assistive technology processing is provided. The method includes sensing in a computer display a drawing of a path across different portions of displayed content in the computer display. Thereafter, a sequence of the different portions of the displayed content can be identified from the path. As such, meta-data indicative of the sequence can be generated in the memory of the computer and the content can be annotated with the generated meta-data. Finally, the portions of the content can be processed with assistive technology in an order dictated by the sequence. | 2016-02-25 |
20160055139 | AUTOMATICALLY ADJUSTING SPREADSHEET FORMULAS AND/OR FORMATTING - In some embodiments, a computer-implemented spreadsheet management method is provided that automatically copies formatting and formulas from appropriate peer rows to an updated row. In some embodiments, the method automatically determines which peer rows, if any, should be used as the source of copied formatting and formulas. In some embodiments, the method automatically fixes formulas that are affected by the updated row in order to maintain consistency throughout the spreadsheet. | 2016-02-25 |
20160055140 | PEER TO PEER SPREADSHEET PROCESSING - A distributed system and process for sharing a spreadsheet model. A spreadsheet to be shared is configured by defining input fields, processing parameters for the input fields, and output fields, and a template including the input and output fields is created. The template is shared with a remote user, who enters data into the input fields of the template. The input data is transferred for processing, after which results are provided to the remote user in the defined output fields of the template. | 2016-02-25 |
20160055141 | STRING COMPARISON RESULTS FOR CHARACTER STRINGS USING FREQUENCY DATA - A similarity between character strings is assessed by identifying first and second character strings as candidate similar character strings, determining a frequency of occurrence for at least one of the first and second character strings from a collection of character strings, and designating the first and second character strings as similar based on the determined frequency of occurrence. | 2016-02-25 |
20160055142 | System and Method for Metadata Enhanced Inventory Management of a Communications System - A method for management entity operations includes parsing a request to collect data for an entity in a communications system, the parsing to produce a parsed request and dependency information related to the request, and generating sets of model elements in accordance with context tokens and content tokens derived from the parsed request, the content tokens including extrinsic metadata and intrinsic metadata of the parsed request. The method also includes generating a platform-neutral description of results of the request from an optimized graph derived from the sets of model elements, executing the request to collect the data as requested, and storing the data as collected. | 2016-02-25 |
20160055143 | MULTI-USER SEARCH SYSTEM WITH METHODOLOGY FOR BYPASSING INSTANT INDEXING - Multi-user computer search system with methodology for bypassing instant indexing of documents. In some embodiments, for example, a system for bypassing instant indexing includes a token store storing a set of token for a current version of a document and a tokenizer server configured to tokenize a new version of the document and to generate a set of tokens for the new version of the document. The system further includes an instant indexer server configured to determine tokens to index the document by based on identified differences between the set of tokens for the new version of the document and the set of tokens for the current version of the document, to determine whether the new version of the document is a bypass document version or non-bypass document version, and to generate an index mutation for the new version of the document including a specification of whether the generated index mutation is a bypass index mutation or a non-bypass index mutation based on whether the new version of the document is a bypass document version or non-bypass document version. The system also includes an index mutation server configured to provide the generated index mutation to an index server, if the generated index mutation is a non-bypass index mutation, or not provide the generated index mutation to the index server, if the generated index mutation is a bypass index mutation. | 2016-02-25 |
20160055144 | STRING COMPARISON RESULTS FOR CHARACTER STRINGS USING FREQUENCY DATA - A similarity between character strings is assessed by identifying first and second character strings as candidate similar character strings, determining a frequency of occurrence for at least one of the first and second character strings from a collection of character strings, and designating the first and second character strings as similar based on the determined frequency of occurrence. | 2016-02-25 |
20160055145 | ESSAY MANAGER AND AUTOMATED PLAGIARISM DETECTOR - Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for essay managing and plagiarism detecting are disclosed. A method includes receiving one or more essay drafts in response to an essay prompt that is provided by an online college application. The method includes determining one or more subject-verb pairs and one or more adjective-noun pairs for the one or more essay drafts by parsing the one or more essay drafts. The method includes storing the one or more essay drafts and the one or more subject-verb pairs and one or more adjective-noun pairs for the one or more essay drafts. The method includes receiving an additional essay draft in response to an additional essay prompt that is provided by an additional online college application. The method includes determining one or more additional subject-verb pairs and one or more additional adjective-noun pairs for the additional essay draft. | 2016-02-25 |
20160055146 | DOCUMENT PROCESSING DEVICE, DOCUMENT PROCESSING METHOD, PROGRAM, AND INFORMATION STORAGE MEDIUM - Displaying supplemental information for an element in a document based on changes in a user's ability to read the document. A document processing device configured to: acquire information on a document including a plurality of words; acquire pieces of supplemental information being linked with the plurality of words; decide whether or not a piece of supplemental information linked with corresponding one of the plurality of words is to be displayed based on a frequency with which each of the plurality of words has appeared; and control displaying the plurality of words and the pieces of supplemental information. In the deciding, it is decided whether or not the corresponding one of the piece of supplemental information is to be displayed based on a frequency with which each of the plurality of words has been displayed along with the piece of supplemental information. | 2016-02-25 |
20160055147 | METHOD AND SYSTEM FOR PROCESSING SEMANTIC FRAGMENTS - The present invention discloses a method and system for processing semantic fragments. Some embodiments of the present invention provides a method for processing semantic fragments. The method comprises: obtaining a plurality of groups of semantic fragments, the plurality of groups of semantic fragments at least including a first group of semantic fragments generated from a first data processing flow and a second group of semantic fragments generated from a second data processing flow, the first data processing flow being different from the second data processing flow; and merging the first group of semantic fragment and the second group of semantic fragment based on semantic equivalence. A corresponding system is also disclosed. | 2016-02-25 |
20160055148 | TranslateMe - Software Application to Translate Message(s)/Picture(s) through Human Collaboration - TranslateMe is an Application to help a User get the Translation of a message(word or sentences)/picture(s) by sending it to a particular Language Group(s) that the User intends to get translation for. The User seeking to get the message/picture translated sends it to that intended Language Group Users who are proficient in that Language and receives the translated response instantly. The message/picture Translation is purely done by interaction/collaboration with humans using this application. This application is not limited to any specific language, computer device. It can be used to various widely spoken languages all around the world and would be developed for desktop, mobile, tablet and other portable devices. | 2016-02-25 |