08th week of 2016 patent applcation highlights part 53 |
Patent application number | Title | Published |
20160056050 | HIGH ASPECT RATIO PLASMA ETCH FOR 3D NAND SEMICONDUCTOR APPLICATIONS - Embodiments of the present disclosure provide methods for forming features in a film stack that may be utilized to form stair-like structures with accurate profiles control in manufacturing three dimensional (3D) stacking of semiconductor chips. In one example, a method of etching a material layer disposed on a substrate using synchronized RF pulses includes providing an etching gas mixture into a processing chamber having a film stack disposed on a substrate, synchronously pulsing a RF source power and a RF bias power into the etching gas mixture at a ratio of less than 0.5, and etching the film stack disposed on the substrate. | 2016-02-25 |
20160056051 | EXTERNAL GETTERING METHOD AND DEVICE - Disclosed embodiments include external gettering provided by electronic packaging. An external gettering element for a semiconductor substrate, which may be incorporated as part of an electronic packaging for the structure, is disclosed. Semiconductor structures and stacked semiconductor structures including an external gettering element are also disclosed. An encapsulation mold compound providing external gettering is also disclosed. Methods of fabricating such devices are also disclosed. | 2016-02-25 |
20160056052 | METHOD FOR DISSOLVING A SILICON DIOXIDE LAYER - This disclosure relates to a method for dissolving a silicon dioxide layer in a structure, including, from the back surface thereof to the front surface thereof, a supporting substrate, the silicon dioxide layer and a semiconductor layer, the dissolution method being implemented in a furnace in which structures are supported on a support, the dissolution method resulting in the diffusion of oxygen atoms included in the silicon dioxide layer through the semiconductor layer and generating volatile products, and the furnace including traps suitable for reacting with the volatile products, so as to reduce the concentration gradient of the volatile products parallel to the front surface of at least one structure. | 2016-02-25 |
20160056053 | METHOD AND APPARATUS TO DEPOSIT PURE TITANIUM THIN FILM AT LOW TEMPERATURE USING TITANIUM TETRAIODIDE PRECURSOR - Methods of depositing highly conformal and pure titanium films at low temperatures are provided. Methods involve exposing a substrate to titanium tetraiodide, purging the chamber, exposing the substrate to a plasma, purging the chamber, and repeating these operations. Titanium films are deposited at low temperatures less than about 450° C. | 2016-02-25 |
20160056054 | ETCHING METHOD, ETCHING LIQUID AND ETCHING LIQUID KIT TO BE USED IN SAID METHOD, AND SEMICONDUCTOR SUBSTRATE PRODUCT MANUFACTURING METHOD - There is provided an etching method of a semiconductor substrate that includes a first layer containing germanium (Ge) and a second layer containing at least one metal element selected from nickel platinum (NiPt), titanium (Ti), nickel (Ni), and cobalt (Co), the method including: bringing an etching liquid which contains a specific acid compound into contact with the second layer and selectively removing the second layer. | 2016-02-25 |
20160056055 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE THEREOF - A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method for manufacturing a semiconductor device that comprises ordering and performing processing steps in a manner that prevents warpage deformation from occurring to a wafer and/or die due to mismatching thermal coefficients. | 2016-02-25 |
20160056056 | Interconnect Structures for Wafer Level Package and Methods of Forming Same - A method for forming a device package includes forming a molding compound around a die and laminating a polymer layer over the die. A top surface of the die is covered by a film layer while the molding compound is formed, and the polymer layer extends laterally past edge portions of the die. The method further includes forming a conductive via in the polymer layer, wherein the conductive via is electrically connected to a contact pad at a top surface of the die. | 2016-02-25 |
20160056057 | SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME - Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a method including forming a first die package, the first die package including a first die, a first electrical connector, and a first redistribution layer, the first redistribution layer being coupled to the first die and the first electrical connector, forming an underfill over the first die package, patterning the underfill to have an opening to expose a portion of the first electrical connector, and bonding a second die package to the first die package with a bonding structure, the bonding structure being coupled to the first electrical connector in the opening of the underfill. | 2016-02-25 |
20160056058 | MICROELECTRONIC PACKAGES AND METHODS THEREFOR - A method of making a microelectronic assembly can include molding a dielectric material around at least two conductive elements which project above a height of a substrate having a microelectronic element mounted thereon, so that remote surfaces of the conductive elements remain accessible and exposed within openings extending from an exterior surface of the molded dielectric material. The remote surfaces can be disposed at heights from said surface of said substrate which are lower or higher than a height of the exterior surface of the molded dielectric material from the substrate surface. The conductive elements can be arranged to simultaneously carry first and second different electric potentials: e.g., power, ground or signal potentials. | 2016-02-25 |
20160056059 | COMPONENT FOR SEMICONDUCTOR PROCESS CHAMBER HAVING SURFACE TREATMENT TO REDUCE PARTICLE EMISSION - Examples of the disclosure generally relate to a component for use in a semiconductor process chamber includes a body having machined surfaces including a first surface and a second surface. The first surface is configured to interface with a support member of the semiconductor process chamber. The second surface is configured to face a processing region of the semiconductor process chamber. A treated area of the second surface includes relatively flatter peaks than an untreated area of the machined surfaces and exhibits an average roughness between 1 and 30 micro-inches. | 2016-02-25 |
20160056060 | CLEANING MEMBER, CLEANING APPARATUS, AND CLEANING METHOD - A cleaning member configured to clean a semiconductor substrate by relatively sliding over a surface of the semiconductor substrate is disclosed. The cleaning member includes a holding portion; and a brush portion supported by the holding portion and including an ion exchange resin. | 2016-02-25 |
20160056061 | REAL TIME LIQUID PARTICLE COUNTER (LPC) END POINT DETECTION SYSTEM - Embodiments of the present invention generally relate to a method and apparatus for ex-situ cleaning of a chamber component. More particularly, embodiments of the present invention generally relate to a method and apparatus for endpoint detection during ex-situ cleaning of a chamber component used in a semiconductor processing chamber. In one embodiment, a system for cleaning parts disposed in a liner with a cleaning fluid is provided. The system comprises a portable cart, a liquid particle counter (LPC) carried by the portable cart, the LPC configured for detachable coupling to a fluid outlet port formed through the liner, the LPC operable to sample rinsate solution exiting the line, and a pump carried by the portable cart and configured for fluid coupling to the liner in a detachable manner, the pump operable to recirculate rinsate solution through the liner. | 2016-02-25 |
20160056062 | IONIZER AND SUBSTRATE TRANSFER SYSTEM HAVING THE SAME, AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - An ionizer includes a body extending in a first direction, a sheath gas nozzle installed in a lower portion of the body and having a spray hole and an electrode needle disposed within the spray hole to generate a corona discharge, a gas supply provided in the body and configured to be in fluid communication with the spray hole to supply a gas to the spray hole such that ions generated by the electrode needle are spayed out to the outside of the ionizer from the spray hole, and a pair of first and second guiding plates disposed at opposite sides of the sheath gas nozzle and extending downward from first and second sides of the body opposite to each other to guide the ions sprayed from the spray hole to be directed to a target. A semiconductor device may be manufactured using the ionizer. | 2016-02-25 |
20160056063 | UNDERFILL DISPENSING WITH CONTROLLED FILLET PROFILE - A method includes placing an underfill-shaping cover on a package component of a package, with a device die of the package extending into an opening of the underfill-shaping cover. An underfill is dispensed into the opening of the underfill-shaping cover. The underfill fills a gap between the device die and the package component through capillary. The method further includes, with the underfill-shaping cover on the package component, curing the underfill. After the curing the underfill, the underfill-shaping cover is removed from the package. | 2016-02-25 |
20160056064 | ANOMALY DETECTION SYSTEM AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, there is provided an anomaly detection system for a second unit incidental to a first unit that processes a substrate. The anomaly detection system includes a collecting unit, a first calculating unit, a second calculating unit, and a determining unit. The collecting unit is configured to collect a plurality of types of parameters related to a state of the second unit. The first calculating unit is configured to calculate a divergence of a coordinate point from a reference space in a virtual coordinate space of a plurality of types of parameters, the coordinate point being indicated by the plurality of types of collected parameters. The second calculating unit is configured to accumulate the calculated divergence and calculate a cumulative divergence. The determining unit is configured to compare the calculated cumulative divergence with a threshold value and determine an anomaly in the second unit. | 2016-02-25 |
20160056065 | METHOD AND APPARATUS FOR REMOVING EXPERIMENTAL ARTIFACTS FROM ENSEMBLE IMAGES - A method and apparatus wherein a photoluminescence in a semiconductor wafer is excited using an ultraviolet light source. A plurality of partial raw images of the photoluminescence is generated. The plurality of partial raw images includes at least one equipment-generated artifact The at least one equipment-generated artifact is removed from the cluster of partial raw images using the equipment-generated artifact image to generate a cluster of partial processed images. A plurality of clusters of partial processed images is generated. The plurality of clusters of partial processed images are aligned and combined to generate a wafer image tree of the at least one equipment-generated artifact. | 2016-02-25 |
20160056066 | ADHESIVE SHEET USED IN MANUFACTURE OF SEMICONDUCTOR DEVICE, ADHESIVE SHEET INTEGRATED WITH DICING TAPE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The present invention provides an adhesive sheet used in manufacture of a semiconductor device, containing a filler having an average particle size of 0.3 μm or less and an acrylic resin, wherein the content of the filler is in the range of 20 to 45% by weight with respect to the entire adhesive sheet, and the content of the acrylic resin is in the range of 40 to 70% by weight with respect to entire resin components. | 2016-02-25 |
20160056067 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment, includes a plurality of wires, a first dielectric film, and a second dielectric film. The plurality of wires are arranged above a semiconductor substrate so as to extend in a first direction and aligned via a first cavity. The first dielectric film has a plurality of portions arranged above the plurality of wires so as to extend in a second direction substantially perpendicular to the plurality of wires and aligned along the first direction via a second cavity leading to the first cavity. The second dielectric film is formed above the first dielectric film so as to cover the second cavity. | 2016-02-25 |
20160056068 | THIN FILM AND METHOD FOR MANUFACTURING THIN FILM - The present invention provides a kind of thin film and a fabrication method of thin films. The method comprises implanting ions under the surface of the original substrate by ion-implanting method, hence creating a thin film layer, a splitting layer and a remaining material layer on the original substrate; wherein, the thin film layer is on the surface of the original substrate and the splitting layer is between the thin film layer and the remaining material layer; the implanted ions are distributed in the splitting layer. Make the target substrate be in contact with the thin film layer of the original substrate, and then bond the original substrate to the target substrate by wafer-bonding method to form a bonding unit. Place the bonding unit into a prepared container to heat the bonding unit, so that the thin film layer is split off from the remaining material layer. After the splitting of the thin film layer and the remaining material layer, continue to heat the thin film layer and the target substrate in the prepared container for scheduled time under the condition of high pressure atmosphere. The present invention can greatly reduce the defect density of thin films, and the thin films fabricated thereby are with a large size, an equal area to that of the wafer, nanoscale thickness and good uniformity of film thickness. | 2016-02-25 |
20160056069 | Methods of Forming Memory Arrays - Some embodiments include methods of forming memory arrays. An assembly is formed which has an upper level over a lower level. The lower level includes circuitry. The upper level includes semiconductor material within a memory array region, and includes insulative material in a region peripheral to the memory array region. First and second trenches are formed to extend into the semiconductor material. The first and second trenches pattern the semiconductor material into a plurality of pedestals. The second trenches extend into the peripheral region. Contact openings are formed within the peripheral region to extend from the second trenches to the first level of circuitry. Conductive material is formed within the second trenches and within the contact openings. The conductive material forms sense/access lines within the second trenches and forms electrical contacts within the contact openings to electrically couple the sense/access lines to the lower level of circuitry. | 2016-02-25 |
20160056070 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Both enhancement of embeddability of a wiring groove and suppression of the generation of a coupling failure between a wiring and a coupling member are simultaneously achieved. In a cross-section perpendicular to a direction passing through the contact and a direction in which the second wiring extends, the center of the contact is more close to a first side surface of the second wiring than the center of the second wiring. In addition, when a region where the first side surface of the second wiring overlaps the contact in the direction in which the second wiring extends, is set to be an overlapping region, at least the lower part of the overlapping region has an inclination steeper than that of other portions of the side surface of the second wiring. | 2016-02-25 |
20160056071 | FLOWABLE DIELECTRIC FOR SELECTIVE ULTRA LOW-K PORE SEALING - Implementations of the methods and apparatus disclosed herein relate to pore sealing of porous dielectric films using flowable dielectric material. The methods involve exposing a substrate having an exposed porous dielectric film thereon to a vapor phase dielectric precursor under conditions such that a flowable dielectric material selectively deposits in the pores of the porous dielectric material. The pores can be filled with the deposited flowable dielectric material without depositing a continuous film on any exposed metal surface. | 2016-02-25 |
20160056072 | MULTILAYERED CONTACT STRUCTURE HAVING NICKEL, COPPER, AND NICKEL-IRON LAYERS - A three dimensional multi-die package includes a first die and second die. The first die includes a contact attached to solder. The second die is thinned by adhesively attaching a handler to a top side of the second die and thinning a bottom side of the second die. The second die includes a multilayer contact of layered metallurgy that inhibits transfer of adhesive thereto. The layered metallurgy includes at least one layer that is wettable to the solder. The multilayer contact may include a Nickel layer, a Copper layer upon the Nickel layer, and a Nickel-Iron layer upon the Copper layer. The multilayer contact may also include a Nickel layer, a Copper-Tin layer upon the Nickel layer, and a Tin layer upon the Copper-Tin layer. | 2016-02-25 |
20160056073 | Semiconductor Constructions; and Methods for Providing Electrically Conductive Material Within Openings - Some embodiments include methods for depositing copper-containing material utilizing physical vapor deposition of the copper-containing material while keeping a temperature of the deposited copper-containing material at greater than 100° C. Some embodiments include methods in which openings are lined with a metal-containing composition, copper-containing material is physical vapor deposited over the metal-containing composition while a temperature of the copper-containing material is no greater than about 0° C., and the copper-containing material is then annealed while the copper-containing material is at a temperature in a range of from about 180° C. to about 250° C. Some embodiments include methods in which openings are lined with a composition containing metal and nitrogen, and the lined openings are at least partially filled with copper-containing material. Some embodiments include semiconductor constructions having a metal nitride liner along sidewall peripheries of an opening, and having copper-containing material within the opening and directly against the metal nitride liner. | 2016-02-25 |
20160056074 | METHOD FOR VOID-FREE COBALT GAP FILL - Provided herein are methods of depositing void-free cobalt into features with high aspect ratios. Methods involve (a) partially filling a feature with cobalt, (b) exposing the feature to a plasma generated from nitrogen-containing gas to selectively inhibit cobalt nucleation on surfaces near or at the top of the feature, optionally repeating (a) and (b), and depositing bulk cobalt into the feature by chemical vapor deposition. Methods may also involve exposing a feature including a barrier layer to a plasma generated from nitrogen-containing gas to selectively inhibit cobalt nucleation. The methods may be performed at low temperatures less than about 400° C. using cobalt-containing precursors. | 2016-02-25 |
20160056075 | PRECUT METAL LINES - Embodiments of the present invention provide a method for cuts of sacrificial metal lines in a back end of line structure. Sacrificial Mx+1 lines are formed above metal Mx lines. A line cut lithography stack is deposited and patterned over the sacrificial Mx+1 lines and a cut cavity is formed. The cut cavity is filled with dielectric material. A selective etch process removes the sacrificial Mx+1 lines, preserving the dielectric that fills in the cut cavity. Precut metal lines are then formed by depositing metal where the sacrificial Mx+1 lines were removed. Thus embodiments of the present invention provide precut metal lines, and do not require metal cutting. By avoiding the need for metal cutting, the risks associated with metal cutting are avoided. | 2016-02-25 |
20160056076 | INTERCONNECT STRUCTURE - Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer. | 2016-02-25 |
20160056077 | METHOD FOR VOID-FREE COBALT GAP FILL - Provided herein are methods of depositing void-free cobalt into features with high aspect ratios. Methods involve (a) partially filling a feature with cobalt, (b) exposing the feature to a plasma generated from nitrogen-containing gas to selectively inhibit cobalt nucleation on surfaces near or at the top of the feature, optionally repeating (a) and (b), and depositing bulk cobalt into the feature by chemical vapor deposition. Methods may also involve exposing a feature including a barrier layer to a plasma generated from nitrogen-containing gas to selectively inhibit cobalt nucleation. The methods may be performed at low temperatures less than about 400° C. using cobalt-containing precursors. Methods may also involve using a remote plasma source to generate the nitrogen-based plasma. Methods also involve annealing the substrate. | 2016-02-25 |
20160056078 | Metal Pad Structure Over TSV to Reduce Shorting of Upper Metal Layer - Various embodiments of mechanisms for forming a slotted metal pad over a TSV in substrate are provided. The dielectric structures in the slotted metal pad reduce dishing effect during planarization of the slotted metal pad. As a result, the risk of having metal stringers in upper metal level(s) caused by the dishing effect is greatly reduced. | 2016-02-25 |
20160056079 | Method of Manufacturing a Package-on-Package Type Semiconductor Package - A method for manufacturing a semiconductor package, for example a package-on-package type semiconductor device package. As non-limiting examples, various aspects of this disclosure provide high-yield methods for manufacturing a package-on-package type semiconductor package, or a portion thereof. | 2016-02-25 |
20160056080 | SEMICONDUCTOR PIECE MANUFACTURING METHOD AND SUBSTRATE DICING METHOD - A semiconductor piece manufacturing method includes: a process of forming a groove on a front surface side including a first groove portion having a first width from a front surface of a substrate and a second groove portion that is positioned in a lower part that communicates with the first groove portion and has a second width larger than the first width; and a process of forming a groove on a rear surface side having a width greater than the first width along the second groove portion from a rear surface of the substrate by a rotating cutting member. | 2016-02-25 |
20160056081 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate. | 2016-02-25 |
20160056082 | CHEMICAL MECHANICAL POLISHING METHOD FOR FIRST INTERLAYER DIELECTRIC LAYER - A method for manufacturing a semiconductor device includes providing a semiconductor substrate comprising a low-density region and a high-density region, forming a first gate structure in the low-density region and a second gate structure in the high-density region, form an etch stop layer on the first and second gate structures, and forming an interlayer dielectric layer on the etch stop layer and on the semiconductor substrate. The method further includes performing a first chemical mechanical polishing (CMP) process on the etch stop layer to expose a surface of a portion of the etch stop layer disposed on the first gate structure, performing a second CMP process on the etch stop layer to expose a surface of a portion of the etch stop layer disposed on the second gate structure, and performing a third CMP process to completely remove the etch stop layer. | 2016-02-25 |
20160056083 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device includes forming an active pattern and a gate electrode crossing the active pattern on a substrate, forming a first contact connected to the active pattern at a side of the gate electrode, forming a second contact connected to the gate electrode, and forming a third contact connected to the first contact at the side of the gate electrode. The third contact is formed using a photomask different from that used to form the first contact. A bottom surface of the third contact is disposed at a level in the device lower than the level of a top surface of the first contact. | 2016-02-25 |
20160056084 | POWER SEMICONDUCTOR DEVICE AND METHOD THEREFOR - A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions. | 2016-02-25 |
20160056085 | SEMICONDUCTOR DEVICE TESTING APPARATUS, SEMICONDUCTOR DEVICE TESTING METHOD, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device testing apparatus according to an embodiment includes: a first terminal and a second terminal that apply voltage to a semiconductor device; and a light source that irradiates the semiconductor device with ultraviolet light. | 2016-02-25 |
20160056086 | Temporary Bonding Scheme - A method includes filling a trench formed in a first integrated circuit carrier with temporary bonding material to form a temporary bonding layer. At least one chip is bonded over the temporary bonding layer. | 2016-02-25 |
20160056087 | PACKAGE-ON-PACKAGE STRUCTURE WITH ORGANIC INTERPOSER - A device comprises a substrate having a die mounted on the first side of the substrate and a moldable underfill (MUF) disposed on the first side of the substrate and around the die. An interposer is mounted on the first side of the substrate, with the interposer having lands disposed on a first side of the interposer. The interposer mounted to the substrate by connectors bonded to a second side of the interposer, the connectors providing electrical connectivity between the interposer and the substrate. A package is mounted on the first side of the interposer and is electrically connected to the lands. At least one of the lands is aligned directly over the die and wherein a pitch of the connectors is different than a pitch of the lands. | 2016-02-25 |
20160056088 | Cold Plate, Device Comprising a Cold Plate and Method for Fabricating a Cold Plate - A cold plate includes a single piece member and a channel. A top side of the channel is open. A bottom side of the channel opposite the top side has an inlet and an outlet. | 2016-02-25 |
20160056089 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICE - A semiconductor device includes: a first semiconductor element; a first substrate provided on the first semiconductor element and including a cavity with reduced pressure; coolant held inside the cavity; a second semiconductor element provided on the first substrate; and a heat spreading member thermally connected to the first substrate and provided with a hole communicated with the cavity. | 2016-02-25 |
20160056090 | TSV Formation - A device includes a substrate having a front side and a backside, the backside being opposite the front side. An isolation layer is disposed on the front side of the substrate, wherein first portions of isolation layer and the substrate are in physical contact. A through substrate via (TSV) extends from the front side to the backside of the substrate. An oxide liner is on a sidewall of the TSV. The oxide liner extends between second portions of the substrate and the isolation layer. A dielectric layer having a metal pad is disposed over the isolation layer on the front side of the substrate. The metal pad and the TSV are formed of a same material. | 2016-02-25 |
20160056091 | SEMICONDUCTOR PACKAGE AND ELECTRONIC APPARATUS INCLUDING THE SAME - Provided are a curved semiconductor package, and a device including the semiconductor package. The semiconductor package includes: a flexible printed circuit board (PCB) including a fixed bent portion formed as an arch-shape and including a first surface facing a first direction and a second surface opposite to the first surface; at least one semiconductor chip attached to the second surface of the fixed bent portion of the flexible PCB; and a mold layer having rigidity and formed on the second surface of the fixed bending portion of the flexible PCB while surrounding the at least one semiconductor chip. | 2016-02-25 |
20160056092 | Leadframe and method of manufacturing the same - A hybrid leadframe is provided comprising a thin leadframe layer comprising a diepad and a structured region; and a metal layer being thicker than the thin leadframe layer and arranged on the diepad. | 2016-02-25 |
20160056093 | SOLDER FLOW-IMPEDING PLUG ON A LEAD FRAME - Embodiments described herein relate to a packaged component including a lead frame and a non-conductive plug disposed between two or more adjacent sections of the lead frame. The plug is composed of a non-conductive material functions to impede the flow of solder along edges of the two or more adjacent sections during second level solder reflow events that occur after encapsulation of the packaged component. The plug includes a main portion disposed within a space between the two or more adjacent sections, and one or more overlap portions extending from the main portion. The one or more overlap portions are disposed on an internal surface of at least one of the two or more adjacent sections. At least one component is mounted on one of the plurality of sections of the lead frame. | 2016-02-25 |
20160056094 | BALL GRID ARRAY PACKAGE WITH MORE SIGNAL ROUTING STRUCTURES - A semiconductor package includes a substrate, a die mounted on a first side of the substrate, an array of solder balls mounted on a second, opposite side of the substrate, and a signal-routing structure mounted on the first side of the substrate and adjacent to the die. The substrate and the signal-routing structure provide electrical connections between die pads on the die and some of the solder balls. | 2016-02-25 |
20160056095 | Leadframe Strip with Sawing Enhancement Feature - A leadframe strip includes a plurality of leads chemically etched into a metal sheet, a plurality of support structures chemically etched into the metal sheet, and a plurality of connecting structures chemically etched into the metal sheet. Each of the connecting structures is integrally connected at a first end to one of the leads and integrally connected at a second end to one of the support structures so that the leads are held in place by the support structures. The width of each connecting structure is at a minimum between the first and second ends of that connecting structure, increases from the minimum in a direction toward the first end, and increases from the minimum in a direction toward the second end. A method of manufacturing such a leadframe strip is also provided. | 2016-02-25 |
20160056096 | POWER SEMICONDUCTOR DEVICE AND PREPARATION METHOD THEREOF - A preparation method for a power semiconductor device includes: providing a lead frame containing a plurality of chip mounting units, one side edge of a die paddle of each chip mounting unit is bent and extended upwardly and one lead connects to the bent side edge of the die paddle and extends in an opposite direction from the die paddle; attaching a semiconductor chip to the top surface of the die paddle; forming metal bumps on each electrode at the front of the semiconductor chip with a top end of each metal bump protruding out of a plane of the top surface of the lead; heating the metal bump and pressing a top end of each metal bump by a pressing plate forming a flat top end surface that is flush with the top surface of the lead; and cutting the lead frame to separate individual chip mounting units. | 2016-02-25 |
20160056097 | SEMICONDUCTOR DEVICE WITH INSPECTABLE SOLDER JOINTS - A Quad Flat Non-leaded (QFN) semiconductor die package has a semiconductor die mounted on a die flag of a lead frame. A covers the semiconductor die. The housing has a base and sides. There are electrically conductive mounting feet, each of which has an exposed base portion in the base of the housing and an exposed side portion in the one of the sides of the housing. Bond wires electrically connect electrodes of the semiconductor die to respective ones of the mounting feet. | 2016-02-25 |
20160056098 | SEMICONDUCTOR DEVICE EMPLOYING ALUMINUM ALLOY LEAD-FRAME WITH ANODIZED ALUMINUM - A semiconductor device comprises an aluminum alloy lead-frame with a passivation layer covering an exposed portion of the aluminum alloy lead-frame. Since aluminum alloy is a low-cost material, and its hardness and flexibility are suitable for deformation process, such as punching, bending, molding and the like, aluminum alloy lead frame is suitable for mass production; furthermore, since its weight is much lower than copper or iron-nickel material, aluminum alloy lead frame is very convenient for the production of semiconductor devices. | 2016-02-25 |
20160056099 | INTEGRATED CIRCUIT WITH ON-DIE DECOUPLING CAPACITORS - A semiconductor device has an on-die decoupling capacitor that is shared between alternative high-speed interfaces. A capacitance pad is connected to the decoupling capacitor and internal connection pads are connected respectively to the alternative interfaces. Internal connection bond wires connect the decoupling capacitor to the selected interface through the capacitance pad and the internal connection pads in the same process as connecting the die to external electrical contacts of the device. | 2016-02-25 |
20160056100 | Packages Having Integrated Devices and Methods of Forming Same - An embodiment device package includes a discrete device, a first connector on a bottom surface of the discrete device, and a second connector on a top surface of the discrete device. The first connector bonds the discrete device to a first package component, and the second connector bonds the discrete device to a second package component. | 2016-02-25 |
20160056101 | CHIP-STACKED SEMICONDUCTOR PACKAGE - A chip-stacked semiconductor package including a first chip having a plurality of first real bump pads and a plurality of first dummy bump pads, a second chip on the first chip, the second chip including a plurality of real bumps and a plurality of bridge dummy bumps, the plurality of real bumps electrically connected to the plurality of first real bump pads, the plurality of bridge dummy bumps connected to the plurality of first dummy bump pads, and a sealing member sealing the first chip and the second chip may be provided. | 2016-02-25 |
20160056102 | DUAL SIDE SOLDER RESIST LAYERS FOR CORELESS PACKAGES AND PACKAGES WITH AN EMBEDDED INTERCONNECT BRIDGE AND THEIR METHODS OF FABRICATION - A coreless package substrate with dual side solder resist layers is disclosed. The coreless package substrate has a top side and a bottom side opposite of the top side and includes a single build-up structure formed of at least one insulating layer, at least one via, and at least one conductive layer. The coreless package substrate also includes a bottom plurality of contact pads on the bottom side, and a top plurality of contact pads on the top side. A bottom solder resist layer is on the bottom side, and a top solder resist layer is on the top side. The concept of dual side solder resist is extended to packages with interconnect bridge with C4 interconnection pitch over a wide range. | 2016-02-25 |
20160056103 | SEMICONDUCTOR PACKAGES WITH A SUBSTRATE BETWEEN A PAIR OF SUBSTRATES - Semiconductor packages are provided. A semiconductor package includes a first substrate including a first semiconductor chip thereon. The semiconductor package includes a second substrate on the first substrate, the second substrate including a second semiconductor chip thereon. Moreover, the semiconductor package includes a third substrate between the first and second substrates. | 2016-02-25 |
20160056104 | SELF-ALIGNED BACK END OF LINE CUT - Embodiments of the present invention provide a method for self-aligned metal cuts in a back end of line structure. Sacrificial Mx+1 lines are formed above metal Mx lines. Spacers are formed on each Mx+1 sacrificial line. The gap between the spacers is used to determine the location and thickness of cuts to the Mx metal lines. This ensures that the Mx metal line cuts do not encroach on vias that interconnect the Mx and Mx+1 levels. It also allows for reduced limits in terms of via enclosure rules, which enables increased circuit density. | 2016-02-25 |
20160056105 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate, a first passivation layer disposed on the substrate, and an under bump metallurgy layer disposed on the first passivation layer. An additional under bump metallurgy layer is disposed on the first passivation layer, isolated from the under bump metallurgy layer; and a conductive pillar disposed on the additional under bump metallurgy layer. | 2016-02-25 |
20160056106 | STRUCTURE WITH SELF ALIGNED RESIST LAYER ON AN INTERCONNECT SURFACE AND METHOD OF MAKING SAME - A structure is provided with a self-aligned resist layer on a surface of metal interconnects for use in forming air gaps in an insulator material and method of fabricating the same. The non-lithographic method includes applying a resist on a structure comprising at least one metal interconnect formed in an insulator material. The method further includes blanket-exposing the resist to energy and developing the resist to expose surfaces of the insulator material while protecting the metal interconnects. The method further includes forming air gaps in the insulator material by an etching process, while the metal interconnects remain protected by the resist. | 2016-02-25 |
20160056107 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A wiring structure thereof includes a first interlayer insulating film, a first wiring and a first electrode for the capacitive element embedded in the first interlayer insulating film, a barrier insulating film formed over the first interlayer insulating film to cover the wiring and the electrode, a second interlayer insulating film formed over the barrier insulating film, and a second wiring and a second electrode for the capacitive element embedded in the second interlayer insulating film. The lower surface of the second wiring is positioned in the middle of the thickness of the second interlayer layer film, and the lower surface of the second electrode is in contact with the barrier insulating film. The barrier insulating film of a portion interposed between both electrodes functions as a capacitance insulating film of the capacitive element and is thicker than the barrier insulating film of a portion covering the first wiring. | 2016-02-25 |
20160056108 | WIRING FOR SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME - A method for forming a wiring for a semiconductor device according to an aspect of the present invention includes: forming a predetermined pattern on a first surface of a silicon substrate by selectively etching the first surface; coating, with a metal layer, a selected area of the first surface, including an area whereat the predetermined pattern is formed; forming organic material in the first surface to fill an etched portion and cover the coated metal layer; forming a plurality of via holes in the organic material and connecting the metal wiring to the coated metal layer through the via holes; and grinding a second surface corresponding to the first surface to remove a part of the metal layer formed in the etched portion. | 2016-02-25 |
20160056109 | E-FUSE STRUCTURE OF SEMICONDUCTOR DEVICE - Provided is an e-fuse structure of a semiconductor device having improved fusing performance so as to enable a program operation at a low voltage. The e-fuse structure includes a first metal pattern formed at a first vertical level, the first metal pattern including a first part extending in a first direction and a second part extending in the first direction and positioned to be adjacent to the first part, and a third part adjacent to the second part, the second part being positioned between the first part and the third part, the first part and the second part being electrically connected to each other, and the third part being electrically disconnected from the second part; and a second metal pattern electrically connected to the first metal pattern and formed at a second vertical level different from the first vertical level. | 2016-02-25 |
20160056110 | METHOD OF FORMING A PATTERN - A method of forming a pattern includes forming a mask pattern on a substrate; etching the substrate by deep reactive ion etching (DRIE) and by using the mask pattern as an etch mask; partially removing the mask pattern to expose a portion of an upper surface of the substrate; and etching the exposed portion of the upper surface of the substrate. In the method, when a pattern is formed by DRIE, an upper portion of the pattern does not protrude or scarcely protrudes, and scallops of a sidewall of the pattern are smooth, and thus a conformal material layer may be easily formed on a surface of the pattern. | 2016-02-25 |
20160056111 | HYDROGEN-FREE SILICON-BASED DEPOSITED DIELECTRIC FILMS FOR NANO DEVICE FABRICATION - Embodiments of the present invention provide hydrogen-free dielectric films and methods of fabrication. A hydrogen-free precursor, such as tetraisocyanatosilane, and hydrogen-free reactants, such as nitrogen, oxygen (O2/O3) and nitrous oxide are used with chemical vapor deposition processes (PECVD, thermal CVD, SACVD, HDP CVD, and PE and Thermal ALD) to create hydrogen-free dielectric films. In some embodiments, there are multilayer dielectric films with sublayers of various materials such as silicon oxide, silicon nitride, and silicon oxynitride. In embodiments, the hydrogen-free reactants may include Tetra Isocyanato Silane, along with a hydrogen-free gas including, but not limited to, N2, O2, O3, N2O, CO2, CO and a combination thereof of these H-Free gases. Plasma may be used to enhance the reaction between the TICS and the other H-free gasses. The plasma may be controlled during film deposition to achieve variable density within each sublayer of the films. | 2016-02-25 |
20160056112 | INTERCONNECT STRUCTURE - Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer. | 2016-02-25 |
20160056113 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - Semiconductor devices and methods for manufacturing a semiconductor device include a first semiconductor substrate in which a first scribe line region and a first chip region are defined, a first alignment mark inside the first semiconductor substrate and in the first scribe line region so as to be spaced apart from an upper side of the first semiconductor substrate, a second semiconductor substrate on the first semiconductor substrate and in which a second scribe line region and a second chip region are defined, and a second alignment mark inside the second semiconductor substrate and in the second scribe line region so as to be spaced apart from an upper side of the second semiconductor substrate, wherein the second semiconductor substrate is on the first semiconductor substrate so that positions of the first alignment mark and the second alignment mark correspond to each other. | 2016-02-25 |
20160056114 | TRENCHED FARADAY SHIELDING - A device includes a semiconductor substrate having a surface with a trench, first and second conduction terminals supported by the semiconductor substrate, a control electrode supported by the semiconductor substrate between the first and second conduction terminals and configured to control flow of charge carriers during operation between the first and second conduction terminals, and a Faraday shield supported by the semiconductor substrate and disposed between the control electrode and the second conduction terminal. At least a portion of the Faraday shield is disposed in the trench. | 2016-02-25 |
20160056115 | OPTICAL SEMICONDUCTOR DEVICE - A technique is provided which can prevent the quality of an electrical signal from degrading in an optical semiconductor device. | 2016-02-25 |
20160056116 | FABRICATING PILLAR SOLDER BUMP - A substrate bonding method is able to reliably bond substrates while avoiding a reduction in yield made worse by finer pitches. The substrate bonding method can include: forming an adhesive resin layer on a surface of a first substrate on which a pad has been formed; forming an opening on the adhesive resin layer above the pad; filling the opening with molten solder to form a pillar-shaped solder bump; and applying heat and pressure to the first substrate and a second substrate while a terminal formed on the second substrate is aligned with the solder bump. | 2016-02-25 |
20160056117 | Directly Sawing Wafers Covered with Liquid Molding Compound - A method includes forming a passivation layer over a metal pad, wherein the metal pad is further overlying a semiconductor substrate of a wafer. A Post-Passivation Interconnect (PPI) is formed to electrically couple to the metal pad, wherein a portion of the PPI is overlying the passivation layer. A metal bump is formed over and electrically coupled to the PPI. The method further includes applying a molding compound over the metal bump and the PPI, applying a release film over the molding compound, pressing the release film against the molding compound, and curing the molding compound when the release film is pressed against the molding compound. The release film is then removed from the molding compound. The wafer is sawed into dies using a blade, with the blade cutting through the molding compound. | 2016-02-25 |
20160056118 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND SEMICONDUCTOR LIGHT EMITTING DEVICE PACKAGE USING THE SAME - A semiconductor light emitting device includes a multi-region solder pad. The semiconductor light emitting device includes a light emitting diode (LED) chip having a first surface on which first and second electrodes are disposed and a second surface opposing the first surface. A passivation layer is disposed on a surface of the LED chip such that bonding regions of the first and second electrodes are exposed through the passivation layer. A solder pad is disposed in each respective bonding region and has a plurality of separated regions. A solder bump is disposed in each respective bonding region and covers the plurality of separated regions of the respective solder pad. In the semiconductor light emitting device, separation between the solder pad and the solder bump may thereby be effectively prevented by ensuring that an interface between a solder pad and a solder bump is not entirely damaged. | 2016-02-25 |
20160056119 | FLIP CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A flip chip package and a manufacturing method thereof are disclosed. The flip chip package in accordance with an embodiment of the present invention includes: a substrate; a plurality of pads formed on the substrate; a solder resist covering the substrate in such a way that the pads are exposed; a chip mounted on the substrate in such a way that the chip is electrically connected with the pads; a plurality of bumps formed, respectively, on the pads in such a way that the bumps are interposed between the pads and the chip; an under-fill flowing between the substrate and the chip and being filled in between the substrate and the chip; and an opening placed in between the plurality of bumps in such a way that a flowing space of the under-fill is provided in between the plurality of bumps. | 2016-02-25 |
20160056120 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND ADHESIVE FOR MOUNTING FLIP CHIP - The present invention aims to provide a method for producing a semiconductor device, the method being capable of achieving high reliability by suppressing voids. The present invention also aims to provide a flip-chip mounting adhesive for use in the method for producing a semiconductor device. The present invention relates to a method for producing a semiconductor device, including: step 1 of positioning a semiconductor chip on a substrate via an adhesive, the semiconductor chip including bump electrodes each having an end made of solder; step 2 of heating the semiconductor chip at a temperature of the melting point of the solder or higher to solder and bond the bump electrodes of the semiconductor chip to an electrode portion of the substrate, and concurrently to temporarily attach the adhesive; and step 3 of removing voids by heating the adhesive under a pressurized atmosphere, wherein the adhesive has an activation energy ΔE of 100 kJ/mol or less, a reaction rate of 20% or less at 2 seconds at 260° C., and a reaction rate of 40% or less at 4 seconds at 260° C., as determined by differential scanning calorimetry and Ozawa method. | 2016-02-25 |
20160056121 | Metallized electric component - Various embodiments provide a metallized electric component for an electronic module, wherein the metallized electric component comprises a conductive electric element; and a metallization structure arranged over the conductive electric element and comprising at least a surface metallization layer, wherein the surface metallization layer comprises gold and silver and has a thickness between 2 nm and 100 nm. | 2016-02-25 |
20160056122 | SEMICONDUCTOR PACKAGE HAVING OVERHANG PORTION - A semiconductor package may include a substrate, and a structural body disposed over the substrate. The semiconductor package may include a semiconductor chip stacked over the structural body, and having an overhang portion projecting over a side surface of the structural body and overhanging out over the side surface of the structural body. The semiconductor package may include one or more bonding pads disposed on the overhang portion, and one or more wires electrically coupling the bonding pads to the substrate. The semiconductor package may include a wire fixing film attached onto the structural body, and overhanging out over the side surface of the structural body to fix the one or more wires. | 2016-02-25 |
20160056123 | SEALING SHEET, METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, AND SUBSTRATE WITH SEALING SHEET - Provided are a sealing sheet capable of suppressing generation of voids due to satisfactory embeddability in irregularities of a semiconductor element or an adherend and with satisfactory workability before and after the sealing sheet is bonded to the adherend; a method for producing a semiconductor device using the sealing sheet; and a substrate with the sealing sheet bonded thereto. The sealing sheet includes a base material, and an under-fill material provided thereon having the following characteristics: a 90° peel strength from the base material of 1 mN/20 mm or more and 50 mN/20 mm or less; a rupture elongation of 10% or more at 25° C.; a minimum viscosity of 20,000 Pa·s or less at a temperature of 40° C. or more and 100° C. or less; and a minimum viscosity of 100 Pa·s or more at a temperature of 100° C. or more and 200° C. or less. | 2016-02-25 |
20160056124 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Chip cracking that occurs when a dicing step using a blade is carried out to acquire semiconductor chips with the reduced thickness of a semiconductor wafer is suppressed. When the semiconductor wafer is cut at the dicing step for the semiconductor wafer, a blade is advanced as follows: in dicing in a first direction (Y-direction in FIG. | 2016-02-25 |
20160056125 | Hybrid Interconnect for Chip Stacking - Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a substrate, and adhering a first semiconductor device. Chip stacks are formed by providing a plurality of semiconductor devices and bonding them to the substrate and the first semiconductor device. At least one of the provided semiconductor devices is physically connected to both the substrate and the first semiconductor device it is stack on. Other semiconductor devices may stacked by forming conductive channels in the first semiconductor device, and placing the other semiconductor devices in physical contact with the first semiconductor device and the conductive channels. | 2016-02-25 |
20160056126 | INTERCONNECT STRUCTURES FOR WAFER LEVEL PACKAGE AND METHODS OF FORMING SAME - A device package includes a plurality of dies, a molding compound extending along sidewalls of the plurality of dies, and a polymer layer over and contacting the molding compound. The molding compound comprises a non-planar top surface, and a total thickness variation (TTV) of a top surface of the polymer layer is less than a TTV of the non-planar top surface of the molding compound. The device package further includes a conductive feature on the polymer layer, wherein the conductive feature is electrically connected at least one of the plurality of dies. | 2016-02-25 |
20160056127 | SEMICONDUCTOR PACKAGE - A semiconductor package according to an embodiment of the inventive concept includes: a package substrate includes: a first through-hole disposed in a chip region; a second through-hole disposed in a edge region; a first bonding pad disposed on the edge region, the first bonding pad being adjacent to the first through-hole; and a second bonding pad disposed on the edge region, the second bonding pad being spaced apart from the first bonding pad, the second bonding pad being adjacent to the second through-hole, wherein one of a semiconductor chips disposed in the chip region is connected to the second bonding pad by a second bonding wire, and a second pattern connected to the second bonding pad is extended to the second through-hole. | 2016-02-25 |
20160056128 | CHIP PACKAGE MODULE AND PACKAGE SUBSTRATE - A chip package module and a package substrate are disclosed herein. The package substrate provides a double-sided wiring structure, wherein a circuit layer is electrically connected with at least one chip, and wherein a heat-conduction wiring layer is extended to the underneath layer so as to increase the heat-conduction area and enhance the heat-dissipation efficiency. The present invention can apply to light emitting diode chips or solar chips to overcome the heat-dissipation problem. | 2016-02-25 |
20160056129 | SEMICONDUCTOR STRUCTURE INCLUDING A THROUGH ELECTRODE, AND METHOD FOR FORMING THE SAME - A semiconductor structure including a through electrode includes a lamination body including at least three layers, including respective vertically aligned electrode parts, the electrode part on the surface of an uppermost layer and including an aperture, the electrode part of the intermediate layer having an aperture smaller than the aperture of the uppermost layer; a through-hole extending from the aperture of the electrode part on the uppermost layer to the surface of the electrode part on a lowermost layer, the through-hole having a depressed part on a side wall thereof between the electrode parts therein; an insulating layer disposed on the entire side wall in the through-hole at a part other than on surfaces of the electrode parts; and a conductive material filling the through-hole from the surface of the electrode part on the lowermost layer to the surface of the electrode part on the uppermost layer. | 2016-02-25 |
20160056130 | SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING POWER TSVS - A semiconductor device including power TSVs for stably supplying a power source is described. A semiconductor device includes a chip power pad placed in a first region of a chip, power through silicon vias (TSVs) connected to the chip power pad and placed in the second region of each of the chips, and metal lines configured to couple the chip power pad and the power TSVs. | 2016-02-25 |
20160056131 | SEMICONDUCTOR DEVICE - A primary surface of a normally-off field-effect transistor ( | 2016-02-25 |
20160056132 | Low-Inductance Circuit Arrangement Comprising Load Current Collecting Conductor Track - A circuit arrangement includes at least two semiconductor chip having first and second load terminals that are each connected to one another, a first load current collecting conductor track, and also an external terminal electrically conductively connected thereto. For each of the semiconductor chips there is at least one electrical connection conductor electrically conductively connected to the first load terminal of the relevant semiconductor chip and also to the first load current collecting conductor track. The total inductance of all the connection conductors with which the first load terminal of the second of the semiconductor chips is connected to the first load current collecting conductor track has at least twice the inductance of that section of the first load current collecting conductor track which is formed between the second connection location of the first of the semiconductor chips and the second connection location of the second of the semiconductor chips. | 2016-02-25 |
20160056133 | HIGH EFFICIENCY MODULE | 2016-02-25 |
20160056134 | LIGHT-EMITTING DEVICE - A light-emitting device of an embodiment of the present application comprises light-emitting units; a transparent structure having cavities configured to accommodate at least one of the light-emitting units; and a conductive element connecting at least two of the light-emitting units. | 2016-02-25 |
20160056135 | POWER DEVICE CASSETTE WITH AUXILIARY EMITTER CONTACT - A press pack module includes a collector module terminal, an emitter module terminal, a gate module terminal, and an auxiliary module terminal. Each IGBT cassette within the module includes a set of shims, two contact pins, and an IGBT die. The first contact pin provides part of a first electrical connection between the gate module terminal and the IGBT gate pad. The second contact pin provides part of a second electrical connection between the auxiliary module terminal and a shim that in turn contacts the IGBT emitter pad. The electrical connection between the auxiliary emitter terminal and each emitter pad of the many IGBTs is a balanced impedance network. The balanced network is not part of the high current path through the module. By supplying a gate drive signal between the gate and auxiliary emitter terminals, simultaneous IGBT turn off in high speed and high current switching conditions is facilitated. | 2016-02-25 |
20160056136 | ELECTRICAL INTERCONNECT STRUCTURE FOR AN EMBEDDED SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THEREOF - An electronics package includes a first dielectric substrate having a first plurality of vias formed through a thickness thereof, a metalized contact layer coupled to a top surface of the first dielectric substrate, and a first die positioned within a first die opening formed through the thickness of the first dielectric substrate. Metalized interconnects are formed on a bottom surface of the first dielectric substrate and extend through the first plurality of vias to contact the metalized contact layer. A second dielectric substrate is coupled to the first dielectric substrate and has a second plurality of vias formed through a thickness thereof. Metalized interconnects extend through the second plurality of vias to contact the first plurality of metalized interconnects and contact pads of the first die. A first conductive element electrically couples the first die to the metalized contact layer. | 2016-02-25 |
20160056137 | SEMICONDUCTOR CHIP AND ELECTRONIC COMPONENT - According to one embodiment, a semiconductor chip includes: a semiconductor layer; an upper electrode provided on the semiconductor layer; and a lower electrode provided under the semiconductor layer, the lower electrode being under an active region of the semiconductor layer, the lower electrode not being under a termination region of the semiconductor layer, an element being disposed in the active region, and the termination region being beside the active region. | 2016-02-25 |
20160056138 | VERTICAL SENSE DEVICES IN VERTICAL TRENCH MOSFET - Vertical sense devices in vertical trench MOSFET. In accordance with an embodiment of the present invention, an electronic circuit includes a vertical trench metal oxide semiconductor field effect transistor configured for switching currents of at least one amp and a current sensing field effect transistor configured to provide an indication of drain to source current of the MOSFET. A current sense ratio of the current sensing FET is at least 15 thousand and may be greater than 29 thousand. | 2016-02-25 |
20160056139 | Circuit Protection Device - A circuit protection device is provided and includes a first insulation layer, a second insulation layer, a thermal fuse, a diode, a first exterior electrode pad, a second exterior electrode pad, and a third exterior electrode pad. The second insulation layer is positioned above a top surface of the first insulation layer. The thermal fuse is packaged in the first insulation layer and having a first electrode end and a second electrode end positioned opposite to the first electrode end. The diode is packaged in the second insulation layer and having a first electrode surface and a second electrode surface positioned opposite to the first electrode surface. The first exterior electrode pad is positioned on a bottom surface of the first insulation layer and electrically connected to the first electrode surface and the first electrode end. The second exterior electrode pad is positioned on the bottom surface and electrically connected to the second electrode end, while the third exterior electrode pad is positioned on the bottom surface and electrically connected to the second electrode surface. | 2016-02-25 |
20160056140 | Semiconductor Device - To solve a problem in that an antenna or a circuit including a thin film transistor is damaged due to discharge of electric charge accumulated in an insulator (a problem of electrostatic discharge), a semiconductor device includes a first insulator, a circuit including a thin film transistor provided over the first insulator, an antenna which is provided over the circuit and is electrically connected to the circuit, and a second insulator provided over the antenna, a first conductive film provided between the first insulator and the circuit, and a second conductive film provided between the second insulator and the antenna. | 2016-02-25 |
20160056141 | Solid-State Power Controller Channel Protection Systems and Methods - A scalable solid-state power controller system is provided with channel protection features. A plurality of output channels may be combined to provide a combined channel output. The current provided at the combined channel output is sourced from the plurality of output channels and each channel is protected from faults such as overcurrent events. | 2016-02-25 |
20160056142 | SEMICONDUCTOR DEVICE - According to one embodiment, semiconductor device includes a first semiconductor region; a second semiconductor region; a first insulating layer; a second insulating layer; a third semiconductor region; and an interconnect layer. The second semiconductor region is provided on the first semiconductor region, and second semiconductor region is connected to the first semiconductor region. The first insulating layer surrounds a first portion of the second semiconductor region. The second insulating layer surrounds a second portion of the second semiconductor region. The third semiconductor region is provided on the second portion of the second semiconductor region, the third semiconductor region is connected to the second portion, and the third semiconductor region is surrounded by the second insulating layer. And the interconnect layer is provided on the second semiconductor region and the third semiconductor region, and the interconnect layer is electrically connected to the second semiconductor region and the third semiconductor region. | 2016-02-25 |
20160056143 | LIGHT EMITTING DEVICE PACKAGE - A light emitting device package include: a lead frame having one surface with a recess portion provided therein and including a first mounting region positioned on the one surface and a second mounting region positioned in the recess portion; a light emitting device mounted on the first mounting region and electrically connected to the lead frame; and a Zener diode mounted on the second mounting region and connected to the lead frame by a wire. The wire is positioned within the recess portion and is disposed to have a height lower than the first mounting region. | 2016-02-25 |
20160056144 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device includes: depositing a thin film semiconductor layer on a semiconductor substrate with an insulating film therebetween, the insulating film having been formed on a surface of the semiconductor substrate; ion-implanting first impurity ions into the thin film semiconductor layer under a condition where a range of the first impurity ions becomes smaller than a film thickness of the thin film semiconductor layer when being deposited; and selectively ion-implanting second impurity ions into the thin film semiconductor layer with a dose quantity more than a dose quantity of the first impurity ions, in which a diode for detecting temperature is formed by a region into which the first impurity ions have been implanted and a region into which the second impurity ions have been implanted in the thin film semiconductor layer. | 2016-02-25 |
20160056145 | SEMICONDUCTOR DEVICE - Performance of a semiconductor device is improved. The semiconductor device includes a substrate composed of silicon, a semiconductor layer composed of p-type nitride semiconductor provided on the substrate, and a transistor including a channel layer provided on the semiconductor layer. The semiconductor device further includes an n-type source region provided in the channel layer, and an n-type drain region provided in the channel layer separately from the source region in a plan view. | 2016-02-25 |
20160056146 | Electrostatic Discharge (ESD) Silicon Controlled Rectifier (SCR) with Lateral Gated Section - In an embodiment, an ESD protection circuit may include an STI-bound SCR and a gated SCR that may be electrically in parallel with the STI-bound SCR. The gated SCR may be perpendicular to the STI-bound SCR in a plane of the semiconductor substrate. In an embodiment, the gated SCR may trigger more quickly and turn on more quickly than the STI-bound SCR. The STI-bound SCR may form the main current path for an ESD event. A low capacitive load with rapid response to ESD events may thus be formed. In an embodiment, the anode of the two SCRs may be shared. | 2016-02-25 |
20160056147 | Single Junction Bi-Directional Electrostatic Discharge (ESD) Protection Circuit - In an embodiment, an ESD protection circuit may include a silicon-controlled rectifier (SCR) and a diode sharing a PN junction and forming a bi-directional ESD circuit. The single PN junction may reduce the capacitive load on the pin, which may allow the high speed circuit to meet its performance goals. In an embodiment, a floating P-well contact may be placed between two neighboring SCRs, to control triggering of the SCRs. | 2016-02-25 |
20160056148 | SEMICONDUCTOR DEVICE - A semiconductor device is provided with a first well region of a first conduction type having a first voltage (voltage VB) applied thereto, a second well region of a second conduction type formed in the surface layer section of the first well region and having a second voltage (voltage VS) different from the first voltage applied thereto, and a charge extracting region of the first conduction type formed in the surface layer section of the second well region and having the first voltage applied thereto. This inhibits the operation of a parasitic bipolar transistor. | 2016-02-25 |
20160056149 | SEMICONDUCTOR DEVICE - A P-type epitaxial growth layer is formed on a P-type semiconductor substrate with an N-type buried region and a P-type buried region interposed therebetween. A cathode region, an anode region, and an N-type sinker region are formed in P-type epitaxial growth layer. A resistance element is formed on a surface of an isolation region that electrically isolates anode region and N-type sinker region. Resistance element has: one end portion electrically connected to each of anode region and N-type sinker region; and the other end portion electrically connected to a ground potential. | 2016-02-25 |