08th week of 2016 patent applcation highlights part 55 |
Patent application number | Title | Published |
20160056250 | Recessed Salicide Structure to Integrate a Flash Memory Device with a High K, Metal Gate Logic Device - Some embodiments of the present disclosure provide an integrated circuit (IC) for an embedded flash memory device. The IC includes a flash memory cell having a memory cell gate. A silicide contact pad is arranged in a recess of the memory cell gate. A top surface of the silicide contact pad is recessed relative to a top surface of the memory cell gate. Dielectric side-wall spacers extend along sidewalls of the recess from the top surface of the memory cell gate to the top surface of the silicide contact pad. | 2016-02-25 |
20160056251 | SEMICONDUCTOR SWITCHING DEVICE INCLUDING CHARGE STORAGE STRUCTURE - A semiconductor switching device includes a first load terminal electrically connected to source zones of transistor cells. The source zones form first pn junctions with body zones. A second load terminal is electrically connected to a drain construction that forms second pn junctions with the body zones. Control structures, which include a control electrode and charge storage structures, directly adjoin the body zones. The control electrode controls a load current through the body zones. The charge storage structures insulate the control electrode from the body zones and contain a control charge adapted to induce inversion channels in the body zones in the absence of a potential difference between the control electrode and the first load electrode. | 2016-02-25 |
20160056252 | PIEZORESISTIVE RESONATOR WITH MULTI-GATE TRANSISTOR - An embodiment includes a first nonplanar transistor including a first fin that includes first source and drain nodes, and a first channel between the first source and drain nodes; a second nonplanar transistor including a second fin that includes second source and drain nodes, and a second channel between the second source and drain nodes; a nonplanar gate on the first fin between the first source and drain nodes and on the second fin between the second source and drain nodes; and first insulation included between the gate and the first fin and second insulation between the gate and the second fin; wherein the gate mechanically resonates at a first frequency when at least one of the gate and the first fin is actuated with alternating current (AC) to produce periodic forces on the gate. Other embodiments are described herein. | 2016-02-25 |
20160056253 | INTEGRATED CIRCUITS WITH DIFFUSION BARRIER LAYERS AND PROCESSES FOR PREPARING INTEGRATED CIRCUITS INCLUDING DIFFUSION BARRIER LAYERS - Integrated circuits with a diffusion barrier layers, and processes for preparing integrated circuits including diffusion barrier layers are provided herein. An exemplary integrated circuit includes a semiconductor substrate comprising a semiconductor material, a compound gate dielectric overlying the semiconductor substrate, and a gate electrode overlying the compound gate dielectric. In this embodiment, the compound gate dielectric includes a first dielectric layer, a diffusion barrier layer overlying the first dielectric layer; and a second dielectric layer overlying the diffusion barrier layer; wherein the diffusion barrier layer is made of a material that is less susceptible to diffusion of the semiconductor material than the first dielectric layer, less susceptible to diffusion of oxygen than the second dielectric layer, or both. | 2016-02-25 |
20160056254 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH OFFSET SIDEWALL STRUCTURE - A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate ( | 2016-02-25 |
20160056255 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF - A semiconductor device is provided including a substrate and a plurality of gate stacks. The gate stack includes a dielectric layer disposed on the substrate, a first capping layer disposed on the dielectric layer, a second capping layer disposed on the first capping layer, and a gate electrode layer covering the second capping layer. The first capping layer having a roughened surface may enhance the formation of the second capping layer. The second capping layer has a bottom portion and a sidewall portion, and the thickness of the bottom portion is formed to be greater than the thickness of the sidewall portion, so that the dielectric property of the second capping layer may be significantly improved. Further, a method for manufacturing the semiconductor device also provides herein. | 2016-02-25 |
20160056256 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device is disclosed. The device includes a foundation layer including first and second layers being different from each other in material, and the foundation layer including a surface on which a boundary of the first and second layers is presented, a catalyst layer on the surface of the foundation layer, and the catalyst layer including a protruding area. The device further includes a graphene layer being in contact with the protruding area. | 2016-02-25 |
20160056257 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device includes: a silicon carbide semiconductor layer; and an electrode layer in contact with the silicon carbide semiconductor layer. In a case where the electrode layer is equally divided into two in a thickness direction in one cross section of the electrode layer in the thickness direction to obtain a first region facing the silicon carbide semiconductor layer and a second region opposite to the silicon carbide semiconductor layer, an area of a carbon portion containing the carbon in the first region is wider than an area of the carbon portion in the second region. At an interface region located up to 300 nm from an interface between the silicon carbide semiconductor layer and the electrode layer, the carbon portion includes a plurality of portions disposed with a space interposed therebetween, and a ratio of area occupied by the carbon portion is not more than 40%. | 2016-02-25 |
20160056258 | SEMICONDUCTOR DEVICES HAVING POLYSILICON GATE PATTERNS AND METHODS OF FABRICATING THE SAME - A semiconductor device including a gate insulation pattern on a substrate, and a semiconductor gate pattern including an amorphous silicon pattern and a polycrystalline silicon pattern stacked on a side of the gate insulation pattern opposite to the substrate. The amorphous silicon pattern includes anti-diffusion impurities that suppress diffusion of impurity ions in the semiconductor gate pattern. | 2016-02-25 |
20160056259 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method of fabricating the same include a semiconductor substrate, a high-k dielectric pattern and a metal-containing pattern sequentially being stacked on the semiconductor substrate, a gate pattern including poly semiconductor and disposed on the metal-containing pattern, and a protective layer disposed on the gate pattern, wherein the protective layer includes oxide, nitride and/or oxynitride of the poly semiconductor. | 2016-02-25 |
20160056260 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a thermal oxide film on one surface of an SiC substrate by thermal oxidation at a temperature of 1150° C. or above in a gas atmosphere including nitrogen and oxygen, and introducing highly-concentrated nitrogen to one surface of the SiC substrate while forming the thermal oxide film; forming a highly-concentrated n-type SiC layer on one surface of the SiC substrate such that the thermal oxide film is removed from one surface of the SiC substrate by etching and, thereafter, one surface of the SiC substrate is exposed to radicals so that Si—N bonded bodies and C—N bonded bodies on one surface of the SiC substrate are removed while leaving nitrogen introduced into a lattice of SiC out of highly-concentrated nitrogen introduced into one surface of the SiC substrate; and forming an ohmic electrode layer on one surface of the SiC substrate. | 2016-02-25 |
20160056261 | EMBEDDED SIGMA-SHAPED SEMICONDUCTOR ALLOYS FORMED IN TRANSISTORS - A method of forming a semiconductor device is disclosed wherein sigma-shaped cavities are formed in alignment with a gate structure such that a cavity tip of the sigma-shaped cavities has a small lateral distance to the channel region, while a lateral distance from the silicon-germanium material filled into the cavity and extending along the sidewall of the gate structure above the active region is at least maintained, if not increased. A semiconductor device is formed wherein the semiconductor device comprises a gate structure disposed over an active region of a semiconductor substrate. The gate structure has a gate electrode and a sidewall spacer structure with a first spacer of L-shape and a second spacer disposed on the first spacer. In alignment with the gate structure, sigma-shaped cavities are formed in the active region and embedded SiGe material is epitaxially grown in the sigma-shaped cavities. | 2016-02-25 |
20160056262 | METAL GATE AND MANUFUACTURING PROCESS THEREOF - Some embodiments of the present disclosure provide a semiconductor device including a semiconductive substrate, a metal gate including a metallic layer proximal to the semiconductive substrate. A dielectric layer surrounds the metal gate. The dielectric layer includes a first surface facing the semiconductive substrate and a second surface opposite to the first surface. A sidewall spacer surrounds the metallic layer with a greater longitudinal height. The sidewall spacer is disposed between the metallic layer and the dielectric layer. An etch stop layer over the metal gate comprises a surface substantially coplanar with the second surface of the dielectric layer. The etch stop layer has a higher resistance to etchant than the dielectric layer. A portion of the etch stop layer is over the sidewall spacer. | 2016-02-25 |
20160056263 | METHODS OF FORMING A GATE CAP LAYER ABOVE A REPLACEMENT GATE STRUCTURE - A method includes performing a first chemical mechanical polishing process to define a polished replacement gate structure having a dished upper surface, wherein the polished dished upper surface of the polished replacement gate structure has a substantially curved concave configuration. A gate cap layer is formed above the polished replacement gate structure, wherein a bottom surface of the gate cap layer corresponds to the polished dished upper surface of the polished replacement gate structure. | 2016-02-25 |
20160056264 | Semiconductor Device and Manufacturing Method of the Same - Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode. | 2016-02-25 |
20160056265 | METHODS OF MAKING A SELF-ALIGNED CHANNEL DRIFT DEVICE - An isolation region is formed in a semiconductor substrate to laterally define and electrically isolate a device region and first and second laterally adjacent well regions are formed in the device region. A gate structure is formed above the device region such that the first well region extends below an entirety of the gate structure and a well region interface formed between the first and second well regions is laterally offset from a drain-side edge of the gate structure. Source and drain regions are formed in the device region such that the source region extends laterally from a source-side edge of the gate structure and across a first portion of the first well region to a first inner edge of the isolation region and the drain region extends laterally from the drain-side edge and across a second portion of the first well region. | 2016-02-25 |
20160056266 | TRENCH GATE TYPE SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - A method of producing a trench gate type MOSFET is provided in which each intersection trench is formed as a two-stage trench structure. A gate trench is backfilled with a mask material and the mask material is then patterned to form a mask used for forming each intersection trench. The intersection trench intersecting the gate trench is provided so as to be deeper than the gate trench. A Schottky electrode is provided in the bottom of each intersection trench | 2016-02-25 |
20160056267 | MANUFACTURE METHOD OF TFT SUBSTRATE AND STURCTURE THEREOF - The present invention provides a manufacture method of an oxide semiconductor TFT substrate, and the method comprises steps of: | 2016-02-25 |
20160056268 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE IMPROVING THE PROCESS SPEED - A method for fabricating a semiconductor device improving the process speed is provided. The method includes forming a fin on a substrate, forming a gate electrode on the fin, first ion-implanting a first impurity to amorphize a region including portions of the fin positioned at opposite sides of the gate electrode, forming a stress inducing layer on the substrate and the fin, and annealing the substrate to recrystallize the amorphized region, wherein after the forming of the fin and before the annealing, the method further includes second ion-implanting a second impurity different from the first impurity into the fin. | 2016-02-25 |
20160056269 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a channel layer on a substrate, forming a sacrificial layer on the channel layer, forming a hardmask pattern on the sacrificial layer, and performing a patterning process using the hardmask pattern as an etch mask to form a channel portion with an exposed top surface. The channel and sacrificial layers may be formed of silicon germanium, and the sacrificial layer may have a germanium content higher than that of the channel layer. | 2016-02-25 |
20160056270 | STRUCTURE AND METHOD FOR DEFECT PASSIVATION TO REDUCE JUNCTION LEAKAGE FOR FINFET DEVICE - The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate of a first semiconductor material; shallow trench isolation (STI) features formed in the semiconductor substrate; and a fin-like active region of a second semiconductor material epitaxy grown on the semiconductor substrate. The first semiconductor material has a first lattice constant and the second semiconductor material has a second lattice constant different from the first lattice constant. The fin-like active region further includes fluorine species. | 2016-02-25 |
20160056271 | METHOD OF FORMING FIN FIELD EFFECT TRANSISTOR - A method of making a Fin field effect transistor (FinFET) includes forming a fin having a first height above a first surface of a substrate, wherein a portion of the fin has first tapered sidewalls, and the fin has a top surface. The method includes forming an insulation region over a portion of the first surface of the substrate, wherein a top of portion of the insulation region defines a second surface. The method further includes covering the first tapered sidewalls and the top surface with a gate dielectric. The method further includes forming a conductive gate strip traversing over the gate dielectric, wherein the conductive gate strip has second tapered sidewalls along a longitudinal direction perpendicular to the first height, and a space between the second tapered sidewalls in the longitudinal direction is greater at a location nearest to the substrate than at a location farthest from the substrate. | 2016-02-25 |
20160056272 | Semiconductor Device - To provide a semiconductor device having a structure capable of suppressing deterioration of its electrical characteristics which becomes apparent with miniaturization. The semiconductor device includes a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a source electrode and a drain electrode in contact with the second oxide semiconductor film; a third oxide semiconductor film over the second oxide semiconductor film, the source electrode, and the drain electrode; a gate insulating film over the third oxide semiconductor film; and a gate electrode over the gate insulating film. A first interface between the gate electrode and the gate insulating film has a region closer to the insulating surface than a second interface between the first oxide semiconductor film and the second oxide semiconductor film. | 2016-02-25 |
20160056273 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Certain embodiments provide a semiconductor device including a semiconductor substrate, a semiconductor element, and wiring. The semiconductor element has an electrode provided on a surface of the semiconductor substrate. The electrode includes a junction layer joined to the surface of the semiconductor substrate, a diffusion-suppressing layer provided on the junction layer, and a pad layer provided on the diffusion-suppressing layer. The wiring is provided on a back surface of the semiconductor substrate and on an inner surface of a through hole which penetrates the semiconductor substrate immediately below the electrode. The wiring is electrically connected to the electrode. | 2016-02-25 |
20160056274 | SEMICONDUCTOR DEVICE - The semiconductor device includes: a channel layer, a barrier layer, a first insulating film, and a second insulating film, each of which is formed above a substrate; a trench that penetrates the second insulating film, the first insulating film, and the barrier layer to reach the middle of the channel layer; and a gate electrode arranged in the trench and over the second insulating film via a gate insulating film. The bandgap of the second insulating film is smaller than that of the first insulating film, and the bandgap of the second insulating film is smaller than that of the gate insulating film GI. Accordingly, a charge (electron) can be accumulated in the second (upper) insulating film, thereby allowing the electric field strength at a corner of the trench to be improved. As a result, a channel is fully formed even at a corner of the trench, thereby allowing an ON-resistance to be reduced and an ON-current to be increased. | 2016-02-25 |
20160056275 | FIELD EFFECT TRANSISTOR AND SEMICONDUCTOR DEVICE - A field effect transistor includes multi-finger electrodes, a gate terminal electrode, a drain terminal electrode, a source terminal and a source terminal electrode. Each of the multi-finger electrodes includes two finger gate electrodes, a finger drain electrode, and at least two finger source electrodes. Finger electrodes are arranged so as to intersect with the first straight line at an angle of approximately +45 degrees and approximately −45 degrees alternately. The gate terminal electrode commonly bundles and connects the finger gate electrodes of two adjacent cell regions. The drain terminal electrode commonly bundles and connects the finger drain electrodes of two adjacent cell regions. And the source terminal electrode commonly bundles and connects the finger source electrodes of two adjacent cell regions. The gate terminal electrodes and the drain terminal electrodes are alternately provided in a connecting region of the multi-finger electrodes of two adjacent cell regions. | 2016-02-25 |
20160056276 | TRANSISTOR STRUCTURE WITH IMPROVED UNCLAMPED INDUCTIVE SWITCHING IMMUNITY - A laterally diffused metal oxide semiconductor (LDMOS) transistor structure with improved unclamped inductive switching immunity. The LDMOS includes a substrate and an adjacent epitaxial layer both of a first conductivity type. A gate structure is above the epitaxial layer. A drain region and a source region, both of a second conductivity type, are within the epitaxial layer. A channel is formed between the source and drain region and arranged below the gate structure. A body structure of the first conductivity type is at least partially formed under the gate structure and extends laterally under the source region, wherein the epitaxial layer is less doped than the body structure. A conductive trench-like feed-through element passes through the epitaxial layer and contacts the substrate and the source region. The LDMOS includes a tub region of the first conductivity type formed under the source region, and adjacent laterally to and in contact with said body structure and said trench-like feed-through element. | 2016-02-25 |
20160056277 | Structure and Method and FinFET Device - The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes The device includes a strain-relaxed buffer (SRB) stack over a substrate, a first fin structure disposed over the SRB stack and a liner layer extending along the portion of the second SRB layer and the first semiconductor material layer of the first fin structure. | 2016-02-25 |
20160056278 | TUNNELING FIELD EFFECT TRANSISTORS (TFETS) WITH UNDOPED DRAIN UNDERLAP WRAP-AROUND REGIONS - Tunneling field effect transistors (TFETs) with undoped drain underlap wrap-around regions are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region formed above a substrate. The homojunction active region includes a doped source region, an undoped channel region, a wrapped-around region, and a doped drain region. A gate electrode and gate dielectric layer are formed on the undoped channel region, between the source and wrapped-around regions. | 2016-02-25 |
20160056279 | SEMICONDUCTOR DEVICE - A semiconductor device includes a fin-shaped silicon layer and a pillar-shaped silicon layer on the fin-shaped silicon layer, where a width of a bottom part of the pillar-shaped silicon layer is equal to a width of a top part of the fin-shaped silicon layer. A gate insulating film and a metal gate electrode are around the pillar-shaped silicon layer and a metal gate line extends in a direction perpendicular to the fin-shaped silicon layer and is connected to the metal gate electrode. A nitride film is on an entire top surface of the metal gate electrode and the metal gate line, except for the bottom of a contact. | 2016-02-25 |
20160056280 | Minority Carrier Conversion Structure - According to an embodiment of a semiconductor device, the semiconductor device includes a power device well in a semiconductor substrate, a logic device well in the substrate and spaced apart from the power device well by a separation region of the substrate, and a minority carrier conversion structure including a first doped region of a first conductivity type in the separation region, a second doped region of a second conductivity type in the separation region and a conducting layer connecting the first and second doped regions. The second doped region includes a first part interposed between the first doped region and the power device well and a second part interposed between the first doped region and the logic device well. | 2016-02-25 |
20160056281 | EDGE TERMINATION FOR SUPER-JUNCTION MOSFETS - Edge termination for super-junction MOSFETs. In accordance with an embodiment of the present invention, a super-junction metal oxide semiconductor field effect transistor (MOSFET) includes a core super-junction region including a plurality of parallel core plates coupled to a source terminal of the super-junction MOSFET. The super-junction MOSFET also includes a termination region surrounding the core super-junction region comprising a plurality of separated floating termination segments configured to force breakdown into the core super-junction region and not in the termination region. Each termination segment has a length dimension less than a length dimension of the core plates. | 2016-02-25 |
20160056282 | SEMICONDUCTOR DEVICE - In a semiconductor device including a bootstrap diode and a high voltage electric field transistor on a p-type semiconductor substrate, a cavity is formed in an n | 2016-02-25 |
20160056283 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, semiconductor device including: a first semiconductor region; a second semiconductor region provided on the first semiconductor region; a third semiconductor region provided on the second semiconductor region, and the third semiconductor region having a higher impurity concentration than an impurity concentration of the first semiconductor region; a gate insulating film being in contact with the third semiconductor region, the second semiconductor region, and the first semiconductor region, and the gate insulating film having a region in which a nitrogen concentration becomes a lower concentration further away from a juncture portion of the third semiconductor region, the second semiconductor region, and the first semiconductor region, or being contact with the third semiconductor region, the second semiconductor region, and the first semiconductor region via a nitrogen-including layer; and a gate electrode provided on the gate insulating film. | 2016-02-25 |
20160056284 | RECTIFIER DIODE - A pseudo-Schottky diode has an n-channel trench MOSFET which includes: a cathode, an anode, and located between the cathode and the anode, the following elements: a highly n | 2016-02-25 |
20160056285 | HIGH-VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE WITH INCREASED CUTOFF FREQUENCY - A HVMOS transistor structure includes a semiconductor substrate; a gate overlying the semiconductor substrate; a gate dielectric layer between the gate and the semiconductor substrate; a sidewall spacer on each sidewall of the gate; a drain structure in the semiconductor substrate on one side of the gate; an ion well of the first conductivity type in the semiconductor substrate; a source structure in the semiconductor substrate being space apart from the drain structure; and a channel region between the drain structure and the source structure, wherein the channel region substantially consisting of two gate-overlapping regions of the first conductivity type having doping concentrations different from each other. | 2016-02-25 |
20160056286 | HIGH GAIN DEVICE - A method of forming a device is disclosed. A substrate having a high gain (HG) device region for a HG transistor is provided. A HG gate is formed on the substrate in the HG device region. The HG gate includes sidewall spacers on its sidewalls. Heavily doped regions are formed adjacent to the HG gate. Inner edges of the heavily doped regions are aligned with about outer edges of the sidewall spacers of the HG gate. The heavily doped regions serve as HG source/drain (S/D) regions of the HG gate. The HG S/D regions do not include lightly doped drain (LDD) regions or halo regions. | 2016-02-25 |
20160056287 | SEMICONDUCTOR MEMORY DEVICE HAVING AN ELECTRICALLY FLOATING BODY TRANSISTOR - An IC may include an array of memory cells formed in a semiconductor, including memory cells arranged in rows and columns, each memory cell may include a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, wherein the floating body region is bounded on a first side by a first insulating region having a first thickness and on a second side by a second insulating region having a second thickness, and a gate region above the floating body region and the second insulating region and is insulated from the floating body region by an insulating layer; and control circuitry configured to provide electrical signals to said buried region. | 2016-02-25 |
20160056288 | CIRCUIT ELEMENT INCLUDING A LAYER OF A STRESS-CREATING MATERIAL PROVIDING A VARIABLE STRESS - An integrated circuit includes a first transistor having a first source region, a first drain region, a first channel region, a first gate electrode, and a first layer of a first stress-creating material, the first stress-creating material providing a stress that is variable in response to a signal acting on the first stress-creating material, wherein the first layer of the first stress-creating material is arranged to provide a first variable stress in the first channel region of the first transistor, the first variable stress being variable in response to a first signal acting on the first stress-creating material. The integrated circuit also includes a second transistor having a second source region, a second drain region, a second channel region, and a second gate electrode. | 2016-02-25 |
20160056289 | SEMICONDUCTOR DEVICE INCLUDING GATE ELECTRODE FOR APPLYING TENSILE STRESS TO SILICON SUBSTRATE, AND METHOD OF MANUFACTURING THE SAME - A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced. | 2016-02-25 |
20160056290 | Metal-Insensitive Epitaxy Formation - The present disclosure provides a method forming a field effect transistor (FET) in accordance with some embodiments. The method includes performing an etching process to a semiconductor substrate, thereby forming recesses in source and drain (S/D) regions of the semiconductor substrate; forming a passivation material layer of a first semiconductor in the recesses; and epitaxially growing a second semiconductor material, thereby forming S/D features in the recesses, wherein the S/D features are separated from the semiconductor substrate by the passivation material layer. | 2016-02-25 |
20160056291 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR - A semiconductor device includes: a first substrate on which a first field effect transistor is provided; and a second substrate on which a second field effect transistor of a second conductive type is provided; the first and second substrates being bonded to each other at the substrate faces thereof on which the first and second field transistors are provided, respectively; the first field effect transistor and the second field effect transistor being electrically connected to each other. | 2016-02-25 |
20160056292 | METAL GATE STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a substrate including a first active region, a second active region and an isolation disposed between the first active region and the second active region; a plurality of gates disposed over the substrate and including a first gate extended over the first active region, the isolation and the second active region, and a second gate over the first active region and the second active region; and an inter-level dielectric (ILD) disposed over the substrate and surrounding the plurality of gates, wherein the second gate is configured not to conduct current flow and includes a first section disposed over the first active region and a second section disposed over the second active region, a portion of the ILD is disposed between the first section and the second section. | 2016-02-25 |
20160056293 | NON-PLANAR SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED FIN WITH TOP BLOCKING LAYER - Non-planar semiconductor devices having self-aligned fins with top blocking layers and methods of fabricating non-planar semiconductor devices having self-aligned fins with top blocking layers are described. For example, a semiconductor structure includes a semiconductor fin disposed above a semiconductor substrate and having a top surface. An isolation layer is disposed on either side of the semiconductor fin, and recessed below the top surface of the semiconductor fin to provide a protruding portion of the semiconductor fin. The protruding portion has sidewalls and the top surface. A gate blocking layer has a first portion disposed on at least a portion of the top surface of the semiconductor fin, and has a second portion disposed on at least a portion of the sidewalls of the semiconductor fin. The first portion of the gate blocking layer is continuous with, but thicker than, the second portion of the gate blocking layer. A gate stack is disposed on the first and second portions of the gate blocking layer. | 2016-02-25 |
20160056294 | EPITAXIAL GROWTH OF SILICON FOR FINFETS WITH NON-RECTANGULAR CROSS-SECTIONS - FinFET devices with epitaxially grown fins and methods for fabricating them are provided. Embodiments include forming at least two shallow trench isolation (STI) regions, filled with dielectric material, adjacent to but separate from each other in a silicon substrate; epitaxially growing a silicon-based layer between each adjacent pair of STI regions to form a fin with a non-rectangular cross-section extending from each STI region to each adjacent STI region; forming a gate oxide over and perpendicular to each fin; and forming a gate electrode over the gate oxide to form a FinFET. | 2016-02-25 |
20160056295 | FinFET Transistor with U-Shaped Channel - A semiconductor device having a u-shaped FinFET and methods of forming the same are disclosed. The semiconductor device includes a substrate and a fin over the substrate, wherein the fin has a u-shape from a top view with first and second arm portions and a bridge portion connecting the first and second arm portions. The semiconductor device further includes a first gate over the substrate, engaging the fin at both the first and second arm portions and the bridge portion. A source region of the FinFET is formed in the first arm portion, a drain region of the FinFET is formed in the second arm portion, and a channel region of the FinFET is formed in the fin between the source region and the drain region. | 2016-02-25 |
20160056296 | FIN FET AND METHOD OF FABRICATING SAME - A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode. | 2016-02-25 |
20160056297 | METAL OXIDE TFT WITH IMPROVED SOURCE/DRAIN CONTACTS AND RELIABILITY - A method including providing a substrate with a gate, a layer of gate insulator material adjacent the gate, and a layer of metal oxide semiconductor material positioned on the gate insulator opposite the gate, forming a selectively patterned etch stop passivation layer and heating at elevated temperature in an oxygen-containing or nitrogen-containing or inert ambience to selectively increase the carrier concentration in regions of the metal oxide semiconductor not covered by the etch stop layer, on which overlying and spaced apart source/drain metals are formed. Subsequently heating the transistor in an oxygen-containing or nitrogen-containing or inert ambience to further improve the source/drain contacts and adjust the threshold voltage to a desired level. Providing additional passivation layer(s) on top of the transistor with electric insulation and barrier property to moisture and chemicals in the surrounding environment. | 2016-02-25 |
20160056298 | SEMICONDUCTOR DEVICE - A semiconductor device with significantly low off-state current is provided. An oxide semiconductor material in which holes have a larger effective mass than electrons is used. A transistor is provided which includes a gate electrode layer, a gate insulating layer, an oxide semiconductor layer including a hole whose effective mass is 5 or more times, preferably 10 or more times, further preferably 20 or more times that of an electron in the oxide semiconductor layer, a source electrode layer in contact with the oxide semiconductor layer, and a drain electrode layer in contact with the oxide semiconductor layer. | 2016-02-25 |
20160056299 | SEMICONDUCTOR DEVICE - A decrease in on-state current in a semiconductor device including an oxide semiconductor film is suppressed. A transistor including an oxide semiconductor film, an insulating film which includes oxygen and silicon, a gate electrode adjacent to the oxide semiconductor film, the oxide semiconductor film provided to be in contact with the insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the interface with the insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. | 2016-02-25 |
20160056300 | THIN FILM TRANSISTOR AND FABRICATING METHOD THEREOF - A thin film transistor and a fabricating method thereof is provided. The thin film transistor includes a gate, a gate insulation layer, a semiconductor layer, a conductive pattern, a first electrode and a second electrode. The gate is disposed on a substrate. The gate insulation layer is disposed on the substrate to cover the gate. | 2016-02-25 |
20160056301 | RECONFIGURABLE ELECTRONIC DEVICES AND OPERATION METHOD THEREOF - Provided is a reconfigurable electronic device which is implemented by forming independent upper gates and lower gates, wherein in comparison with an existing reconfigurable electronic device having the same function, a degree of integration is greatly increased, a non-volatile memory function is included in the device, and in operation of a reconfigurable circuit based on an independent lower electrode array, dynamic parasitic component is decreased and a complexity of wire lines can be reduced, so that power consumption can be reduced. In addition, in comparison with an existing reconfigurable electronic device, the device exhibits remarkably excellent performance in terms of various characteristics such as diversity of functions of a multi-functional device, alignment margin in process, performance of implementation of infinitesimal electrical doping in a channel, compatibility with bottom-up and top-down method in process, and compatibility with a 1D or 2D material. | 2016-02-25 |
20160056302 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE - A three-dimensional (3D) semiconductor device includes first interlayer dielectric layers and word lines that are alternately stacked on a substrate; select lines formed on the first interlayer dielectric layers and the word lines; etch stop patterns formed on the select lines to contact the select lines; channel holes formed to pass through the select lines, the first interlayer dielectric layers, and the word lines; channel layers formed on surfaces of the channel holes; insulating layers formed in the channel holes, the insulating layers having an upper surface that is lower than upper surfaces of the etch stop patterns; impurity-doped layers formed in channel holes on upper surface of the insulating layers; and a second interlayer dielectric layer formed over the etch stop patterns and the impurity-doped layers. | 2016-02-25 |
20160056303 | Bootstrap MOS for High Voltage Applications - A device includes a p-well region, and a first High-Voltage N-type Well (HVNW) region and a second HVNW region contacting opposite edges of the p-well region. A P-type Buried Layer (PBL) has opposite edges in contact with the first HVNW region and the second HVNW region. An n-type buried well region is underlying the PBL. The p-well region and the n-type buried well region are in contact with a top surface and a bottom surface, respectively, of the PBL. The device further includes a n-well region in a top portion of the p-well region, an n-type source region in the n-well region, a gate stack overlapping a portion of the p-well region and a portion of the second HVNW region, and a channel region under the gate stack. The channel region interconnects the n-well region and the second HVNW region. | 2016-02-25 |
20160056304 | NANOWIRE NANOELECTROMECHANICAL FIELD-EFFECT TRANSISTORS - A three-terminal nano-electro-mechanical field-effect transistor (NEMFET) includes a source electrode, a gate electrode, a drain electrode and a nanoelectromechanically suspended channel bridging the source electrode and the drain electrode. The nanoelectromechanically suspended channel includes a moveable nanowire and a dielectric coating on a surface of the nanowire facing the gate electrode. A thickness of a gap between the nanowire and the gate electrode is determined by a thickness of the dielectric coating. | 2016-02-25 |
20160056305 | SEMICONDUCTOR DEVICE - A semiconductor device including a p or p+ doped portion and an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion. The device further includes an insulating portion provided adjacent the drift portion and at least one of the doped portions in a region where the drift portion and the at least one doped portion meet. The device further includes at least one additional portion, wherein the at least one additional portion is located such that, when the doped portions and the at least one additional portion are biased, the electrical potential lines leave the semiconductor drift portion homogeneously. | 2016-02-25 |
20160056306 | SEMICONDUCTOR DEVICE - A p-type anode layer ( | 2016-02-25 |
20160056307 | SOLAR CELLS AND MODULES INCLUDING CONDUCTIVE TAPES AND METHODS OF MAKING AND USING THE SAME - The inventors of the present disclosure recognized that elimination or reduction of the silver paste and/or silver busbars on the front and/or rear surfaces of solar cells and solar modules would advantageously lower the total cost of the solar cell and/or solar module. The inventors of the present disclosure recognized that the silver paste on the front and rear surface of solar cells or solar modules can be eliminated or the amount of silver paste reduced by replacing the silver busbars with a solderable tape including a conductive metal foil and a nonconductive adhesive. | 2016-02-25 |
20160056308 | SOLAR CELLS AND MODULES INCLUDING CONDUCTIVE TAPES AND METHODS OF MAKING AND USING THE SAME - The inventors of the present disclosure recognized that elimination or reduction of the silver paste and/or silver busbars on the front and/or rear surfaces of solar cells and solar modules would advantageously lower the total cost of the solar cell and/or solar module. The inventors of the present disclosure recognized that the silver paste on the front and rear surface of solar cells or solar modules can be eliminated or the amount of silver paste reduced by replacing the silver busbars with a solderable tape including a conductive metal foil and a nonconductive adhesive. | 2016-02-25 |
20160056309 | METHOD AND OPTOELECTRONIC STRUCTURE PROVIDING POLYSILICON PHOTONIC DEVICES WITH DIFFERENT OPTICAL PROPERTIES IN DIFFERENT REGIONS - Method and structural embodiments are described which provide an integrated structure using polysilicon material having different optical properties in different regions of the structure. | 2016-02-25 |
20160056310 | Tetra-Lateral Position Sensing Detector - The present invention is directed to a position sensing detector made of a photodiode having a semi insulating substrate layer; a buffered layer that is formed directly atop the semi-insulating substrate layer, an absorption layer that is formed directly atop the buffered layer substrate layer, a cap layer that is formed directly atop the absorption layer, a plurality of cathode electrodes electrically coupled to the buffered layer or directly to the cap layer, and at least one anode electrode electrically coupled to a p-type region in the cap layer. The position sensing detector has a photo-response non-uniformity of less than 2% and a position detection error of less than 10 μm across the active area. | 2016-02-25 |
20160056311 | SOLAR CELL - A solar cell, including a substrate; and an electrode on at least one surface of the substrate. The electrode may be prepared from an electrode paste including tungsten oxide particles, and the electrode may have an adhesive strength of about 4 N/mm to about 6 N/mm with respect to a ribbon for interconnecting solar cells, as measured under conditions of a peeling angle of 180° and a stretching rate of 50 mm/min. | 2016-02-25 |
20160056312 | BACK CONTACT SUBSTRATE FOR A PHOTOVOLTAIC CELL OR MODULE - A back contact substrate for a photovoltaic cell, including a carrier substrate and an electrode, the electrode including a conductive coating including a metallic thin film based on a metal or metal alloy; a barrier to selenization thin film for protecting the conductive coating and based on at least one among MoxOyNz, WxOyNz, TaxOyNz, NbxOyNz, RexOyNz. | 2016-02-25 |
20160056313 | COMPOUND SEMICONDUCTOR SINGLE CRYSTAL INGOT FOR PHOTOELECTRIC CONVERSION DEVICES, PHOTOELECTRIC CONVERSION DEVICE, AND PRODUCTION METHOD FOR COMPOUND SEMICONDUCTOR SINGLE CRYSTAL INGOT FOR PHOTOELECTRIC CONVERSION DEVICES - The present invention increases the conversion efficiency of a photoelectric conversion element that uses cadmium zinc telluride or cadmium telluride (Cd(Zn)Te) compound semiconductor single crystals containing a group 1A element as an impurity. A heat-resistant pot is filled with raw material and a group 1A element, which is reacted with a portion of the raw material, and the container is heated, thereby melting the raw material into a melt and diffusing the dissociated group 1A element in the melt, producing single crystals from the melt. Compound semiconductor single crystals for photoelectric conversion elements having a hole concentration of 4×10 | 2016-02-25 |
20160056314 | Multilayer Thin-Film Back Contact System For Flexible Photovoltaic Devices On Polymer Substrates - A polymer substrate and back contact structure for a photovoltaic element, and a photovoltaic element include a CIGS photovoltaic structure, a polymer substrate having a device side at which the photovoltaic element can be located and a back side opposite the device side. A layer of dielectric is optionally formed at the back side of the polymer substrate. A metal structure is formed at the device side of the polymer substrate. | 2016-02-25 |
20160056315 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and the like having high quantum efficiency or high sensitivity in a near-infrared to infrared region is provided. The semiconductor device includes: a substrate; a multiple quantum well structure disposed on the substrate, and including a plurality of pairs of a layer a and a layer b; and a crystal-adjusting layer disposed between the substrate and the multiple quantum well structure. The crystal-adjusting layer includes a first adjusting layer which is made of the same material as the substrate and is in contact with the substrate, and a second adjusting layer which is made of the same material as the layer a or the layer b of the multiple quantum well structure and is in contact with the multiple quantum well structure. | 2016-02-25 |
20160056316 | Three Dimensional Photovoltaic Module - A three dimensional photovoltaic module that allows for the absorption of solar energy from various angles in a three hundred sixty degree arrangement has a base panel unit and a solar structure. The solar structure has a plurality of solar cells, each having a first photovoltaic cell and a second photovoltaic cell, wherein each of the plurality of solar cells absorbs light from two opposing sides. A concentrated photovoltaic lens directs light and traps light in an interior volume, allowing for internal absorption of light in addition to the external absorption of light. The base panel unit has a rotational base to which the solar structure is connected, and a magnetic base about which the rotational base is magnetically levitated. A plurality of magnets positioned around the rotational base generates a magnetic vortex that in combination with the magnetic base allows the rotational base and the solar structure to rotate. | 2016-02-25 |
20160056317 | LOW-BANDGAP, MONOLITHIC, MULTI-BANDGAP, OPTOELECTRONIC DEVICES - Low bandgap, monolithic, multi-bandgap, optoelectronic devices ( | 2016-02-25 |
20160056318 | ADVANCED CPV SOLAR CELL ASSEMBLY PROCESS - This disclosure relates to a solar cell assembly structure for supporting a concentrator photovoltaic cell structure (3420), comprising a semiconducting structure and a diode, wherein the semiconducting structure comprises a first semiconducting region at least a part of which for placing the concentrator photovoltaic cell structure, and a second semiconducting region for realizing the diode within or on the second semiconducting region and wherein the part of the first semiconducting region for placing the concentrator photovoltaic cell structure and the second semiconducting region are not vertically overlapping. | 2016-02-25 |
20160056319 | PHOTOVOLTAIC MODULE WITH INTEGRATED CURRENT COLLECTION AND INTERCONNECTION - A photovoltaic module includes a first photovoltaic cell, a second photovoltaic cell, and a collector-connector which is configured to collect current from the first photovoltaic cell and to electrically connect the first photovoltaic cell with the second photovoltaic cell. The collector-connector may include an electrically insulating carrier and at least one electrical conductor which electrically connects the first photovoltaic cell to the second photovoltaic cell. | 2016-02-25 |
20160056320 | METHOD AND DEVICE FOR IMPROVING POWER GENERATION EFFICIENCY OF A SOLAR CELL - The present invention provides a method for improving power generation efficiency of a solar cell, comprising: providing a synergistic structure for allowing the solar cell to receive light through thereof, wherein the synergistic structure is a three-dimensional structure; the three-dimensional structure has a surface area that is larger than a surface area of the solar cell, a refractive index of substances that used to construct the three-dimensional structure is higher than a refractive index of environmental substances around the solar cell, and improving an interface condition of the solar cell could increase light introduced into the solar cell and improving power generation efficiency of the solar cell. | 2016-02-25 |
20160056321 | Large-Scale Space-Based Solar Power Station: Efficient Power Generation Tiles - A space-based solar power station, a power generating satellite module and/or a method for collecting solar radiation and transmitting power generated using electrical current produced therefrom is provided. Each solar power station includes a plurality of satellite modules. The plurality of satellite modules each include a plurality of modular power generation tiles including a photovoltaic solar radiation collector, a power transmitter and associated control electronics. Numerous embodiments relate to efficient power generation tiles. In one embodiment, an efficient power generation tile includes: at least one photovoltaic material; and at least one concentrator that redirects incident solar radiation towards a photovoltaic material such that the photovoltaic material experiences a greater solar flux relative to the case where the photovoltaic material experiences unaltered solar radiation. | 2016-02-25 |
20160056322 | SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME - A solar cell is discussed, and the solar cell includes: a semiconductor substrate; a tunneling layer on a surface of the semiconductor substrate; a buffer layer on the tunneling layer, wherein the buffer layer is a separate layer from the tunneling layer and includes an intrinsic buffer portion, and wherein at least one of a material, a composition and a crystalline structure of the buffer layer is different from those of the tunneling layer; a conductive type region on the tunneling layer, and including a first conductive type region having a first conductive type and a second conductive type region having a second conductive type; and an electrode connected to the conductive type region. The buffer layer is positioned adjacent to the tunneling layer and is apart from the electrode. | 2016-02-25 |
20160056323 | Tandem Junction Photovoltaic Cell - A tandem junction photovoltaic cell has a first p-n junction with a first energy band gap, and a second p-n junction with a second energy band gap less than the first energy band gap. The junctions are separated by a quantum tunneling junction. The first p-n junction captures higher energy photons and allows lower energy photons to pass through and be captured by the second p-n junction. Quantum dots positioned within the first p-n junction promote quantum tunneling of charge carriers to increase the current generated by the first p-n junction and match the current of the second p-n junction for greater efficiency. | 2016-02-25 |
20160056324 | LIGHT ENHANCEMENT OF LIGHT EMITTING DIODES - A multi-layered semiconductor die having an ITO layer being the topmost layer with a predetermined and generally uniform thickness. A ZnO seed layer with a predetermined and generally uniform thickness is sputtered the ITO layer, forming a generally roof shingle pattern with the ITO layer. The seed layer has a periphery having a generally beveled edge, which is operable to enhance light emitted by a light source. A ZnO nanostructure layer is deposited on top of the seed layer including at least two or more nanocone arrays. The nanocone arrays are configured to have bases and tips and the bases are configured to be in close proximity so as to be almost touching but not connected. Gaps are formed between each tip of each nanocone array. The nanostructure being operable to enhance light dispersion of the light source. | 2016-02-25 |
20160056325 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes: an n-type semiconductor layer and a p-type semiconductor layer; an active layer disposed between the n-type semiconductor layer and the p-type semiconductor layer; and an electron blocking layer disposed between the active layer and the p-type semiconductor layer and doped with a p-type dopant element. The electron blocking layer is formed of Al | 2016-02-25 |
20160056326 | Optoelectronic Semiconductor Chip and Method for the Production Thereof - A method for producing an optoelectronic semiconductor chip is disclosed. A substrate is provided and a first layer is grown. An etching process is carrying out to initiate V-defects. A second layer is grown and a quantum film structure is grown. An optoelectronic semiconductor chip is also disclosed. The method can be used to produce the optoelectronic semiconductor chip. | 2016-02-25 |
20160056327 | NITRIDE LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING THE SAME - Provided is a nitride light emitting element which achieves a high light extraction efficiency even at a low operation voltage and which can be manufactured by means of a simple process. A nitride light emitting element | 2016-02-25 |
20160056328 | GREEN-LIGHT EMITTING DEVICE INCLUDING QUATERNARY QUANTUM WELL ON VICINAL C-PLANE - Example embodiments relate to a green-light emitting device including a quaternary quantum well on a vicinal c-plane. The light-emitting device includes a substrate having a vicinal c-plane surface and a light-emitting layer on the vicinal c-plane surface of the substrate. The light-emitting layer includes a quantum well layer of Al | 2016-02-25 |
20160056329 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor light emitting element includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type separated from the first semiconductor layer in a first direction, a light emitting layer provided between the first and second semiconductor layers, and a first intermediate unit provided between the first semiconductor layer and the light emitting layer. The light emitting layer includes a well layer including a nitride semiconductor including In. The first intermediate unit includes stacked bodies. The stacked bodies are arranged in the first direction. Each of the stacked bodies includes a first layer of In | 2016-02-25 |
20160056330 | LIGHT-EMITTING DEVICE COMPRISING ACTIVE NANOWIRES AND CONTACT NANOWIRES AND METHOD OF FABRICATION - A light-emitting device comprises a set of nanowires over the whole surface of a substrate, comprising at least a first series of first nanowires and a second series of second nanowires; the first series comprising first nanowires emitting light under electrical control, connected between a first and a second type of electrical contact to emit light under electrical control, the first nanowires covered by at least one conducting layer transparent at the wavelength of the light-emitting device, layer in contact with the first type of electrical contact; the second series comprising second nanowires, encapsulated in a layer of metal allowing the first electrical contact to be formed; the second electrical contact being on the back face of the substrate, opposite to the face comprising the nanowires, and provided by a conducting layer facing the first series of nanowires. A method of fabrication of the light-emitting device is provided. | 2016-02-25 |
20160056331 | NANOSTRUCTURE SEMICONDUCTOR LIGHT EMITTING DEVICE - A nanostructure semiconductor light emitting device includes: a base layer formed of a first-conductivity type nitride semiconductor material; and a plurality of light emitting nanostructures disposed on the base layer to be spaced apart from each other, wherein each of the plurality of light emitting nanostructures includes: a nanocore formed of a first conductivity-type nitride semiconductor material, an active layer disposed on a surface of the nanocore and including a quantum well which is divided into first and second regions having different indium (In) composition ratios in a thickness direction thereof; and a second conductivity-type semiconductor layer disposed on the active layer, and an In composition ratio in the first region is higher than an In composition ratio in the second region. | 2016-02-25 |
20160056332 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A high luminance semiconductor light emitting device including a metallic reflecting layer formed using a non-transparent semiconductor substrate is provided. The device includes a GaAs substrate; a metal layer disposed on the GaAs substrate; and a light emitting diode structure. The light emitting diode structure includes a patterned metal contact layer and a patterned insulating layer disposed on the metal layer, a p type cladding layer disposed on the patterned metal contact layer and the patterned insulating layer, a multi-quantum well layer disposed on the p type cladding layer, an n type cladding layer disposed on the multi-quantum well layer, and a window layer disposed on the n type cladding layer. The GaAs substrate and the light emitting diode structure are bonded by using the metal layer. | 2016-02-25 |
20160056333 | NITRIDE SEMICONDUCTOR MULTILAYER FILM REFLECTOR AND LIGHT-EMITTING DEVICE USING THE SAME - Achieving resistance reduction of a nitride semiconductor multilayer film reflector. In the nitride semiconductor multilayer film reflector, a first semiconductor layer ( | 2016-02-25 |
20160056334 | LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - A light emitting device is provided to include an n-type semiconductor layer, a p-type semiconductor layer, an active layer, and an electron blocking layer disposed between the p-type semiconductor layer and the active layer. The p-type semiconductor layer includes a hole injection layer, a p-type contact layer, and a hole transport layer. The hole transport layer includes a plurality of undoped layers and at least one intermediate doped layer disposed between the undoped layers. At least one of the undoped layers includes a zone in which hole concentration decreases with increasing distance from the hole injection layer or the p-type contact layer, and the intermediate doped layer is disposed to be at least partially overlapped with a region of the hole transport layer, the region having the hole concentration of 62% to 87% of the hole concentration of the p-type contact layer. | 2016-02-25 |
20160056335 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to an embodiment, a semiconductor light emitting device includes a first semiconductor layer, a second semiconductor layer, a dielectric film and an electrode. The first semiconductor layer is capable of emitting light. The second semiconductor layer has a first major surface in contact with the first semiconductor layer and a second major surface opposite to the first major surface, the second major surface including a first region having convex structures and a second region not having the convex structures. The dielectric film is provided at least at a tip portion of the convex structures, and the electrode is provided above the second region. | 2016-02-25 |
20160056336 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device includes a substrate, a first reflective layer disposed on the substrate and including first openings, a first conductivity-type semiconductor layer grown in and extending from the first openings and connected on the first reflective layer, a second reflective layer disposed on the first conductivity-type semiconductor layer and including second openings having lower surfaces disposed to be spaced apart from upper surfaces of the first openings, and a plurality of light-emitting nanostructures including nanocores extending from the second openings and formed of a first conductivity-type semiconductor material, and active layers and second conductivity-type semiconductor layers sequentially disposed on the nanocores. | 2016-02-25 |
20160056337 | NEAR-INFRARED LIGHT-EMITTING DIODE AND METHOD FOR MANUFACTURING THE SAME - The present invention relates generally to a near-infrared light-emitting diode (LED) and the method for manufacturing the same. When preparing the light-emitting layer of the near-infrared LED according to the present invention, the CsSnXX′ | 2016-02-25 |
20160056338 | LIGHT EMITTING DEVICE AND LIGHTING SYSTEM - A light emitting device includes a first electrode, a first semiconductor layer disposed on the first electrode and including a first conductive dopant, a second semiconductor layer disposed on the first semiconductor layer and including the first conductive dopant having a doping concentration lower than a doping concentration of the first semiconductor layer, a third semiconductor layer disposed on the second semiconductor layer to adjust stress, a first conductive semiconductor layer on the third semiconductor layer, an active layer on the first conductive semiconductor layer, a second conductive semiconductor layer on the active layer; and a second electrode on the second conductive semiconductor layer, the third semiconductor layer has a doping concentration in a range between the doping concentration of the second semiconductor layer and a doping concentration of the first conductive semiconductor layer, and the doping concentration of the third semiconductor layer is increased toward the first conductive semiconductor layer. | 2016-02-25 |
20160056339 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF PRODUCING THE SAME - The invention is a semiconductor light emitting device successively including a conductive support substrate, a metal layer, and a light emitting part successively including an n-type current spreading layer, an n-type cladding layer, an active layer, a p-type cladding layer, and a p-type current spreading layer, which are made of an AlGaInP-based semiconductor layer. This device also includes a first thin ohmic electrode partially covering the p-type current spreading layer and a second thin ohmic electrode partially provided between the metal and n-type current spreading layers. The first and second thin ohmic electrodes are disposed so as not to overlap when seen from above. The lattice constant of the n-type current spreading layer matches that of the n-type cladding layer. The invention provides a P-side-up metal reflection type of semiconductor light emitting device having high luminance that inhibits increase in thickness of semiconductor layers and keeps current from locally concentrating. | 2016-02-25 |
20160056340 | LIGHT EMITTING DEVICE LIGHT-AMPLIFIED WITH GRAPHENE AND METHOD FOR MANUFACTURING SAME - The purpose of the present invention is to provide a method for manufacturing a light-amplified optoelectronic in device, on which pristine or doped graphene is transferred. Specifically, the method includes the steps of: depositing a first electrode, as a thin film, on the light emitting device; transferring pristine or doped graphene on the electrode thin film; etching the light emitting device in contact with the electrode thin film on which the transferred graphene has been transferred, thereby removing a part of the electrode thereon; spin-coating photoresist on the etched light emitting device; removing the photoresist from the spin-coated light emitting device, thereby forming an electrode thin film in a spin form and the pristine transferred to or graphene doped to the electrode thin film; and depositing metal on a second electrode. | 2016-02-25 |
20160056341 | SEMICONDUCTOR LIGHT EMITTING ELEMENT - A semiconductor light emitting element includes a base body, a first semiconductor layer, a second semiconductor layer, a first light emitting layer, a first conductive layer, a third semiconductor layer, a fourth semiconductor layer, a second light emitting layer, a second conductive layer, a first member, and a second member. The first member includes a first end portion and a second end portion. The first end portion is positioned between the base body and the first conductive layer and electrically connected to the first conductive layer, the second end portion not overlapping the second conductive layer. The second member includes a third end portion and a fourth end portion. The third end portion is positioned between the base body and the second conductive layer and electrically connected to the second conductive layer. The fourth end portion is electrically connected to the second end portion. | 2016-02-25 |
20160056342 | MASK, MASK GROUP, MANUFACTURING METHOD OF PIXELS AND PIXEL STRUCTURE - Embodiments of the disclosure provide a mask, a mask group, a manufacturing method of pixels and a pixel structure. The mask includes a shielding region and an opening region which are alternately arranged. A width of the opening region is twice of a width of one sub pixel, and a width of the shielding region between two adjacent opening regions is four times of the width of one sub pixel. | 2016-02-25 |
20160056343 | OPTOELECTRONIC SEMICONDUCTOR COMPONENT - An optoelectronic semiconductor component includes an optoelectronic semiconductor chip having side areas, a surface at a top side of the semiconductor chip, and a surface at a bottom side of the semiconductor chip; a shaped body having a surface at a top side of the shaped body and a surface at an underside of the shaped body; at least one plated-through hole including an electrically conductive material; and an electrically conductive connection electrically conductively connected to the semiconductor chip and the plated-through hole, wherein the side areas of the optoelectronic semiconductor chip are covered by the shaped body, and the surface at the top side and/or the surface at the bottom side of the optoelectronic semiconductor chip are completely free of the shaped body. | 2016-02-25 |
20160056344 | SEMICONDUCTOR COMPONENT AND METHOD OF FABRICATING A SEMICONDUCTOR COMPONENT - An optoelectronic semiconductor component includes a semiconductor chip having a semiconductor layer sequence including an active region that generates radiation; a radiation exit surface running parallel to the active region; a mounting side surface that fixes the semiconductor component and runs obliquely or perpendicularly to the radiation exit surface and at which at least one contact area for external electrical contacting is accessible; a molded body molded onto the semiconductor chip in places and forming the mounting side surface at least in regions; and a contact track arranged on the molded body and electrically conductively connecting the semiconductor chip to the at least one contact area. | 2016-02-25 |
20160056345 | LIGHT EMITTING ELEMENT PACKAGE - A light-emitting element package, according to one embodiment of the present invention, comprises: a circuit board including first and second regions having different heights; light-emitting elements respectively disposed in the first and second regions; and phosphor layers respectively disposed on the light-emitting elements, wherein the light-emitting elements are disposed within a 100-μm distance in the horizontal direction. | 2016-02-25 |
20160056346 | METHOD OF PRODUCING AN OPTOELECTRONIC COMPONENT - A method of producing an optoelectronic component includes providing a substrate with an optoelectronic semiconductor chip arranged on a surface of the substrate; providing a mask having a lower layer and an upper layer, wherein the lower layer has a lower opening and the upper layer has an upper opening, which openings jointly form a continuous mask opening, and the lower opening has a larger area than the upper opening; arranging the mask above the surface of the substrate such that the lower layer faces the surface of the substrate and the mask opening is arranged above the optoelectronic semiconductor chip; spraying a layer onto the optoelectronic semiconductor chip through the mask opening; and removing the mask. | 2016-02-25 |
20160056347 | WHITE LIGHT EMITTING DIODE WITH SINGLE CRYSTAL PHOSPHOR AND THE MANNER OF PRODUCTION - According to the invention, the diode with a single crystal phosphor placed over the chip comprises the fact that the single crystal phosphor, created by LnYAG and/or YAP and/or GGAG hosts, doped with the atoms selected from the Ce | 2016-02-25 |
20160056348 | LIGHT-EMITTING APPARATUS - The present application discloses a light-emitting apparatus having a light-emitting device and a wavelength conversion layer. The light-emitting device has a first top surface and a first side surface, and the wavelength conversion layer has a second top surface and a second side surface and covers the first top surface. A ratio of a distance between the first top surface to the second top surface and a distance between the first side surface and the second side surface is between 1.1˜1.3. | 2016-02-25 |
20160056349 | ASSEMBLY THAT EMITS ELECTROMAGNETIC RADIATION AND METHOD OF PRODUCING AN ASSEMBLY THAT EMITS ELECTROMAGNETIC RADIATION - An electromagnetic radiation emitting assembly includes a carrier, an electromagnetic radiation emitting component arranged above the carrier, and a potting material at least partly surrounding the electromagnetic radiation emitting component and into which are embedded phosphor that converts the electromagnetic radiation and heat-conducting particles that conduct heat arising during operation of the electromagnetic radiation emitting assembly, wherein a phosphor concentration in the potting material near the electromagnetic radiation emitting component is greater than a particle concentration of the heat-conducting particles in the potting material near the electromagnetic radiation emitting component, and a particle concentration of the heat-conducting particles in the potting material near the electromagnetic radiation emitting component is greater than in the potting material remote from the electromagnetic radiation emitting component. | 2016-02-25 |