08th week of 2021 patent applcation highlights part 54 |
Patent application number | Title | Published |
20210057148 | IGNITION COIL - An ignition coil for use in an internal combustion engine includes a primary coil, a secondary coil, a core, and a magnet. The core creates a closed magnetic circuit through which magnetic flux produced upon energization of the primary coil flows. The core has formed therein a gap through which the magnetic circuit passes. The magnet is disposed in the gap and has magnetic domains whose magnetization vectors are at least partially oriented obliquely relative to a gap direction. The orientation of the magnetization vectors in the magnet minimizes an energy loss when primary energy is transformed into secondary energy. | 2021-02-25 |
20210057149 | INDIRECT ADDITIVE MANUFACTURING PROCESS FOR FABRICATING BONDED SOFT MAGNETS - A bonded soft magnet object comprising bonded soft magnetic particles of an iron-containing alloy having a soft magnet characteristic, wherein the bonded soft magnetic particles have a particle size of at least 200 nm and up to 100 microns. Also described herein is a method for producing the bonded soft magnet by indirect additive manufacturing (IAM), such as by: (i) producing a soft magnet preform by bonding soft magnetic particles with an organic binder, wherein the magnetic particles have an iron-containing alloy composition with a soft magnet characteristic, and wherein the particles of the soft magnet material have a particle size of at least 200 nm and up to 100 microns; (ii) subjecting the preform to an elevated temperature sufficient to remove the organic binder to produce a binder-free preform; and (iii) sintering the binder-free preform at a further elevated temperature to produce the bonded soft magnet. | 2021-02-25 |
20210057150 | IGNITION COIL FOR INTERNAL COMBUSTION ENGINE AND PRODUCTION METHOD FOR THE SAME - An ignition coil includes a not-illustrated coil, a plate assembly, and a case assembly. The plate assembly and the case assembly are combined with each other by laser welding at a recess and a rib (projection) which are respective abutting portions, thereby forming storage spaces for storing the coil. | 2021-02-25 |
20210057151 | A METHOD AND AN APPARATUS FOR PRODUCING A COIL FOR ELECTRIC APPARATUS - A method for producing a coil for electric apparatus of the present invention is the method for producing a coil for electric apparatus for cutting spirally a block-shaped workpiece formed with a cylindrical portion corresponding to the coil in a circumferential direction of the cylindrical portion, the spiral coil is formed by turning a cutting means while moving it relatively to the workpiece from a part corresponding to one end of the coil to a part corresponding the other end of the coil along a machining line spirally set in the circumferential direction of the cylindrical portion. According to the invention, since the coil is formed by cutting the continuous cutting machining plane without generating a step in design from the block-shaped workpiece formed with a cylindrical portion corresponding to the coil using a wire-tool etc., it is possible to constitute a high-quality coil. | 2021-02-25 |
20210057152 | CERAMIC PACKAGE FOR FILLING LIQUID-COMPONENT CONTAINING ELECTROLYTE | 2021-02-25 |
20210057153 | MULTILAYER ELECTRONIC COMPONENT - A multilayer electronic component includes a body including a dielectric layer and an internal electrode, and an external electrode including an electrode layer disposed on the body and connected to the internal electrode, a first plating layer disposed on the electrode layer, and a conductive resin layer disposed on the first plating layer. The first plating layer has surface roughness higher at an interface with the conductive resin layer than at an interface with the electrode layer, and the conductive resin layer includes a conductive metal and a base resin. | 2021-02-25 |
20210057154 | MULTILAYER CERAMIC ELECTRONIC COMPONENT AND METHOD FOR PRODUCING THE SAME - A multilayer ceramic electronic component includes a multilayer body including a plurality of stacked ceramic layers and a plurality of stacked inner electrode layers, and outer electrodes on end surfaces of the multilayer body. The outer electrodes include underlying electrode layers on the end surfaces, conductive resin layers that cover the underlying electrode layers, and plating layers that cover the conductive resin layers. The underlying electrode layers are joined to the plating layers in connecting portions without the conductive resin layers interposed between the underlying electrode layers and the plating layers. | 2021-02-25 |
20210057155 | MULTILAYER CERAMIC ELECTRONIC COMPONENT - A multilayer ceramic electronic component includes a ceramic element assembly and outer electrodes provided on respective end surfaces of the ceramic element assembly. Each outer electrode includes an underlying electrode layer that is provided on the ceramic element assembly and that includes a sintered metal and glass and a conductive resin layer that is provided on the underlying electrode layer and that includes a metal filler and a resin. The underlying electrode layer satisfies at least one condition of a condition that a maximum exposure length of the glass exposed at the interface between the underlying electrode layer and the conductive resin layer is about 3.8 μm or less and a condition that an exposure rate of the glass exposed at the interface between the underlying electrode layer and the conductive resin layer is about 10.1% or less. | 2021-02-25 |
20210057156 | DIELECTRIC CERAMIC COMPOSITION AND MULTILAYER CERAMIC CAPACITOR COMPRISING THE SAME - A dielectric ceramic composition and a multilayer ceramic capacitor comprising the same are provided. The dielectric ceramic composition includes a BaTiO | 2021-02-25 |
20210057157 | MULTI-LAYERED CERAMIC CAPACITOR AND METHOD OF MANUFACTURING THE SAME - A multilayer ceramic capacitor includes a ceramic body including a dielectric layer and first and second internal electrodes disposed to oppose each other with the dielectric layer interposed therebetween, and first and second external electrodes disposed outside of the ceramic body and connected to the first and second internal electrodes, respectively. The ceramic body includes an active portion including of the first and second internal electrodes disposed to oppose each other with the dielectric layer interposed therebetween to form capacitance, and a cover portion disposed in upper and lower portions of the active portion. The cover portion has a larger number of pores than the dielectric layer of the active portion, and the cover portion includes a ceramic-polymer composite filled with a polymer in the pores of the cover portion. | 2021-02-25 |
20210057158 | MULTILAYER CERAMIC CAPACITOR - A multilayer ceramic capacitor includes a body including a dielectric layer and first and second internal electrodes disposed with the dielectric layer interposed therebetween; first and second through electrodes penetrating the body, connected to the first and second internal electrodes, respectively, and including nickel; first and second external electrodes, and connected to the first through electrode; and third and fourth external electrodes spaced apart from the first and second external electrodes, and connected to the second through electrode. Each of the first to fourth external electrodes includes a sintered electrode including nickel, and a first plating layer and a second plating layer stacked on the sintered electrode in order. | 2021-02-25 |
20210057159 | MULTILAYER CERAMIC CAPACITOR - A multilayer ceramic capacitor includes a body including a dielectric layer and first and second internal electrodes disposed with the dielectric layer interposed therebetween; first and second connection electrodes penetrating the body in a direction perpendicular to the dielectric layer and connected to the first internal electrode; third and fourth connection electrodes penetrating the body in a in a direction perpendicular to the dielectric layer and connected to the second internal electrode; first and second external electrodes disposed on both surfaces of the body, and connected to the first and second connection electrodes; and third and fourth external electrodes connected to the third and fourth connection electrodes, and at least a portion of the first and second connection electrodes is exposed to the surface of the body. | 2021-02-25 |
20210057160 | MULTILAYER CAPACITOR AND BOARD HAVING THE SAME MOUNTED THEREON - A multilayer capacitor includes a capacitor body including a dielectric layer and a plurality of internal electrodes, and external electrodes disposed on both ends of the capacitor body and connected to exposed portions of the plurality of internal electrodes, respectively. Each of the external electrodes includes a conductive layer disposed on the capacitor body to be connected to one or more of the plurality of internal electrodes, a conductive resin layer covering the conductive layer, and including a plurality of metal particles, a plurality of elastic fine powder particles each having an elastic powder particle and a metal film plated on a surface of the elastic powder particle, and a conductive resin surrounding the plurality of metal particles and the plurality of elastic fine powder particles and contacting the conductive layer, and a plating layer covering the conductive resin layer. | 2021-02-25 |
20210057161 | MULTILAYER CERAMIC ELECTRONIC COMPONENT - A multilayer ceramic electronic component includes a ceramic body and outer electrodes on two end surfaces of the ceramic body. Each of the outer electrodes includes a base electrode layer that is on the ceramic body and includes a sintered metal and glass, and a conductive resin layer that is on the base electrode layer and includes a metal filler and a resin. When a maximum thickness of the conductive resin layers that respectively lie on end surfaces of the ceramic body is denoted as T1 and when a maximum thickness of conductive resin layers adjacent to a first main surface and second main surface of the ceramic body or a first side surface or a second side surface of the ceramic body is denoted as T2, T1/T2 is about 2.4 or more. | 2021-02-25 |
20210057162 | MULTILAYER CERAMIC ELECTRONIC COMPONENT - A multilayer ceramic electronic component includes a stacked body, and an external electrode including an underlying electrode layer containing a conductive metal and a glass component, a resin layer containing a thermosetting resin and no metal component, and a plating layer. The underlying electrode layer extends from a first or second end surface, and covers a portion of each of first and second main surfaces and first and second lateral surfaces. The resin layer covers the underlying electrode layer on the second main surface adjacent to the first or second end surface. The plating layer covers a portion of the surface of the underlying electrode layer that is not covered with the resin layer, and covers the surface of the resin layer. | 2021-02-25 |
20210057163 | MULTILAYER CERAMIC CAPACITOR, CIRCUIT SUBSTRATE AND MANUFACTURE METHOD THEREFOR - A multilayer ceramic capacitor includes a ceramic main including first internal electrodes each drawn out to and reaching a pair of end surfaces and second internal electrodes each drawn out to and reaching a pair of side surfaces. A pair of end-surface external electrodes are respectively provided on the pair of end surfaces to be connected to the first internal electrodes, and a pair of side-surface external electrodes are respectively provided on the pair of side surfaces to be connected to the second internal electrodes. Each of the second internal electrodes has drawn-out parts that extend from an electrode main part and reach the pair of side surfaces, and with respect to each of the pair of side surfaces, two or more of the drawn-out parts are provided to extend from the electrode main part and reach the side surface. | 2021-02-25 |
20210057164 | MULTILAYER CERAMIC ELECTRONIC COMPONENT - A multilayer ceramic electronic component includes a body including an internal electrode alternately arranged with a dielectric layer; and an external electrode disposed on the body and connected to the internal electrode. The internal electrode includes a plurality of nickel (Ni) grains, and a composite layer including tin (Sn) and nickel (Ni) is disposed at a grain boundary of the nickel (Ni) grains. | 2021-02-25 |
20210057165 | Electrolytic Capacitor with Improved Connection Part - In an embodiment an electrolytic capacitor includes a capacitor element being housed by a can. A covering element is configured to close an opening of the can. A connection element comprises an external terminal for applying an electrical signal and a lead tab being electrically coupled to the capacitor element and to the external terminal. The connection element comprises an upper washer and a lower washer respectively having an opening to receive a rivet to fix the external terminal and the lead tab to the covering element. The upper washer is configured to either comprise a cavity to receive a head of the rivet or a protrusion or a tapered lateral surface. | 2021-02-25 |
20210057166 | ELECTROLYTIC CAPACITOR - By making the capacity retention rate to be high, an electrolyte capacitor with high capacitance in high frequency range is provided. In the electrolyte capacitor which includes an electrode foil and an electrode solution and which is used in the frequency range of 100 kHZ, a capacitance at 100 kHz is 50% or more relative to a capacitance at 120 Hz. | 2021-02-25 |
20210057167 | CAPACITOR WITH VOLUMETRICALLY EFFICIENT HERMETIC PACKAGING - An improved method of forming a capacitor, and capacitor formed thereby, is described. The method comprises forming an anode with an anode lead extending therefrom, forming a dielectric on the anode, forming a solid cathode layer on the dielectric and forming a hermetic encasement on the capacitor wherein the hermetic encasement comprises a conformal non-conductive layer. | 2021-02-25 |
20210057168 | PHOTOELECTRIC CONVERSION ELEMENT AND IMAGING DEVICE - A photoelectric conversion element according to an embodiment of the present disclosure includes: a first electrode including a plurality of electrodes independent from each other; a second electrode disposed to be opposed to the first electrode; a photoelectric conversion layer including a quantum dot; and a semiconductor layer including an oxide semiconductor material. The photoelectric conversion layer is provided between the first electrode and the second electrode. The semiconductor layer is provided between the first electrode and the photoelectric conversion layer. A conduction band of the photoelectric conversion layer has an energy level equal to or higher than an energy level of a conduction band of the semiconductor layer. | 2021-02-25 |
20210057169 | Method for Manufacturing Perovskite Solar Cell Module and Perovskite Solar Cell Module - Disclosures of the present invention mainly describe a method for manufacturing perovskite solar cell module. At first, a laser scribing is adopted for forming multi transparent conductive films (TCFs) on a transparent substrate. Subsequently, by using a first mask, multi HTLs, active layers, and ETLs are sequentially formed on the TCFs. Consequently, by the use of a second make, each of the ETLs is formed with an electrically connecting layer thereon, such that a perovskite solar cell module comprising a plurality of solar cell units is hence completed on the transparent substrate. It is worth explaining that, during the whole manufacturing process, each of the solar cell units is prevented from receiving bad influences that are provided by laser scribing or manufacture environment, such that each of the solar cell units is able to exhibit outstanding photoelectric conversion efficiency. | 2021-02-25 |
20210057170 | ULTRALOW-TEMPERATURE AND HIGH-CAPACITY SUPERCAPACITOR AND PREPARATION METHOD THEREFOR - Disclosed are an ultra-low temperature and high-capacity supercapacitor and a preparation method thereof. The electrode material used in the ultra-low temperature and high capacity supercapacitor is a composite porous carbon material comprising micropores and mesopores, the specific surface area of the electrode material is greater than 2500 m | 2021-02-25 |
20210057171 | ELECTRICAL SWITCH CONTACT SETS - Electrical switch contact sets are disclosed. A disclosed example apparatus includes a movable platform having first and second contacts, where the first and second contacts electrically coupled via the movable platform, and a stationary portion having third and fourth contacts, where the movable platform is movable to bring the first and second contacts in contact with the third and fourth contacts, respectively, to simultaneously close a current path of an electrical circuit associated with the first, second, third and fourth contacts. | 2021-02-25 |
20210057172 | CIRCUIT INTERRUPTER - A circuit interrupter includes: a first fixed terminal including a first fixed contact; a movable contactor which is formed as a separate part from the first fixed terminal and includes a first movable contact; a holding unit configured to hold the movable contactor so that the first movable contact is connected to the first fixed contact; and a squib configured to generate gas by combustion. In the circuit interrupter, pressure of the gas generated by the squib causes movement of the movable contactor in a direction away from the first fixed terminal so that the first movable contact is separated from the first fixed contact. | 2021-02-25 |
20210057173 | ACTIVE COVER PLATES - A variety of active cover plate configurations with prongs configured to contact side screw terminals of electrical receptacles are described. In one illustrative embodiment, an active cover plate includes a multi-gang face plate configured to be installed over a multi-gang light switch installation, the multi-gang faceplate including at least two apertures sized to accept a manually manipulatable element of switches in the multi-gang light switch installation. Prongs extend rearward from the multi-gang faceplate around at least one of the apertures. | 2021-02-25 |
20210057174 | BUTTON - A button is disclosed. The button includes: a lower button shell, which is a hollow structure with an upper opening, and is provided with a first sliding pin hole through a side wail of the lower button shell; an upper button shell, which is a hollow structure with a lower opening, wherein a side wall of the upper button shell is provided with a second sliding pin hole, the upper button shell is sleeved on the lower button shell, and the second sliding pin hole is directly opposite to the first sliding pin hole; a moveable tray, which is located at a central position in the lower button shell; a sliding arm, one end of which is rotatably connected to the moveable tray; a sliding pin, which is located in the lower button shell. | 2021-02-25 |
20210057175 | SWITCH APPARATUS FOR AUTOMOBILE - A switch apparatus for an automobile with a reduced size by installing a touch type switch apparatus inside a dial switch apparatus is provided. A switch apparatus for an automobile according to the present disclosure includes a main body which has an open lower side, a cover body which is inserted into the open lower side of the main body and is coupled to the main body, a dial switch apparatus which is installed on the main body and has an annular wheel knob rotatable with a virtual rotation axis disposed in a vertical direction as a rotation center, a touch type switch apparatus which is installed on the main body and has a capacitive touch pad which is touched by a user and pressed in an up-down direction, a main PCB which is coupled to the cover body to be disposed in the main body and into which a switch signal is input from the dial switch apparatus and the touch type switch apparatus, and a case body which is coupled to the main body and has a hole, through which the wheel knob and the capacitive touch pad are exposed, on an upper side, in which the capacitive touch pad is disposed inside the wheel knob. | 2021-02-25 |
20210057176 | VACUUM INTERRUPTER - Provided is a small-sized, reliable vacuum interrupter that does not involve upsizing and complication of the reduction load application mechanism. A vacuum interrupter of the present invention includes a magnetic body disposed on a circumferential edge around a stem surface of at least one of a moving current-carrying stem and a fixed current-carrying stem. The magnetic body includes a lower magnetic permeance portion having a lower magnetic permeance than the other portion. The lower magnetic permeance portion produces a magnetic field parallel to the axial direction. Arc discharge is driven in the direction of the parallel magnetic field, thus being extinguished. | 2021-02-25 |
20210057177 | BREAKER - A breaker includes a tank, first to third fixed contacts provided inside the tank, first to third movable contacts that are provided inside the tank and are movable, and first to third operation devices provided outside the tank to move the first to third movable, respectively. The first to third operation devices respectively include first to third torsion bars serving as a driving source to move the first to third movable contacts, respectively. | 2021-02-25 |
20210057178 | Switching Device - A switching device is disclosed. In an embodiment a switching device includes at least one stationary contact and a movable contact in a switching chamber configured to contain a gas containing H | 2021-02-25 |
20210057179 | LATCH RELAY CAPABLE OF REAL-TIME STATE CONTROL, STATE CONTROL METHOD FOR LATCH RELAY, AND BATTERY PACK COMPRISING LATCH RELAY CAPABLE OF REAL-TIME STATE CONTROL - The present invention relates to a technology that monitors a normal operation state through whether the flow of minute current is maintained in real time when a latch relay is turned on and allows the latch relay to be forcibly turned off through current prestored in a supercapacitor when an off operation of the latch relay is not normally performed. | 2021-02-25 |
20210057180 | MINIATURE SUPER SURFACE MOUNT FUSE AND MANUFACTURING METHOD THEREOF - The present disclosure discloses a miniature super surface mount fuse, comprising: a fuse element provided with a low overload fusing point and at least two high breaking capacity fusing points connected in series with the low overload fusing point and respectively arranged on two sides of the low overload fusing point, at least two cavity plates provided with cavities, the low overload fusing point and the high breaking capacity fusing points being located at corresponding positions of the cavities; the present disclosure further provides a manufacturing method for a surface mount fuse; the miniature super surface mount fuse of the present disclosure can provide the protection for the civil consumer electronic circuit under various overload conditions without the occurrence of safety hazards such as smoking or cracking of the housing or explosion. | 2021-02-25 |
20210057181 | ENHANCED THERMAL TRANSFER NOZZLE AND SYSTEM - Some embodiments include an x-ray system, comprising: a structure having a hole having an axially extending wall; and a nozzle disposed in the hole; wherein the nozzle and the axially extending wall form a plurality of axially extending helical fluid channels. Some embodiments include an x-ray system formed by shaping tubing to form a plurality of axially extending helical flutes; and forming a plurality of axially extending helical fluid channels by inserting the shaped tubing into a hole in a structure. | 2021-02-25 |
20210057182 | METHOD OF ENHANCING THE ENERGY AND BEAM CURRENT ON RF BASED IMPLANTER - Methods and a system of an ion implantation system are configured for increasing beam current above a maximum kinetic energy of a first charge state from an ion source without changing the charge state at the ion source. Ions having a first charge state are provided from an ion source and are selected into a first RF accelerator and accelerated in to a first energy. The ions are stripped to convert them to ions having various charge states. A charge selector receives the ions of various charge states and selects a final charge state at the first energy. A second RF accelerator accelerates the ions to final energy spectrum. A final energy filter filters the ions to provide the ions at a final charge state at a final energy to a workpiece. | 2021-02-25 |
20210057183 | ACCURATE WAVELENGTH CALIBRATION IN CATHODOLUMINESCENCE SEM - A scanning electron microscope having a spectrometer with a sensor having a plurality of pixels, wherein the spectrometer directs different wavelengths of collected light onto different pixels. An optical model is formed and an error function is minimized to find values for the model, such that wavelength detection may be corrected using the model. The model can correct for errors generated by effects such as the motion of the electron beam over the specimen, aberrations introduced by optical elements, and imperfections of the optical elements. A correction function may also be employed to account for effects not captured by the optical model. | 2021-02-25 |
20210057184 | HIGH FREQUENCY ANTENNA AND PLASMA PROCESSING DEVICE - A high-frequency antenna of an embodiment is installed on a window of a chamber, and includes first and second antenna elements and first and second relaying portions. The first antenna element extends over a first angle range in a circumferential direction, and the second antenna element extends in the circumferential direction over a second angle range deviating from the first angle range. The second antenna element is arranged away from the window compared to the first antenna element, and is arranged on the outer peripheral side from the first antenna element. The first relaying portion extends toward the side away from the window from the first antenna element, and the second relaying portion extends toward the outer peripheral side, from the first relaying portion to the second antenna element. | 2021-02-25 |
20210057185 | PLASMA ANTENNA AND APPARATUS FOR GENERATING PLASMA HAVING THE SAME - Provided are a plasma antenna and a plasma generating apparatus including the same. The plasma antenna includes a first antenna inducing electromagnetic fields by using an RF signal, a second antenna inducing electromagnetic fields by using the RF signal, and a capacitor connected between an input terminal of the first antenna and an input terminal of the second antenna. | 2021-02-25 |
20210057186 | METHODS AND APPARATUS FOR DEPOSITING ALUMINUM BY PHYSICAL VAPOR DEPOSITION (PVD) - Methods and apparatus for performing physical vapor deposition in a reactor chamber to form aluminum material on a substrate including: depositing a first aluminum layer atop a substrate to form a first aluminum region having a first grain size and a second aluminum layer atop the first aluminum layer, wherein the second aluminum layer has a second grain size larger than the first grain size; and depositing aluminum atop the second aluminum layer under conditions sufficient to increase the second grain size. | 2021-02-25 |
20210057187 | SUBSTRATE SUPPORT UNIT AND SUBSTRATE PROCESSING APPARATUS INCLUDING THE SAME - Provided are a substrate support unit capable of controlling a gradient between a center zone and an edge zone by adjusting impedances of center and edge electrodes constituting a lower electrode in a process chamber, and a substrate processing apparatus including the same. The substrate processing apparatus includes a housing, a shower head unit introduce a process gas for processing a substrate into the housing, and a support unit having an electrostatic chuck on which the substrate is mounted. The electrostatic chuck includes a dielectric plate constituting a body, a first heater configured to heat a first zone of the dielectric plate, and a second heater configured to heat a second zone of the dielectric plate. An etch rate for each zone of the substrate is controlled by adjusting an impedance or a voltage applied to each of the first heater and the second heater. | 2021-02-25 |
20210057188 | RADIO FREQUENCY POWER SUPPLY SYSTEM, PLASMA PROCESSOR, AND FREQUENCY-TUNING MATCHING - Disclosed are a radio-frequency power supply system, a plasma processor, and a corresponding frequency-tuning matching method applied to a plasma processor having an ultra-low frequency bias radio-frequency power source. The frequency-tuning matching method comprises an impedance segment frequency matching obtaining step including partitioning a low frequency radio-frequency power output period into a plurality of impedance matching segments, and during each impedance matching segment, tuning output frequency of a high frequency radio-frequency source, detecting reflected power of the high frequency radio-frequency power supply, and after experiencing one or more low frequency radio-frequency power output period, obtaining and storing the segment matching frequency for each impedance matching segment. In the subsequent variable-frequency matching step, output frequency of the high frequency radio-frequency power supply is set to periodically vary in the stored plurality of segment matching frequencies so as to match characteristic impedance in respective impedance matching segment. | 2021-02-25 |
20210057189 | GENERATOR WITH CONTROLLABLE SOURCE IMPEDANCE - A power supply system controls the source impedance of a generator in real time utilizing two amplifiers having asymmetrical power profiles in reference to a nominal load impedance that are diametrically opposite in reference to the nominal load impedance. Variations in power profiles may be achieved by using different topologies for each of the amplifiers or implementing a phase delay network. The output power from the first and second amplifiers may be combined using a combiner circuit or device and the output power from the combiner is transmitted to a plasma load. The output power of each amplifier may be independently controlled to alter one or more characteristics of the output power signal provided by the individual amplifiers. By changing the ratio of the output power of the first amplifier to the output power of the second amplified, the source impedance of the generators may be varied in real time. | 2021-02-25 |
20210057190 | LARGE AREA MICROWAVE PLASMA CVD APPARATUS AND CORRESPONDING METHOD FOR PROVIDING SUCH DEPOSITION - A large area microwave plasma chemical vapour deposition, LA MPCVD reactor apparatus and method for large area microwave chemical vapour deposition, comprising a reactor chamber adapted to provide a plasma region in an interior of the reactor chamber by electromagnetic energy at a first frequency, and a CRLH waveguide section adapted to operate with an infinite wavelength at the first frequency and having in a wall a coupler means arranged to couple electromagnetic energy from an interior of the CRLH waveguide section to the interior of the reactor chamber. | 2021-02-25 |
20210057191 | REACTOR SYSTEM COUPLED TO AN ENERGY EMITTER CONTROL CIRCUIT - A microwave energy source that generates a microwave energy is disclosed. The microwave energy source has an on-state and an off-state. A control circuit is coupled to the microwave energy source and includes an output to generate a control signal that adjusts a pulse frequency of the microwave energy. A voltage generator applies a non-zero voltage to the microwave energy source during the off-state. A frequency and a duty cycle of the non-zero voltage is based on a frequency and a duty cycle of the control signal. A waveguide is coupled to the microwave energy source. The waveguide has a supply gas inlet that receives a supply gas, a reaction zone that generates a plasma, a process inlet that injects a raw material into the reaction zone, and an outlet that outputs a powder based on a mixture of the supply gas and the raw material within the plasma. | 2021-02-25 |
20210057192 | ACTIVE GAS GENERATION APPARATUS - In the present invention, a high-voltage side electrode component further includes a conductive film disposed on an upper surface of a dielectric electrode independently of a metal electrode. The conductive film is disposed between at least one gas ejection port and the metal electrode in plan view, and the conductive film is set to ground potential. | 2021-02-25 |
20210057193 | HOLLOW CATHODE, AN APPARATUS INCLUDING A HOLLOW CATHODE FOR MANUFACTURING A SEMICONDUCTOR DEVICE, AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING A HOLLOW CATHODE - A hollow cathode includes an insulation plate having cathode holes. Bottom electrodes are below the insulation plate. The bottom electrodes define first holes having a width greater than a width of the cathode holes. Top electrodes are at an opposite side of the insulation plate from the bottom electrodes. The top electrodes define second holes aligned with the first holes along a direction orthogonal to the upper surface of the insulation plate. | 2021-02-25 |
20210057194 | EDGE RING, PLASMA PROCESSING APPARATUS, AND MANUFACTURING METHOD OF EDGE RING - An edge ring includes a first member made of a first material and having a contact surface with plasma generated inside the processing container, and a second member made of a second material having Young's modulus lower than that of the first material. The second member is provided on a side opposite to the contact surface of the first member such that a combined structure of the first member and the second member surrounds a periphery of a substrate placed on a stage inside a processing container of a plasma processing apparatus. | 2021-02-25 |
20210057195 | SYNTHETIC WAVELENGTHS FOR ENDPOINT DETECTION IN PLASMA ETCHING - Described is a method for determining an endpoint of an etch process using optical emission spectroscopy (OES) data as an input. OES data is acquired by a spectrometer in a plasma etch processing chamber. The acquired time-evolving spectral data is first filtered and de-meaned, and thereafter transformed into transformed spectral data, or trends, using multivariate analysis such as principal components analysis, in which previously calculated principal component weights are used to accomplish the transform. Grouping of the principal components weights into two separate groups corresponding to positive and negative natural wavelengths, creates separate signed trends (synthetic wavelengths). | 2021-02-25 |
20210057196 | SPUTTERING TARGET - A sputtering target comprising a target material, wherein a sputtering face of the target material has a ramp provided to reduce a thickness of the target material at a position where erosion concentrates most intensively during sputtering. | 2021-02-25 |
20210057197 | SEPARATING IONS IN AN ION TRAP - A method is disclosed comprising: trapping ions in an ion trap ( | 2021-02-25 |
20210057198 | SAMPLE SUPPORT, IONIZATION METHOD, AND MASS SPECTROMETRY METHOD - A sample support body is for ionization of a sample. The sample support body includes a substrate including a first surface and a second surface on sides opposite to each other, and a conduction layer provided at least on the first surface. A plurality of through-holes opening on the first surface and the second surface are formed in an effective region of the substrate, the effective region being for ionizing components of the sample. A width of a second opening on the second surface side is larger than a width of a first opening on the first surface side in each of the plurality of through-holes. | 2021-02-25 |
20210057199 | METHODS AND DEVICES FOR HIGH-THROUGHPUT DATA INDEPENDENT ANALYSIS - A method of analyzing a sample, the method includes separating precursor ions from the sample into narrow mass range groups based on mass-to-charge ratio; fragmenting the ions from each group to create groups of fragment ions; and mass analyzing fragment ions from each group of fragment ions using a long transient time mass analyzer, wherein the separation and fragmentation are decoupled from the mass analyzing and the cycle time of the high transient mass analyzer is greater than about five times longer than the cycle time of a narrow mass range scan time, and wherein the separation and fragmentation has a high duty cycle and the mass analyzing has a high duty cycle. | 2021-02-25 |
20210057200 | MASS SPECTROMETER AND MASS CALIBRATION METHOD IN MASS SPECTROMETER - A matrix-derived peak information acquisition unit ( | 2021-02-25 |
20210057201 | HUMIDIFICATION OF LASER ABLATED SAMPLE FOR ANALYSIS - Humidification systems and methods to introduce water vapor to a laser-ablated sample prior to introduction to an ICP torch are described. A system embodiment includes, but is not limited to, a water vapor generator configured to control production of a water vapor stream and to transfer the water vapor stream to at least one of a sample chamber of a laser ablation device or a mixing chamber in fluid communication with the laser ablation device, wherein the mixing chamber is configured to receive a laser-ablated sample from the laser ablation device and direct the laser-ablated sample to an inductively coupled plasma torch. | 2021-02-25 |
20210057202 | ION FLOW GUIDE DEVICES AND METHODS - Certain configurations of devices are described herein that include DC multipoles that are effective to direct ions. In some instances, the devices include a first multipole configured to provide a DC electric field effective to direct first ions of an entering particle beam along a first exit trajectory that is substantially orthogonal to an entry trajectory of the particle beam. The devices may also include a second multipole configured to provide a DC electric field effective to direct the received first ions from the first multipole along a second exit trajectory that is substantially orthogonal to the first exit trajectory. | 2021-02-25 |
20210057203 | IMR-MS REACTION CHAMBER - The present invention relates to a reaction chamber ( | 2021-02-25 |
20210057204 | METHOD AND SYSTEM FOR MEASURING INERT GAS BY ION PROBE - A method and system for measuring an inert gas by an ion probe. Embedding a to-be-measured sample into an epoxy resin, to obtain a sample target, where the to-be-measured sample includes an inert gas atom; after putting the obtained sample target into an analysis chamber of the ion probe, vacuumizing the analysis chamber, where the ion probe includes a primary ion source, an electron gun, a mass analyzer, and an ion detector; bombarding the sample target by using a primary ion beam formed by the primary ion source to release the inert gas atom in the sample target; ionizing the released inert gas atom by using an electron beam formed by the electron gun to form an inert gas ion; and analyzing a secondary ion containing the inert gas ion by using the mass analyzer and the ion detector to achieve measurement of the inert gas. | 2021-02-25 |
20210057205 | GERMICIDAL AMALGAM LAMP WITH TEMPERATURE SENSOR FOR OPTIMIZED OPERATION - A germicidal UV amalgam lamp with an elongated tubular lamp body and at least two filaments located on opposite ends of the lamp body. The lamp body is hermetically sealed with a pinch-sealed portion at both opposite ends, confining a gas volume in which a gas discharge can be produced along a discharge path between the filaments. Each filament has two electrical connectors, each including an internal portion connected to the filament and pinch-sealed into the lamp body. Each connector also includes an external portion located outside the lamp body for electrical connection of the lamp to a controlled power supply. The pinch-sealed portion bears a socket with an electrical temperature sensor and at least two electrical connections mounted to the socket. The at least two electrical connections of the temperature sensor are connected in parallel to the electrical connectors of the filament. | 2021-02-25 |
20210057206 | METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE - A method includes providing a first plate including a first surface, a second surface opposite to the first surface, and a first recess indented from the first surface towards the second surface; providing a semiconductor structure including a third surface, a fourth surface opposite to the third surface, and a first sidewall extending between the third surface and the fourth surface; placing the semiconductor structure over the first plate; and disposing a priming material over the third surface of the semiconductor structure, wherein a peripheral portion of the fourth surface of the semiconductor structure is in contact with the first surface of the first plate upon the disposing of the priming material. | 2021-02-25 |
20210057207 | FILM FORMING METHOD AND FILM FORMING APPARATUS - A film forming method includes: rotating a rotary table to revolve a substrate which is placed on the rotary table and has a recess in its surface; supplying a raw material gas to a first region on the rotary table; supplying an ammonia gas to a second region on the rotary table; forming a first SiN film in the recess by supplying the raw material gas to the first region and supplying the ammonia gas to the second region at a first flow rate, while the rotary table rotates at a first rotation speed; and forming a second SiN film in the recess such that the second SiN film is laminated on the first SiN film by supplying the raw material gas to the first region and supplying the ammonia gas to the second region at a second flow rate, while the rotary table rotates at a second rotation speed. | 2021-02-25 |
20210057208 | METHOD TO CLEAN SNO2 FILM FROM CHAMBER - A plasma processing system is provided. The system includes a hydrogen gas supply and a hydrocarbon gas supply and a processing chamber. The system includes a first mass flow controller (MFC) for controlling hydrogen gas flow into the processing chamber and a second MFC for controlling hydrocarbon gas flow into the processing chamber. The system includes a plasma source for generating plasma at the processing chamber. The plasma is for etching SnO | 2021-02-25 |
20210057209 | CLEANING METHOD, SEMICONDUCTOR MANUFACTURING METHOD AND A SYSTEM THEREOF - A cleaning method applied in semiconductor manufacturing is provided. The method includes: receiving a substrate having a surface; identifying a location of a particle on the surface of the substrate; moving a cleaning apparatus toward the location of the particle; performing a cleaning operation, thereby removing the particle by spraying a cleaning liquid from the cleaning apparatus flowing against gravity and toward the surface of the substrate; detecting the surface of the substrate; and performing a second cleaning operation when a cleaning result of the detection is not acceptable. A semiconductor manufacturing method and a system for cleaning a substrate are also provided. | 2021-02-25 |
20210057210 | Surface Treatment Compositions and Methods - This disclosure relates to methods and compositions for treating a semiconductor substrate having a pattern disposed on a surface of the substrate. | 2021-02-25 |
20210057211 | Epitaxies of a Chemical Compound Semiconductor - Methods and structures includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure. Thereby structures are formed. | 2021-02-25 |
20210057212 | METHOD OF PROCESSING SUBSTRATE, DEVICE MANUFACTURING METHOD, AND PLASMA PROCESSING APPARATUS - A disclosed method of processing a substrate includes (a) providing a substrate in a chamber of a plasma processing apparatus. The substrate has a patterned organic mask. The method further includes (b) generating plasma from a processing gas in the chamber in a state where the substrate is accommodated in the chamber. The method further includes (c) periodically applying a pulsed negative direct-current voltage to an upper electrode of the plasma processing apparatus, during execution of the generating plasma (that is, the above (b)). In the applying a pulsed negative direct-current voltage, ions from the plasma are supplied to the upper electrode, so that a silicon-containing material which is released from the upper electrode is deposited on the substrate. | 2021-02-25 |
20210057213 | NON-PLASMA ETCH OF TITANIUM-CONTAINING MATERIAL LAYERS WITH TUNABLE SELECTIVITY TO ALTERNATE METALS AND DIELECTRICS - Embodiments provide a non-plasma etch, such as a gas-phase and/or remote plasma etch, of titanium-containing material layers with tunable selectivity to other material layers. A substrate is received within a process chamber, and the substrate has exposed material layers including a titanium-containing material layer and at least one additional material layer. The additional material layer is selectively etched with respect to the titanium-containing material layer by exposing the substrate to a controlled environment including a halogen-containing gas. For one embodiment, the halogen-containing gas includes a fluorine-based gas. For one embodiment, the titanium-containing material layer is a titanium or a titanium nitride material layer. For one embodiment, the additional material layer includes tungsten, tungsten oxide, hafnium oxide, silicon oxide, silicon-germanium, silicon, silicon nitride, and/or aluminum oxide. A non-selective etch with respect to the titanium-containing material layer can be performed by modulating the process parameters such as temperature. | 2021-02-25 |
20210057214 | METHOD FOR DEPOSITING SILICON OXIDE FILM HAVING IMPROVED QUALITY BY PEALD USING BIS(DIETHYLAMINO)SILANE - In a method of depositing a silicon oxide film using bis(diethylamino)silane (BDEAS) on a substrate in a reaction space by plasma-enhanced atomic layer deposition (PEALD), each repeating deposition cycle of PEALD includes steps of: (i) adsorbing BDEAS on the substrate placed on a susceptor having a temperature of higher than 400° C. in an atmosphere substantially suppressing thermal decomposition of BDEAS in the reaction space; and (ii) exposing the substrate on which BDEAS is adsorbed to an oxygen plasma in the atmosphere in the reaction space, thereby depositing a monolayer or sublayer of silicon oxide. | 2021-02-25 |
20210057215 | TREATMENTS TO ENHANCE MATERIAL STRUCTURES - A method of forming a semiconductor structure includes pre-cleaning a surface of a substrate, forming an interfacial layer on the pre-cleaned surface of the substrate, depositing a high-κ dielectric layer on the interfacial layer, performing a plasma nitridation process to insert nitrogen atoms in the deposited high-κ dielectric layer, and performing a post-nitridation anneal process to passivate chemical bonds in the plasma nitridated high-κ dielectric layer. | 2021-02-25 |
20210057216 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE - A method for forming a crystalline high-k dielectric layer and controlling the crystalline phase and orientation of the crystal growth of the high-k dielectric layer during an anneal process. The crystalline phase and orientation of the crystal growth of the dielectric layer may be controlled using seeding sections of the dielectric layer serving as nucleation sites and using a capping layer mask during the anneal process. The location of the nucleation sites and the arrangement of the capping layer allow the orientation and phase of the crystal growth of the dielectric layer to be controlled during the anneal process. Based on the dopants and the process controls used the phase can be modified to increase the permittivity and/or the ferroelectric property of the dielectric layer. | 2021-02-25 |
20210057217 | HEAT TREATMENT METHOD AND HEAT TREATMENT APPARATUS - A heat treatment method includes: forming an amorphous silicon film having a hydrogen concentration in a film of 5×10 | 2021-02-25 |
20210057218 | LASER ANNEALING DEVICE AND THIN FILM CRYSTALLIZATION METHOD USING SAME - A laser annealing device includes a stage, a laser generator, and a reflective member. The stage supports a substrate with a thin film formed thereon to be processed, and may be moved in a first direction at a set or predetermined speed. The laser generator irradiates a first area of the thin film with a laser beam while the stage is moved. The reflective member reflects a part of the laser beam, which is reflected from the first area of the thin film, to a second area of the thin film. The first area and the second area are spaced apart from each other. | 2021-02-25 |
20210057219 | UNDERLAYERS FOR EUV LITHOGRAPHY - New lithographic compositions for use as EUV silicon hardmask layers are provided. The present invention provides methods of fabricating microelectronic structures and the resulting structures formed thereby using EUV lithographic processes. The method involves utilizing a silicon hardmask layer immediately below the photoresist layer. The silicon hardmask layer can either be directly applied to the substrate, or it can be applied to any intermediate layer(s) that may be applied to the substrate. The preferred silicon hardmask layers are formed from spin-coatable, polymeric compositions. The inventive method improves adhesion and reduces or eliminates pattern collapse issues. | 2021-02-25 |
20210057220 | ETCHING METHOD AND ETCHING APPARATUS - An etching method includes: forming a second film on a workpiece target including a processing target film, a layer including a plurality of convex portions formed on the processing target film, and a first film that covers the plurality of convex portions and the processing target film exposed between the plurality of convex portions; etching the second film in a state where the second film remains on a portion of the first film that covers a side surface of each of the plurality of convex portions; and etching the first film in a state where the second film remains on the portion of the first film that covers the side surface of each of the plurality of convex portions, thereby exposing a top portion of each of the plurality of convex portions and the processing target film between the plurality of convex portions. | 2021-02-25 |
20210057221 | METHOD FOR PREPARING OHMIC CONTACT ELECTRODE OF GALLIUM NITRIDE-BASED DEVICE - A method for preparing an ohmic contact electrode of a GaN-based device. Said method comprises the following steps: growing a first dielectric layer ( | 2021-02-25 |
20210057222 | LAMINATED ELEMENT MANUFACTURING METHOD - A laminated element manufacturing method includes a first forming step of forming a first modified region along a line to cut by irradiating a semiconductor substrate of a first wafer with a laser light along the line to cut, a first grinding step of grinding the semiconductor substrate of the first wafer, a bonding step of bonding a circuit layer of a second wafer to the semiconductor substrate of the first wafer, a second forming step of forming a second modified region along the line to cut by irradiating a semiconductor substrate of the second wafer with a laser light along the line to cut, and a second grinding step of grinding the semiconductor substrate of the second wafer. | 2021-02-25 |
20210057223 | METHODS FOR DEPOSITING A MOLYBDENUM NITRIDE FILM ON A SURFACE OF A SUBSTRATE BY A CYCLICAL DEPOSITION PROCESS AND RELATED SEMICONDUCTOR DEVICE STRUCTURES INCLUDING A MOLYBDENUM NITRIDE FILM - Methods for depositing a molybdenum nitride film on a surface of a substrate are disclosed. The methods may include: providing a substrate into a reaction chamber; and depositing a molybdenum nitride film directly on the surface of the substrate by performing one or more unit deposition cycles of cyclical deposition process, wherein a unit deposition cycle may include, contacting the substrate with a first vapor phase reactant comprising a molybdenum halide precursor, and contacting the substrate with a second vapor phase reactant comprising a nitrogen precursor. Semiconductor device structures including a molybdenum nitride film are also disclosed. | 2021-02-25 |
20210057224 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE - A nano-crystalline high-k film and methods of forming the same in a semiconductor device are disclosed herein. The nano-crystalline high-k film may be initially deposited as an amorphous matrix layer of dielectric material and self-contained nano-crystallite regions may be formed within and suspended in the amorphous matrix layer. As such, the amorphous matrix layer material separates the self-contained nano-crystallite regions from one another preventing grain boundaries from forming as leakage and/or oxidant paths within the dielectric layer. Dopants may be implanted in the dielectric material and crystal phase of the self-contained nano-crystallite regions maybe modified to change one or more of the permittivity of the high-k dielectric material and/or a ferroelectric property of the dielectric material. | 2021-02-25 |
20210057225 | WAFER PROCESSING METHOD - There is provided a wafer processing method for reducing a thickness of a wafer. The wafer has a front side and a back side opposite to the front side. The wafer has a device area where a plurality of devices are formed on the front side and a peripheral marginal area including a curved peripheral edge. A protective layer for covering the plural devices are formed on the front side in the device area. The wafer processing method includes a plasma etching step of supplying an etching gas in a plasma condition to the front side of the wafer by using the protective layer as a mask, thereby removing the peripheral marginal area including the curved peripheral edge, a protective member attaching step of attaching a protective member to the front side of the wafer, and a grinding step of grinding the back side of the wafer. | 2021-02-25 |
20210057226 | DEPOSITION PROCESS - A method of patterning a substrate includes receiving a substrate having microfabricated structures, including mandrels; executing a deposition process that deposits a first material on the mandrels, the deposition process including cyclically moving the substrate through a set of deposition modules. The substrate is moved through the set of deposition modules so that the first material is deposited at a first thickness at top portions of the mandrels and at a second thickness at bottom portions of mandrels, the first thickness being greater than the second thickness. The method includes executing a spacer deposition process that conformally deposits a second material on the substrate; executing a spacer open etch that removes depositions of the second material from over a top surface of the mandrels; removing the first material and the mandrels from the substrate, leaving sidewall spacers; and transferring a pattern defined by the sidewall spacers into an underlying layer. | 2021-02-25 |
20210057227 | ELEMENT CHIP SMOOTHING METHOD AND ELEMENT CHIP MANUFACTURING METHOD - An element chip smoothing method including: an element chip preparation step of preparing at least one element chip including a first surface covered with a resin film, a second surface opposite the first surface, and a sidewall connecting the first surface to the second surface and having ruggedness; a sidewall cleaning step of exposing the element chip to a first plasma, to remove deposits adhering to the sidewall, with the resin film allowed to continue to exist; a sidewall oxidation step of exposing the element chip to a second plasma, after the sidewall cleaning step, to oxidize a surface of the sidewall, with the resin film allowed to continue to exist; and a sidewall etching step of exposing the element chip to a third plasma, after the sidewall oxidation step, to etch the sidewall, with the resin film allowed to continue to exist. | 2021-02-25 |
20210057228 | METHOD OF ETCHING, DEVICE MANUFACTURING METHOD, AND PLASMA PROCESSING APPARATUS - In a disclosed method, etching a film by using plasma of a first processing gas and etching the film by using plasma of a second processing gas are alternately repeated. The first processing gas and the second processing gas each include a fluorocarbon gas. In etching the film by using the plasma of the first processing gas and etching the film by using the plasma of the second processing gas, radio frequency power is used to attract ions to the substrate. The first processing gas further includes an additive gas that is a source for nitrogen or sulfur and fluorine. In the first processing gas, the flow rate of the additive gas is smaller than the flow rate of the fluorocarbon gas. | 2021-02-25 |
20210057229 | ETCHING METHOD AND SUBSTRATE PROCESSING APPARATUS - There is provision of an etching method including a step of preparing a substrate over which a boron film or a boron-containing film is formed, a step of supplying a process gas containing chlorine gas, fluorine-containing gas, and hydrogen-containing gas, and a step of etching the boron film or the boron-containing film via a mask using a plasma formed from the process gas. | 2021-02-25 |
20210057230 | CARBON-BASED DIELECTRIC MATERIALS FOR SEMICONDUCTOR STRUCTURE FABRICATION AND THE RESULTING STRUCTURES - Carbon-based dielectric materials for semiconductor structure fabrication, and the resulting structures, are described. In an example, method of patterning a layer for a semiconductor structure includes forming a plurality of trenches in a dielectric layer above a semiconductor layer above a substrate to form a patterned dielectric layer. The method also includes filling the plurality of trenches with an adamantane-based carbon hardmask material. The method also includes removing the patterned dielectric layer selective to the adamantane-based carbon hardmask material. The method also includes using the adamantane-based carbon hardmask material to pattern the semiconductor layer. | 2021-02-25 |
20210057231 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE WITH REDUCED TRENCH DISTORTIONS - A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench. | 2021-02-25 |
20210057232 | SEMICONDUCTOR PACKAGES WITH INDICATIONS OF DIE-SPECIFIC INFORMATION - Semiconductor device packages and associated methods are disclosed herein. In some embodiments, the semiconductor device package includes (1) a first surface and a second surface opposite the first surface; (2) a semiconductor die positioned between the first and second surfaces; and (3) an indication positioned in a designated area of the first surface. The indication includes a code presenting information for operating the semiconductor die. The code is configured to be read by an indication scanner coupled to a controller. | 2021-02-25 |
20210057233 | SEMICONDUCTOR PACKAGES WITH PATTERNS OF DIE-SPECIFIC INFORMATION - Semiconductor device packages and associated methods are disclosed herein. In some embodiments, the semiconductor device package includes (1) a first surface and a second surface opposite the first surface; (2) a semiconductor die positioned between the first and second surfaces; and (3) a pattern positioned in a designated area of the first surface. The pattern includes multiple bit areas. Each of the bit areas represents a first bit information or a second bit information. the pattern presents information for operating the semiconductor die. The pattern is configured to be read by a pattern scanner. | 2021-02-25 |
20210057234 | Temporary Post-Assisted Embedding of Semiconductor Dies - A method includes: providing a semiconductor die having a first main surface, a second main surface opposite the first main surface, and an edge between the first main surface and the second main surface; applying a temporary spacer to a first part of the first main surface of the semiconductor die, the first part being positioned inward from a peripheral part of the first main surface; after applying the temporary spacer, embedding the semiconductor die at least partly in an embedding material, the embedding material covering the edge and the peripheral part of the first main surface of the semiconductor die and contacting a sidewall of the temporary spacer; and after the embedding, removing the temporary spacer from the first main surface of the semiconductor die to expose the first part of the first main surface of the semiconductor die. A semiconductor device produced by the method is also provided. | 2021-02-25 |
20210057235 | SUBSTRATE TREATMENT METHOD AND SUBSTRATE TREATMENT DEVICE - TMAH, hydrogen peroxide and water are mixed to make alkaline etching liquid containing TMAH, the hydrogen peroxide and the water and not containing hydrogen fluoride compound. The etching liquid is supplied to a substrate on which a polysilicon film and a silicon oxide film are exposed, thereby etching the polysilicon film while inhibiting etching the silicon oxide film. | 2021-02-25 |
20210057236 | EXHAUST GAS PROCESSING APPARATUS - There is provided an exhaust gas processing apparatus configured to cause a processing gas to be exposed to or come into contact with a liquid and thereby detoxify the processing gas. The exhaust gas processing apparatus comprises a suction casing provided with an inlet which the processing gas is sucked into and with an outlet which the processing gas is flowed out from; a liquid tank configured to receive an outlet-side part of the suction casing and store the liquid therein; and one or multiple spray nozzles placed in the liquid tank. The outlet of the suction casing is arranged to be located above a liquid surface of the liquid stored in the liquid tank. The one or multiple spray nozzles are configured to spray the liquid from around the outlet of the suction casing to a peripheral part of the outlet. | 2021-02-25 |
20210057237 | STAGE AND PLASMA PROCESSING APPARATUS - A stage includes a base having an accommodation space therein, a dielectric layer provided on a first surface of the base and having a placement surface on which a substrate is placed, the dielectric layer including therein a plurality of heaters, and a heater control board disposed in the accommodation space and configured to drive the plurality of heaters. The base has an inlet in a second surface thereof that is opposite the first surface, the inlet being configured to introduce a coolant into the accommodation space. | 2021-02-25 |
20210057238 | METHODS AND APPARATUS FOR CONTACTLESS SUBSTRATE WARPAGE CORRECTION - Embodiments of methods and apparatus for reducing warpage of a substrate are provided herein. In some embodiments, a method for reducing warpage of a substrate includes heating the substrate with an epoxy layer to at least a glass transition temperature of the epoxy layer while allowing the substrate to expand; subsequently constraining the substrate with a clamping force exerted towards the substrate from a top direction by applying a high pressure gas to the substrate and from a bottom direction by applying a vacuum pressure to the substrate; and rapidly cooling the substrate while the substrate is constrained. | 2021-02-25 |
20210057239 | APPARATUS AND METHOD FOR TREATING SUBSTRATE - An apparatus for treating a substrate includes a process chamber having a process space therein, a support unit that supports the substrate in the process space, a heating member that heats the substrate supported on the support unit, and an exhaust unit that evacuates the process space. The exhaust unit includes an exhaust duct and a heat retention unit having a retention space that retains heat released from the process space. The retention space surrounds an adjacent area located adjacent to the process chamber in the exhaust duct. | 2021-02-25 |
20210057240 | Semiconductor Packages - A semiconductor package includes a mounting substrate, a first semiconductor chip on the mounting substrate and electrically connected to the mounting substrate, a heat dissipation element on an upper surface of the first semiconductor chip, where the heat dissipation element comprises a sidewall comprising an inclined surface and an upper surface directly connected to the inclined surface, and a package molding portion on the mounting substrate and the inclined surface of the heat dissipation element. The package molding portion exposes at least a portion of the upper surface of the heat dissipation element, the upper surface of the heat dissipation element is parallel to the upper surface of the first semiconductor chip, and an angle formed by the upper surface of the heat dissipation element and the inclined surface of the heat dissipation element is an obtuse angle. | 2021-02-25 |
20210057241 | SEMICONDUCTOR MANUFACTURING DEVICE - According to one embodiment, a semiconductor manufacturing device includes a chemical solution preparation tank configured to prepare a solution; a chamber configured to discharge the chemical solution prepared at the chemical solution preparation tank to a substrate; a pressure sensor configured to measure a pressure inside the chemical solution preparation tank; and a variable opening valve arranged between the chemical solution preparation tank and an exhaust pipe. | 2021-02-25 |
20210057242 | Chip Front Surface Touchless Pick and Place Tool or Flip Chip Bonder - A piece of pick and place tool or a chip bonding equipment, which has innovative designs enabling chip(s) on a tape to get picked up without touching its front surface, is invented. The designs use levitation technologies to receive and hold the chips detached from the tape from a face-down position. A streamline design is also invented to provide better productivity. The invented pick and place tool or chip bonder is particularly useful for applications which require using chips with zero tolerance of particle and/or contamination on the chip front surfaces. | 2021-02-25 |
20210057243 | SUBSTRATE PROCESSING SYSTEM - A substrate processing system installed on a floor face is provided. The substrate processing system includes a substrate transfer module, a supporting table including a top plate disposed separately from the floor face, a plurality of substrate processing modules disposed on the top plate and coupled to the substrate transfer module along a lateral side of the substrate transfer module, and a plurality of power units disposed below the top plate. Further, the plurality of power units correspond to the plurality of substrate processing modules, respectively, and each of the power units is configured to supply electric power to the corresponding processing module. | 2021-02-25 |
20210057244 | METHOD AND APPARATUS FOR PROCESSING A SUBSTRATE USING NON-CONTACT TEMPERATURE MEASUREMENT - Methods and apparatus for processing a substrate are provided. The apparatus, for example, can include a process chamber comprising a chamber body defining a processing volume and having a view port coupled to the chamber body; a substrate support disposed within the processing volume and having a support surface to support a substrate; and an infrared temperature sensor (IRTS) disposed outside the chamber body adjacent the view port to measure a temperature of the substrate when being processed in the processing volume, the IRTS movable relative to the view port for scanning the substrate through the view port. | 2021-02-25 |
20210057245 | HEAT TREATMENT METHOD AND HEAT TREATMENT APPARATUS OF LIGHT IRRADIATION TYPE - Film information about a thin film formed on the front surface of a semiconductor wafer, substrate information about the semiconductor wafer, and an installation angle of an upper radiation thermometer are set and input. Emissivity of the front surface of the semiconductor wafer formed with a multilayer film is calculated based on the various kinds of information. Further, a weighted average efficiency of the emissivity of the front surface of the semiconductor wafer is determined based on a sensitivity distribution of the upper radiation thermometer. Front surface temperature of the semiconductor wafer at the time of heat treatment is measured using the determined weighted average efficiency of the emissivity. The emissivity is determined based on the film information and the like, so that the front surface temperature of the semiconductor wafer can be accurately measured even when thin films are formed in multiple layers. | 2021-02-25 |
20210057246 | MAPPING OF A REPLACEMENT PARTS STORAGE CONTAINER - A method for detecting positions of replacement parts, wafers, or empty carriers for a replacement part stored at a replacement parts storage container is provided. A container is received at a at a load port of a factory interface of an electronics processing system. The container is configured to store replacement parts for a process chamber of the electronics processing system. A robot arm is moved according to a first mapping pattern to identify, using a detection system at a distal end of an end effector of the robot arm, positions of one or more replacement parts in the container. Regions of the container that do not contain replacement parts are determined. The robot arm is moved according to a second mapping pattern to identify, within the regions of the container that do not contain replacement parts, using the detection system, a position in the container of at least one of a wafer or an empty carrier for a replacement part. A mapping of positions of the one or more replacement parts and of positions of at least one of the empty carrier or the wafer in the container is recorded in a storage medium. | 2021-02-25 |
20210057247 | SYSTEMS AND METHODS FOR SEMICONDUCTOR STRUCTURE SAMPLE PREPARATION AND ANALYSIS - Systems and methods are provided for determining defects in a semiconductor structure sample that is prepared for analysis by microscopy. A semiconductor structure sample preparation and analysis system includes a semiconductor structure sample that includes a structure, a protective capping layer on the structure, and a gap filler material on the protective capping layer. A microscopy apparatus acquires an image of the semiconductor structure sample. Sample defect recognition circuitry determines the presence of a defect in the semiconductor structure sample based on the acquired image. | 2021-02-25 |